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Differential D46171

AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL
ClosedPublic

Authored by tstellar on Apr 26 2018, 9:09 PM.

Details

Reviewers
arsenm
nhaehnle
Commits
rG46bbbc33c02f: AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL
rL334665: AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL

Diff Detail

Repository
rL LLVM

Event Timeline

tstellar created this revision.Apr 26 2018, 9:09 PM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptApr 26 2018, 9:09 PM
Harbormaster completed remote builds in B17484: Diff 144273.Apr 26 2018, 9:09 PM
arsenm added inline comments.May 3 2018, 3:06 AM
test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir
4 ↗(On Diff #144273)

I think you can drop the IR

tstellar updated this revision to Diff 146993.May 15 2018, 9:49 PM

Rebase patch.

Harbormaster completed remote builds in B18158: Diff 146993.May 15 2018, 9:49 PM
tstellar added inline comments.May 15 2018, 9:50 PM
test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir
4 ↗(On Diff #144273)

The Machine IR needs the %global0 reference.

arsenm accepted this revision.Jun 7 2018, 12:32 AM

LGTM

This revision is now accepted and ready to land.Jun 7 2018, 12:32 AM
Closed by commit rL334665: AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL (authored by tstellar). · Explain WhyJun 13 2018, 3:35 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
4 lines
2 lines
10 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
37 lines
37 lines

Diff 151264

llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td

Show All 16 Lines
def gi_vsrc0 : def gi_vsrc0 :
GIComplexOperandMatcher<s32, "selectVSRC0">, GIComplexOperandMatcher<s32, "selectVSRC0">,
GIComplexPatternEquiv<sd_vsrc0>; GIComplexPatternEquiv<sd_vsrc0>;
def gi_vop3mods0 : def gi_vop3mods0 :
GIComplexOperandMatcher<s32, "selectVOP3Mods0">, GIComplexOperandMatcher<s32, "selectVOP3Mods0">,
GIComplexPatternEquiv<VOP3Mods0>; GIComplexPatternEquiv<VOP3Mods0>;
def gi_vop3mods :
GIComplexOperandMatcher<s32, "selectVOP3Mods">,
GIComplexPatternEquiv<VOP3Mods>;
class GISelSop2Pat < class GISelSop2Pat <
SDPatternOperator node, SDPatternOperator node,
Instruction inst, Instruction inst,
ValueType dst_vt, ValueType dst_vt,
ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat <
(dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))), (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
(inst src0_vt:$src0, src1_vt:$src1) (inst src0_vt:$src0, src1_vt:$src1)
Show All 14 Lines

llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Linesprivate:
bool selectG_LOAD(MachineInstr &I) const; bool selectG_LOAD(MachineInstr &I) const;
bool selectG_STORE(MachineInstr &I) const; bool selectG_STORE(MachineInstr &I) const;
InstructionSelector::ComplexRendererFns InstructionSelector::ComplexRendererFns
selectVSRC0(MachineOperand &Root) const; selectVSRC0(MachineOperand &Root) const;
InstructionSelector::ComplexRendererFns InstructionSelector::ComplexRendererFns
selectVOP3Mods0(MachineOperand &Root) const; selectVOP3Mods0(MachineOperand &Root) const;
InstructionSelector::ComplexRendererFns
selectVOP3Mods(MachineOperand &Root) const;
const SIInstrInfo &TII; const SIInstrInfo &TII;
const SIRegisterInfo &TRI; const SIRegisterInfo &TRI;
const AMDGPURegisterBankInfo &RBI; const AMDGPURegisterBankInfo &RBI;
const AMDGPUTargetMachine &TM; const AMDGPUTargetMachine &TM;
const SISubtarget &STI; const SISubtarget &STI;
bool EnableLateStructurizeCFG; bool EnableLateStructurizeCFG;
#define GET_GLOBALISEL_PREDICATES_DECL #define GET_GLOBALISEL_PREDICATES_DECL
Show All 13 Lines

llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Show First 20 Lines • Show All 502 Lines • ▼ Show 20 Linesbool AMDGPUInstructionSelector::select(MachineInstr &I,
CodeGenCoverage &CoverageInfo) const { CodeGenCoverage &CoverageInfo) const {
if (!isPreISelGenericOpcode(I.getOpcode())) if (!isPreISelGenericOpcode(I.getOpcode()))
return true; return true;
switch (I.getOpcode()) { switch (I.getOpcode()) {
default: default:
break; break;
case TargetOpcode::G_FMUL:
case TargetOpcode::G_FADD:
case TargetOpcode::G_FPTOUI: case TargetOpcode::G_FPTOUI:
case TargetOpcode::G_OR: case TargetOpcode::G_OR:
return selectImpl(I, CoverageInfo); return selectImpl(I, CoverageInfo);
case TargetOpcode::G_ADD: case TargetOpcode::G_ADD:
return selectG_ADD(I); return selectG_ADD(I);
case TargetOpcode::G_BITCAST: case TargetOpcode::G_BITCAST:
return selectCOPY(I); return selectCOPY(I);
case TargetOpcode::G_CONSTANT: case TargetOpcode::G_CONSTANT:
Show All 23 Lines
AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const { AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const {
return {{ return {{
[=](MachineInstrBuilder &MIB) { MIB.add(Root); }, [=](MachineInstrBuilder &MIB) { MIB.add(Root); },
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // src0_mods [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // src0_mods
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
}}; }};
} }
InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectVOP3Mods(MachineOperand &Root) const {
return {{
[=](MachineInstrBuilder &MIB) { MIB.add(Root); },
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // src_mods
}};
}

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir

# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
--- |
define amdgpu_kernel void @fadd(i32 addrspace(1)* %global0) {ret void}
...
---
name: fadd
legalized: true
regBankSelected: true
# GCN-LABEL: name: fadd
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1
%3:vgpr(s64) = COPY $vgpr3_vgpr4
; fadd vs
; GCN: V_ADD_F32_e64
%4:vgpr(s32) = G_FADD %1, %0
; fadd sv
; GCN: V_ADD_F32_e64
%5:vgpr(s32) = G_FADD %0, %1
; fadd vv
; GCN: V_ADD_F32_e64
%6:vgpr(s32) = G_FADD %1, %2
G_STORE %4, %3 :: (store 4 into %ir.global0)
G_STORE %5, %3 :: (store 4 into %ir.global0)
G_STORE %6, %3 :: (store 4 into %ir.global0)
...
---

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir

# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
--- |
define amdgpu_kernel void @fmul(i32 addrspace(1)* %global0) {ret void}
...
---
name: fmul
legalized: true
regBankSelected: true
# GCN-LABEL: name: fmul
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1
%3:vgpr(s64) = COPY $vgpr3_vgpr4
; fmul vs
; GCN: V_MUL_F32_e64
%4:vgpr(s32) = G_FMUL %1, %0
; fmul sv
; GCN: V_MUL_F32_e64
%5:vgpr(s32) = G_FMUL %0, %1
; fmul vv
; GCN: V_MUL_F32_e64
%6:vgpr(s32) = G_FMUL %1, %2
G_STORE %4, %3 :: (store 4 into %ir.global0)
G_STORE %5, %3 :: (store 4 into %ir.global0)
G_STORE %6, %3 :: (store 4 into %ir.global0)
...
---