[RISCV] AsmParser support for the li pseudo instruction

[niosHD]

Summary

The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. The actual expansion to real instructions is similar to the expansion performed by the GNU Assembler.

This patch supersedes D41949.

Note that I marked this patch as WIP because I am currently traveling but plan to add compression tests to this patch in an update next week. Comments on the current state are appreciated though.

[asb]

I'll wait for the version with compression tests for a full review, but at a first read-through I think this is looking good. Thanks!

[niosHD]

I finally found the time to work on this patch, sorry for the delay.

This revision contains two notable updates. First, compression tests have been added. Second, I replaced the ADDIW, which was emitted for the first ADDI (similar to gas) in 64-bit mode, through a regular ADDI. Doing so provides more compression opportunities and also makes the code in 64-bit mode more similar to the one in 32-bit mode (i.e., enables shared tests in rvi-aliases-valid.s and rvc-aliases-valid.s).

With these updates, this patch is now ready for review.

PS Even though I am confident that replacing the first ADDIW with ADDI is correct, a second opinion is still appreciated. ;)

[niosHD]

Ping! Some feedback would be nice before I rebase this patch (which is less fun as it should be due to the recent improvements on the ASM parser)...

[asb]

The approach looks good. I'm out of office today, but will get a full review for you tomorrow.

[niosHD]

Rebased the patch. Luckily, it was not as bad as I anticipated. :)

There is no rush. I just wanted to make sure that the patch is not forgotten.

[asb]

By way of update: the only thing stopping me from committing this right now is convincing myself that there's never a reason to use addiw rather than addi for the first constant when expanding li for RV64. I'm just going to step through some more examples...

[niosHD]

In case it helps, my reasoning is as follows. There are basically two situations which can occur:

1. ADDI(W) is the first instruction of the expanded li and the source register is x0. The ADDIW instruction, as used before, would calculate the result as SignExtend64<32>(x0 + SignExtend64<12>(imm)). Considering that x0 is always 0, the result is therefore simply `SignExtend64<32>(SignExtend64<12>(imm)) = SignExtend64<12>(imm) which is also what the ADDI instruction gives us. (i.e., x0+SignExtend64<12>(imm) = SignExtend64<12>(imm) )
2. The ADDI(W) instruction follows a LUI instruction. The LUI instruction itself already performs sign extension to 64-bit meaning that the input register to the ADDI(W) instruction is a proper 64-bit signed value where the upper 32 bits are a copy of bit 31 (the MSB of the LUI immediate). Using LUI+ADDIW therefore calculates SignExtend64<32>(SignExtend64<32>(lui_imm << 12) + SignExtend64<12>(addi_imm))). Using LUI+ADDI gets us SignExtend64<32>(lui_imm << 12) + SignExtend64<12>(addi_imm)) which should be the same result in the end.

HTH,
Mario

[asb]

Ok, there _is_ a problem using addi rather than addiw. Consider loading the immediate 0x7fffffff.

# GCC approach:
lui a0, 524288
addiw a0, a0, -1
# Approach in this pass
lui a1, 524288
addi a1, a1, -1

Using addiw means that the value 0x000000007fffffff ends up in the register, but using addi we end up with the incorrect 0xffffffff7fffffff in register a1.

We could probably have some logic that determines whether for a particular constant using addi is safe, but addiw seems like a safe general approach.

[niosHD]

Thank you for finding the flaw in my thinking. I obviously missed that everything falls apart due to the sign extension of the LUI instruction...

I'll update the patch to use the ADDIW instruction again.

[sabuasal]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1188

Nit: why is this a switch, are you expecting to be handling more Pseudo instructions?

[niosHD]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1188

Yes, I expected that other pseudo instructions that expand to multiple instructions (e.g., la, symbol versions of lb, sb, ...) will be expanded here in the future too. Anyway, since we currently do not have the code and given that it is a small change anyway, I will go with the if instead.

Thank you for the comment!

[niosHD]

Updated the patch to emit ADDIW again and rebased it.

Especially for RV64, there are definitely a several missed opportunities regarding compression as can be seen by the check lines of the rv64c-aliases-valid.s test file. However, having a correct baseline is definitely more important than performing aggressive optimisation at the moment. Thanks again to Alex for finding the flaw in my reasoning.

[niosHD]

@asb I just missed my opportunity in the call to ping you regarding this patch. ;) Are there any remaining issues with it that I missed?

[asb]

Looks good to me. Many thanks for your work on this - I'm committing now.

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

 #include "MCTargetDesc/RISCVMCExpr.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "MCTargetDesc/RISCVTargetStreamer.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Casting.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/Support/TargetRegistry.h"
 
+#include <limits>
+
 using namespace llvm;
 
 // Include the auto-generated portion of the compress emitter.
 #define GEN_COMPRESS_INSTR
 #include "RISCVGenCompressInstEmitter.inc"
 
 namespace {
 struct RISCVOperand;
 
 class RISCVAsmParser : public MCTargetAsmParser {
   SMLoc getLoc() const { return getParser().getTok().getLoc(); }
   bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); }
 
   RISCVTargetStreamer &getTargetStreamer() {
     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
     return static_cast<RISCVTargetStreamer &>(TS);
   }
 
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
                                       unsigned Kind) override;
 
   bool generateImmOutOfRangeError(OperandVector &Operands, uint64_t ErrorInfo,
-                                  int Lower, int Upper, Twine Msg);
+                                  int64_t Lower, int64_t Upper, Twine Msg);
 
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
                                bool MatchingInlineAsm) override;
 
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
 
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
 
   bool ParseDirective(AsmToken DirectiveID) override;
 
+  // Helper to actually emit an instruction to the MCStreamer. Also, when
+  // possible, compression of the instruction is performed.
+  void emitToStreamer(MCStreamer &S, const MCInst &Inst);
+
+  // Helper to emit a combination of LUI, ADDI(W), and SLLI instructions that
+  // synthesize the desired immedate value into the destination register.
+  void emitLoadImm(unsigned DestReg, int64_t Value, MCStreamer &Out);
+
+  /// Helper for processing MC instructions that have been successfully matched
+  /// by MatchAndEmitInstruction. Modifications to the emitted instructions,
+  /// like the expansion of pseudo instructions (e.g., "li"), can be performed
+  /// in this method.
+  bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
+
 // Auto-generated instruction matching functions
 #define GET_ASSEMBLER_HEADER
 #include "RISCVGenAsmMatcher.inc"
 
   OperandMatchResultTy parseImmediate(OperandVector &Operands);
   OperandMatchResultTy parseRegister(OperandVector &Operands,
                                      bool AllowParens = false);
   OperandMatchResultTy parseMemOpBaseReg(OperandVector &Operands);
bool isFRMArg() const {
     if (!SVal || SVal->getKind() != MCSymbolRefExpr::VK_None)
       return false;
 
     StringRef Str = SVal->getSymbol().getName();
 
     return RISCVFPRndMode::stringToRoundingMode(Str) != RISCVFPRndMode::Invalid;
   }
 
+  bool isImmXLen() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(Imm, VK);
+    // Given only Imm, ensuring that the actually specified constant is either
+    // a signed or unsigned 64-bit number is unfortunately impossible.
+    bool IsInRange = isRV64() ? true : isInt<32>(Imm) || isUInt<32>(Imm);
+    return IsConstantImm && IsInRange && VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isUImmLog2XLen() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK;
     if (!isImm())
       return false;
     if (!evaluateConstantImm(Imm, VK) || VK != RISCVMCExpr::VK_RISCV_None)
       return false;
     return (isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm);
if ((IsRegFPR32 && Kind == MCK_FPR64) ||
       (IsRegFPR32C && Kind == MCK_FPR64C)) {
     Op.Reg.RegNum = convertFPR32ToFPR64(Reg);
     return Match_Success;
   }
   return Match_InvalidOperand;
 }
 
 bool RISCVAsmParser::generateImmOutOfRangeError(
-    OperandVector &Operands, uint64_t ErrorInfo, int Lower, int Upper,
+    OperandVector &Operands, uint64_t ErrorInfo, int64_t Lower, int64_t Upper,
     Twine Msg = "immediate must be an integer in the range") {
   SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
   return Error(ErrorLoc, Msg + " [" + Twine(Lower) + ", " + Twine(Upper) + "]");
 }
 
 bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                              OperandVector &Operands,
                                              MCStreamer &Out,
                                              uint64_t &ErrorInfo,
                                              bool MatchingInlineAsm) {
   MCInst Inst;
 
   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
   default:
     break;
-  case Match_Success: {
-    MCInst CInst;
-    bool Res = compressInst(CInst, Inst, getSTI(), Out.getContext());
-    CInst.setLoc(IDLoc);
-    Inst.setLoc(IDLoc);
-    Out.EmitInstruction((Res ? CInst : Inst), getSTI());
-    return false;
-  }
+  case Match_Success:
+    return processInstruction(Inst, IDLoc, Out);
   case Match_MissingFeature:
     return Error(IDLoc, "instruction use requires an option to be enabled");
   case Match_MnemonicFail:
     return Error(IDLoc, "unrecognized instruction mnemonic");
   case Match_InvalidOperand: {
     SMLoc ErrorLoc = IDLoc;
     if (ErrorInfo != ~0U) {
       if (ErrorInfo >= Operands.size())
         return Error(ErrorLoc, "too few operands for instruction");
 
       ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
       if (ErrorLoc == SMLoc())
         ErrorLoc = IDLoc;
     }
     return Error(ErrorLoc, "invalid operand for instruction");
   }
+  case Match_InvalidImmXLen:
+    if (isRV64()) {
+      SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
+      return Error(ErrorLoc, "operand must be a constant 64-bit integer");
+    }
+    return generateImmOutOfRangeError(Operands, ErrorInfo,
+                                      std::numeric_limits<int32_t>::min(),
+                                      std::numeric_limits<uint32_t>::max());
   case Match_InvalidUImmLog2XLen:
     if (isRV64())
       return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
   case Match_InvalidUImmLog2XLenNonZero:
     if (isRV64())
       return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 6) - 1);
     return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
bool RISCVAsmParser::parseDirectiveOption() {
 
   // Unknown option.
   Warning(Parser.getTok().getLoc(),
           "unknown option, expected 'rvc' or 'norvc'");
   Parser.eatToEndOfStatement();
   return false;
 }
 
+void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
+  MCInst CInst;
+  bool Res = compressInst(CInst, Inst, getSTI(), S.getContext());
+  CInst.setLoc(Inst.getLoc());
+  S.EmitInstruction((Res ? CInst : Inst), getSTI());
+}
+
+void RISCVAsmParser::emitLoadImm(unsigned DestReg, int64_t Value,
+                                 MCStreamer &Out) {
+  if (isInt<32>(Value)) {
+    // Emits the MC instructions for loading a 32-bit constant into a register.
+    //
+    // Depending on the active bits in the immediate Value v, the following
+    // instruction sequences are emitted:
+    //
+    // v == 0                        : ADDI
+    // v[0,12) != 0 && v[12,32) == 0 : ADDI
+    // v[0,12) == 0 && v[12,32) != 0 : LUI
+    // v[0,32) != 0                  : LUI+ADDI
+    //
+    int64_t Hi20 = ((Value + 0x800) >> 12) & 0xFFFFF;
+    int64_t Lo12 = SignExtend64<12>(Value);
+    unsigned SrcReg = RISCV::X0;
+
+    if (Hi20) {
+      emitToStreamer(Out,
+                     MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Hi20));
+      SrcReg = DestReg;
+    }
+
+    if (Lo12 || Hi20 == 0)
+      emitToStreamer(Out, MCInstBuilder(RISCV::ADDI)
+                              .addReg(DestReg)
+                              .addReg(SrcReg)
+                              .addImm(Lo12));
+    return;
+  }
+  assert(STI->hasFeature(RISCV::Feature64Bit) &&
+         "Target must be 64-bit to support a >32-bit constant");
+
+  // In the worst case, for a full 64-bit constant, a sequence of 8 instructions
+  // (i.e., LUI+ADDI+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emmitted. Note
+  // that the first two instructions (LUI+ADDI) can contribute up to 32 bits
+  // while the following ADDI instructions contribute up to 12 bits each.
+  //
+  // On the first glance, implementing this seems to be possible by simply
+  // emitting the most significant 32 bits (LUI+ADDI) followed by as many left
+  // shift (SLLI) and immediate additions (ADDI) as needed. However, due to the
+  // fact that ADDI performs a sign extended addition, doing it like that would
+  // only be possible when at most 11 bits of the ADDI instructions are used.
+  // Using all 12 bits of the ADDI instructions, like done by GAS, actually
+  // requires that the constant is processed starting with the least significant
+  // bit.
+  //
+  // In the following, constants are processed from LSB to MSB but instruction
+  // emission is performed from MSB to LSB by recursively calling
+  // emitLoadImm. In each recursion, first the lowest 12 bits are removed
+  // from the constant and the optimal shift amount, which can be greater than
+  // 12 bits if the constant is sparse, is determined. Then, the shifted
+  // remaining constant is processed recursively and gets emitted as soon as it
+  // fits into 32 bits. The emission of the shifts and additions is subsequently
+  // performed when the recursion returns.
+  //
+  int64_t Lo12 = SignExtend64<12>(Value);
+  int64_t Hi52 = (Value + 0x800) >> 12;
+  int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52);
+  Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
+
+  emitLoadImm(DestReg, Hi52, Out);
+
+  emitToStreamer(Out, MCInstBuilder(RISCV::SLLI)
+                          .addReg(DestReg)
+                          .addReg(DestReg)
+                          .addImm(ShiftAmount));
+
+  if (Lo12)
+    emitToStreamer(Out, MCInstBuilder(RISCV::ADDI)
+                            .addReg(DestReg)
+                            .addReg(DestReg)
+                            .addImm(Lo12));
+}
+
+bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
+                                        MCStreamer &Out) {
+  Inst.setLoc(IDLoc);
+
+  switch (Inst.getOpcode()) {
+  case RISCV::PseudoLI: {
+    auto Reg = Inst.getOperand(0).getReg();
+    int64_t Imm = Inst.getOperand(1).getImm();
+    // On RV32 the immediate here can either be a signed or an unsigned
+    // 32-bit number. Sign extension has to be performed to ensure that Imm
+    // represents the expected signed 64-bit number.
+    if (!isRV64())
+      Imm = SignExtend64<32>(Imm);
+    emitLoadImm(Reg, Imm, Out);
+    return false;
+  }
+  }
+
+  emitToStreamer(Out, Inst);
+  return false;
+}
+
 extern "C" void LLVMInitializeRISCVAsmParser() {
   RegisterMCAsmParser<RISCVAsmParser> X(getTheRISCV32Target());
   RegisterMCAsmParser<RISCVAsmParser> Y(getTheRISCV64Target());
 }

lib/Target/RISCV/RISCVInstrFormats.td

class RVInst<dag outs, dag ins, string opcodestr, string argstr,
   dag InOperandList = ins;
   let AsmString = opcodestr # "\t" # argstr;
   let Pattern = pattern;
 
   let TSFlags{4-0} = format.Value;
 }
 
 // Pseudo instructions
-class Pseudo<dag outs, dag ins, list<dag> pattern>
-    : RVInst<outs, ins, "", "", pattern, InstFormatPseudo> {
+class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
+    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
 // Instruction formats are listed in the order they appear in the RISC-V
 // instruction set manual (R, I, S, B, U, J) with sub-formats (e.g. RVInstR4,
 // RVInstRAtomic) sorted alphabetically.
 

lib/Target/RISCV/RISCVInstrInfo.td

def RetFlag      : SDNode<"RISCVISD::RET_FLAG", SDTNone,
                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 def SelectCC     : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC,
                           [SDNPInGlue]>;
 
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//
 
+class ImmXLenAsmOperand<string prefix, string suffix = ""> : AsmOperandClass {
+  let Name = prefix # "ImmXLen" # suffix;
+  let RenderMethod = "addImmOperands";
+  let DiagnosticType = !strconcat("Invalid", Name);
+}
+
 class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass {
   let Name = prefix # "Imm" # width # suffix;
   let RenderMethod = "addImmOperands";
   let DiagnosticType = !strconcat("Invalid", Name);
 }
 
 class SImmAsmOperand<int width, string suffix = "">
     : ImmAsmOperand<"S", width, suffix> {

 def bare_symbol : Operand<XLenVT> {
   let ParserMatchClass = BareSymbol;
   let MCOperandPredicate = [{
      return MCOp.isBareSymbolRef();
   }];
 }
 
 // A parameterized register class alternative to i32imm/i64imm from Target.td.
-def ixlenimm : Operand<XLenVT>;
+def ixlenimm : Operand<XLenVT> {
+  let ParserMatchClass = ImmXLenAsmOperand<"">;
+}
 
 // Standalone (codegen-only) immleaf patterns.
 def simm32     : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>;
 def simm32hi20 : ImmLeaf<XLenVT, [{return isShiftedInt<20, 12>(Imm);}]>;
 
 // Addressing modes.
 // Necessary because a frameindex can't be matched directly in a pattern.
 def AddrFI : ComplexPattern<iPTR, 1, "SelectAddrFI", [frameindex], []>;

 
 // TODO la
 // TODO lb lh lw
 // TODO RV64I: ld
 // TODO sb sh sw
 // TODO RV64I: sd
 
 def : InstAlias<"nop",           (ADDI      X0,      X0,       0)>;
-// TODO li
+
+// Note that the size is 32 because up to 8 32-bit instructions are needed to
+// generate an arbitrary 64-bit immediate. However, the size does not really
+// matter since PseudoLI is currently only used in the AsmParser where it gets
+// expanded to real instructions immediately.
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 32,
+    isCodeGenOnly = 0, isAsmParserOnly = 1 in
+def PseudoLI : Pseudo<(outs GPR:$rd), (ins ixlenimm:$imm), [],
+                      "li", "$rd, $imm">;
+
 def : InstAlias<"mv $rd, $rs",   (ADDI GPR:$rd, GPR:$rs,       0)>;
 def : InstAlias<"not $rd, $rs",  (XORI GPR:$rd, GPR:$rs,      -1)>;
 def : InstAlias<"neg $rd, $rs",  (SUB  GPR:$rd,      X0, GPR:$rs)>;
 
 let Predicates = [IsRV64] in {
 def : InstAlias<"negw $rd, $rs",   (SUBW  GPR:$rd,      X0, GPR:$rs)>;
 def : InstAlias<"sext.w $rd, $rs", (ADDIW GPR:$rd, GPR:$rs,       0)>;
 } // Predicates = [IsRV64]

test/MC/RISCV/rv32c-aliases-valid.s

+# RUN: llvm-mc -triple=riscv32 -mattr=+c -riscv-no-aliases < %s \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
+# RUN:     | llvm-objdump -d -riscv-no-aliases - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
+
+# The following check prefixes are used in this test:
+# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
+# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion)
+
+# CHECK-EXPAND: lui a2, 524288
+li x12, 0x80000000
+# CHECK-EXPAND: c.li a2, -1
+li x12, 0xFFFFFFFF

test/MC/RISCV/rv32i-aliases-invalid.s

 # RUN: not llvm-mc %s -triple=riscv32 -riscv-no-aliases 2>&1 | FileCheck %s
 # RUN: not llvm-mc %s -triple=riscv32 2>&1 | FileCheck %s
 
 # TODO ld
 # TODO sd
 
+li x0, 4294967296   # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
+li x0, -2147483649  # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
+li t4, foo          # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
+
 negw x1, x2   # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 sext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
+
+foo:
+  .space 4

test/MC/RISCV/rv32i-aliases-valid.s

 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases \
-# RUN:     | FileCheck -check-prefixes=CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv32 \
-# RUN:     | FileCheck -check-prefixes=CHECK-ALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -riscv-no-aliases -d - \
-# RUN:     | FileCheck -check-prefixes=CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -d - \
-# RUN:     | FileCheck -check-prefixes=CHECK-ALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
+
+# The following check prefixes are used in this test:
+# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
+# CHECK-ALIAS....Match the alias (tests instr. to alias mapping)
+# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion)
+
+# CHECK-EXPAND: lui a2, 524288
+li x12, 0x80000000
+# CHECK-EXPAND: addi a2, zero, -1
+li x12, 0xFFFFFFFF
 
 # CHECK-INST: csrrs t4, 3202, zero
 # CHECK-ALIAS: rdinstreth t4
 rdinstreth x29
 # CHECK-INST: csrrs s11, 3200, zero
 # CHECK-ALIAS: rdcycleh s11
 rdcycleh x27
 # CHECK-INST: csrrs t3, 3201, zero
 # CHECK-ALIAS: rdtimeh t3
 rdtimeh x28

test/MC/RISCV/rv64c-aliases-valid.s

+# RUN: llvm-mc -triple=riscv64 -mattr=+c -riscv-no-aliases < %s \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c < %s \
+# RUN:     | llvm-objdump -d -riscv-no-aliases - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
+
+# The following check prefixes are used in this test:
+# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
+# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion)
+
+# CHECK-EXPAND: c.li a2, 1
+# CHECK-EXPAND: c.slli a2, 31
+li x12, 0x80000000
+# CHECK-EXPAND: c.li a2, 1
+# CHECK-EXPAND: c.slli a2, 32
+# CHECK-EXPAND: c.addi a2, -1
+li x12, 0xFFFFFFFF
+
+# CHECK-EXPAND: c.li t0, 1
+# CHECK-EXPAND: c.slli t0, 32
+li t0, 0x100000000
+# CHECK-EXPAND: c.li t1, -1
+# CHECK-EXPAND: c.slli t1, 63
+li t1, 0x8000000000000000
+# CHECK-EXPAND: c.li  t1, -1
+# CHECK-EXPAND: c.slli t1, 63
+li t1, -0x8000000000000000
+# CHECK-EXPAND: lui t2, 9321
+# CHECK-EXPAND: addi t2, t2, -1329
+# CHECK-EXPAND: c.slli t2, 35
+li t2, 0x1234567800000000
+# CHECK-EXPAND: c.li t3, 7
+# CHECK-EXPAND: c.slli t3, 36
+# CHECK-EXPAND: c.addi t3, 11
+# CHECK-EXPAND: c.slli t3, 24
+# CHECK-EXPAND: c.addi t3, 15
+li t3, 0x700000000B00000F
+# CHECK-EXPAND: lui t4, 583
+# CHECK-EXPAND: addi t4, t4, -1875
+# CHECK-EXPAND: c.slli t4, 14
+# CHECK-EXPAND: addi t4, t4, -947
+# CHECK-EXPAND: c.slli t4, 12
+# CHECK-EXPAND: addi t4, t4, 1511
+# CHECK-EXPAND: c.slli t4, 13
+# CHECK-EXPAND: addi t4, t4, -272
+li t4, 0x123456789abcdef0
+# CHECK-EXPAND: c.li t5, -1
+li t5, 0xFFFFFFFFFFFFFFFF

test/MC/RISCV/rv64i-aliases-invalid.s

 # RUN: not llvm-mc %s -triple=riscv64 -riscv-no-aliases 2>&1 | FileCheck %s
 # RUN: not llvm-mc %s -triple=riscv64 2>&1 | FileCheck %s
 
+li t5, 0x10000000000000000 # CHECK: :[[@LINE]]:8: error: unknown operand
+li t4, foo                 # CHECK: :[[@LINE]]:8: error: operand must be a constant 64-bit integer
+
 rdinstreth x29 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 rdcycleh x27   # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 rdtimeh x28    # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
+
+foo:
+  .space 8

test/MC/RISCV/rv64i-aliases-valid.s

 # RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases \
-# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv64 \
-# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-objdump -riscv-no-aliases -d - \
-# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-objdump -d - \
-# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
+
+# The following check prefixes are used in this test:
+# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
+# CHECK-ALIAS....Match the alias (tests instr. to alias mapping)
+# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion)
 
 # TODO ld
 # TODO sd
 
+# CHECK-EXPAND: addi a2, zero, 1
+# CHECK-EXPAND: slli a2, a2, 31
+li x12, 0x80000000
+# CHECK-EXPAND: addi a2, zero, 1
+# CHECK-EXPAND: slli a2, a2, 32
+# CHECK-EXPAND: addi a2, a2, -1
+li x12, 0xFFFFFFFF
+
+# CHECK-EXPAND: addi t0, zero, 1
+# CHECK-EXPAND: slli t0, t0, 32
+li t0, 0x100000000
+# CHECK-EXPAND: addi t1, zero, -1
+# CHECK-EXPAND: slli t1, t1, 63
+li t1, 0x8000000000000000
+# CHECK-EXPAND: addi t1, zero, -1
+# CHECK-EXPAND: slli t1, t1, 63
+li t1, -0x8000000000000000
+# CHECK-EXPAND: lui t2, 9321
+# CHECK-EXPAND: addi t2, t2, -1329
+# CHECK-EXPAND: slli t2, t2, 35
+li t2, 0x1234567800000000
+# CHECK-EXPAND: addi t3, zero, 7
+# CHECK-EXPAND: slli t3, t3, 36
+# CHECK-EXPAND: addi t3, t3, 11
+# CHECK-EXPAND: slli t3, t3, 24
+# CHECK-EXPAND: addi t3, t3, 15
+li t3, 0x700000000B00000F
+# CHECK-EXPAND: lui t4, 583
+# CHECK-EXPAND: addi t4, t4, -1875
+# CHECK-EXPAND: slli t4, t4, 14
+# CHECK-EXPAND: addi t4, t4, -947
+# CHECK-EXPAND: slli t4, t4, 12
+# CHECK-EXPAND: addi t4, t4, 1511
+# CHECK-EXPAND: slli t4, t4, 13
+# CHECK-EXPAND: addi t4, t4, -272
+li t4, 0x123456789abcdef0
+# CHECK-EXPAND: addi t5, zero, -1
+li t5, 0xFFFFFFFFFFFFFFFF
+
 # CHECK-INST: subw t6, zero, ra
 # CHECK-ALIAS: negw t6, ra
 negw x31, x1
 # CHECK-INST: addiw t6, ra, 0
 # CHECK-ALIAS: sext.w t6, ra
 sext.w x31, x1

test/MC/RISCV/rvc-aliases-valid.s

+# RUN: llvm-mc -triple=riscv32 -mattr=+c -riscv-no-aliases < %s \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+c -riscv-no-aliases < %s \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
+# RUN:     | llvm-objdump -d -riscv-no-aliases - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c < %s \
+# RUN:     | llvm-objdump -d -riscv-no-aliases - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
+
+# The following check prefixes are used in this test:
+# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
+# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion)
+
+# CHECK-EXPAND: c.li a0, 0
+li x10, 0
+# CHECK-EXPAND: c.li a0, 1
+li x10, 1
+# CHECK-EXPAND: c.li a0, -1
+li x10, -1
+# CHECK-EXPAND: addi a0, zero, 2047
+li x10, 2047
+# CHECK-EXPAND: addi a0, zero, -2047
+li x10, -2047
+# CHECK-EXPAND: c.lui a1, 1
+# CHECK-EXPAND: addi a1, a1, -2048
+li x11, 2048
+# CHECK-EXPAND: addi a1, zero, -2048
+li x11, -2048
+# CHECK-EXPAND: c.lui a1, 1
+# CHECK-EXPAND: addi a1, a1, -2047
+li x11, 2049
+# CHECK-EXPAND: lui a1, 1048575
+# CHECK-EXPAND: addi a1, a1, 2047
+li x11, -2049
+# CHECK-EXPAND: c.lui a1, 1
+# CHECK-EXPAND: c.addi a1, -1
+li x11, 4095
+# CHECK-EXPAND: lui a1, 1048575
+# CHECK-EXPAND: c.addi a1, 1
+li x11, -4095
+# CHECK-EXPAND: c.lui a2, 1
+li x12, 4096
+# CHECK-EXPAND: lui a2, 1048575
+li x12, -4096
+# CHECK-EXPAND: c.lui a2, 1
+# CHECK-EXPAND: c.addi a2, 1
+li x12, 4097
+# CHECK-EXPAND: lui a2, 1048575
+# CHECK-EXPAND: c.addi a2, -1
+li x12, -4097
+# CHECK-EXPAND: lui a2, 524288
+# CHECK-EXPAND: c.addi a2, -1
+li x12, 2147483647
+# CHECK-EXPAND: lui a2, 524288
+# CHECK-EXPAND: c.addi a2, 1
+li x12, -2147483647
+# CHECK-EXPAND: lui a2, 524288
+li x12, -2147483648
+# CHECK-EXPAND: lui a2, 524288
+li x12, -0x80000000

test/MC/RISCV/rvi-aliases-valid.s

 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases \
-# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv32 \
-# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
 # RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases\
-# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv64 \
-# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -d -riscv-no-aliases - \
-# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -d - \
-# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-objdump -d -riscv-no-aliases - \
-# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-objdump -d - \
-# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
+
+# The following check prefixes are used in this test:
+# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
+# CHECK-ALIAS....Match the alias (tests instr. to alias mapping)
+# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion)
 
 # TODO la
 # TODO lb lh lw
 # TODO sb sh sw
 
 # CHECK-INST: addi zero, zero, 0
 # CHECK-ALIAS: nop
 nop
-# TODO li
+
+# CHECK-INST: addi a0, zero, 0
+# CHECK-ALIAS: mv a0, zero
+li x10, 0
+# CHECK-EXPAND: addi a0, zero, 1
+li x10, 1
+# CHECK-EXPAND: addi a0, zero, -1
+li x10, -1
+# CHECK-EXPAND: addi a0, zero, 2047
+li x10, 2047
+# CHECK-EXPAND: addi a0, zero, -2047
+li x10, -2047
+# CHECK-EXPAND: lui a1, 1
+# CHECK-EXPAND: addi a1, a1, -2048
+li x11, 2048
+# CHECK-EXPAND: addi a1, zero, -2048
+li x11, -2048
+# CHECK-EXPAND: lui a1, 1
+# CHECK-EXPAND: addi a1, a1, -2047
+li x11, 2049
+# CHECK-EXPAND: lui a1, 1048575
+# CHECK-EXPAND: addi a1, a1, 2047
+li x11, -2049
+# CHECK-EXPAND: lui a1, 1
+# CHECK-EXPAND: addi a1, a1, -1
+li x11, 4095
+# CHECK-EXPAND: lui a1, 1048575
+# CHECK-EXPAND: addi a1, a1, 1
+li x11, -4095
+# CHECK-EXPAND: lui a2, 1
+li x12, 4096
+# CHECK-EXPAND: lui a2, 1048575
+li x12, -4096
+# CHECK-EXPAND: lui a2, 1
+# CHECK-EXPAND: addi a2, a2, 1
+li x12, 4097
+# CHECK-EXPAND: lui a2, 1048575
+# CHECK-EXPAND: addi a2, a2, -1
+li x12, -4097
+# CHECK-EXPAND: lui a2, 524288
+# CHECK-EXPAND: addi a2, a2, -1
+li x12, 2147483647
+# CHECK-EXPAND: lui a2, 524288
+# CHECK-EXPAND: addi a2, a2, 1
+li x12, -2147483647
+# CHECK-EXPAND: lui a2, 524288
+li x12, -2147483648
+# CHECK-EXPAND: lui a2, 524288
+li x12, -0x80000000
+
 # CHECK-INST: addi t6, zero, 0
 # CHECK-ALIAS: mv t6, zero
 mv x31, zero
 # CHECK-INST: xori t6, ra, -1
 # CHECK-ALIAS: not t6, ra
 not x31, x1
 # CHECK-INST: sub t6, zero, ra
 # CHECK-ALIAS: neg t6, ra