AMDGPU/SI: Don't promote alloca to vector for AddrSpaceCast instruction.

[cfang]

Summary

We have no logic to promote alloca to vector for an AddrSpaceCast instruction.

[arsenm]

Needs tests

[cfang]

Add a test.

[yaxunl]

test/CodeGen/AMDGPU/vector-alloca-addrspacecast.ll

26

address space 4 is constant address space. Do you intend to cast %tmp to generic address space? If so, you should use the default address space (0) since that is generic address space.

[cfang]

Fix addrspacecast in the test since generic address space is 0 (default) now. Thanks, Sam!

[cfang]

What do you think of the test? Thanks;

[cfang]

Update the test:

1. correct a few wrong checking;
2. Remove the -amdgiz from the triple since it is no longer necessary;
3. Add "-data-layout=A5" to explicitly specify the data layout for address space 5 for alloca
   • and to remove the "target:" line for the same data layout purpose.

[arsenm]

LGTM

lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp

 // TODO: Check isTriviallyVectorizable for calls and handle other
 // instructions.
 static bool canVectorizeInst(Instruction *Inst, User *User) {
   switch (Inst->getOpcode()) {
   case Instruction::Load: {
     LoadInst *LI = cast<LoadInst>(Inst);
     // Currently only handle the case where the Pointer Operand is a GEP so check for that case.
     return isa<GetElementPtrInst>(LI->getPointerOperand()) && !LI->isVolatile();
   }
   case Instruction::BitCast:
-  case Instruction::AddrSpaceCast:
     return true;
   case Instruction::Store: {
     // Must be the stored pointer operand, not a stored value, plus
     // since it should be canonical form, the User should be a GEP.
     StoreInst *SI = cast<StoreInst>(Inst);
     return (SI->getPointerOperand() == User) && isa<GetElementPtrInst>(User) && !SI->isVolatile();
   }
   default:
     return false;
   }

test/CodeGen/AMDGPU/vector-alloca-addrspacecast.ll

+; RUN: opt -S -mtriple=amdgcn-- -data-layout=A5 -amdgpu-promote-alloca -sroa -instcombine < %s | FileCheck -check-prefix=OPT %s
+
+; Should give up promoting alloca to vector with an addrspacecast.
+
+; OPT-LABEL: @vector_addrspacecast(
+; OPT: alloca [3 x i32]
+; OPT: store i32 0, i32 addrspace(5)* %a0, align 4
+; OPT: store i32 1, i32 addrspace(5)* %a1, align 4
+; OPT: store i32 2, i32 addrspace(5)* %a2, align 4
+; OPT: %tmp = getelementptr [3 x i32], [3 x i32] addrspace(5)* %alloca, i64 0, i64 %index
+; OPT: %ac = addrspacecast i32 addrspace(5)* %tmp to i32*
+; OPT: %data = load i32, i32* %ac, align 4
+define amdgpu_kernel void @vector_addrspacecast(i32 addrspace(1)* %out, i64 %index) {
+entry:
+  %alloca = alloca [3 x i32], addrspace(5)
+  %a0 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %alloca, i32 0, i32 0
+  %a1 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %alloca, i32 0, i32 1
+  %a2 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %alloca, i32 0, i32 2
+  store i32 0, i32 addrspace(5)* %a0
+  store i32 1, i32 addrspace(5)* %a1
+  store i32 2, i32 addrspace(5)* %a2
+  %tmp = getelementptr [3 x i32], [3 x i32] addrspace(5)* %alloca, i64 0, i64 %index
+  %ac = addrspacecast i32 addrspace(5)* %tmp to i32 *
+  %data = load i32, i32 * %ac
+  store i32 %data, i32 addrspace(1)* %out
+  ret void
+}