AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.cvt.pkrtz

[arsenm]

Have you tried enabling the tablegen selector build? I’ve been avoiding commiting any of these kind of simple selectors without that

[tstellar]

In D45907#1074205, @arsenm wrote:

Have you tried enabling the tablegen selector build? I’ve been avoiding commiting any of these kind of simple selectors without that

Yes, it only generates code for stand-alone patterns and instruction patterns that use specify register classes for operands rather than types.

[tstellar]

Actually, I just discovered -warn-on-skipped-patterns on it looks like most patterns are skipped because the ComplexPatterns is not mapped to GlobalISel. It looks like the pkrtz pattern doesn't match because it uses a SDNode.

[arsenm]

Have you tried enabling the tablegen selector build? I’ve been avoiding commiting any of these kind of simple selectors without that

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

155

Separate line

553

Ditto

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir

4–8

I think you can drop the IR section, even with the intrinsic declaration

[tstellar]

Rewrite patch to use TableGen'd instruction selector.

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir

4–8

It complained about function cvt_pkrtz not being defined in the IR, but I was able to drop the intrinsic declaration.

[tstellar]

Rebase to pull in updated TableGen pattern classes.

[tstellar]

Ping.

[arsenm]

LGTM

lib/Target/AMDGPU/AMDGPUInstructionSelector.h

struct GEPInfo {
     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
   };
 
   MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
   bool selectCOPY(MachineInstr &I) const;
   bool selectG_CONSTANT(MachineInstr &I) const;
   bool selectG_ADD(MachineInstr &I) const;
   bool selectG_GEP(MachineInstr &I) const;
+  bool selectG_INTRINSIC(MachineInstr &I) const;
   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
   bool selectG_LOAD(MachineInstr &I) const;
   bool selectG_STORE(MachineInstr &I) const;
   unsigned getSALUOpcode(const MachineInstr &I) const;

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const {
   I.eraseFromParent();
   return true;
 }
 
 bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const {
   return selectG_ADD(I);
 }
 
+bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
+  unsigned IntrinsicID =  I.getOperand(1).getIntrinsicID();
+
+  switch (IntrinsicID) {
+  default: break;
+  case Intrinsic::amdgcn_cvt_pkrtz:
+    return selectSimple(I);
+  }
+  return false;
+}
+
 static MachineInstr *
 buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt,
          unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3,
          unsigned VM, bool Compr, unsigned Enabled, bool Done) {
   DebugLoc DL = Insert->getDebugLoc();
   MachineBasicBlock &BB = *Insert->getParent();
   unsigned Opcode = Done ? AMDGPU::EXP_DONE : AMDGPU::EXP;
   return BuildMI(BB, Insert, DL, TII.get(Opcode))
unsigned AMDGPUInstructionSelector::getVALUOpcode(const MachineInstr &I) const {
   const MachineRegisterInfo &MRI = MF->getRegInfo();
   unsigned Size0 = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
   switch (I.getOpcode()) {
   default: break;
   case TargetOpcode::G_FPTOUI:
     if (Size0 == 32 &&
         RBI.getSizeInBits(I.getOperand(1).getReg(), MRI, TRI) == 32)
       return AMDGPU::V_CVT_U32_F32_e64;
+  case TargetOpcode::G_INTRINSIC:
+    switch (I.getOperand(1).getIntrinsicID()) {
+      default: break;
+      case Intrinsic::amdgcn_cvt_pkrtz:
+        return AMDGPU::V_CVT_PKRTZ_F16_F32_e64;
+    }
     break;
   case TargetOpcode::G_OR:
     if (Size0 == 32)
       return AMDGPU::V_OR_B32_e64;
     break;
   }
   return AMDGPU::INSTRUCTION_LIST_END;
 }
bool AMDGPUInstructionSelector::selectSimpleVALU(MachineInstr &I) const {
   MachineFunction *MF = BB->getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();
   const DebugLoc &DL = I.getDebugLoc();
   unsigned Opcode = getVALUOpcode(I);
   if (Opcode == AMDGPU::INSTRUCTION_LIST_END)
     return false;
 
   const MCInstrDesc &Desc = TII.get(Opcode);
+  unsigned OpIdx = 0;
+  if (I.getOperand(OpIdx).isIntrinsicID())
+    ++OpIdx;
+
   MachineInstrBuilder VALU =
-      BuildMI(*BB, &I, DL, Desc, I.getOperand(0).getReg());
-  for (unsigned i = 1, OpIdx = 1, e = Desc.NumOperands; i != e; ++i) {
+      BuildMI(*BB, &I, DL, Desc, I.getOperand(OpIdx++).getReg());
+  if (I.getOperand(OpIdx).isIntrinsicID())
+    ++OpIdx;
+  for (unsigned i = 1, e = Desc.NumOperands; i != e; ++i) {
     int RegClassID = Desc.OpInfo[i].RegClass;
     if (RegClassID == -1) {
       // Input / Output modifiers
       VALU.addImm(0);
       continue;
     }
 
     const TargetRegisterClass *RC = TRI.getRegClass(RegClassID);
bool AMDGPUInstructionSelector::select(MachineInstr &I,
   case TargetOpcode::G_ADD:
     return selectG_ADD(I);
   case TargetOpcode::G_BITCAST:
     return selectCOPY(I);
   case TargetOpcode::G_CONSTANT:
     return selectG_CONSTANT(I);
   case TargetOpcode::G_GEP:
     return selectG_GEP(I);
+  case TargetOpcode::G_INTRINSIC:
+    return selectG_INTRINSIC(I);
   case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
     return selectG_INTRINSIC_W_SIDE_EFFECTS(I);
   case TargetOpcode::G_LOAD:
     return selectG_LOAD(I);
   case TargetOpcode::G_STORE:
     return selectG_STORE(I);
   }
   return false;
 }

test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir

+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+
+--- |
+  define void @cvt_pkrtz(i32 addrspace(1)* %global0) { ret void }
+
+  declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #0
+
+  attributes #0 = { readnone speculatable }
+...
+---
+
+name:            cvt_pkrtz
+legalized:       true
+regBankSelected: true
+
+# GCN-LABEL: name: cvt_pkrtz
+body: |
+  bb.0:
+    liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:vgpr(s32) = COPY $vgpr0
+    %2:vgpr(s32) = COPY $vgpr1
+    %3:vgpr(s64) = COPY $vgpr3_vgpr4
+
+    ; cvt_pkrtz vs
+    ; GCN: V_CVT_PKRTZ_F16_F32_e64
+    %4:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %1, %0
+
+    ; cvt_pkrtz sv
+    ; GCN: V_CVT_PKRTZ_F16_F32_e64
+    %5:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
+
+    ; cvt_pkrtz vv
+    ; GCN: V_CVT_PKRTZ_F16_F32_e64
+    %6:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %1, %2
+
+    %7:vgpr(s32) = G_BITCAST %4
+    %8:vgpr(s32) = G_BITCAST %5
+    %9:vgpr(s32) = G_BITCAST %6
+    G_STORE %7, %3 :: (store 4 into %ir.global0)
+    G_STORE %8, %3 :: (store 4 into %ir.global0)
+    G_STORE %9, %3 :: (store 4 into %ir.global0)
+...
+---