AMDGPU/GlobalISel: Implement select() for 32-bit G_FPTOUI

[nhaehnle]

One bikeshed, apart of that LGTM.

test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

20–26

I personally find the check lines easy to miss when they're indented like that and would prefer them to start at column 0. Admittedly I haven't checked the style elsewhere in LLVM.

[tstellar]

Rewrote the pactch to use the TableGen'd instruction selector.

[tstellar]

test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

20–26

YAML syntax does not allow this unfortunately.

[nhaehnle]

Looks reasonable.

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

622–624

I assume the intention is to make this the default as soon as it works for all?

[tstellar]

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

622–624

Yes, once I have a testing baseline, and it doesn't cause regressions, I will make it default.

[arsenm]

test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

20–26

I've just been using update_mir_test_checks for all of these global isel tests

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

 
 unsigned AMDGPUInstructionSelector::getVALUOpcode(const MachineInstr &I) const {
   const MachineBasicBlock *BB = I.getParent();
   const MachineFunction *MF = BB->getParent();
   const MachineRegisterInfo &MRI = MF->getRegInfo();
   unsigned Size0 = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
   switch (I.getOpcode()) {
   default: break;
+  case TargetOpcode::G_FPTOUI:
+    if (Size0 == 32 &&
+        RBI.getSizeInBits(I.getOperand(1).getReg(), MRI, TRI) == 32)
+      return AMDGPU::V_CVT_U32_F32_e64;
+    break;
   case TargetOpcode::G_OR:
     if (Size0 == 32)
       return AMDGPU::V_OR_B32_e64;
     break;
   }
   return AMDGPU::INSTRUCTION_LIST_END;
 }
 
bool AMDGPUInstructionSelector::selectSimpleVALU(MachineInstr &I) const {
   if (Opcode == AMDGPU::INSTRUCTION_LIST_END)
     return false;
 
   const MCInstrDesc &Desc = TII.get(Opcode);
   MachineInstrBuilder VALU =
       BuildMI(*BB, &I, DL, Desc, I.getOperand(0).getReg());
   for (unsigned i = 1, OpIdx = 1, e = Desc.NumOperands; i != e; ++i) {
     int RegClassID = Desc.OpInfo[i].RegClass;
-    if (RegClassID == -1)
+    if (RegClassID == -1) {
+      // Input / Output modifiers
+      VALU.addImm(0);
       continue;
+    }
 
     const TargetRegisterClass *RC = TRI.getRegClass(RegClassID);
     const MachineOperand &MO = I.getOperand(OpIdx++);
     if (!RC->isAllocatable()) {
       // constrainSelectedInstRegOperands() cannot handle non-allocatble register
       // classes like VS_*, so we need to constrain those registers manually.
       const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI);
       unsigned Size = RBI.getSizeInBits(MO.getReg(), MRI, TRI);
bool AMDGPUInstructionSelector::select(MachineInstr &I,
                                        CodeGenCoverage &CoverageInfo) const {
 
   if (!isPreISelGenericOpcode(I.getOpcode()))
     return true;
 
   switch (I.getOpcode()) {
   default:
     break;
+  case TargetOpcode::G_FPTOUI:
   case TargetOpcode::G_OR:
     return selectSimple(I);
   case TargetOpcode::G_ADD:
     return selectG_ADD(I);
   case TargetOpcode::G_BITCAST:
     return selectCOPY(I);
   case TargetOpcode::G_CONSTANT:
     return selectG_CONSTANT(I);
   case TargetOpcode::G_GEP:
     return selectG_GEP(I);

test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+
+--- |
+  define amdgpu_kernel void @fptoui(i32 addrspace(1)* %global0) {ret void}
+...
+---
+
+name:            fptoui
+legalized:       true
+regBankSelected: true
+
+# GCN-LABEL: name: fptoui
+body: |
+  bb.0:
+    liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:vgpr(s32) = COPY $vgpr0
+    %2:vgpr(s64) = COPY $vgpr3_vgpr4
+
+    ; fptoui s
+    ; GCN: V_CVT_U32_F32_e64
+    %3:vgpr(s32) = G_FPTOUI %0
+
+    ; fptoui v
+    ; GCN: V_CVT_U32_F32_e64
+    %4:vgpr(s32) = G_FPTOUI %1
+
+    G_STORE %3, %2 :: (store 4 into %ir.global0)
+    G_STORE %4, %2 :: (store 4 into %ir.global0)
+...
+---