AMDGPU/GlobalISel: Implement select() for 32-bit G_FPTOUI

[nhaehnle]

One bikeshed, apart of that LGTM.

test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

20–26 ↗

(On Diff #143312)

I personally find the check lines easy to miss when they're indented like that and would prefer them to start at column 0. Admittedly I haven't checked the style elsewhere in LLVM.

[tstellar]

Rewrote the pactch to use the TableGen'd instruction selector.

[tstellar]

test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

20–26 ↗

(On Diff #143312)

YAML syntax does not allow this unfortunately.

[nhaehnle]

Looks reasonable.

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

535–537 ↗

(On Diff #143676)

I assume the intention is to make this the default as soon as it works for all?

[tstellar]

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

535–537 ↗

(On Diff #143676)

Yes, once I have a testing baseline, and it doesn't cause regressions, I will make it default.

[arsenm]

test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

20–26 ↗

(On Diff #143312)

I've just been using update_mir_test_checks for all of these global isel tests

llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td

 
 include "AMDGPU.td"
 
 def sd_vsrc0 : ComplexPattern<i32, 1, "">;
 def gi_vsrc0 :
     GIComplexOperandMatcher<s32, "selectVSRC0">,
     GIComplexPatternEquiv<sd_vsrc0>;
 
+def gi_vop3mods0 :
+    GIComplexOperandMatcher<s32, "selectVOP3Mods0">,
+    GIComplexPatternEquiv<VOP3Mods0>;
+
 class GISelSop2Pat <
   SDPatternOperator node,
   Instruction inst,
   ValueType dst_vt,
   ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
 
   (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
   (inst src0_vt:$src0, src1_vt:$src1)

llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.h

void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
   bool selectG_LOAD(MachineInstr &I) const;
   bool selectG_STORE(MachineInstr &I) const;
 
   InstructionSelector::ComplexRendererFns
   selectVSRC0(MachineOperand &Root) const;
 
+  InstructionSelector::ComplexRendererFns
+  selectVOP3Mods0(MachineOperand &Root) const;
+
   const SIInstrInfo &TII;
   const SIRegisterInfo &TRI;
   const AMDGPURegisterBankInfo &RBI;
   const AMDGPUTargetMachine &TM;
   const SISubtarget &STI;
   bool EnableLateStructurizeCFG;
 #define GET_GLOBALISEL_PREDICATES_DECL
 #include "AMDGPUGenGlobalISel.inc"

llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

bool AMDGPUInstructionSelector::select(MachineInstr &I,
                                        CodeGenCoverage &CoverageInfo) const {
 
   if (!isPreISelGenericOpcode(I.getOpcode()))
     return true;
 
   switch (I.getOpcode()) {
   default:
     break;
+  case TargetOpcode::G_FPTOUI:
   case TargetOpcode::G_OR:
     return selectImpl(I, CoverageInfo);
   case TargetOpcode::G_ADD:
     return selectG_ADD(I);
   case TargetOpcode::G_BITCAST:
     return selectCOPY(I);
   case TargetOpcode::G_CONSTANT:
     return selectG_CONSTANT(I);

 /// This will select either an SGPR or VGPR operand and will save us from
 /// having to write an extra tablegen pattern.
 InstructionSelector::ComplexRendererFns
 AMDGPUInstructionSelector::selectVSRC0(MachineOperand &Root) const {
   return {{
       [=](MachineInstrBuilder &MIB) { MIB.add(Root); }
   }};
 }
+
+InstructionSelector::ComplexRendererFns
+AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const {
+  return {{
+      [=](MachineInstrBuilder &MIB) { MIB.add(Root); },
+      [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // src0_mods
+      [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
+      [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }  // omod
+  }};
+}

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

+# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+
+--- |
+  define amdgpu_kernel void @fptoui(i32 addrspace(1)* %global0) {ret void}
+...
+---
+
+name:            fptoui
+legalized:       true
+regBankSelected: true
+
+# GCN-LABEL: name: fptoui
+body: |
+  bb.0:
+    liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
+
+    ; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+    %0:sgpr(s32) = COPY $sgpr0
+
+    ; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr0
+
+    %2:vgpr(s64) = COPY $vgpr3_vgpr4
+
+    ; fptoui s
+    ; GCN: V_CVT_U32_F32_e64 0, [[SGPR]], 0, 0
+    %3:vgpr(s32) = G_FPTOUI %0
+
+    ; fptoui v
+    ; GCN: V_CVT_U32_F32_e64 0, [[VGPR]], 0, 0
+    %4:vgpr(s32) = G_FPTOUI %1
+
+    G_STORE %3, %2 :: (store 4 into %ir.global0)
+    G_STORE %4, %2 :: (store 4 into %ir.global0)
+...
+---