AMDGPU/GlobalISel: Implement select() for G_BITCAST s32 <--> <2 x s16>

[nhaehnle]

LGTM

[tstellar]

Simplify code by using a new TargetRegisterInfo callback.

lib/Target/AMDGPU/AMDGPUInstructionSelector.h

struct GEPInfo {
     const MachineInstr &GEP;
     SmallVector<unsigned, 2> SgprParts;
     SmallVector<unsigned, 2> VgprParts;
     int64_t Imm;
     GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
   };
 
   MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
+  bool selectCOPY(MachineInstr &I) const;
   bool selectG_CONSTANT(MachineInstr &I) const;
   bool selectG_ADD(MachineInstr &I) const;
   bool selectG_GEP(MachineInstr &I) const;
   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
   bool selectG_LOAD(MachineInstr &I) const;

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

 
 using namespace llvm;
 
 AMDGPUInstructionSelector::AMDGPUInstructionSelector(
     const SISubtarget &STI, const AMDGPURegisterBankInfo &RBI)
     : InstructionSelector(), TII(*STI.getInstrInfo()),
       TRI(*STI.getRegisterInfo()), RBI(RBI), AMDGPUASI(STI.getAMDGPUAS()) {}
 
+bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
+  MachineBasicBlock *BB = I.getParent();
+  MachineFunction *MF = BB->getParent();
+  MachineRegisterInfo &MRI = MF->getRegInfo();
+  I.setDesc(TII.get(TargetOpcode::COPY));
+  unsigned Size = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
+  for (const MachineOperand &MO : I.operands()) {
+    if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
+      continue;
+    const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI);
+    if (!OpBank)
+      continue;
+
+    const TargetRegisterClass *RC;
+    if (OpBank->getID() == AMDGPU::SGPRRegBankID) {
+      RC = Size == 32 ? &AMDGPU::SGPR_32RegClass : &AMDGPU::SReg_64RegClass;
+    } else {
+      assert(OpBank->getID() == AMDGPU::VGPRRegBankID);
+      RC = Size == 32 ? &AMDGPU::VGPR_32RegClass : &AMDGPU::VReg_64RegClass;
+    }
+    RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
+  }
+  return true;
+}
+
 MachineOperand
 AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
                                            unsigned SubIdx) const {
 
   MachineInstr *MI = MO.getParent();
   MachineBasicBlock *BB = MO.getParent()->getParent();
   MachineFunction *MF = BB->getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();
bool AMDGPUInstructionSelector::select(MachineInstr &I,
 
   switch (I.getOpcode()) {
   default:
     break;
   case TargetOpcode::G_OR:
     return selectSimple(I);
   case TargetOpcode::G_ADD:
     return selectG_ADD(I);
+  case TargetOpcode::G_BITCAST:
+    return selectCOPY(I);
   case TargetOpcode::G_CONSTANT:
     return selectG_CONSTANT(I);
   case TargetOpcode::G_GEP:
     return selectG_GEP(I);
   case TargetOpcode::G_LOAD:
     return selectG_LOAD(I);
   case TargetOpcode::G_STORE:
     return selectG_STORE(I);
   }
   return false;
 }

test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir

+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
+
+--- |
+  define amdgpu_kernel void @bitcast(i32 addrspace(1)* %global0) {ret void}
+...
+---
+
+name:            bitcast
+legalized:       true
+regBankSelected: true
+
+# GCN-LABEL: name: bitcast
+# GCN: [[A:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+# GCN: [[B:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
+# GCN: FLAT_STORE_DWORD [[B]], [[A]]
+
+body: |
+  bb.0:
+    liveins: $sgpr0, $vgpr3_vgpr4
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s64) = COPY $vgpr3_vgpr4
+    %2:vgpr(<2 x s16>) = G_BITCAST %0
+    %3:vgpr(s32) = G_BITCAST %2
+    G_STORE %3, %1 :: (store 4 into %ir.global0)
+...
+---