AMDGPU: Legalize the operand of SI_INIT_M0

[nhaehnle]

Summary

This fixes a case where the argument to a sendmsg intrinsic
ends up in a VGPR, for whatever reason.

The underlying performance issue is that a multiplication that
can be an s_mul_i32 is instead needlessly generated as
v_mul_u32_u24, but this is not addressed by this patch.

Change-Id: I61fd4034314d5acdf6074632c30b65364dfa7328

[rampitec]

lib/Target/AMDGPU/SIInstrInfo.cpp

3303

Do not you want to return SRegs[0] here (after the loop) if SubRegs == 1 and if not move creation of DstReg after that? It will save some code duplication.

[nhaehnle]

lib/Target/AMDGPU/SIInstrInfo.cpp

3303

That's what I had at first, but it doesn't work because the loop uses RI.getSubRegFromChannel(i), and if the SrcReg is an SGPR32 this fails because it has no subregs...

This was apparently never noticed because so far, the function was only used for resource descriptors and samplers.

[rampitec]

LGTM

lib/Target/AMDGPU/SIInstrInfo.cpp

 
 unsigned SIInstrInfo::readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
                                          MachineRegisterInfo &MRI) const {
   const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
   const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC);
   unsigned DstReg = MRI.createVirtualRegister(SRC);
   unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32;
 
+  if (SubRegs == 1) {
+    BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
+            get(AMDGPU::V_READFIRSTLANE_B32), DstReg)
+        .addReg(SrcReg);
+    return DstReg;
+  }
+
   SmallVector<unsigned, 8> SRegs;
   for (unsigned i = 0; i < SubRegs; ++i) {
     unsigned SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
     BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
             get(AMDGPU::V_READFIRSTLANE_B32), SGPR)
         .addReg(SrcReg, 0, RI.getSubRegFromChannel(i));
     SRegs.push_back(SGPR);
   }
 
   MachineInstrBuilder MIB =
       BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
               get(AMDGPU::REG_SEQUENCE), DstReg);
   for (unsigned i = 0; i < SubRegs; ++i) {
     MIB.addReg(SRegs[i]);
     MIB.addImm(RI.getSubRegFromChannel(i));
   }
   return DstReg;
if (MI.getOpcode() == AMDGPU::INSERT_SUBREG) {
     if (DstRC != Src0RC) {
       MachineBasicBlock *MBB = MI.getParent();
       MachineOperand &Op = MI.getOperand(1);
       legalizeGenericOperand(*MBB, MI, DstRC, Op, MRI, MI.getDebugLoc());
     }
     return;
   }
 
+  // Legalize SI_INIT_M0
+  if (MI.getOpcode() == AMDGPU::SI_INIT_M0) {
+    MachineOperand &Src = MI.getOperand(0);
+    if (Src.isReg() && RI.hasVGPRs(MRI.getRegClass(Src.getReg())))
+      Src.setReg(readlaneVGPRToSGPR(Src.getReg(), MI, MRI));
+    return;
+  }
+
   // Legalize MIMG and MUBUF/MTBUF for shaders.
   //
   // Shaders only generate MUBUF/MTBUF instructions via intrinsics or via
   // scratch memory access. In both cases, the legalization never involves
   // conversion to the addr64 form.
   if (isMIMG(MI) ||
       (AMDGPU::isShader(MF.getFunction().getCallingConv()) &&
        (isMUBUF(MI) || isMTBUF(MI)))) {

test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.ll

 ; GCN-NOT: s_mov_b32 m0
 ; GCN: s_sendmsghalt sendmsg(MSG_GS_DONE, GS_OP_NOP)
 define amdgpu_kernel void @test_gs_done_halt() {
 body:
   call void @llvm.amdgcn.s.sendmsghalt(i32 3, i32 0)
   ret void
 }
 
+; TODO: This should use s_mul_i32 instead of v_mul_u32_u24 + v_readfirstlane!
+;
+; GCN-LABEL: {{^}}test_mul24:
+; GCN: v_mul_u32_u24_e32
+; GCN: v_readfirstlane_b32
+; GCN: s_mov_b32 m0,
+; GCN: s_sendmsg sendmsg(MSG_INTERRUPT)
+define amdgpu_gs void @test_mul24(i32 inreg %arg) {
+body:
+  %tmp1 = and i32 %arg, 511
+  %tmp2 = mul nuw nsw i32 %tmp1, 12288
+  call void @llvm.amdgcn.s.sendmsg(i32 1, i32 %tmp2)
+  ret void
+}
+
 declare void @llvm.amdgcn.s.sendmsg(i32, i32) #0
 declare void @llvm.amdgcn.s.sendmsghalt(i32, i32) #0
 
 attributes #0 = { nounwind }