[mips] Implement GetWriteFlag() for mips

[mstojanovic]

Summary

The read/write flag is set by manually decoding the instruction that caused the exception. It is implemented this way because the the cause register which contains the needed flag was removed from the signal context structure which the user handler receives from the kernel.

[sdardis]

lib/sanitizer_common/sanitizer_linux.cc

1741–1742

Use uint32_t here.

1753

You need to add s(w|d)(l|r) under an #ifdef __mips_isa_rev < 6 clause.

1763

You need to add l(w|d)(l|r) under an #ifdef __mips_isa_rev < 6 clause.

1763

You may also want to add lwpc and lwupc to this list as well, but they are only for MIPSR6.

test/sanitizer_common/TestCases/Posix/illegal_read_test.cc

12

Add:

return 0;

here.

test/sanitizer_common/TestCases/Posix/illegal_write_test.cc

11

Add:

return 0;

here.

[mstojanovic]

Comments addressed.

[sdardis]

lib/sanitizer_common/sanitizer_linux.cc

1739

This should be:

__mips__

not __mips64 as asan can be built for MIPS32.

1744

This should be (uint32_t *) not (long *).

1747

FIXME: Add support for FPU, microMIPS, DSP, MSA memory instructions.

[mstojanovic]

Fixed macro and types, added a comment.

[sdardis]

LGTM. Keep on eye on the buildbots when you commit this in case there are sanitizer implementations can't distinguish between illegal reads and writes.

lib/sanitizer_common/sanitizer_linux.cc

#elif SANITIZER_OPENBSD
   uptr err = ucontext->sc_err;
 #elif SANITIZER_SOLARIS && defined(__i386__)
   const int Err = 13;
   uptr err = ucontext->uc_mcontext.gregs[Err];
 #else
   uptr err = ucontext->uc_mcontext.gregs[REG_ERR];
 #endif // SANITIZER_FREEBSD
   return err & PF_WRITE ? WRITE : READ;
+#elif defined(__mips__)
+  uint32_t *exception_source;
+  uint32_t faulty_instruction;
+  uint32_t op_code;
+
+  exception_source = (uint32_t *)ucontext->uc_mcontext.pc;
+  faulty_instruction = (uint32_t)(*exception_source);
+
+  op_code = (faulty_instruction >> 26) & 0x3f;
+
+  // FIXME: Add support for FPU, microMIPS, DSP, MSA memory instructions.
+  switch (op_code) {
+    case 0x28:  // sb
+    case 0x29:  // sh
+    case 0x2b:  // sw
+    case 0x3f:  // sd
+#if __mips_isa_rev < 6
+    case 0x2c:  // sdl
+    case 0x2d:  // sdr
+    case 0x2a:  // swl
+    case 0x2e:  // swr
+#endif
+      return SignalContext::WRITE;
+
+    case 0x20:  // lb
+    case 0x24:  // lbu
+    case 0x21:  // lh
+    case 0x25:  // lhu
+    case 0x23:  // lw
+    case 0x27:  // lwu
+    case 0x37:  // ld
+#if __mips_isa_rev < 6
+    case 0x1a:  // ldl
+    case 0x1b:  // ldr
+    case 0x22:  // lwl
+    case 0x26:  // lwr
+#endif
+      return SignalContext::READ;
+#if __mips_isa_rev == 6
+    case 0x3b:  // pcrel
+      op_code = (faulty_instruction >> 19) & 0x3;
+      switch (op_code) {
+        case 0x1:  // lwpc
+        case 0x2:  // lwupc
+          return SignalContext::READ;
+      }
+#endif
+  }
+  return SignalContext::UNKNOWN;
 #elif defined(__arm__)
   static const uptr FSR_WRITE = 1U << 11;
   uptr fsr = ucontext->uc_mcontext.error_code;
   return fsr & FSR_WRITE ? WRITE : READ;
 #elif defined(__aarch64__)
   static const u64 ESR_ELx_WNR = 1U << 6;
   u64 esr;
   if (!Aarch64GetESR(ucontext, &esr)) return UNKNOWN;

test/sanitizer_common/TestCases/Posix/illegal_read_test.cc

+// Test that there was an illegal READ memory access.
+// RUN: %clangxx -O0 %s -o %t && not %run %t 2>&1 | FileCheck %s
+
+// REQUIRES: stable-runtime
+
+volatile int *null = 0;
+volatile int a;
+
+int main(int argc, char **argv) {
+  a = *null;
+  return 0;
+}
+
+// CHECK: The signal is caused by a READ memory access.

test/sanitizer_common/TestCases/Posix/illegal_write_test.cc

+// Test that there was an illegal WRITE memory access.
+// RUN: %clangxx -O0 %s -o %t && not %run %t 2>&1 | FileCheck %s
+
+// REQUIRES: stable-runtime
+
+volatile int *null = 0;
+
+int main(int argc, char **argv) {
+  *null = 0;
+  return 0;
+}
+
+// CHECK: The signal is caused by a WRITE memory access.