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[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0
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Authored by sabuasal on Apr 12 2018, 11:28 AM.

Details

Summary

GCC compresses the pseudo instruction "mv rd, rs", which is an alias of
"addi rd, rs, 0", to "c.mv rd, rs".

In LLVM we rely on the canonical MC instruction (MCInst) to do our compression
checks and since there is no rule to compress "addi rd, rs, 0" --> "c.mv
rd, rs" we lose this compression opportunity to gcc.

In this patch we fix that by adding an addi to c.mv compression pattern, the
instruction "mv rd, rs" will be compressed to "c.mv rd, rs" just like
gcc does.

Patch by Zhaoshi Zheng (zzheng) and Sameer (sabuasal).

Diff Detail

Repository
rL LLVM

Event Timeline

sabuasal created this revision.Apr 12 2018, 11:28 AM
sabuasal edited the summary of this revision. (Show Details)Apr 12 2018, 11:36 AM
asb accepted this revision.Apr 12 2018, 12:13 PM

Thanks! Looks good to me.

This revision is now accepted and ready to land.Apr 12 2018, 12:13 PM
This revision was automatically updated to reflect the committed changes.