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[AMDGPU] Ensure there are enough registers for wave dispatch

Authored by tpr on Apr 10 2018, 1:30 PM.



This fixes the number of SGPRs and VGPRs in the *_RSRC1 register to
allow for registers set up in wave dispatch, even if those registers are
not used in the shader.

Change-Id: I6575f0e0d2a528d1319d0b289f0ebe4510fa5771

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Event Timeline

tpr created this revision.Apr 10 2018, 1:30 PM
nhaehnle accepted this revision.Apr 11 2018, 12:48 AM

That seems reasonable.

This revision is now accepted and ready to land.Apr 11 2018, 12:48 AM
This revision was automatically updated to reflect the committed changes.

I think this is the wrong way to solve this. I know I have a patch where I started to fix this before. I don’t like inspecting the IR types in the AsmPrinter to determine the used number of registers. The way this is determined is more complicated than the type size in bits, so this really needs to determine this from what legalization decided to do.

Arguably we could also just report the number used by the shader and it’s the runtime’s responsibility to round up from the number of registers used, but since we are sort of just emitting the raw config register value that doesn’t really work

t-tye added a comment.Apr 12 2018, 2:40 PM

I believe the metadata does have the actual (ie non-granulated rounded up value) register count. So the runtime could access the information from there.