AMDGPU: Remove max_scratch_backing_memory_byte_size from kernel header

[kzhuravl]

Summary

1. Remove max_scratch_backing_memory_byte_size from kernel header
2. Make it a reserved field
3. Ignore it while parsing assembly for backwards compatibility
4. Bump up minor version of kernel header

[artem.tamazov]

Is it so that max_scratch_backing_memory_byte_size is not needed at all for Gfx7-9?

[kzhuravl]

In D45452#1062203, @artem.tamazov wrote:

Is it so that max_scratch_backing_memory_byte_size is not needed at all for Gfx7-9?

Yes.

[artem.tamazov]

LGTM

lib/Target/AMDGPU/AMDKernelCodeT.h

typedef struct amd_kernel_code_s {
 
   /// Range of bytes to consider prefetching expressed as an offset
   /// and size. The offset is from the start (possibly negative) of
   /// amd_kernel_code_t object. Set both to 0 if no prefetch
   /// information is available.
   int64_t kernel_code_prefetch_byte_offset;
   uint64_t kernel_code_prefetch_byte_size;
 
-  /// Number of bytes of scratch backing memory required for full
-  /// occupancy of target chip. This takes into account the number of
-  /// bytes of scratch per work-item, the wavefront size, the maximum
-  /// number of wavefronts per CU, and the number of CUs. This is an
-  /// upper limit on scratch. If the grid being dispatched is small it
-  /// may only need less than this. If the kernel uses no scratch, or
-  /// the Finalizer has not computed this value, it must be 0.
-  uint64_t max_scratch_backing_memory_byte_size;
+  /// Reserved. Must be 0.
+  uint64_t reserved0;
 
   /// Shader program settings for CS. Contains COMPUTE_PGM_RSRC1 and
   /// COMPUTE_PGM_RSRC2 registers.
   uint64_t compute_pgm_resource_registers;
 
   /// Code properties. See amd_code_property_mask_t for a full list of
   /// properties.
   uint32_t code_properties;

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
 
   getTargetStreamer().EmitDirectiveHSACodeObjectISA(Major, Minor, Stepping,
                                                     VendorName, ArchName);
   return false;
 }
 
 bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
                                                amd_kernel_code_t &Header) {
+  // max_scratch_backing_memory_byte_size is deprecated. Ignore it while parsing
+  // assembly for backwards compatibility.
+  if (ID == "max_scratch_backing_memory_byte_size") {
+    Parser.eatToEndOfStatement();
+    return false;
+  }
+
   SmallString<40> ErrStr;
   raw_svector_ostream Err(ErrStr);
   if (!parseAmdKernelCodeField(ID, getParser(), Header, Err)) {
     return TokError(Err.str());
   }
   Lex();
   return false;
 }

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 
 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
                                const FeatureBitset &Features) {
   IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(Features);
 
   memset(&Header, 0, sizeof(Header));
 
   Header.amd_kernel_code_version_major = 1;
-  Header.amd_kernel_code_version_minor = 1;
+  Header.amd_kernel_code_version_minor = 2;
   Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
   Header.amd_machine_version_major = ISA.Major;
   Header.amd_machine_version_minor = ISA.Minor;
   Header.amd_machine_version_stepping = ISA.Stepping;
   Header.kernel_code_entry_byte_offset = sizeof(Header);
   // wavefront_size is specified as a power of 2: 2^6 = 64 threads.
   Header.wavefront_size = 6;
 

lib/Target/AMDGPU/Utils/AMDKernelCodeTInfo.h

 FIELD2(amd_code_version_minor,        kernel_code_version_minor,  amd_kernel_code_version_minor),
 FIELD2(amd_machine_kind,              machine_kind,               amd_machine_kind),
 FIELD2(amd_machine_version_major,     machine_version_major,      amd_machine_version_major),
 FIELD2(amd_machine_version_minor,     machine_version_minor,      amd_machine_version_minor),
 FIELD2(amd_machine_version_stepping,  machine_version_stepping,   amd_machine_version_stepping),
 
 FIELD(kernel_code_entry_byte_offset),
 FIELD(kernel_code_prefetch_byte_size),
-FIELD(max_scratch_backing_memory_byte_size),
 
 COMPPGM1(granulated_workitem_vgpr_count,  compute_pgm_rsrc1_vgprs,          VGPRS),
 COMPPGM1(granulated_wavefront_sgpr_count, compute_pgm_rsrc1_sgprs,          SGPRS),
 COMPPGM1(priority,                        compute_pgm_rsrc1_priority,       PRIORITY),
 COMPPGM1(float_mode,                      compute_pgm_rsrc1_float_mode,     FLOAT_MODE), // TODO: split float_mode
 COMPPGM1(priv,                            compute_pgm_rsrc1_priv,           PRIV),
 COMPPGM1(enable_dx10_clamp,               compute_pgm_rsrc1_dx10_clamp,     DX10_CLAMP),
 COMPPGM1(debug_mode,                      compute_pgm_rsrc1_debug_mode,     DEBUG_MODE),

test/MC/AMDGPU/hsa-exp.s

 // Make sure a line with whitespace won't break anything:
 
   workitem_vgpr_count = 16
 .end_amd_kernel_code_t
 
 // ASM-LABEL: {{^}}amd_kernel_code_t_minimal:
 // ASM: .amd_kernel_code_t
 // ASM: amd_code_version_major = 7
-// ASM: amd_code_version_minor = 1
+// ASM: amd_code_version_minor = 2
 // ASM: amd_machine_kind = 1
 // ASM: amd_machine_version_major = 7
 // ASM: amd_machine_version_minor = 0
 // ASM: amd_machine_version_stepping = 0
 // ASM: kernel_code_entry_byte_offset = 256
 // ASM: kernel_code_prefetch_byte_size = 0
-// ASM: max_scratch_backing_memory_byte_size = 0
 // ASM: granulated_workitem_vgpr_count = 1
 // ASM: granulated_wavefront_sgpr_count = 1
 // ASM: priority = 0
 // ASM: float_mode = 0
 // ASM: priv = 0
 // ASM: enable_dx10_clamp = 0
 // ASM: debug_mode = 0
 // ASM: enable_ieee_mode = 0

test/MC/AMDGPU/hsa.s

 // ASM: amd_code_version_major = 100
 // ASM: amd_code_version_minor = 100
 // ASM: amd_machine_kind = 0
 // ASM: amd_machine_version_major = 5
 // ASM: amd_machine_version_minor = 5
 // ASM: amd_machine_version_stepping = 5
 // ASM: kernel_code_entry_byte_offset = 512
 // ASM: kernel_code_prefetch_byte_size = 1
-// ASM: max_scratch_backing_memory_byte_size = 1
 // ASM: granulated_workitem_vgpr_count = 1
 // ASM: granulated_wavefront_sgpr_count = 1
 // ASM: priority = 1
 // ASM: float_mode = 1
 // ASM: priv = 1
 // ASM: enable_dx10_clamp = 1
 // ASM: debug_mode = 1
 // ASM: enable_ieee_mode = 1

 // Make sure a line with whitespace won't break anything:
 
   workitem_vgpr_count = 16
 .end_amd_kernel_code_t
 
 // ASM-LABEL: {{^}}amd_kernel_code_t_minimal:
 // ASM: .amd_kernel_code_t
 // ASM: amd_code_version_major = 1
-// ASM: amd_code_version_minor = 1
+// ASM: amd_code_version_minor = 2
 // ASM: amd_machine_kind = 1
 // ASM: amd_machine_version_major = 7
 // ASM: amd_machine_version_minor = 0
 // ASM: amd_machine_version_stepping = 0
 // ASM: kernel_code_entry_byte_offset = 256
 // ASM: kernel_code_prefetch_byte_size = 0
-// ASM: max_scratch_backing_memory_byte_size = 0
 // ASM: granulated_workitem_vgpr_count = 1
 // ASM: granulated_wavefront_sgpr_count = 1
 // ASM: priority = 0
 // ASM: float_mode = 0
 // ASM: priv = 0
 // ASM: enable_dx10_clamp = 0
 // ASM: debug_mode = 0
 // ASM: enable_ieee_mode = 0