[AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32
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Authored by dp on Apr 9 2018, 9:37 AM.

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rL LLVM
dp created this revision.Apr 9 2018, 9:37 AM
artem.tamazov accepted this revision.Apr 9 2018, 11:56 AM

Looks good.

This revision is now accepted and ready to land.Apr 9 2018, 11:56 AM
dp updated this revision to Diff 142020.Apr 11 2018, 8:52 AM

This change breaks SDWA peepholer which started to produce code with undefined physical registers:

    • Bad machine code: Using an undefined physical register ***
  • function: select_v2f16
  • instruction: %70:vgpr_32 = V_CNDMASK_B32_sdwa 0, %42:vgpr_32, 0, %37:vgpr_32, 0, 5, 0, 5, 5, implicit $vcc, implicit $exec
  • operand 10: implicit $vcc

As a temporary solution I disabled SDWA peepholer for V_CNDMASK_B32.
I propose to integrate this patch as is and file a bug for this issue to be resolved separately.
Is this acceptable?

This revision was automatically updated to reflect the committed changes.