[DebugInfo] Convert intrinsic llvm.dbg.label to MachineInstr.

[HsiangKai]

Summary

In order to convert LLVM IR to MachineInstr, we need a new TargetOpcode,
DBG_LABEL, to 'lower' intrinsic llvm.dbg.label. The patch
creates this new TargetOpcode and convert intrinsic llvm.dbg.label to
MachineInstr through SelectionDAG.

In SelectionDAG, debug information is stored in SDDbgInfo. We create a
new data member of SDDbgInfo for labels and use the new data member,
SDDbgLabel, to create DBG_LABEL MachineInstr.

The new DBG_LABEL MachineInstr uses label metadata from LLVM IR as its
parameter. So, the backend could get metadata information of labels from
DBG_LABEL MachineInstr.

[aprantl]

Thanks, this looks mostly fine! Have you considered just allowing the DBG_VALUE MachineInstr to carry a DILabel insetad of just DILocalVariables? Would that simplify the code or make it harder to understand?

include/llvm/CodeGen/SelectionDAG.h

152 ↗

(On Diff #141241)

I suppose this depends on the language, but I'd expect most C++ functions to at most a handful of labels and usually zero. Perhaps use a SmallVector size of 1, 2, or 4, or even a std::vector?

[HsiangKai]

Update according to review comments.

[HsiangKai]

In D45341#1060380, @aprantl wrote:

Thanks, this looks mostly fine! Have you considered just allowing the DBG_VALUE MachineInstr to carry a DILabel insetad of just DILocalVariables? Would that simplify the code or make it harder to understand?

The formats of DBG_VALUE are

DBG_VALUE Reg, 0, DILocalVariable, DIExpression
DBG_VALUE FrameIndex, Imm, DILocalVariable, DIExpression
DBG_VALUE Imm, Imm, DILocalVariable, DIExpression

When processing DBG_VALUE, there are assumptions about these operands. Take a snippet from lib/CodeGen/PrologEpilogInserter.cpp as an example,

if (MI.isDebugValue()) {

assert(i == 0 && "Frame indices can only appear as the first "
                 "operand of a DBG_VALUE machine instruction");
unsigned Reg;
int64_t Offset =
    TFI->getFrameIndexReference(Fn, MI.getOperand(0).getIndex(), Reg);
MI.getOperand(0).ChangeToRegister(Reg, false /*isDef*/);
auto *DIExpr = DIExpression::prepend(MI.getDebugExpression(),
                                     DIExpression::NoDeref, Offset);
MI.getOperand(3).setMetadata(DIExpr);
continue;

}

If we add the possibility of operand(0) as DILabel, it will complicate the implementation.

I think to create DBG_LABEL is easier to understand and easier to maintain.

[aprantl]

Okay, let's do a separate machine instruction then!

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

754 ↗

(On Diff #141990)

Again, the comment should be on the declaration, not the definition.

lib/CodeGen/SelectionDAG/InstrEmitter.h

116 ↗

(On Diff #141990)

don't repeat the name in the comment

lib/CodeGen/SelectionDAG/SDNodeDbgValue.h

118 ↗

(On Diff #141990)

Please don't repeat the class name in comments.

120 ↗

(On Diff #141990)

extra newline

130 ↗

(On Diff #141990)

///

133 ↗

(On Diff #141990)

///

136 ↗

(On Diff #141990)

///

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

918 ↗

(On Diff #141990)

perhaps use a range-based for?

931 ↗

(On Diff #141990)

Do you have test coverage for both paths?

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

7779 ↗

(On Diff #141990)

The comment should be on the function *declaration*, and not repeat the function name:
/// Add a dbg_label SDNode.

http://llvm.org/docs/CodingStandards.html#doxygen-use-in-documentation-comments

test/DebugInfo/Generic/debug-label-mi.ll

5 ↗

(On Diff #141990)

can you also check the !dbg attachment?

[aprantl]

test/DebugInfo/Generic/debug-label-mi.ll

27 ↗

(On Diff #141990)

you can reduce the size of the testcase by manually making all !dbg attachments of the other instructions point to the same location. That will make it more obvious what the relevant part of the test is.

[HsiangKai]

Update according to reviewers' comments.

[HsiangKai]

1. Use range-based for in lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp:918
2. Check !dbg attachment in the test case.

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

931 ↗

(On Diff #141990)

I will try to create test cases for both paths.

[aprantl]

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

915 ↗

(On Diff #142633)

/// This method handles the target-independent form
don't repeat the function name.

[HsiangKai]

• Update the test case.

[HsiangKai]

Add test case.

[HsiangKai]

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

931 ↗

(On Diff #141990)

Add test case 'test/DebugInfo/Generic/debug-label-opt.ll' for both paths.

llvm/trunk/include/llvm/CodeGen/MachineInstr.h

public:
   /// Return the debug variable referenced by
   /// this DBG_VALUE instruction.
   const DILocalVariable *getDebugVariable() const;
 
   /// Return the complex address expression referenced by
   /// this DBG_VALUE instruction.
   const DIExpression *getDebugExpression() const;
 
+  /// Return the debug label referenced by
+  /// this DBG_LABEL instruction.
+  const DILabel *getDebugLabel() const;
+
   /// Emit an error referring to the source location of this instruction.
   /// This should only be used for inline assembly that is somehow
   /// impossible to compile. Other errors should have been handled much
   /// earlier.
   ///
   /// If this method returns, the caller should try to recover from the error.
   void emitError(StringRef Msg) const;
 
public:
   bool isCFIInstruction() const {
     return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
   }
 
   // True if the instruction represents a position in the function.
   bool isPosition() const { return isLabel() || isCFIInstruction(); }
 
   bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
+  bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
+  bool isDebugInstr() const { return isDebugValue() || isDebugLabel(); }
 
   /// A DBG_VALUE is indirect iff the first operand is a register and
   /// the second operand is an immediate.
   bool isIndirectDebugValue() const {
     return isDebugValue()
       && getOperand(0).isReg()
       && getOperand(1).isImm();
   }
bool isMetaInstruction() const {
     default:
       return false;
     case TargetOpcode::IMPLICIT_DEF:
     case TargetOpcode::KILL:
     case TargetOpcode::CFI_INSTRUCTION:
     case TargetOpcode::EH_LABEL:
     case TargetOpcode::GC_LABEL:
     case TargetOpcode::DBG_VALUE:
+    case TargetOpcode::DBG_LABEL:
     case TargetOpcode::LIFETIME_START:
     case TargetOpcode::LIFETIME_END:
       return true;
     }
   }
 
   /// Return true if this is a transient instruction that is either very likely
   /// to be eliminated during register allocation (such as copy-like

llvm/trunk/include/llvm/CodeGen/SelectionDAG.h

 class GlobalValue;
 struct KnownBits;
 class LLVMContext;
 class MachineBasicBlock;
 class MachineConstantPoolValue;
 class MCSymbol;
 class OptimizationRemarkEmitter;
 class SDDbgValue;
+class SDDbgLabel;
 class SelectionDAG;
 class SelectionDAGTargetInfo;
 class TargetLibraryInfo;
 class TargetLowering;
 class TargetMachine;
 class TargetSubtargetInfo;
 class Value;
 

 /// parameters separately:  they may not have code generated for them, they
 /// should always go at the beginning of the function regardless of other code
 /// motion, and debug info for them is potentially useful even if the parameter
 /// is unused.  Right now only byval parameters are handled separately.
 class SDDbgInfo {
   BumpPtrAllocator Alloc;
   SmallVector<SDDbgValue*, 32> DbgValues;
   SmallVector<SDDbgValue*, 32> ByvalParmDbgValues;
+  SmallVector<SDDbgLabel*, 4> DbgLabels;
   using DbgValMapType = DenseMap<const SDNode *, SmallVector<SDDbgValue *, 2>>;
   DbgValMapType DbgValMap;
 
 public:
   SDDbgInfo() = default;
   SDDbgInfo(const SDDbgInfo &) = delete;
   SDDbgInfo &operator=(const SDDbgInfo &) = delete;
 
   void add(SDDbgValue *V, const SDNode *Node, bool isParameter) {
     if (isParameter) {
       ByvalParmDbgValues.push_back(V);
     } else     DbgValues.push_back(V);
     if (Node)
       DbgValMap[Node].push_back(V);
   }
 
+  void add(SDDbgLabel *L) {
+    DbgLabels.push_back(L);
+  }
+
   /// Invalidate all DbgValues attached to the node and remove
   /// it from the Node-to-DbgValues map.
   void erase(const SDNode *Node);
 
   void clear() {
     DbgValMap.clear();
     DbgValues.clear();
     ByvalParmDbgValues.clear();
+    DbgLabels.clear();
     Alloc.Reset();
   }
 
   BumpPtrAllocator &getAlloc() { return Alloc; }
 
   bool empty() const {
-    return DbgValues.empty() && ByvalParmDbgValues.empty();
+    return DbgValues.empty() && ByvalParmDbgValues.empty() && DbgLabels.empty();
   }
 
   ArrayRef<SDDbgValue*> getSDDbgValues(const SDNode *Node) {
     DbgValMapType::iterator I = DbgValMap.find(Node);
     if (I != DbgValMap.end())
       return I->second;
     return ArrayRef<SDDbgValue*>();
   }
 
   using DbgIterator = SmallVectorImpl<SDDbgValue*>::iterator;
+  using DbgLabelIterator = SmallVectorImpl<SDDbgLabel*>::iterator;
 
   DbgIterator DbgBegin() { return DbgValues.begin(); }
   DbgIterator DbgEnd()   { return DbgValues.end(); }
   DbgIterator ByvalParmDbgBegin() { return ByvalParmDbgValues.begin(); }
   DbgIterator ByvalParmDbgEnd()   { return ByvalParmDbgValues.end(); }
+  DbgLabelIterator DbgLabelBegin() { return DbgLabels.begin(); }
+  DbgLabelIterator DbgLabelEnd()   { return DbgLabels.end(); }
 };
 
 void checkForCycles(const SelectionDAG *DAG, bool force = false);
 
 /// This is used to represent a portion of an LLVM function in a low-level
 /// Data Dependence DAG representation suitable for instruction selection.
 /// This DAG is constructed as the first step of instruction selection in order
 /// to allow implementation of machine specific optimizations
class SelectionDAG {
 
   /// Pool allocation for machine-opcode SDNode operands.
   BumpPtrAllocator OperandAllocator;
   ArrayRecycler<SDUse> OperandRecycler;
 
   /// Pool allocation for misc. objects that are created once per SelectionDAG.
   BumpPtrAllocator Allocator;
 
-  /// Tracks dbg_value information through SDISel.
+  /// Tracks dbg_value and dbg_label information through SDISel.
   SDDbgInfo *DbgInfo;
 
   uint16_t NextPersistentId = 0;
 
 public:
   /// Clients of various APIs that cause global effects on
   /// the DAG can optionally implement this interface.  This allows the clients
   /// to handle the various sorts of updates that happen.
SDDbgValue *getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr,
                                     unsigned FI, const DebugLoc &DL,
                                     unsigned O);
 
   /// Creates a VReg SDDbgValue node.
   SDDbgValue *getVRegDbgValue(DIVariable *Var, DIExpression *Expr,
                               unsigned VReg, bool IsIndirect,
                               const DebugLoc &DL, unsigned O);
 
+  /// Creates a SDDbgLabel node.
+  SDDbgLabel *getDbgLabel(DILabel *Label, const DebugLoc &DL, unsigned O);
+
   /// Transfer debug values from one node to another, while optionally
   /// generating fragment expressions for split-up values. If \p InvalidateDbg
   /// is set, debug values are invalidated after they are transferred.
   void transferDbgValues(SDValue From, SDValue To, unsigned OffsetInBits = 0,
                          unsigned SizeInBits = 0, bool InvalidateDbg = true);
 
   /// Remove the specified node from the system. If any of its
   /// operands then becomes dead, remove them as well. Inform UpdateListener
static const fltSemantics &EVTToAPFloatSemantics(EVT VT) {
     case MVT::ppcf128: return APFloat::PPCDoubleDouble();
     }
   }
 
   /// Add a dbg_value SDNode. If SD is non-null that means the
   /// value is produced by SD.
   void AddDbgValue(SDDbgValue *DB, SDNode *SD, bool isParameter);
 
+  /// Add a dbg_label SDNode.
+  void AddDbgLabel(SDDbgLabel *DB);
+
   /// Get the debug values which reference the given SDNode.
   ArrayRef<SDDbgValue*> GetDbgValues(const SDNode* SD) {
     return DbgInfo->getSDDbgValues(SD);
   }
 
 public:
   /// Return true if there are any SDDbgValue nodes associated
   /// with this SelectionDAG.
   bool hasDebugValues() const { return !DbgInfo->empty(); }
 
   SDDbgInfo::DbgIterator DbgBegin() { return DbgInfo->DbgBegin(); }
   SDDbgInfo::DbgIterator DbgEnd()   { return DbgInfo->DbgEnd(); }
 
   SDDbgInfo::DbgIterator ByvalParmDbgBegin() {
     return DbgInfo->ByvalParmDbgBegin();
   }
 
   SDDbgInfo::DbgIterator ByvalParmDbgEnd()   {
     return DbgInfo->ByvalParmDbgEnd();
   }
 
+  SDDbgInfo::DbgLabelIterator DbgLabelBegin() {
+    return DbgInfo->DbgLabelBegin();
+  }
+  SDDbgInfo::DbgLabelIterator DbgLabelEnd() {
+    return DbgInfo->DbgLabelEnd();
+  }
+
   /// To be invoked on an SDNode that is slated to be erased. This
   /// function mirrors \c llvm::salvageDebugInfo.
   void salvageDebugInfo(SDNode &N);
 
   void dump() const;
 
   /// Create a stack temporary, suitable for holding the specified value type.
   /// If minAlign is specified, the slot size will have at least that alignment.

llvm/trunk/include/llvm/Support/TargetOpcodes.def

 /// virtual registers have been created for all the instructions, and it's
 /// only needed in cases where the register classes implied by the
 /// instructions are insufficient. It is emitted as a COPY MachineInstr.
   HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS)
 
 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
 HANDLE_TARGET_OPCODE(DBG_VALUE)
 
+/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic
+HANDLE_TARGET_OPCODE(DBG_LABEL)
+
 /// REG_SEQUENCE - This variadic instruction is used to form a register that
 /// represents a consecutive sequence of sub-registers. It's used as a
 /// register coalescing / allocation aid and must be eliminated before code
 /// emission.
 // In SDNode form, the first operand encodes the register class created by
 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
 // pair.  Once it has been lowered to a MachineInstr, the regclass operand
 // is no longer present.

llvm/trunk/include/llvm/Target/Target.td

def COPY_TO_REGCLASS : StandardPseudoInstruction {
   let isAsCheapAsAMove = 1;
 }
 def DBG_VALUE : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "DBG_VALUE";
   let hasSideEffects = 0;
 }
+def DBG_LABEL : StandardPseudoInstruction {
+  let OutOperandList = (outs);
+  let InOperandList = (ins unknown:$label);
+  let AsmString = "DBG_LABEL";
+  let hasSideEffects = 0;
+}
 def REG_SEQUENCE : StandardPseudoInstruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins unknown:$supersrc, variable_ops);
   let AsmString = "";
   let hasSideEffects = 0;
   let isAsCheapAsAMove = 1;
 }
 def COPY : StandardPseudoInstruction {

llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

static bool emitDebugValueComment(const MachineInstr *MI, AsmPrinter &AP) {
   if (MemLoc)
     OS << '+' << Offset << ']';
 
   // NOTE: Want this comment at start of line, don't emit with AddComment.
   AP.OutStreamer->emitRawComment(OS.str());
   return true;
 }
 
+/// This method handles the target-independent form of DBG_LABEL, returning
+/// true if it was able to do so.  A false return means the target will need
+/// to handle MI in EmitInstruction.
+static bool emitDebugLabelComment(const MachineInstr *MI, AsmPrinter &AP) {
+  if (MI->getNumOperands() != 1)
+    return false;
+
+  SmallString<128> Str;
+  raw_svector_ostream OS(Str);
+  OS << "DEBUG_LABEL: ";
+
+  const DILabel *V = MI->getDebugLabel();
+  if (auto *SP = dyn_cast<DISubprogram>(V->getScope())) {
+    StringRef Name = SP->getName();
+    if (!Name.empty())
+      OS << Name << ":";
+  }
+  OS << V->getName();
+
+  // NOTE: Want this comment at start of line, don't emit with AddComment.
+  AP.OutStreamer->emitRawComment(OS.str());
+  return true;
+}
+
 AsmPrinter::CFIMoveType AsmPrinter::needsCFIMoves() const {
   if (MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI &&
       MF->getFunction().needsUnwindTableEntry())
     return CFI_M_EH;
 
   if (MMI->hasDebugInfo())
     return CFI_M_Debug;
 
for (auto &MI : MBB) {
         EmitInlineAsm(&MI);
         break;
       case TargetOpcode::DBG_VALUE:
         if (isVerbose()) {
           if (!emitDebugValueComment(&MI, *this))
             EmitInstruction(&MI);
         }
         break;
+      case TargetOpcode::DBG_LABEL:
+        if (isVerbose()) {
+          if (!emitDebugLabelComment(&MI, *this))
+            EmitInstruction(&MI);
+        }
+        break;
       case TargetOpcode::IMPLICIT_DEF:
         if (isVerbose()) emitImplicitDef(&MI);
         break;
       case TargetOpcode::KILL:
         if (isVerbose()) emitKill(&MI, *this);
         break;
       default:
         EmitInstruction(&MI);

llvm/trunk/lib/CodeGen/MachineInstr.cpp

if (i + NumOps > OpIdx) {
         *GroupNo = Group;
       return i;
     }
     ++Group;
   }
   return -1;
 }
 
+const DILabel *MachineInstr::getDebugLabel() const {
+  assert(isDebugLabel() && "not a DBG_LABEL");
+  return cast<DILabel>(getOperand(0).getMetadata());
+}
+
 const DILocalVariable *MachineInstr::getDebugVariable() const {
   assert(isDebugValue() && "not a DBG_VALUE");
   return cast<DILocalVariable>(getOperand(2).getMetadata());
 }
 
 const DIExpression *MachineInstr::getDebugExpression() const {
   assert(isDebugValue() && "not a DBG_VALUE");
   return cast<DIExpression>(getOperand(3).getMetadata());
if (isDebugValue() && MO.isMetadata()) {
       if (DIV && !DIV->getName().empty())
         OS << "!\"" << DIV->getName() << '\"';
       else {
         LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
         unsigned TiedOperandIdx = getTiedOperandIdx(i);
         MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
                  ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
       }
+    } else if (isDebugLabel() && MO.isMetadata()) {
+      // Pretty print DBG_LABEL instructions.
+      auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
+      if (DIL && !DIL->getName().empty())
+        OS << "\"" << DIL->getName() << '\"';
+      else {
+        LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
+        unsigned TiedOperandIdx = getTiedOperandIdx(i);
+        MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
+                 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
+      }
     } else if (i == AsmDescOp && MO.isImm()) {
       // Pretty print the inline asm operand descriptor.
       OS << '$' << AsmOpCount++;
       unsigned Flag = MO.getImm();
       switch (InlineAsm::getKind(Flag)) {
       case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
       case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
       case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;

llvm/trunk/lib/CodeGen/PatchableFunction.cpp

static bool doesNotGeneratecode(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default: return false;
   case TargetOpcode::IMPLICIT_DEF:
   case TargetOpcode::KILL:
   case TargetOpcode::CFI_INSTRUCTION:
   case TargetOpcode::EH_LABEL:
   case TargetOpcode::GC_LABEL:
   case TargetOpcode::DBG_VALUE:
+  case TargetOpcode::DBG_LABEL:
     return true;
   }
 }
 
 bool PatchableFunction::runOnMachineFunction(MachineFunction &MF) {
   if (!MF.getFunction().hasFnAttribute("patchable-function"))
     return false;
 

llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h

public:
   /// (which do not go into the machine instrs.)
   static unsigned CountResults(SDNode *Node);
 
   /// EmitDbgValue - Generate machine instruction for a dbg_value node.
   ///
   MachineInstr *EmitDbgValue(SDDbgValue *SD,
                              DenseMap<SDValue, unsigned> &VRBaseMap);
 
+  /// Generate machine instruction for a dbg_label node.
+  MachineInstr *EmitDbgLabel(SDDbgLabel *SD);
+
   /// EmitNode - Generate machine code for a node and needed dependencies.
   ///
   void EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
                 DenseMap<SDValue, unsigned> &VRBaseMap) {
     if (Node->isMachineOpcode())
       EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap);
     else
       EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap);

llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

else
     MIB.addReg(0U, RegState::Debug);
 
   MIB.addMetadata(Var);
   MIB.addMetadata(Expr);
 
   return &*MIB;
 }
 
+MachineInstr *
+InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
+  MDNode *Label = SD->getLabel();
+  DebugLoc DL = SD->getDebugLoc();
+  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
+         "Expected inlined-at fields to agree");
+
+  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
+  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
+  MIB.addMetadata(Label);
+
+  return &*MIB;
+}
+
 /// EmitMachineNode - Generate machine code for a target-specific node and
 /// needed dependencies.
 ///
 void InstrEmitter::
 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
                 DenseMap<SDValue, unsigned> &VRBaseMap) {
   unsigned Opc = Node->getMachineOpcode();
 

llvm/trunk/lib/CodeGen/SelectionDAG/SDNodeDbgValue.h

public:
 
   /// setIsInvalidated / isInvalidated - Setter / getter of the "Invalidated"
   /// property. A SDDbgValue is invalid if the SDNode that produces the value is
   /// deleted.
   void setIsInvalidated() { Invalid = true; }
   bool isInvalidated() const { return Invalid; }
 };
 
+/// Holds the information from a dbg_label node through SDISel.
+/// We do not use SDValue here to avoid including its header.
+class SDDbgLabel {
+  MDNode *Label;
+  DebugLoc DL;
+  unsigned Order;
+
+public:
+  SDDbgLabel(MDNode *Label, DebugLoc dl, unsigned O)
+      : Label(Label), DL(std::move(dl)), Order(O) {}
+
+  /// Returns the MDNode pointer for the label.
+  MDNode *getLabel() const { return Label; }
+
+  /// Returns the DebugLoc.
+  DebugLoc getDebugLoc() const { return DL; }
+
+  /// Returns the SDNodeOrder.  This is the order of the preceding node in the
+  /// input.
+  unsigned getOrder() const { return Order; }
+};
+
 } // end llvm namespace
 
 #endif

llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

for (; DI != DE; ++DI) {
              "emitting DBG_VALUE out of order");
       if (MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap))
         DbgMIs.push_back(DbgMI);
     }
 
     MachineBasicBlock *InsertBB = Emitter.getBlock();
     MachineBasicBlock::iterator Pos = InsertBB->getFirstTerminator();
     InsertBB->insert(Pos, DbgMIs.begin(), DbgMIs.end());
+
+    SDDbgInfo::DbgLabelIterator DLI = DAG->DbgLabelBegin();
+    SDDbgInfo::DbgLabelIterator DLE = DAG->DbgLabelEnd();
+    // Now emit the rest according to source order.
+    LastOrder = 0;
+    for (const auto &InstrOrder : Orders) {
+      unsigned Order = InstrOrder.first;
+      MachineInstr *MI = InstrOrder.second;
+      if (!MI)
+        continue;
+
+      // Insert all SDDbgLabel's whose order(s) are before "Order".
+      for (; DLI != DLE &&
+             (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order;
+             ++DLI) {
+        MachineInstr *DbgMI = Emitter.EmitDbgLabel(*DLI);
+        if (DbgMI) {
+          if (!LastOrder)
+            // Insert to start of the BB (after PHIs).
+            BB->insert(BBBegin, DbgMI);
+          else {
+            // Insert at the instruction, which may be in a different
+            // block, if the block was split by a custom inserter.
+            MachineBasicBlock::iterator Pos = MI;
+            MI->getParent()->insert(Pos, DbgMI);
+          }
+        }
+      }
+      if (DLI == DLE)
+        break;
+
+      LastOrder = Order;
+    }
   }
 
   InsertPos = Emitter.getInsertPos();
   return Emitter.getBlock();
 }
 
 /// Return the basic block label.
 std::string ScheduleDAGSDNodes::getDAGName() const {
   return "sunit-dag." + BB->getFullName();
 }

llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

case ISD::ADD:
       }
     }
   }
 
   for (SDDbgValue *Dbg : ClonedDVs)
     AddDbgValue(Dbg, Dbg->getSDNode(), false);
 }
 
+/// Creates a SDDbgLabel node.
+SDDbgLabel *SelectionDAG::getDbgLabel(DILabel *Label,
+                                      const DebugLoc &DL, unsigned O) {
+  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
+         "Expected inlined-at fields to agree");
+  return new (DbgInfo->getAlloc()) SDDbgLabel(Label, DL, O);
+}
+
 namespace {
 
 /// RAUWUpdateListener - Helper for ReplaceAllUsesWith - When the node
 /// pointed to by a use iterator is deleted, increment the use iterator
 /// so that it doesn't dangle.
 ///
 class RAUWUpdateListener : public SelectionDAG::DAGUpdateListener {
   SDNode::use_iterator &UI;

 void SelectionDAG::AddDbgValue(SDDbgValue *DB, SDNode *SD, bool isParameter) {
   if (SD) {
     assert(DbgInfo->getSDDbgValues(SD).empty() || SD->getHasDebugValue());
     SD->setHasDebugValue(true);
   }
   DbgInfo->add(DB, SD, isParameter);
 }
 
+void SelectionDAG::AddDbgLabel(SDDbgLabel *DB) {
+  DbgInfo->add(DB);
+}
+
 SDValue SelectionDAG::makeEquivalentMemoryOrdering(LoadSDNode *OldLoad,
                                                    SDValue NewMemOp) {
   assert(isa<MemSDNode>(NewMemOp.getNode()) && "Expected a memop node");
   // The new memory operation must have the same position as the old load in
   // terms of memory dependency. Create a TokenFactor for the old load and new
   // memory operation and update uses of the old load's output chain to use that
   // TokenFactor.
   SDValue OldChain = SDValue(OldLoad, 1);

llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

if (N.getNode()) {
       // virtual register info from the FuncInfo.ValueMap.
       if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, true,
                                     N)) {
         DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
       }
     }
     return nullptr;
   }
+  case Intrinsic::dbg_label: {
+    const DbgLabelInst &DI = cast<DbgLabelInst>(I);
+    DILabel *Label = DI.getLabel();
+    assert(Label && "Missing label");
+
+    SDDbgLabel *SDV;
+    SDV = DAG.getDbgLabel(Label, dl, SDNodeOrder);
+    DAG.AddDbgLabel(SDV);
+    return nullptr;
+  }
   case Intrinsic::dbg_value: {
     const DbgValueInst &DI = cast<DbgValueInst>(I);
     assert(DI.getVariable() && "Missing variable");
 
     DILocalVariable *Variable = DI.getVariable();
     DIExpression *Expression = DI.getExpression();
     dropDanglingDebugInfo(Variable, Expression);
     const Value *V = DI.getValue();

llvm/trunk/test/DebugInfo/Generic/debug-label-mi.ll

+; Test DBG_LABEL MachineInstr for label debugging.
+; RUN: llc -fast-isel=false -debug-only=isel %s -o /dev/null 2> %t.debug
+; RUN: cat %t.debug | FileCheck %s --check-prefix=CHECKMI
+;
+; CHECKMI: DBG_LABEL "top", debug-location !9
+; CHECKMI: DBG_LABEL "done", debug-location !11
+;
+; RUN: llc -fast-isel=false %s -o - | FileCheck %s --check-prefix=CHECKASM
+;
+; CHECKASM: #DEBUG_LABEL: foo:top 
+; CHECKASM: #DEBUG_LABEL: foo:done
+
+source_filename = "debug-label-mi.c"
+
+; Function Attrs: noinline nounwind optnone
+define i32 @foo(i32 signext %a, i32 signext %b) #0 !dbg !4 {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i32, align 4
+  %sum = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  store i32 %b, i32* %b.addr, align 4
+  br label %top
+
+top:                                              ; preds = %entry
+  call void @llvm.dbg.label(metadata !8), !dbg !9
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = load i32, i32* %b.addr, align 4
+  %add = add nsw i32 %0, %1
+  store i32 %add, i32* %sum, align 4
+  br label %done
+
+done:                                             ; preds = %top
+  call void @llvm.dbg.label(metadata !10), !dbg !11
+  %2 = load i32, i32* %sum, align 4
+  ret i32 %2
+}
+
+; Function Attrs: nounwind readnone speculatable
+declare void @llvm.dbg.label(metadata)
+
+attributes #0 = { noinline nounwind optnone uwtable }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: false, emissionKind: FullDebug, enums: !2)
+!1 = !DIFile(filename: "debug-label-mi.c", directory: "./")
+!2 = !{}
+!3 = !{i32 2, !"Debug Info Version", i32 3}
+!4 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, unit: !0, retainedNodes: !2)
+!5 = !DISubroutineType(types: !6)
+!6 = !{!7, !7, !7}
+!7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+!8 = !DILabel(scope: !4, name: "top", file: !1, line: 4)
+!9 = !DILocation(line: 4, column: 1, scope: !4)
+!10 = !DILabel(scope: !4, name: "done", file: !1, line: 7)
+!11 = !DILocation(line: 7, column: 1, scope: !4)

llvm/trunk/test/DebugInfo/Generic/debug-label-opt.ll

+; Test DBG_LABEL MachineInstr under optimization.
+; The test case is generated by clang with -O2 is on.
+; RUN: llc -fast-isel=false -debug-only=isel %s -o /dev/null 2> %t.debug
+; RUN: cat %t.debug | FileCheck %s --check-prefix=CHECKMI
+;
+; CHECKMI: DBG_LABEL "end_sum", debug-location !18
+; CHECKMI: DBG_LABEL "end", debug-location !20
+source_filename = "debug-label-opt.c"
+
+define i32 @foo(i32* nocapture readonly %a, i32 %n) local_unnamed_addr !dbg !7 {
+entry:
+  call void @llvm.dbg.value(metadata i32* %a, metadata !13, metadata !DIExpression()), !dbg !6
+  call void @llvm.dbg.value(metadata i32 %n, metadata !14, metadata !DIExpression()), !dbg !6
+  call void @llvm.dbg.value(metadata i32 0, metadata !15, metadata !DIExpression()), !dbg !6
+  switch i32 %n, label %end_sum [
+    i32 2, label %end_sum.sink.split
+    i32 3, label %if.then3
+  ], !dbg !6
+
+if.then3:                                         ; preds = %entry
+  %arrayidx4 = getelementptr inbounds i32, i32* %a, i64 1, !dbg !6
+  br label %end_sum.sink.split, !dbg !6
+
+end_sum.sink.split:                               ; preds = %entry, %if.then3
+  %a.sink = phi i32* [ %arrayidx4, %if.then3 ], [ %a, %entry ]
+  %.sink = phi i64 [ 2, %if.then3 ], [ 1, %entry ]
+  %0 = load i32, i32* %a.sink, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %a, i64 %.sink
+  %1 = load i32, i32* %arrayidx1, align 4
+  %add = add nsw i32 %1, %0
+  br label %end_sum, !dbg !6
+
+end_sum:                                          ; preds = %end_sum.sink.split, %entry
+  %sum.0 = phi i32 [ 0, %entry ], [ %add, %end_sum.sink.split ]
+  call void @llvm.dbg.value(metadata i32 %sum.0, metadata !15, metadata !DIExpression()), !dbg !6
+  call void @llvm.dbg.label(metadata !16), !dbg !18
+  %2 = load i32, i32* %a, align 4, !dbg !6
+  %mul = mul nsw i32 %2, %sum.0, !dbg !19
+  call void @llvm.dbg.value(metadata i32 %mul, metadata !15, metadata !DIExpression()), !dbg !6
+  call void @llvm.dbg.label(metadata !17), !dbg !20
+  ret i32 %mul, !dbg !6
+}
+
+; Function Attrs: nounwind readnone speculatable
+declare void @llvm.dbg.label(metadata)
+
+; Function Attrs: nounwind readnone speculatable
+declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4, !5}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+!1 = !DIFile(filename: "debug-label-opt.c", directory: "./")
+!2 = !{}
+!3 = !{i32 2, !"Dwarf Version", i32 4}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = !{i32 1, !"wchar_size", i32 4}
+!6 = !DILocation(line: 1, column: 14, scope: !7)
+!7 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0, retainedNodes: !12)
+!8 = !DISubroutineType(types: !9)
+!9 = !{!10, !11, !10}
+!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+!11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64)
+!12 = !{!13, !14, !15, !16, !17}
+!13 = !DILocalVariable(name: "a", arg: 1, scope: !7, file: !1, line: 1, type: !11)
+!14 = !DILocalVariable(name: "n", arg: 2, scope: !7, file: !1, line: 1, type: !10)
+!15 = !DILocalVariable(name: "sum", scope: !7, file: !1, line: 3, type: !10)
+!16 = !DILabel(scope: !7, name: "end_sum", file: !1, line: 10)
+!17 = !DILabel(scope: !7, name: "end", file: !1, line: 13)
+!18 = !DILocation(line: 10, column: 1, scope: !7)
+!19 = !DILocation(line: 11, column: 7, scope: !7)
+!20 = !DILocation(line: 13, column: 1, scope: !7)