[AMDGPU][MC] Added support of 3-element addresses for MIMG instructions

[dp]

Summary

See bug 35999: https://bugs.llvm.org/show_bug.cgi?id=35999

[arsenm]

LGTM

[artem.tamazov]

Looks good.

llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td

multiclass MIMG_NoSampler_Src_Helper_Helper <bits<7> op, string asm,
                                              RegisterClass dst_rc,
                                              int channels, bit d16_bit,
                                              string suffix> {
   def NAME # _V1 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, d16_bit,
                                                    !if(!eq(channels, 1), "AMDGPU", "")>,
                             MIMG_Mask<asm#"_V1"#suffix, channels>;
   def NAME # _V2 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64, d16_bit>,
                             MIMG_Mask<asm#"_V2"#suffix, channels>;
+  def NAME # _V3 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96, d16_bit>,
+                            MIMG_Mask<asm#"_V3"#suffix, channels>;
   def NAME # _V4 # suffix : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128, d16_bit>,
                             MIMG_Mask<asm#"_V4"#suffix, channels>;
 }
 
 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
                                       RegisterClass dst_rc,
                                       int channels> {
   defm NAME : MIMG_NoSampler_Src_Helper_Helper <op, asm, dst_rc, channels, 0, "">;
multiclass MIMG_Store_Addr_Helper_Helper <bits<7> op, string asm,
                                   RegisterClass data_rc,
                                   int channels, bit d16_bit,
                                   string suffix> {
   def NAME # _V1 # suffix : MIMG_Store_Helper <op, asm, data_rc, VGPR_32, d16_bit,
                                                !if(!eq(channels, 1), "AMDGPU", "")>,
                             MIMG_Mask<asm#"_V1"#suffix, channels>;
   def NAME # _V2 # suffix : MIMG_Store_Helper <op, asm, data_rc, VReg_64, d16_bit>,
                             MIMG_Mask<asm#"_V2"#suffix, channels>;
+  def NAME # _V3 # suffix : MIMG_Store_Helper <op, asm, data_rc, VReg_96, d16_bit>,
+                            MIMG_Mask<asm#"_V3"#suffix, channels>;
   def NAME # _V4 # suffix : MIMG_Store_Helper <op, asm, data_rc, VReg_128, d16_bit>,
                             MIMG_Mask<asm#"_V4"#suffix, channels>;
 }
 
 multiclass MIMG_Store_Addr_Helper <bits<7> op, string asm,
                                   RegisterClass data_rc,
                                   int channels> {
   defm NAME : MIMG_Store_Addr_Helper_Helper <op, asm, data_rc, channels, 0, "">;
multiclass MIMG_Atomic_Addr_Helper_m <mimg op,
                                       string asm,
                                       RegisterClass data_rc,
                                       bit is32Bit,
                                       bit enableDasm = 0> {
   // _V* variants have different address size, but the size is not encoded.
   // So only one variant can be disassembled. V1 looks the safest to decode.
   defm _V1 : MIMG_Atomic_Helper_m <op, name # "_V1", asm, asm # "_V1", data_rc, VGPR_32, is32Bit, enableDasm>;
   defm _V2 : MIMG_Atomic_Helper_m <op, name # "_V2", asm, asm # "_V2", data_rc, VReg_64, is32Bit>;
-  defm _V4 : MIMG_Atomic_Helper_m <op, name # "_V3", asm, asm # "_V3", data_rc, VReg_128, is32Bit>;
+  defm _V3 : MIMG_Atomic_Helper_m <op, name # "_V3", asm, asm # "_V3", data_rc, VReg_96, is32Bit>;
+  defm _V4 : MIMG_Atomic_Helper_m <op, name # "_V4", asm, asm # "_V4", data_rc, VReg_128, is32Bit>;
 }
 
 multiclass MIMG_Atomic <mimg op, string asm,
                         RegisterClass data_rc_32 = VGPR_32,   // 32-bit atomics
                         RegisterClass data_rc_64 = VReg_64> { // 64-bit atomics
   // _V* variants have different dst size, but the size is encoded implicitly,
   // using dmask and tfe. Only 32-bit variant is registered with disassembler.
   // Other variants are reconstructed by disassembler using dmask and tfe.
multiclass MIMG_Sampler_Src_Helper_Helper <bits<7> op, string asm,
                                     RegisterClass dst_rc,
                                     int channels, bit wqm,
                                     bit d16_bit, string suffix> {
     def _V1 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm, d16_bit,
                                    !if(!eq(channels, 1), "AMDGPU", "")>,
                        MIMG_Mask<asm#"_V1"#suffix, channels>;
     def _V2 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm, d16_bit>,
                        MIMG_Mask<asm#"_V2"#suffix, channels>;
+    def _V3 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_96, wqm, d16_bit>,
+                       MIMG_Mask<asm#"_V3"#suffix, channels>;
     def _V4 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm, d16_bit>,
                        MIMG_Mask<asm#"_V4"#suffix, channels>;
     def _V8 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm, d16_bit>,
                        MIMG_Mask<asm#"_V8"#suffix, channels>;
     def _V16 # suffix : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm, d16_bit>,
                         MIMG_Mask<asm#"_V16"#suffix, channels>;
 }
 

 
 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
                                     RegisterClass dst_rc,
                                     bit wqm, bit d16_bit,
                                     string prefix,
                                     string suffix> {
   def prefix # _V1 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm, d16_bit, "AMDGPU">;
   def prefix # _V2 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm, d16_bit>;
+  def prefix # _V3 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_96, wqm, d16_bit>;
   def prefix # _V4 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm, d16_bit>;
   def prefix # _V8 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm, d16_bit>;
   def prefix # _V16 # suffix : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm, d16_bit>;
 }
 
 multiclass MIMG_Gather <bits<7> op, string asm, bit wqm=0> {
   defm : MIMG_Gather_Src_Helper<op, asm, VReg_128, wqm, 0, "_V4", "">;
 

llvm/trunk/test/MC/AMDGPU/mimg.s

 
 //===----------------------------------------------------------------------===//
 // Image Load/Store
 //===----------------------------------------------------------------------===//
 
 image_load    v[4:6], v[237:240], s[28:35] dmask:0x7 unorm
 // GCN:  image_load v[4:6], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x00,0xf0,0xed,0x04,0x07,0x00]
 
+image_load    v4, v237, s[28:35]
+// GCN:  image_load v4, v237, s[28:35] ; encoding: [0x00,0x00,0x00,0xf0,0xed,0x04,0x07,0x00]
+
+image_load    v4, v[237:238], s[28:35]
+// GCN:  image_load v4, v[237:238], s[28:35] ; encoding: [0x00,0x00,0x00,0xf0,0xed,0x04,0x07,0x00]
+
+image_load    v4, v[237:239], s[28:35]
+// GCN:  image_load v4, v[237:239], s[28:35] ; encoding: [0x00,0x00,0x00,0xf0,0xed,0x04,0x07,0x00]
+
 image_load    v4, v[237:240], s[28:35]
 // GCN:  image_load v4, v[237:240], s[28:35] ; encoding: [0x00,0x00,0x00,0xf0,0xed,0x04,0x07,0x00]
 
 image_load    v[4:7], v[237:240], s[28:35] dmask:0x7 tfe
 // GCN:  image_load v[4:7], v[237:240], s[28:35] dmask:0x7 tfe ; encoding: [0x00,0x07,0x01,0xf0,0xed,0x04,0x07,0x00]
 
 // Verify support of all possible modifiers.
 // FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
 image_load    v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16
 // NOSICI: error: d16 modifier is not supported on this GPU
 // VI:     image_load v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80]
 // NOGFX9: error: r128 modifier is not supported on this GPU
 
 image_load v5, v[1:4], s[8:15] d16
 // NOSICI: error: d16 modifier is not supported on this GPU
 // GFX89:  image_load v5, v[1:4], s[8:15] d16 ; encoding: [0x00,0x00,0x00,0xf0,0x01,0x05,0x02,0x80]
 
 image_load v5, v[1:4], s[8:15] r128
 // SICIVI: image_load v5, v[1:4], s[8:15] r128 ; encoding: [0x00,0x80,0x00,0xf0,0x01,0x05,0x02,0x00]
 // NOGFX9: error: r128 modifier is not supported on this GPU
 
 image_store   v[193:195], v[237:240], s[28:35] dmask:0x7 unorm
 // GCN: image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x20,0xf0,0xed,0xc1,0x07,0x00]
 
+image_store   v193, v237, s[28:35]
+// GCN: image_store v193, v237, s[28:35] ; encoding: [0x00,0x00,0x20,0xf0,0xed,0xc1,0x07,0x00]
+
+image_store   v193, v[237:238], s[28:35]
+// GCN: image_store v193, v[237:238], s[28:35] ; encoding: [0x00,0x00,0x20,0xf0,0xed,0xc1,0x07,0x00]
+
+image_store   v193, v[237:239], s[28:35]
+// GCN: image_store v193, v[237:239], s[28:35] ; encoding: [0x00,0x00,0x20,0xf0,0xed,0xc1,0x07,0x00]
+
 image_store   v193, v[237:240], s[28:35]
 // GCN: image_store v193, v[237:240], s[28:35] ; encoding: [0x00,0x00,0x20,0xf0,0xed,0xc1,0x07,0x00]
 
 image_store   v[193:194], v[237:240], s[28:35] tfe
 // GCN: image_store v[193:194], v[237:240], s[28:35] tfe ; encoding: [0x00,0x00,0x21,0xf0,0xed,0xc1,0x07,0x00]
 
 // Verify support of all possible modifiers.
 // FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.

 // NOGFX8_0: error: image data size does not match dmask and tfe
 // GFX8_1:   image_load v[5:7], v[1:4], s[8:15] dmask:0xf tfe d16 ; encoding: [0x00,0x0f,0x01,0xf0,0x01,0x05,0x02,0x80]
 // GFX9:     image_load v[5:7], v[1:4], s[8:15] dmask:0xf tfe d16 ; encoding: [0x00,0x0f,0x01,0xf0,0x01,0x05,0x02,0x80]
 
 //===----------------------------------------------------------------------===//
 // Image Load/Store: PCK variants
 //===----------------------------------------------------------------------===//
 
+image_load_mip_pck v5, v1, s[8:15] dmask:0x1
+// GCN: image_load_mip_pck v5, v1, s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1
+// GCN: image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:3], s[8:15] dmask:0x1
+// GCN: image_load_mip_pck v5, v[1:3], s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+
 image_load_mip_pck v5, v[1:4], s[8:15] dmask:0x1
 // GCN: image_load_mip_pck v5, v[1:4], s[8:15] dmask:0x1 ; encoding: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
 
 image_load_mip_pck v[5:6], v[1:4], s[8:15] dmask:0x3
 // GCN: image_load_mip_pck v[5:6], v[1:4], s[8:15] dmask:0x3 ; encoding: [0x00,0x03,0x10,0xf0,0x01,0x05,0x02,0x00]
 
 image_load_mip_pck v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc tfe lwe da
 // GCN: image_load_mip_pck v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc tfe lwe da ; encoding: [0x00,0x71,0x13,0xf2,0x01,0x05,0x02,0x00]
 
 image_load_mip_pck_sgn v[5:6], v[1:4], s[8:15] dmask:0x5
 // GCN: image_load_mip_pck_sgn v[5:6], v[1:4], s[8:15] dmask:0x5 ; encoding: [0x00,0x05,0x14,0xf0,0x01,0x05,0x02,0x00]
 
 image_load_pck v5, v[1:4], s[8:15] dmask:0x1 glc
 // GCN: image_load_pck v5, v[1:4], s[8:15] dmask:0x1 glc ; encoding: [0x00,0x21,0x08,0xf0,0x01,0x05,0x02,0x00]
 
 image_load_pck_sgn v5, v[1:4], s[8:15] dmask:0x1 lwe
 // GCN: image_load_pck_sgn v5, v[1:4], s[8:15] dmask:0x1 lwe ; encoding: [0x00,0x01,0x0e,0xf0,0x01,0x05,0x02,0x00]
 
 image_load_mip_pck v5, v[1:4], s[8:15] dmask:0x1 d16
 // NOSICI: error: invalid operand for instruction
 // NOVI:   error: invalid operand for instruction
 // NOGFX9: error: invalid operand for instruction
 
+image_store_mip_pck v252, v2, s[12:19] dmask:0x1 unorm
+// GCN: image_store_mip_pck v252, v2, s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 unorm
+// GCN: image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store_mip_pck v252, v[2:4], s[12:19] dmask:0x1 unorm
+// GCN: image_store_mip_pck v252, v[2:4], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
+
 image_store_mip_pck v252, v[2:5], s[12:19] dmask:0x1 unorm
 // GCN: image_store_mip_pck v252, v[2:5], s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
 
 image_store_mip_pck v1, v[2:5], s[12:19] dmask:0x1 unorm glc slc lwe da
 // GCN: image_store_mip_pck v1, v[2:5], s[12:19] dmask:0x1 unorm glc slc lwe da ; encoding: [0x00,0x71,0x2e,0xf2,0x02,0x01,0x03,0x00]
 
 image_store_pck v1, v[2:5], s[12:19] dmask:0x1 unorm da
 // GCN: image_store_pck v1, v[2:5], s[12:19] dmask:0x1 unorm da ; encoding: [0x00,0x51,0x28,0xf0,0x02,0x01,0x03,0x00]
 
 image_store_mip_pck v252, v[2:5], s[12:19] dmask:0x1 d16
 // NOSICI: error: invalid operand for instruction
 // NOVI:   error: invalid operand for instruction
 // NOGFX9: error: invalid operand for instruction
 
 //===----------------------------------------------------------------------===//
 // Image Sample
 //===----------------------------------------------------------------------===//
 
 image_sample  v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 unorm
 // GCN: image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 unorm ; encoding: [0x00,0x17,0x80,0xf0,0xed,0xc1,0x27,0x00]
 
+image_sample  v193, v237, s[28:35], s[4:7]
+// GCN: image_sample v193, v237, s[28:35], s[4:7] ; encoding: [0x00,0x00,0x80,0xf0,0xed,0xc1,0x27,0x00]
+
+image_sample  v193, v[237:238], s[28:35], s[4:7]
+// GCN: image_sample v193, v[237:238], s[28:35], s[4:7] ; encoding: [0x00,0x00,0x80,0xf0,0xed,0xc1,0x27,0x00]
+
+image_sample  v193, v[237:239], s[28:35], s[4:7]
+// GCN: image_sample v193, v[237:239], s[28:35], s[4:7] ; encoding: [0x00,0x00,0x80,0xf0,0xed,0xc1,0x27,0x00]
+
 image_sample  v193, v[237:240], s[28:35], s[4:7]
 // GCN: image_sample v193, v[237:240], s[28:35], s[4:7] ; encoding: [0x00,0x00,0x80,0xf0,0xed,0xc1,0x27,0x00]
 
 image_sample  v[193:194], v[237:240], s[28:35], s[4:7] tfe
 // GCN: image_sample v[193:194], v[237:240], s[28:35], s[4:7] tfe ; encoding: [0x00,0x00,0x81,0xf0,0xed,0xc1,0x27,0x00]
 
 // FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
 image_sample  v193, v[237:240], s[28:35], s[4:7] r128

 // NOGFX8_0: error: image data size does not match dmask and tfe
 // GFX8_1:   image_sample v[193:194], v[237:240], s[28:35], s[4:7] dmask:0x7 d16 ; encoding: [0x00,0x07,0x80,0xf0,0xed,0xc1,0x27,0x80]
 // GFX9:     image_sample v[193:194], v[237:240], s[28:35], s[4:7] dmask:0x7 d16 ; encoding: [0x00,0x07,0x80,0xf0,0xed,0xc1,0x27,0x80]
 
 //===----------------------------------------------------------------------===//
 // Image Atomics
 //===----------------------------------------------------------------------===//
 
+image_atomic_add v4, v192, s[28:35] dmask:0x1 unorm glc
+// SICI:  image_atomic_add v4, v192, s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0xc0,0x04,0x07,0x00]
+// GFX89: image_atomic_add v4, v192, s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0xc0,0x04,0x07,0x00]
+
+image_atomic_add v4, v[192:193], s[28:35] dmask:0x1 unorm glc
+// SICI:  image_atomic_add v4, v[192:193], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0xc0,0x04,0x07,0x00]
+// GFX89: image_atomic_add v4, v[192:193], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0xc0,0x04,0x07,0x00]
+
+image_atomic_add v4, v[192:194], s[28:35] dmask:0x1 unorm glc
+// SICI:  image_atomic_add v4, v[192:194], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0xc0,0x04,0x07,0x00]
+// GFX89: image_atomic_add v4, v[192:194], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0xc0,0x04,0x07,0x00]
+
 image_atomic_add v4, v[192:195], s[28:35] dmask:0x1 unorm glc
 // SICI:  image_atomic_add v4, v[192:195], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0xc0,0x04,0x07,0x00]
 // GFX89: image_atomic_add v4, v[192:195], s[28:35] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0xc0,0x04,0x07,0x00]
 
 image_atomic_add v252, v2, s[8:15] dmask:0x1 unorm
 // SICI:  image_atomic_add v252, v2, s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x44,0xf0,0x02,0xfc,0x02,0x00]
 // GFX89: image_atomic_add v252, v2, s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x48,0xf0,0x02,0xfc,0x02,0x00]
 

 
 //===----------------------------------------------------------------------===//
 // Image Gather4
 //===----------------------------------------------------------------------===//
 
 image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1
 // GCN: image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 ; encoding: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
 
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1
+// GCN: image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 ; encoding: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// GCN: image_gather4 v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 ; encoding: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
+
 image_gather4 v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
 // GCN: image_gather4 v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2 ; encoding: [0x00,0x02,0x00,0xf1,0x01,0x05,0x62,0x00]
 
 image_gather4 v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
 // GCN: image_gather4 v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4 ; encoding: [0x00,0x04,0x00,0xf1,0x01,0x05,0x62,0x00]
 
 image_gather4 v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
 // GCN: image_gather4 v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8 ; encoding: [0x00,0x08,0x00,0xf1,0x01,0x05,0x62,0x00]