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Differential D44896

AMDGPU: Set natural stack alignment in DataLayout
ClosedPublic

Authored by arsenm on Mar 26 2018, 7:26 AM.

Details

Reviewers
rampitec
kzhuravl
yaxunl
Summary

Only 4 byte alignment is ever useful, so increasing anything
beyond this may require realigning the stack.

Diff Detail

Event Timeline

arsenm created this revision.Mar 26 2018, 7:26 AM
Herald added subscribers: t-tye, tpr, dstuttard and 2 others. · View Herald TranscriptMar 26 2018, 7:26 AM
rampitec accepted this revision.Mar 26 2018, 9:50 AM

LGTM

This revision is now accepted and ready to land.Mar 26 2018, 9:50 AM
arsenm closed this revision.Mar 27 2018, 12:30 PM

r328656, clang r328657

Revision Contents

PathSize
lib/
Target/
AMDGPU/
4 lines

Diff 139787

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Show First 20 Lines • Show All 255 Lines • ▼ Show 20 Lines
GCNILPSchedRegistry("gcn-ilp", GCNILPSchedRegistry("gcn-ilp",
"Run GCN iterative scheduler for ILP scheduling (experimental)", "Run GCN iterative scheduler for ILP scheduling (experimental)",
createIterativeILPMachineScheduler); createIterativeILPMachineScheduler);
static StringRef computeDataLayout(const Triple &TT) { static StringRef computeDataLayout(const Triple &TT) {
if (TT.getArch() == Triple::r600) { if (TT.getArch() == Triple::r600) {
// 32-bit pointers. // 32-bit pointers.
return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
} }
// 32-bit private, local, and region pointers. 64-bit global, constant and // 32-bit private, local, and region pointers. 64-bit global, constant and
// flat. // flat.
return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32" return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5";
} }
LLVM_READNONE LLVM_READNONE
static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) { static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
if (!GPU.empty()) if (!GPU.empty())
return GPU; return GPU;
if (TT.getArch() == Triple::amdgcn) if (TT.getArch() == Triple::amdgcn)
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