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Differential D44828

Add PowerPC e500(v2) core scheduler and directives.
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Authored by jhibbits on Mar 23 2018, 7:24 AM.

Details

Reviewers
nemanjai
hfinkel
joerg
Commits
rGceb3cd96f7ea: Add PowerPC e500(v2) core scheduler and directives.
rL337345: Add PowerPC e500(v2) core scheduler and directives.

Diff Detail

Event Timeline

jhibbits created this revision.Mar 23 2018, 7:24 AM
Herald added a subscriber: kbarton. · View Herald TranscriptMar 23 2018, 7:24 AM
Harbormaster completed remote builds in B16381: Diff 139592.Mar 23 2018, 7:24 AM
nemanjai accepted this revision.Apr 9 2018, 3:02 PM

Common PPC code LGTM. However, you might want to request a review for the scheduling portions from someone that knows about the CPU (perhaps @joerg).

This revision is now accepted and ready to land.Apr 9 2018, 3:02 PM
Closed by commit rL337345: Add PowerPC e500(v2) core scheduler and directives. (authored by jhibbits). · Explain WhyJul 17 2018, 9:30 PM
This revision was automatically updated to reflect the committed changes.
Herald added a subscriber: llvm-commits. · View Herald TranscriptJul 17 2018, 9:30 PM

Revision Contents

PathSize
lib/
Target/
PowerPC/
6 lines
1 line
2 lines
1 line
PPCScheduleE500.td
PPCScheduleE500mc.td
187 lines
440 lines
1 line

Diff 139592

lib/Target/PowerPC/PPC.td

Show All 29 Lines
def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">; def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">; def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">; def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">; def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">; def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">; def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
def DirectiveE500 : SubtargetFeature<"", "DarwinDirective",
"PPC::DIR_E500", "">;
def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective", def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
"PPC::DIR_E500mc", "">; "PPC::DIR_E500mc", "">;
def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective", def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
"PPC::DIR_E5500", "">; "PPC::DIR_E5500", "">;
def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">; def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">; def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">; def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
def DirectivePwr5x def DirectivePwr5x
▲ Show 20 Lines • Show All 305 Lines • ▼ Show 20 Linesdef : ProcessorModel<"970", G5Model,
Feature64Bit /*, Feature64BitRegs */, Feature64Bit /*, Feature64BitRegs */,
FeatureMFTB]>; FeatureMFTB]>;
def : ProcessorModel<"g5", G5Model, def : ProcessorModel<"g5", G5Model,
[Directive970, FeatureAltivec, [Directive970, FeatureAltivec,
FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
FeatureFRES, FeatureFRSQRTE, FeatureFRES, FeatureFRSQRTE,
Feature64Bit /*, Feature64BitRegs */, Feature64Bit /*, Feature64BitRegs */,
FeatureMFTB, DeprecatedDST]>; FeatureMFTB, DeprecatedDST]>;
def : ProcessorModel<"e500", PPCE500Model,
[DirectiveE500,
FeatureICBT, FeatureBookE,
FeatureISEL, FeatureMFTB]>;
def : ProcessorModel<"e500mc", PPCE500mcModel, def : ProcessorModel<"e500mc", PPCE500mcModel,
[DirectiveE500mc, [DirectiveE500mc,
FeatureSTFIWX, FeatureICBT, FeatureBookE, FeatureSTFIWX, FeatureICBT, FeatureBookE,
FeatureISEL, FeatureMFTB]>; FeatureISEL, FeatureMFTB]>;
def : ProcessorModel<"e5500", PPCE5500Model, def : ProcessorModel<"e5500", PPCE5500Model,
[DirectiveE5500, FeatureMFOCRF, Feature64Bit, [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
FeatureSTFIWX, FeatureICBT, FeatureBookE, FeatureSTFIWX, FeatureICBT, FeatureBookE,
FeatureISEL, FeatureMFTB]>; FeatureISEL, FeatureMFTB]>;
▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCAsmPrinter.cpp

Show First 20 Lines • Show All 1,452 Lines • ▼ Show 20 Lines static const char *const CPUDirectives[] = {
"ppc440", "ppc440",
"ppc601", "ppc601",
"ppc602", "ppc602",
"ppc603", "ppc603",
"ppc7400", "ppc7400",
"ppc750", "ppc750",
"ppc970", "ppc970",
"ppcA2", "ppcA2",
"ppce500",
"ppce500mc", "ppce500mc",
"ppce5500", "ppce5500",
"power3", "power3",
"power4", "power4",
"power5", "power5",
"power5x", "power5x",
"power6", "power6",
"power6x", "power6x",
▲ Show 20 Lines • Show All 145 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,027 Lines • ▼ Show 20 LinesPPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setMinFunctionAlignment(2); setMinFunctionAlignment(2);
if (Subtarget.isDarwin()) if (Subtarget.isDarwin())
setPrefFunctionAlignment(4); setPrefFunctionAlignment(4);
switch (Subtarget.getDarwinDirective()) { switch (Subtarget.getDarwinDirective()) {
default: break; default: break;
case PPC::DIR_970: case PPC::DIR_970:
case PPC::DIR_A2: case PPC::DIR_A2:
case PPC::DIR_E500:
case PPC::DIR_E500mc: case PPC::DIR_E500mc:
case PPC::DIR_E5500: case PPC::DIR_E5500:
case PPC::DIR_PWR4: case PPC::DIR_PWR4:
case PPC::DIR_PWR5: case PPC::DIR_PWR5:
case PPC::DIR_PWR5X: case PPC::DIR_PWR5X:
case PPC::DIR_PWR6: case PPC::DIR_PWR6:
case PPC::DIR_PWR6X: case PPC::DIR_PWR6X:
case PPC::DIR_PWR7: case PPC::DIR_PWR7:
▲ Show 20 Lines • Show All 9,566 Lines • ▼ Show 20 Linesunsigned PPCTargetLowering::combineRepeatedFPDivisors() const {
// Combine multiple FDIVs with the same divisor into multiple FMULs by the // Combine multiple FDIVs with the same divisor into multiple FMULs by the
// reciprocal if there are two or more FDIVs (for embedded cores with only // reciprocal if there are two or more FDIVs (for embedded cores with only
// one FP pipeline) for three or more FDIVs (for generic OOO cores). // one FP pipeline) for three or more FDIVs (for generic OOO cores).
switch (Subtarget.getDarwinDirective()) { switch (Subtarget.getDarwinDirective()) {
default: default:
return 3; return 3;
case PPC::DIR_440: case PPC::DIR_440:
case PPC::DIR_A2: case PPC::DIR_A2:
case PPC::DIR_E500:
case PPC::DIR_E500mc: case PPC::DIR_E500mc:
case PPC::DIR_E5500: case PPC::DIR_E5500:
return 2; return 2;
} }
} }
// isConsecutiveLSLoc needs to work even if all adds have not yet been // isConsecutiveLSLoc needs to work even if all adds have not yet been
// collapsed, and so we need to look through chains of them. // collapsed, and so we need to look through chains of them.
▲ Show 20 Lines • Show All 3,231 Lines • Show Last 20 Lines

lib/Target/PowerPC/PPCSchedule.td

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
include "PPCSchedule440.td" include "PPCSchedule440.td"
include "PPCScheduleG4.td" include "PPCScheduleG4.td"
include "PPCScheduleG4Plus.td" include "PPCScheduleG4Plus.td"
include "PPCScheduleG5.td" include "PPCScheduleG5.td"
include "PPCScheduleP7.td" include "PPCScheduleP7.td"
include "PPCScheduleP8.td" include "PPCScheduleP8.td"
include "PPCScheduleP9.td" include "PPCScheduleP9.td"
include "PPCScheduleA2.td" include "PPCScheduleA2.td"
include "PPCScheduleE500.td"
include "PPCScheduleE500mc.td" include "PPCScheduleE500mc.td"
include "PPCScheduleE5500.td" include "PPCScheduleE5500.td"

lib/Target/PowerPC/PPCScheduleE500.td

  • This file was copied from lib/Target/PowerPC/PPCScheduleE500mc.td.
//===-- PPCScheduleE500mc.td - e500mc Scheduling Defs ------*- tablegen -*-===// //===-- PPCScheduleE500.td - e500 Scheduling Defs ------*- tablegen -*-===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file defines the itinerary class data for the Freescale e500mc 32-bit // This file defines the itinerary class data for the Freescale e500 32-bit
// Power processor. // Power processor.
// //
// All information is derived from the "e500mc Core Reference Manual", // All information is derived from the "e500 Core Reference Manual",
// Freescale Document Number E500MCRM, Rev. 1, 03/2012. // Freescale Document Number E500MCRM, Rev. 1, 03/2012.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Relevant functional units in the Freescale e500mc core: // Relevant functional units in the Freescale e500 core:
// //
// * Decode & Dispatch // * Decode & Dispatch
// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue // Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ). // queues (GIQx) or Branch issue queue (BIQ).
def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1 def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1
def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2 def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2
// * Execute // * Execute
// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX. // 6 pipelined execution units: SU0, SU1, BU, LSU, MU.
// Some instructions can only execute in SFX0 but not SFX1. // Some instructions can only execute in SU0 but not SU1.
// The CFX has a bypass path, allowing non-divide instructions to execute def E500_SU0 : FuncUnit; // Simple unit 0
// while a divide instruction is executed. def E500_SU1 : FuncUnit; // Simple unit 1
def E500_SFX0 : FuncUnit; // Simple unit 0
def E500_SFX1 : FuncUnit; // Simple unit 1
def E500_BU : FuncUnit; // Branch unit def E500_BU : FuncUnit; // Branch unit
def E500_CFX_DivBypass def E500_MU : FuncUnit; // MU pipeline
: FuncUnit; // CFX divide bypass path
def E500_CFX_0 : FuncUnit; // CFX pipeline
def E500_LSU_0 : FuncUnit; // LSU pipeline def E500_LSU_0 : FuncUnit; // LSU pipeline
def E500_FPU_0 : FuncUnit; // FPU pipeline
def E500_GPR_Bypass : Bypass; def E500_GPR_Bypass : Bypass;
def E500_FPR_Bypass : Bypass;
def E500_CR_Bypass : Bypass; def E500_CR_Bypass : Bypass;
def E500_DivBypass : Bypass;
def PPCE500mcItineraries : ProcessorItineraries< def PPCE500Itineraries : ProcessorItineraries<
[E500_DIS0, E500_DIS1, E500_SFX0, E500_SFX1, E500_BU, E500_CFX_DivBypass, [E500_DIS0, E500_DIS1, E500_SU0, E500_SU1, E500_BU,
E500_CFX_0, E500_LSU_0, E500_FPU_0], E500_MU, E500_LSU_0],
[E500_CR_Bypass, E500_GPR_Bypass, E500_FPR_Bypass], [ [E500_CR_Bypass, E500_GPR_Bypass, E500_DivBypass], [
InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[E500_GPR_Bypass, [E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[E500_GPR_Bypass, [E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1, 1], // Latency = 1 [4, 1, 1, 1], // Latency = 1
[E500_GPR_Bypass, [E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass, E500_GPR_Bypass, E500_GPR_Bypass,
E500_CR_Bypass]>, E500_CR_Bypass]>,
InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500_SU0, E500_SU1]>],
[5, 1, 1], // Latency = 1 or 2 [5, 1, 1], // Latency = 1 or 2
[E500_CR_Bypass, [E500_CR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_CFX_0], 0>, InstrStage<1, [E500_MU], 0>,
InstrStage<14, [E500_CFX_DivBypass]>], InstrStage<14, [E500_MU]>],
[17, 1, 1], // Latency=4..35, Repeat= 4..35 [17, 1, 1], // Latency=4..35, Repeat= 4..35
[E500_GPR_Bypass, [E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<8, [E500_FPU_0]>],
[11], // Latency = 8
[E500_FPR_Bypass]>,
InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<8, [E500_FPU_0]>],
[11, 1, 1], // Latency = 8
[NoBypass, NoBypass, NoBypass]>,
InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_CFX_0]>], InstrStage<4, [E500_MU]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1 [7, 1, 1], // Latency = 4, Repeat rate = 1
[E500_GPR_Bypass, [E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_CFX_0]>], InstrStage<4, [E500_MU]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1 [7, 1, 1], // Latency = 4, Repeat rate = 1
[E500_GPR_Bypass, [E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_CFX_0]>], InstrStage<4, [E500_MU]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1 [7, 1, 1], // Latency = 4, Repeat rate = 1
[E500_GPR_Bypass, [E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[E500_GPR_Bypass, [E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[E500_GPR_Bypass, [E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<2, [E500_SFX0]>], InstrStage<2, [E500_SU0]>],
[5, 1], // Latency = 2, Repeat rate = 2 [5, 1], // Latency = 2, Repeat rate = 2
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_BU]>], InstrStage<1, [E500_BU]>],
[4, 1], // Latency = 1 [4, 1], // Latency = 1
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_BU]>], InstrStage<1, [E500_BU]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[E500_CR_Bypass, [E500_CR_Bypass,
E500_CR_Bypass, E500_CR_Bypass]>, E500_CR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_BU]>], InstrStage<1, [E500_BU]>],
[4, 1], // Latency = 1 [4, 1], // Latency = 1
[E500_CR_Bypass, E500_CR_Bypass]>, [E500_CR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[E500_CR_Bypass, E500_GPR_Bypass]>, [E500_CR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3, Repeat rate = 1 [6, 1], // Latency = 3, Repeat rate = 1
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>, InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass], [E500_GPR_Bypass, E500_GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>, InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass], [E500_GPR_Bypass, E500_GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>, InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass], [NoBypass, E500_GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1, 1], // Latency = 3
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
InstrStage<1, [E500_LSU_0]>],
[6, 1, 1], // Latency = 3
[E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>],
[7, 1, 1], // Latency = 4
[E500_FPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
InstrStage<1, [E500_LSU_0]>],
[7, 1, 1], // Latency = 4
[E500_FPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
InstrStage<1, [E500_LSU_0]>],
[7, 1, 1], // Latency = 4
[E500_FPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass],
2>, // 2 micro-ops
InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>, InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>, InstrStage<1, [E500_SU0, E500_SU1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[7, 1], // Latency = r+3 [7, 1], // Latency = r+3
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<3, [E500_LSU_0]>], InstrStage<3, [E500_LSU_0]>],
[6, 1, 1], // Latency = 3, Repeat rate = 3 [6, 1, 1], // Latency = 3, Repeat rate = 3
[E500_GPR_Bypass, [E500_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>]>, InstrStage<1, [E500_LSU_0]>]>,
InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SFX0]>], InstrStage<4, [E500_SU0]>],
[7, 1], [7, 1],
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<2, [E500_SFX0, E500_SFX1]>], InstrStage<2, [E500_SU0, E500_SU1]>],
[5, 1], // Latency = 2, Repeat rate = 4 [5, 1], // Latency = 2, Repeat rate = 4
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0]>], InstrStage<1, [E500_SU0]>],
[5, 1], [5, 1],
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_LSU_0], 0>]>, InstrStage<1, [E500_LSU_0], 0>]>,
InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<5, [E500_SFX0]>], InstrStage<5, [E500_SU0]>],
[8, 1], [8, 1],
[E500_GPR_Bypass, E500_CR_Bypass]>, [E500_GPR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<5, [E500_SFX0]>], InstrStage<5, [E500_SU0]>],
[8, 1], [8, 1],
[E500_GPR_Bypass, E500_CR_Bypass]>, [E500_GPR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SFX0]>], InstrStage<4, [E500_SU0]>],
[7, 1], // Latency = 4, Repeat rate = 4 [7, 1], // Latency = 4, Repeat rate = 4
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SFX0]>], InstrStage<4, [E500_SU0]>],
[7, 1], // Latency = 4, Repeat rate = 4 [7, 1], // Latency = 4, Repeat rate = 4
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500_GPR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1], // Latency = 1, Repeat rate = 1 [4, 1], // Latency = 1, Repeat rate = 1
[E500_GPR_Bypass, E500_CR_Bypass]>, [E500_GPR_Bypass, E500_CR_Bypass]>,
InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0]>], InstrStage<1, [E500_SU0]>],
[4, 1], // Latency = 1, Repeat rate = 1 [4, 1], // Latency = 1, Repeat rate = 1
[E500_CR_Bypass, E500_GPR_Bypass]>, [E500_CR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_SFX0]>], InstrStage<4, [E500_SU0]>],
[7, 1], // Latency = 4, Repeat rate = 4 [7, 1], // Latency = 4, Repeat rate = 4
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500_SU0, E500_SU1]>],
[4, 1], // Latency = 1, Repeat rate = 1 [4, 1], // Latency = 1, Repeat rate = 1
[E500_CR_Bypass, E500_GPR_Bypass]>, [E500_CR_Bypass, E500_GPR_Bypass]>,
InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<1, [E500_SFX0]>], InstrStage<1, [E500_SU0]>],
[4, 1], [4, 1],
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500_GPR_Bypass]>,
InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<2, [E500_FPU_0]>],
[11, 1, 1], // Latency = 8, Repeat rate = 2
[E500_FPR_Bypass,
E500_FPR_Bypass, E500_FPR_Bypass]>,
InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<4, [E500_FPU_0]>],
[13, 1, 1], // Latency = 10, Repeat rate = 4
[E500_FPR_Bypass,
E500_FPR_Bypass, E500_FPR_Bypass]>,
InstrItinData<IIC_FPCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<2, [E500_FPU_0]>],
[11, 1, 1], // Latency = 8, Repeat rate = 2
[E500_CR_Bypass,
E500_FPR_Bypass, E500_FPR_Bypass]>,
InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<68, [E500_FPU_0]>], InstrStage<32, [E500_MU]>],
[71, 1, 1], // Latency = 68, Repeat rate = 68 [35, 1, 1], // Latency = 32, Repeat rate = 32
[E500_FPR_Bypass, [E500_DivBypass]>,
E500_FPR_Bypass, E500_FPR_Bypass]>,
InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrStage<38, [E500_FPU_0]>], InstrStage<29, [E500_MU]>],
[41, 1, 1], // Latency = 38, Repeat rate = 38 [32, 1, 1], // Latency = 29, Repeat rate = 29
[E500_FPR_Bypass, [E500_DivBypass]>,
E500_FPR_Bypass, E500_FPR_Bypass]>, InstrItinData<IIC_VecGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
InstrItinData<IIC_FPFused, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrStage<1, [E500_SU0]>],
InstrStage<4, [E500_FPU_0]>], [4, 1, 1], // Latency = 1, Repeat rate = 1
[13, 1, 1, 1], // Latency = 10, Repeat rate = 4 [NoBypass]>,
[E500_FPR_Bypass, InstrItinData<IIC_VecComplex, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
E500_FPR_Bypass, E500_FPR_Bypass, InstrStage<4, [E500_MU]>],
E500_FPR_Bypass]>, [7, 1, 1], // Latency = 4, Repeat rate = 1
InstrItinData<IIC_FPRes, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, [NoBypass]>
InstrStage<38, [E500_FPU_0]>],
[41, 1], // Latency = 38, Repeat rate = 38
[E500_FPR_Bypass, E500_FPR_Bypass]>
]>; ]>;
// ===---------------------------------------------------------------------===// // ===---------------------------------------------------------------------===//
// e500mc machine model for scheduling and other instruction cost heuristics. // e500 machine model for scheduling and other instruction cost heuristics.
def PPCE500mcModel : SchedMachineModel { def PPCE500Model : SchedMachineModel {
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
let LoadLatency = 5; // Optimistic load latency assuming bypass. let LoadLatency = 5; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the // This is overriden by OperandCycles if the
// Itineraries are queried instead. // Itineraries are queried instead.
let CompleteModel = 0; let CompleteModel = 0;
let Itineraries = PPCE500mcItineraries; let Itineraries = PPCE500Itineraries;
} }

lib/Target/PowerPC/PPCScheduleE500mc.td

  • This file was copied to lib/Target/PowerPC/PPCScheduleE500.td.
Show All 13 Lines
// Freescale Document Number E500MCRM, Rev. 1, 03/2012. // Freescale Document Number E500MCRM, Rev. 1, 03/2012.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Relevant functional units in the Freescale e500mc core: // Relevant functional units in the Freescale e500mc core:
// //
// * Decode & Dispatch // * Decode & Dispatch
// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue // Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ). // queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1 def E500mc_DIS0 : FuncUnit; // Dispatch stage - insn 1
def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2 def E500mc_DIS1 : FuncUnit; // Dispatch stage - insn 2
// * Execute // * Execute
// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX. // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
// Some instructions can only execute in SFX0 but not SFX1. // Some instructions can only execute in SFX0 but not SFX1.
// The CFX has a bypass path, allowing non-divide instructions to execute // The CFX has a bypass path, allowing non-divide instructions to execute
// while a divide instruction is executed. // while a divide instruction is executed.
def E500_SFX0 : FuncUnit; // Simple unit 0 def E500mc_SFX0 : FuncUnit; // Simple unit 0
def E500_SFX1 : FuncUnit; // Simple unit 1 def E500mc_SFX1 : FuncUnit; // Simple unit 1
def E500_BU : FuncUnit; // Branch unit def E500mc_BU : FuncUnit; // Branch unit
def E500_CFX_DivBypass def E500mc_CFX_DivBypass
: FuncUnit; // CFX divide bypass path : FuncUnit; // CFX divide bypass path
def E500_CFX_0 : FuncUnit; // CFX pipeline def E500mc_CFX_0 : FuncUnit; // CFX pipeline
def E500_LSU_0 : FuncUnit; // LSU pipeline def E500mc_LSU_0 : FuncUnit; // LSU pipeline
def E500_FPU_0 : FuncUnit; // FPU pipeline def E500mc_FPU_0 : FuncUnit; // FPU pipeline
def E500_GPR_Bypass : Bypass; def E500mc_GPR_Bypass : Bypass;
def E500_FPR_Bypass : Bypass; def E500mc_FPR_Bypass : Bypass;
def E500_CR_Bypass : Bypass; def E500mc_CR_Bypass : Bypass;
def PPCE500mcItineraries : ProcessorItineraries< def PPCE500mcItineraries : ProcessorItineraries<
[E500_DIS0, E500_DIS1, E500_SFX0, E500_SFX1, E500_BU, E500_CFX_DivBypass, [E500mc_DIS0, E500mc_DIS1, E500mc_SFX0, E500mc_SFX1, E500mc_BU, E500mc_CFX_DivBypass,
E500_CFX_0, E500_LSU_0, E500_FPU_0], E500mc_CFX_0, E500mc_LSU_0, E500mc_FPU_0],
[E500_CR_Bypass, E500_GPR_Bypass, E500_FPR_Bypass], [ [E500mc_CR_Bypass, E500mc_GPR_Bypass, E500mc_FPR_Bypass], [
InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntSimple, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[E500_GPR_Bypass, [E500mc_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[E500_GPR_Bypass, [E500mc_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntISEL, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1, 1, 1], // Latency = 1 [4, 1, 1, 1], // Latency = 1
[E500_GPR_Bypass, [E500mc_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass, E500mc_GPR_Bypass, E500mc_GPR_Bypass,
E500_CR_Bypass]>, E500mc_CR_Bypass]>,
InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntCompare, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[5, 1, 1], // Latency = 1 or 2 [5, 1, 1], // Latency = 1 or 2
[E500_CR_Bypass, [E500mc_CR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntDivW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_CFX_0], 0>, InstrStage<1, [E500mc_CFX_0], 0>,
InstrStage<14, [E500_CFX_DivBypass]>], InstrStage<14, [E500mc_CFX_DivBypass]>],
[17, 1, 1], // Latency=4..35, Repeat= 4..35 [17, 1, 1], // Latency=4..35, Repeat= 4..35
[E500_GPR_Bypass, [E500mc_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<8, [E500_FPU_0]>], InstrStage<8, [E500mc_FPU_0]>],
[11], // Latency = 8 [11], // Latency = 8
[E500_FPR_Bypass]>, [E500mc_FPR_Bypass]>,
InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<8, [E500_FPU_0]>], InstrStage<8, [E500mc_FPU_0]>],
[11, 1, 1], // Latency = 8 [11, 1, 1], // Latency = 8
[NoBypass, NoBypass, NoBypass]>, [NoBypass, NoBypass, NoBypass]>,
InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_CFX_0]>], InstrStage<1, [E500mc_CFX_0]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1 [7, 1, 1], // Latency = 4, Repeat rate = 1
[E500_GPR_Bypass, [E500mc_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_CFX_0]>], InstrStage<1, [E500mc_CFX_0]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1 [7, 1, 1], // Latency = 4, Repeat rate = 1
[E500_GPR_Bypass, [E500mc_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_CFX_0]>], InstrStage<1, [E500mc_CFX_0]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1 [7, 1, 1], // Latency = 4, Repeat rate = 1
[E500_GPR_Bypass, [E500mc_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntRotate, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[E500_GPR_Bypass, [E500mc_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntShift, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[E500_GPR_Bypass, [E500mc_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<2, [E500_SFX0]>], InstrStage<2, [E500mc_SFX0]>],
[5, 1], // Latency = 2, Repeat rate = 2 [5, 1], // Latency = 2, Repeat rate = 2
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_BrB, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_BU]>], InstrStage<1, [E500mc_BU]>],
[4, 1], // Latency = 1 [4, 1], // Latency = 1
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_BrCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_BU]>], InstrStage<1, [E500mc_BU]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[E500_CR_Bypass, [E500mc_CR_Bypass,
E500_CR_Bypass, E500_CR_Bypass]>, E500mc_CR_Bypass, E500mc_CR_Bypass]>,
InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_BrMCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_BU]>], InstrStage<1, [E500mc_BU]>],
[4, 1], // Latency = 1 [4, 1], // Latency = 1
[E500_CR_Bypass, E500_CR_Bypass]>, [E500mc_CR_Bypass, E500mc_CR_Bypass]>,
InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[E500_CR_Bypass, E500_GPR_Bypass]>, [E500mc_CR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3, Repeat rate = 1 [6, 1], // Latency = 3, Repeat rate = 1
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>, InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass], [E500mc_GPR_Bypass, E500mc_GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>, InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass], [E500mc_GPR_Bypass, E500mc_GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStStore, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>, InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass], [NoBypass, E500mc_GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1, 1], // Latency = 3 [6, 1, 1], // Latency = 3
[E500_GPR_Bypass, [E500mc_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>, InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1, 1], // Latency = 3 [6, 1, 1], // Latency = 3
[E500_GPR_Bypass, [E500mc_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass], E500mc_GPR_Bypass, E500mc_GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[7, 1, 1], // Latency = 4 [7, 1, 1], // Latency = 4
[E500_FPR_Bypass, [E500mc_FPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>, InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[7, 1, 1], // Latency = 4 [7, 1, 1], // Latency = 4
[E500_FPR_Bypass, [E500mc_FPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass], E500mc_GPR_Bypass, E500mc_GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>, InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[7, 1, 1], // Latency = 4 [7, 1, 1], // Latency = 4
[E500_FPR_Bypass, [E500mc_FPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass], E500mc_GPR_Bypass, E500mc_GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>, InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1], 0>, InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[7, 1], // Latency = r+3 [7, 1], // Latency = r+3
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<3, [E500_LSU_0]>], InstrStage<3, [E500mc_LSU_0]>],
[6, 1, 1], // Latency = 3, Repeat rate = 3 [6, 1, 1], // Latency = 3, Repeat rate = 3
[E500_GPR_Bypass, [E500mc_GPR_Bypass,
E500_GPR_Bypass, E500_GPR_Bypass]>, E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>], InstrStage<1, [E500mc_LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_LdStSync, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_LSU_0]>]>, InstrStage<1, [E500mc_LSU_0]>]>,
InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<4, [E500_SFX0]>], InstrStage<4, [E500mc_SFX0]>],
[7, 1], [7, 1],
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<2, [E500_SFX0, E500_SFX1]>], InstrStage<2, [E500mc_SFX0, E500mc_SFX1]>],
[5, 1], // Latency = 2, Repeat rate = 4 [5, 1], // Latency = 2, Repeat rate = 4
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0]>], InstrStage<1, [E500mc_SFX0]>],
[5, 1], [5, 1],
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_LSU_0], 0>]>, InstrStage<1, [E500mc_LSU_0], 0>]>,
InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<5, [E500_SFX0]>], InstrStage<5, [E500mc_SFX0]>],
[8, 1], [8, 1],
[E500_GPR_Bypass, E500_CR_Bypass]>, [E500mc_GPR_Bypass, E500mc_CR_Bypass]>,
InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<5, [E500_SFX0]>], InstrStage<5, [E500mc_SFX0]>],
[8, 1], [8, 1],
[E500_GPR_Bypass, E500_CR_Bypass]>, [E500mc_GPR_Bypass, E500mc_CR_Bypass]>,
InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<4, [E500_SFX0]>], InstrStage<4, [E500mc_SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4 [7, 1], // Latency = 4, Repeat rate = 4
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<4, [E500_SFX0]>], InstrStage<4, [E500mc_SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4 [7, 1], // Latency = 4, Repeat rate = 4
[E500_GPR_Bypass, E500_GPR_Bypass]>, [E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1], // Latency = 1, Repeat rate = 1 [4, 1], // Latency = 1, Repeat rate = 1
[E500_GPR_Bypass, E500_CR_Bypass]>, [E500mc_GPR_Bypass, E500mc_CR_Bypass]>,
InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0]>], InstrStage<1, [E500mc_SFX0]>],
[4, 1], // Latency = 1, Repeat rate = 1 [4, 1], // Latency = 1, Repeat rate = 1
[E500_CR_Bypass, E500_GPR_Bypass]>, [E500mc_CR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<4, [E500_SFX0]>], InstrStage<4, [E500mc_SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4 [7, 1], // Latency = 4, Repeat rate = 4
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0, E500_SFX1]>], InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
[4, 1], // Latency = 1, Repeat rate = 1 [4, 1], // Latency = 1, Repeat rate = 1
[E500_CR_Bypass, E500_GPR_Bypass]>, [E500mc_CR_Bypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<1, [E500_SFX0]>], InstrStage<1, [E500mc_SFX0]>],
[4, 1], [4, 1],
[NoBypass, E500_GPR_Bypass]>, [NoBypass, E500mc_GPR_Bypass]>,
InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<2, [E500_FPU_0]>], InstrStage<2, [E500mc_FPU_0]>],
[11, 1, 1], // Latency = 8, Repeat rate = 2 [11, 1, 1], // Latency = 8, Repeat rate = 2
[E500_FPR_Bypass, [E500mc_FPR_Bypass,
E500_FPR_Bypass, E500_FPR_Bypass]>, E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<4, [E500_FPU_0]>], InstrStage<4, [E500mc_FPU_0]>],
[13, 1, 1], // Latency = 10, Repeat rate = 4 [13, 1, 1], // Latency = 10, Repeat rate = 4
[E500_FPR_Bypass, [E500mc_FPR_Bypass,
E500_FPR_Bypass, E500_FPR_Bypass]>, E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
InstrItinData<IIC_FPCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_FPCompare, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<2, [E500_FPU_0]>], InstrStage<2, [E500mc_FPU_0]>],
[11, 1, 1], // Latency = 8, Repeat rate = 2 [11, 1, 1], // Latency = 8, Repeat rate = 2
[E500_CR_Bypass, [E500mc_CR_Bypass,
E500_FPR_Bypass, E500_FPR_Bypass]>, E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_FPDivD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<68, [E500_FPU_0]>], InstrStage<68, [E500mc_FPU_0]>],
[71, 1, 1], // Latency = 68, Repeat rate = 68 [71, 1, 1], // Latency = 68, Repeat rate = 68
[E500_FPR_Bypass, [E500mc_FPR_Bypass,
E500_FPR_Bypass, E500_FPR_Bypass]>, E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_FPDivS, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<38, [E500_FPU_0]>], InstrStage<38, [E500mc_FPU_0]>],
[41, 1, 1], // Latency = 38, Repeat rate = 38 [41, 1, 1], // Latency = 38, Repeat rate = 38
[E500_FPR_Bypass, [E500mc_FPR_Bypass,
E500_FPR_Bypass, E500_FPR_Bypass]>, E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
InstrItinData<IIC_FPFused, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_FPFused, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<4, [E500_FPU_0]>], InstrStage<4, [E500mc_FPU_0]>],
[13, 1, 1, 1], // Latency = 10, Repeat rate = 4 [13, 1, 1, 1], // Latency = 10, Repeat rate = 4
[E500_FPR_Bypass, [E500mc_FPR_Bypass,
E500_FPR_Bypass, E500_FPR_Bypass, E500mc_FPR_Bypass, E500mc_FPR_Bypass,
E500_FPR_Bypass]>, E500mc_FPR_Bypass]>,
InstrItinData<IIC_FPRes, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>, InstrItinData<IIC_FPRes, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
InstrStage<38, [E500_FPU_0]>], InstrStage<38, [E500mc_FPU_0]>],
[41, 1], // Latency = 38, Repeat rate = 38 [41, 1], // Latency = 38, Repeat rate = 38
[E500_FPR_Bypass, E500_FPR_Bypass]> [E500mc_FPR_Bypass, E500mc_FPR_Bypass]>
]>; ]>;
// ===---------------------------------------------------------------------===// // ===---------------------------------------------------------------------===//
// e500mc machine model for scheduling and other instruction cost heuristics. // e500mc machine model for scheduling and other instruction cost heuristics.
def PPCE500mcModel : SchedMachineModel { def PPCE500mcModel : SchedMachineModel {
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
let LoadLatency = 5; // Optimistic load latency assuming bypass. let LoadLatency = 5; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the // This is overriden by OperandCycles if the
// Itineraries are queried instead. // Itineraries are queried instead.
let CompleteModel = 0; let CompleteModel = 0;
let Itineraries = PPCE500mcItineraries; let Itineraries = PPCE500mcItineraries;
} }

lib/Target/PowerPC/PPCSubtarget.h

Show All 40 Lines enum {
DIR_440, DIR_440,
DIR_601, DIR_601,
DIR_602, DIR_602,
DIR_603, DIR_603,
DIR_7400, DIR_7400,
DIR_750, DIR_750,
DIR_970, DIR_970,
DIR_A2, DIR_A2,
DIR_E500,
DIR_E500mc, DIR_E500mc,
DIR_E5500, DIR_E5500,
DIR_PWR3, DIR_PWR3,
DIR_PWR4, DIR_PWR4,
DIR_PWR5, DIR_PWR5,
DIR_PWR5X, DIR_PWR5X,
DIR_PWR6, DIR_PWR6,
DIR_PWR6X, DIR_PWR6X,
▲ Show 20 Lines • Show All 277 Lines • Show Last 20 Lines