[AArch64] Add patterns matching (fabs (fsub x y)) to (fabd x y)

[t.p.northover]

lib/Target/AArch64/AArch64InstrInfo.td

3090–3091

The 16-bit patterns should probably be guarded by a Requires = [HasNEON, HasFullFP16] clause (unless TableGen has changed so Pat instantiations inherit Requires, which actually wouldn't be a bad idea).

3407

Similar.

[john.brawn]

I'm pretty sure we never get to trying to match the patterns when we don't have FullFP16, due to differences in fp16 type legalization, but looking at AArch64GenAsmMatcher.inc there is indeed no predicate checking so it makes sense to add predicates here.

[john.brawn]

Ping.

[samparker]

LGTM.

lib/Target/AArch64/AArch64InstrInfo.td

 defm ADDP    : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
 defm CMEQ    : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
 defm CMGE    : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
 defm CMGT    : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
 defm CMHI    : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
 defm CMHS    : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
 defm CMTST   : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
 defm FABD    : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>;
+let Predicates = [HasNEON] in {
+foreach VT = [ v2f32, v4f32, v2f64 ] in
+def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>;
+}
+let Predicates = [HasNEON, HasFullFP16] in {
+foreach VT = [ v4f16, v8f16 ] in
+def : Pat<(fabs (fsub VT:$Rn, VT:$Rm)), (!cast<Instruction>("FABD"#VT) VT:$Rn, VT:$Rm)>;
+}
 defm FACGE   : SIMDThreeSameVectorFPCmp<1,0,0b101,"facge",int_aarch64_neon_facge>;
 defm FACGT   : SIMDThreeSameVectorFPCmp<1,1,0b101,"facgt",int_aarch64_neon_facgt>;
 defm FADDP   : SIMDThreeSameVectorFP<1,0,0b010,"faddp",int_aarch64_neon_addp>;
 defm FADD    : SIMDThreeSameVectorFP<0,0,0b010,"fadd", fadd>;
 defm FCMEQ   : SIMDThreeSameVectorFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>;
 defm FCMGE   : SIMDThreeSameVectorFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>;
 defm FCMGT   : SIMDThreeSameVectorFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>;
 defm FDIV    : SIMDThreeSameVectorFP<1,0,0b111,"fdiv", fdiv>;

 defm CMGE     : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
 defm CMGT     : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
 defm CMHI     : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
 defm CMHS     : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
 defm CMTST    : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
 defm FABD     : SIMDFPThreeScalar<1, 1, 0b010, "fabd", int_aarch64_sisd_fabd>;
 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
           (FABD64 FPR64:$Rn, FPR64:$Rm)>;
+let Predicates = [HasFullFP16] in {
+def : Pat<(fabs (fsub f16:$Rn, f16:$Rm)), (FABD16 f16:$Rn, f16:$Rm)>;
+}
+def : Pat<(fabs (fsub f32:$Rn, f32:$Rm)), (FABD32 f32:$Rn, f32:$Rm)>;
+def : Pat<(fabs (fsub f64:$Rn, f64:$Rm)), (FABD64 f64:$Rn, f64:$Rm)>;
 defm FACGE    : SIMDThreeScalarFPCmp<1, 0, 0b101, "facge",
                                      int_aarch64_neon_facge>;
 defm FACGT    : SIMDThreeScalarFPCmp<1, 1, 0b101, "facgt",
                                      int_aarch64_neon_facgt>;
 defm FCMEQ    : SIMDThreeScalarFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>;
 defm FCMGE    : SIMDThreeScalarFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>;
 defm FCMGT    : SIMDThreeScalarFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>;
 defm FMULX    : SIMDFPThreeScalar<0, 0, 0b011, "fmulx", int_aarch64_neon_fmulx>;

test/CodeGen/AArch64/arm64-vabs.ll

;CHECK: fabd.2d
         %tmp3 = call <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
         ret <2 x double> %tmp3
 }
 
 declare <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float>, <2 x float>) nounwind readnone
 declare <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float>, <4 x float>) nounwind readnone
 declare <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double>, <2 x double>) nounwind readnone
 
+define <2 x float> @fabd_2s_from_fsub_fabs(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK-LABEL: fabd_2s_from_fsub_fabs:
+;CHECK: fabd.2s
+        %tmp1 = load <2 x float>, <2 x float>* %A
+        %tmp2 = load <2 x float>, <2 x float>* %B
+        %sub = fsub <2 x float> %tmp1, %tmp2
+        %abs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %sub)
+        ret <2 x float> %abs
+}
+
+define <4 x float> @fabd_4s_from_fsub_fabs(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK-LABEL: fabd_4s_from_fsub_fabs:
+;CHECK: fabd.4s
+        %tmp1 = load <4 x float>, <4 x float>* %A
+        %tmp2 = load <4 x float>, <4 x float>* %B
+        %sub = fsub <4 x float> %tmp1, %tmp2
+        %abs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %sub)
+        ret <4 x float> %abs
+}
+
+define <2 x double> @fabd_2d_from_fsub_fabs(<2 x double>* %A, <2 x double>* %B) nounwind {
+;CHECK-LABEL: fabd_2d_from_fsub_fabs:
+;CHECK: fabd.2d
+        %tmp1 = load <2 x double>, <2 x double>* %A
+        %tmp2 = load <2 x double>, <2 x double>* %B
+        %sub = fsub <2 x double> %tmp1, %tmp2
+        %abs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %sub)
+        ret <2 x double> %abs
+}
+
+declare <2 x float> @llvm.fabs.v2f32(<2 x float>) nounwind readnone
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>) nounwind readnone
+declare <2 x double> @llvm.fabs.v2f64(<2 x double>) nounwind readnone
+
 define <8 x i8> @sabd_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: sabd_8b:
 ;CHECK: sabd.8b
         %tmp1 = load <8 x i8>, <8 x i8>* %A
         %tmp2 = load <8 x i8>, <8 x i8>* %B
         %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
         ret <8 x i8> %tmp3
 }

 ; CHECK: fabd d0, d0, d1
   %vabd.i = tail call double @llvm.aarch64.sisd.fabd.f64(double %a, double %b) nounwind
   ret double %vabd.i
 }
 
 declare double @llvm.aarch64.sisd.fabd.f64(double, double) nounwind readnone
 declare float @llvm.aarch64.sisd.fabd.f32(float, float) nounwind readnone
 
+define float @fabds_from_fsub_fabs(float %a, float %b) nounwind {
+; CHECK-LABEL: fabds_from_fsub_fabs:
+; CHECK: fabd s0, s0, s1
+  %sub = fsub float %a, %b
+  %abs = tail call float @llvm.fabs.f32(float %sub)
+  ret float %abs
+}
+
+define double @fabdd_from_fsub_fabs(double %a, double %b) nounwind {
+; CHECK-LABEL: fabdd_from_fsub_fabs:
+; CHECK: fabd d0, d0, d1
+  %sub = fsub double %a, %b
+  %abs = tail call double @llvm.fabs.f64(double %sub)
+  ret double %abs
+}
+
+declare float @llvm.fabs.f32(float) nounwind readnone
+declare double @llvm.fabs.f64(double) nounwind readnone
+
 define <2 x i64> @uabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
 ; CHECK-LABEL: uabdl_from_extract_dup:
 ; CHECK-NOT: ext.16b
 ; CHECK: uabdl2.2d
   %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
   %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
 
   %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>

test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll

 ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+v8.2a,+fullfp16  | FileCheck %s
 
 declare half @llvm.aarch64.sisd.fabd.f16(half, half)
 declare half @llvm.aarch64.neon.fmax.f16(half, half)
 declare half @llvm.aarch64.neon.fmin.f16(half, half)
 declare half @llvm.aarch64.neon.frsqrts.f16(half, half)
 declare half @llvm.aarch64.neon.frecps.f16(half, half)
 declare half @llvm.aarch64.neon.fmulx.f16(half, half)
+declare half @llvm.fabs.f16(half)
 
 define dso_local half @t_vabdh_f16(half %a, half %b) {
 ; CHECK-LABEL: t_vabdh_f16:
 ; CHECK:         fabd h0, h0, h1
 ; CHECK-NEXT:    ret
 entry:
   %vabdh_f16 = tail call half @llvm.aarch64.sisd.fabd.f16(half %a, half %b)
   ret half %vabdh_f16
 }
 
+define dso_local half @t_vabdh_f16_from_fsub_fabs(half %a, half %b) {
+; CHECK-LABEL: t_vabdh_f16_from_fsub_fabs:
+; CHECK:         fabd h0, h0, h1
+; CHECK-NEXT:    ret
+entry:
+  %sub = fsub half %a, %b
+  %abs = tail call half @llvm.fabs.f16(half %sub)
+  ret half %abs
+}
+
 define dso_local i16 @t_vceqh_f16(half %a, half %b) {
 ; CHECK-LABEL: t_vceqh_f16:
 ; CHECK:         fcmp h0, h1
 ; CHECK-NEXT:    csetm w0, eq
 ; CHECK-NEXT:    ret
 entry:
   %0 = fcmp oeq half %a, %b
   %vcmpd = sext i1 %0 to i16

test/CodeGen/AArch64/fp16_intrinsic_vector_2op.ll

 ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+v8.2a,+fullfp16  | FileCheck %s
 
 declare <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half>, <4 x half>)
 declare <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half>, <8 x half>)
 declare <4 x half> @llvm.aarch64.neon.fminnmp.v4f16(<4 x half>, <4 x half>)
 declare <8 x half> @llvm.aarch64.neon.fminnmp.v8f16(<8 x half>, <8 x half>)
 declare <4 x half> @llvm.aarch64.neon.fmaxnmp.v4f16(<4 x half>, <4 x half>)
 declare <8 x half> @llvm.aarch64.neon.fmaxnmp.v8f16(<8 x half>, <8 x half>)
+declare <4 x half> @llvm.aarch64.neon.fabd.v4f16(<4 x half>, <4 x half>)
+declare <8 x half> @llvm.aarch64.neon.fabd.v8f16(<8 x half>, <8 x half>)
+declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
+declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
 
 define dso_local <4 x half> @t_vdiv_f16(<4 x half> %a, <4 x half> %b) {
 ; CHECK-LABEL: t_vdiv_f16:
 ; CHECK:         fdiv v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
 entry:
   %div.i = fdiv <4 x half> %a, %b
   ret <4 x half> %div.i

 define dso_local <8 x half> @t_vpmaxnmq_f16(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: t_vpmaxnmq_f16:
 ; CHECK:         fmaxnmp v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
 entry:
   %vpmaxnm2.i = tail call <8 x half> @llvm.aarch64.neon.fmaxnmp.v8f16(<8 x half> %a, <8 x half> %b)
   ret <8 x half> %vpmaxnm2.i
 }
+
+define dso_local <4 x half> @t_vabd_f16(<4 x half> %a, <4 x half> %b) {
+; CHECK-LABEL: t_vabd_f16:
+; CHECK:         fabd v0.4h, v0.4h, v1.4h
+; CHECK-NEXT:    ret
+entry:
+  %vabdh_f16 = tail call <4 x half> @llvm.aarch64.neon.fabd.v4f16(<4 x half> %a, <4 x half> %b)
+  ret <4 x half> %vabdh_f16
+}
+
+define dso_local <8 x half> @t_vabdq_f16(<8 x half> %a, <8 x half> %b) {
+; CHECK-LABEL: t_vabdq_f16:
+; CHECK:         fabd v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    ret
+entry:
+  %vabdh_f16 = tail call <8 x half> @llvm.aarch64.neon.fabd.v8f16(<8 x half> %a, <8 x half> %b)
+  ret <8 x half> %vabdh_f16
+}
+
+define dso_local <4 x half> @t_vabd_f16_from_fsub_fabs(<4 x half> %a, <4 x half> %b) {
+; CHECK-LABEL: t_vabd_f16_from_fsub_fabs:
+; CHECK:         fabd v0.4h, v0.4h, v1.4h
+; CHECK-NEXT:    ret
+entry:
+  %sub = fsub <4 x half> %a, %b
+  %abs = tail call <4 x half> @llvm.fabs.v4f16(<4 x half> %sub)
+  ret <4 x half> %abs
+}
+
+define dso_local <8 x half> @t_vabdq_f16_from_fsub_fabs(<8 x half> %a, <8 x half> %b) {
+; CHECK-LABEL: t_vabdq_f16_from_fsub_fabs:
+; CHECK:         fabd v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    ret
+entry:
+  %sub = fsub <8 x half> %a, %b
+  %abs = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %sub)
+  ret <8 x half> %abs
+}