[InstSimplify] fp_binop X, NaN --> NaN

[spatel]

Summary

Building on the recent clarification of FP in IR and identical to current undef operand folding, fold any FP binop with a NaN operand to NaN.

I don't know what to do with the AMDGPU tests that expected to use a NaN FP constant as an int value.

[mike.dvoretsky]

lib/Analysis/InstructionSimplify.cpp

4168

Why are we emitting NaNs from an undef operand here?

4171

According to IEEE 754, we should preserve the payload bits of the NaN operand here (either one if both are NaN). This code creates a NaN with all payload bits unset instead.

[spatel]

lib/Analysis/InstructionSimplify.cpp

4168

See the recent discussion on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2018-March/121481.html

4171

As I understand it, preserving the payload is not required (cc @scanon ) - but we can do that if preferred. And maybe that will preserve the AMDGPU test behavior.

[scanon]

lib/Analysis/InstructionSimplify.cpp

4171

Preserving the payload is not required. It is *recommended* that the payload of the result be the payload of one of the operands, and if we can do that without additional complexity, let's do it. There is no defined rule for choosing which one, but ideally it should be commutative and associative.

Actual hardware implementations off the top of my head, in cases where both are NaN, either return the signaling NaN's payload if one is signaling, or return the "first" operand's payload ("first" in some machine-code assembly operand order), or return a default NaN (arm with DN bit set in FPCR, for example). Other behaviors are possible.

[spatel]

Patch updated:
Propagate the existing NaN constant. We don't try to quiet a signaling NaN. The only case where we would not return the existing constant is a vector with undef elements (in that case just return a default NaN).

This patch doesn't deal with cases where both operands are NaN. That's handled by constant folding. Evidence of that behavior is provided by the fneg tests in the test file (nothing changing here).

The AMDGPU tests now show the expected constant values (but I'm still not sure exactly what was intended in those tests).

[spatel]

In D44521#1040608, @spatel wrote:

This patch doesn't deal with cases where both operands are NaN. That's handled by constant folding. Evidence of that behavior is provided by the fneg tests in the test file (nothing changing here).

That wasn't clear: the fneg tests show evidence that a binop with 2 constant operands is already folded before we reach here. I'm not sure yet if we have test coverage for instructions with 2 NaN operands.

[nhaehnle]

For the AMDGPU imm tests, you could please change the affected ones to operate on i32/i16 instead, so that the result uses v_add_u32? Thanks!

I don't expect this approach to work for the double cases, I think you can just leave those as-is.

[spatel]

In D44521#1040958, @nhaehnle wrote:

For the AMDGPU imm tests, you could please change the affected ones to operate on i32/i16 instead, so that the result uses v_add_u32? Thanks!

I don't expect this approach to work for the double cases, I think you can just leave those as-is.

Do you mean bitcast back and forth? Example:

define amdgpu_kernel void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x) {
  %xbc = bitcast float %x to i32
  %y = add i32 %xbc, -1
  %ybc = bitcast i32 %y to float
  store float %ybc, float addrspace(1)* %out
  ret void
}

$ llc test/CodeGen/AMDGPU/imm.ll -o - -amdgpu-scalarize-global-loads=false  -march=amdgcn -mcpu=tonga -mattr=-flat-for-global
...
	s_load_dwordx2 s[4:5], s[0:1], 0x24
	s_load_dword s0, s[0:1], 0x2c
	s_mov_b32 s7, 0xf000
	s_mov_b32 s6, -1
	s_waitcnt lgkmcnt(0)
	v_add_f32_e64 v0, s0, -1.0
	buffer_store_dword v0, off, s[4:7], 0
	s_endpgm

[nhaehnle]

In D44521#1041180, @spatel wrote:

Do you mean bitcast back and forth? Example:

Yes, except I don't see how end up with -1.0 as inline constant in the v_add. Here's what I get, which looks more correct:

s_load_dwordx2 s[4:5], s[0:1], 0x24
s_load_dword s0, s[0:1], 0x2c
s_mov_b32 s7, 0xf000
s_mov_b32 s6, -1
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s0, -1
v_mov_b32_e32 v0, s0
buffer_store_dword v0, off, s[4:7], 0
s_endpgm

[spatel]

In D44521#1041564, @nhaehnle wrote:

In D44521#1041180, @spatel wrote:

Do you mean bitcast back and forth? Example:

Yes, except I don't see how end up with -1.0 as inline constant in the v_add. Here's what I get, which looks more correct:

s_load_dwordx2 s[4:5], s[0:1], 0x24
s_load_dword s0, s[0:1], 0x2c
s_mov_b32 s7, 0xf000
s_mov_b32 s6, -1
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s0, -1
v_mov_b32_e32 v0, s0
buffer_store_dword v0, off, s[4:7], 0
s_endpgm

Yes - I must've copy-pasted the wrong chunk here. I updated all of the AMDGPU tests other than the f64 ones to be independent of this patch:
rL327890
rL327891

[spatel]

Patch updated:
Removed AMDGPU tests that were made NaN-free.

[nhaehnle]

Thank you for making this change. The rest looks good to me, too.

lib/Analysis/InstructionSimplify.cpp

 }
 
 /// Given operands for a ShuffleVectorInst, fold the result or return null.
 Value *llvm::SimplifyShuffleVectorInst(Value *Op0, Value *Op1, Constant *Mask,
                                        Type *RetTy, const SimplifyQuery &Q) {
   return ::SimplifyShuffleVectorInst(Op0, Op1, Mask, RetTy, Q, RecursionLimit);
 }
 
+static Constant *propagateNaN(Constant *In) {
+  // If the input is a vector with undef elements, just return a default NaN.
+  if (!In->isNaN())
+    return ConstantFP::getNaN(In->getType());
+
+  // Propagate the existing NaN constant when possible.
+  // TODO: Should we quiet a signaling NaN?
+  return In;
+}
+
+static Constant *simplifyFPBinop(Value *Op0, Value *Op1) {
+  if (isa<UndefValue>(Op0) || isa<UndefValue>(Op1))
+    return ConstantFP::getNaN(Op0->getType());
+
+  if (match(Op0, m_NaN()))
+    return propagateNaN(cast<Constant>(Op0));
+  if (match(Op1, m_NaN()))
+    return propagateNaN(cast<Constant>(Op1));
+
+  return nullptr;
+}
+
 /// Given operands for an FAdd, see if we can fold the result.  If not, this
 /// returns null.
 static Value *SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF,
                                const SimplifyQuery &Q, unsigned MaxRecurse) {
   if (Constant *C = foldOrCommuteConstant(Instruction::FAdd, Op0, Op1, Q))
     return C;
 
-  if (isa<UndefValue>(Op0) || isa<UndefValue>(Op1))
-    return ConstantFP::getNaN(Op0->getType());
+  if (Constant *C = simplifyFPBinop(Op0, Op1))
+    return C;
 
   // fadd X, -0 ==> X
   if (match(Op1, m_NegZero()))
     return Op0;
 
   // fadd X, 0 ==> X, when we know X is not -0
   if (match(Op1, m_Zero()) &&
       (FMF.noSignedZeros() || CannotBeNegativeZero(Op0, Q.TLI)))

 
 /// Given operands for an FSub, see if we can fold the result.  If not, this
 /// returns null.
 static Value *SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF,
                                const SimplifyQuery &Q, unsigned MaxRecurse) {
   if (Constant *C = foldOrCommuteConstant(Instruction::FSub, Op0, Op1, Q))
     return C;
 
-  if (isa<UndefValue>(Op0) || isa<UndefValue>(Op1))
-    return ConstantFP::getNaN(Op0->getType());
+  if (Constant *C = simplifyFPBinop(Op0, Op1))
+    return C;
 
   // fsub X, 0 ==> X
   if (match(Op1, m_Zero()))
     return Op0;
 
   // fsub X, -0 ==> X, when we know X is not -0
   if (match(Op1, m_NegZero()) &&
       (FMF.noSignedZeros() || CannotBeNegativeZero(Op0, Q.TLI)))

 }
 
 /// Given the operands for an FMul, see if we can fold the result
 static Value *SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF,
                                const SimplifyQuery &Q, unsigned MaxRecurse) {
   if (Constant *C = foldOrCommuteConstant(Instruction::FMul, Op0, Op1, Q))
     return C;
 
-  if (isa<UndefValue>(Op0) || isa<UndefValue>(Op1))
-    return ConstantFP::getNaN(Op0->getType());
+  if (Constant *C = simplifyFPBinop(Op0, Op1))
+    return C;
 
   // fmul X, 1.0 ==> X
   if (match(Op1, m_FPOne()))
     return Op0;
 
   // fmul nnan nsz X, 0 ==> 0
   if (FMF.noNaNs() && FMF.noSignedZeros() && match(Op1, m_AnyZeroFP()))
     return ConstantFP::getNullValue(Op0->getType());
Value *llvm::SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF,
   return ::SimplifyFMulInst(Op0, Op1, FMF, Q, RecursionLimit);
 }
 
 static Value *SimplifyFDivInst(Value *Op0, Value *Op1, FastMathFlags FMF,
                                const SimplifyQuery &Q, unsigned) {
   if (Constant *C = foldOrCommuteConstant(Instruction::FDiv, Op0, Op1, Q))
     return C;
 
-  if (isa<UndefValue>(Op0) || isa<UndefValue>(Op1))
-    return ConstantFP::getNaN(Op0->getType());
+  if (Constant *C = simplifyFPBinop(Op0, Op1))
+    return C;
 
   // X / 1.0 -> X
   if (match(Op1, m_FPOne()))
     return Op0;
 
   // 0 / X -> 0
   // Requires that NaNs are off (X could be zero) and signed zeroes are
   // ignored (X could be positive or negative, so the output sign is unknown).
Value *llvm::SimplifyFDivInst(Value *Op0, Value *Op1, FastMathFlags FMF,
   return ::SimplifyFDivInst(Op0, Op1, FMF, Q, RecursionLimit);
 }
 
 static Value *SimplifyFRemInst(Value *Op0, Value *Op1, FastMathFlags FMF,
                                const SimplifyQuery &Q, unsigned) {
   if (Constant *C = foldOrCommuteConstant(Instruction::FRem, Op0, Op1, Q))
     return C;
 
-  if (isa<UndefValue>(Op0) || isa<UndefValue>(Op1))
-    return ConstantFP::getNaN(Op0->getType());
+  if (Constant *C = simplifyFPBinop(Op0, Op1))
+    return C;
 
   // Unlike fdiv, the result of frem always matches the sign of the dividend.
   // The constant match may include undef elements in a vector, so return a full
   // zero constant as the result.
   if (FMF.noNaNs()) {
     // 0 % X -> 0
     if (match(Op0, m_Zero()))
       return ConstantFP::getNullValue(Op0->getType());

test/CodeGen/AMDGPU/imm.ll

 ; GCN: buffer_store_dwordx2 [[REG]]
 define amdgpu_kernel void @add_inline_imm_16_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0x0000000000000010
   store double %y, double addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}add_inline_imm_neg_1_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -1
-; GCN: buffer_store_dwordx2 [[REG]]
+; GCN: v_mov_b32_e32 v0, -1
+; GCN: v_mov_b32_e32 v1, v0
+; GCN: buffer_store_dwordx2 v[0:1]
 define amdgpu_kernel void @add_inline_imm_neg_1_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0xffffffffffffffff
   store double %y, double addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}add_inline_imm_neg_2_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -2
-; GCN: buffer_store_dwordx2 [[REG]]
+; GCN: v_mov_b32_e32 v0, -2
+; GCN: v_mov_b32_e32 v1, -1
+; GCN: buffer_store_dwordx2 v[0:1]
 define amdgpu_kernel void @add_inline_imm_neg_2_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0xfffffffffffffffe
   store double %y, double addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}add_inline_imm_neg_16_f64:
-; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
-; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
-; GCN: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -16
-; GCN: buffer_store_dwordx2 [[REG]]
+; GCN: v_mov_b32_e32 v0, -16
+; GCN: v_mov_b32_e32 v1, -1
+; GCN: buffer_store_dwordx2 v[0:1]
 define amdgpu_kernel void @add_inline_imm_neg_16_f64(double addrspace(1)* %out, double %x) {
   %y = fadd double %x, 0xfffffffffffffff0
   store double %y, double addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}add_inline_imm_63_f64:
 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb

test/Transforms/InstSimplify/fp-nan.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 ; Default NaN constant
 
 define double @fadd_nan_op0(double %x) {
 ; CHECK-LABEL: @fadd_nan_op0(
-; CHECK-NEXT:    [[R:%.*]] = fadd double 0x7FF8000000000000, [[X:%.*]]
-; CHECK-NEXT:    ret double [[R]]
+; CHECK-NEXT:    ret double 0x7FF8000000000000
 ;
   %r = fadd double 0x7FF8000000000000, %x
   ret double %r
 }
 
 ; Sign bit is set
 
 define double @fadd_nan_op1(double %x) {
 ; CHECK-LABEL: @fadd_nan_op1(
-; CHECK-NEXT:    [[R:%.*]] = fadd double [[X:%.*]], 0xFFF8000000000000
-; CHECK-NEXT:    ret double [[R]]
+; CHECK-NEXT:    ret double 0xFFF8000000000000
 ;
   %r = fadd double %x, 0xFFF8000000000000
   ret double %r
 }
 
 ; Non-zero payload
 
 define float @fsub_nan_op0(float %x) {
 ; CHECK-LABEL: @fsub_nan_op0(
-; CHECK-NEXT:    [[R:%.*]] = fsub float 0x7FFFFF0000000000, [[X:%.*]]
-; CHECK-NEXT:    ret float [[R]]
+; CHECK-NEXT:    ret float 0x7FFFFF0000000000
 ;
   %r = fsub float 0x7FFFFF0000000000, %x
   ret float %r
 }
 
 ; Signaling
 
 define float @fsub_nan_op1(float %x) {
 ; CHECK-LABEL: @fsub_nan_op1(
-; CHECK-NEXT:    [[R:%.*]] = fsub float [[X:%.*]], 0x7FF1000000000000
-; CHECK-NEXT:    ret float [[R]]
+; CHECK-NEXT:    ret float 0x7FF1000000000000
 ;
   %r = fsub float %x, 0x7FF1000000000000
   ret float %r
 }
 
 ; Signaling and signed
 
 define double @fmul_nan_op0(double %x) {
 ; CHECK-LABEL: @fmul_nan_op0(
-; CHECK-NEXT:    [[R:%.*]] = fmul double 0xFFF0000000000001, [[X:%.*]]
-; CHECK-NEXT:    ret double [[R]]
+; CHECK-NEXT:    ret double 0xFFF0000000000001
 ;
   %r = fmul double 0xFFF0000000000001, %x
   ret double %r
 }
 
 ; Vector type
 
 define <2 x float> @fmul_nan_op1(<2 x float> %x) {
 ; CHECK-LABEL: @fmul_nan_op1(
-; CHECK-NEXT:    [[R:%.*]] = fmul <2 x float> [[X:%.*]], <float 0x7FF8000000000000, float 0x7FF8000000000000>
-; CHECK-NEXT:    ret <2 x float> [[R]]
+; CHECK-NEXT:    ret <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>
 ;
   %r = fmul <2 x float> %x, <float 0x7FF8000000000000, float 0x7FF8000000000000>
   ret <2 x float> %r
 }
 
 ; Vector signed and non-zero payload
 
 define <2 x double> @fdiv_nan_op0(<2 x double> %x) {
 ; CHECK-LABEL: @fdiv_nan_op0(
-; CHECK-NEXT:    [[R:%.*]] = fdiv <2 x double> <double 0xFFF800000000000F, double 0xFFF800000000000F>, [[X:%.*]]
-; CHECK-NEXT:    ret <2 x double> [[R]]
+; CHECK-NEXT:    ret <2 x double> <double 0xFFF800000000000F, double 0xFFF800000000000F>
 ;
   %r = fdiv <2 x double> <double 0xFFF800000000000F, double 0xFFF800000000000F>, %x
   ret <2 x double>  %r
 }
 
 ; Vector with different NaN constant elements
 
 define <2 x half> @fdiv_nan_op1(<2 x half> %x) {
 ; CHECK-LABEL: @fdiv_nan_op1(
-; CHECK-NEXT:    [[R:%.*]] = fdiv <2 x half> [[X:%.*]], <half 0xH7FFF, half 0xHFF00>
-; CHECK-NEXT:    ret <2 x half> [[R]]
+; CHECK-NEXT:    ret <2 x half> <half 0xH7FFF, half 0xHFF00>
 ;
   %r = fdiv <2 x half> %x, <half 0xH7FFF, half 0xHFF00>
   ret <2 x half> %r
 }
 
 ; Vector with undef element
 
 define <2 x double> @frem_nan_op0(<2 x double> %x) {
 ; CHECK-LABEL: @frem_nan_op0(
-; CHECK-NEXT:    [[R:%.*]] = frem <2 x double> <double 0xFFFF000000000000, double undef>, [[X:%.*]]
-; CHECK-NEXT:    ret <2 x double> [[R]]
+; CHECK-NEXT:    ret <2 x double> <double 0x7FF8000000000000, double 0x7FF8000000000000>
 ;
   %r = frem <2 x double> <double 0xFFFF000000000000, double undef>, %x
   ret <2 x double> %r
 }
 
 define float @frem_nan_op1(float %x) {
 ; CHECK-LABEL: @frem_nan_op1(
-; CHECK-NEXT:    [[R:%.*]] = frem float [[X:%.*]], 0x7FF8000000000000
-; CHECK-NEXT:    ret float [[R]]
+; CHECK-NEXT:    ret float 0x7FF8000000000000
 ;
   %r = frem float %x, 0x7FF8000000000000
   ret float %r
 }
 
 ; Special-case: fneg must only change the sign bit (this is handled by constant folding).
 
 define double @fneg_nan_1(double %x) {
;
   %r = fsub <2 x double> <double -0.0, double -0.0>, <double 0xFFF1234567890ABC, double 0x7FF0000000000001>
   ret <2 x double> %r
 }
 
 ; Repeat all tests with fast-math-flags. Alternate 'nnan' and 'fast' for more coverage.
 
 define float @fadd_nan_op0_nnan(float %x) {
 ; CHECK-LABEL: @fadd_nan_op0_nnan(
-; CHECK-NEXT:    [[R:%.*]] = fadd nnan float 0x7FF8000000000000, [[X:%.*]]
-; CHECK-NEXT:    ret float [[R]]
+; CHECK-NEXT:    ret float 0x7FF8000000000000
 ;
   %r = fadd nnan float 0x7FF8000000000000, %x
   ret float %r
 }
 
 define float @fadd_nan_op1_fast(float %x) {
 ; CHECK-LABEL: @fadd_nan_op1_fast(
-; CHECK-NEXT:    [[R:%.*]] = fadd fast float [[X:%.*]], 0x7FF8000000000000
-; CHECK-NEXT:    ret float [[R]]
+; CHECK-NEXT:    ret float 0x7FF8000000000000
 ;
   %r = fadd fast float %x, 0x7FF8000000000000
   ret float %r
 }
 
 define float @fsub_nan_op0_fast(float %x) {
 ; CHECK-LABEL: @fsub_nan_op0_fast(
-; CHECK-NEXT:    [[R:%.*]] = fsub fast float 0x7FF8000000000000, [[X:%.*]]
-; CHECK-NEXT:    ret float [[R]]
+; CHECK-NEXT:    ret float 0x7FF8000000000000
 ;
   %r = fsub fast float 0x7FF8000000000000, %x
   ret float %r
 }
 
 define float @fsub_nan_op1_nnan(float %x) {
 ; CHECK-LABEL: @fsub_nan_op1_nnan(
-; CHECK-NEXT:    [[R:%.*]] = fsub nnan float [[X:%.*]], 0x7FF8000000000000
-; CHECK-NEXT:    ret float [[R]]
+; CHECK-NEXT:    ret float 0x7FF8000000000000
 ;
   %r = fsub nnan float %x, 0x7FF8000000000000
   ret float %r
 }
 
 define float @fmul_nan_op0_nnan(float %x) {
 ; CHECK-LABEL: @fmul_nan_op0_nnan(
-; CHECK-NEXT:    [[R:%.*]] = fmul nnan float 0x7FF8000000000000, [[X:%.*]]
-; CHECK-NEXT:    ret float [[R]]
+; CHECK-NEXT:    ret float 0x7FF8000000000000
 ;
   %r = fmul nnan float 0x7FF8000000000000, %x
   ret float %r
 }
 
 define float @fmul_nan_op1_fast(float %x) {
 ; CHECK-LABEL: @fmul_nan_op1_fast(
-; CHECK-NEXT:    [[R:%.*]] = fmul fast float [[X:%.*]], 0x7FF8000000000000
-; CHECK-NEXT:    ret float [[R]]
+; CHECK-NEXT:    ret float 0x7FF8000000000000
 ;
   %r = fmul fast float %x, 0x7FF8000000000000
   ret float %r
 }
 
 define float @fdiv_nan_op0_fast(float %x) {
 ; CHECK-LABEL: @fdiv_nan_op0_fast(
-; CHECK-NEXT:    [[R:%.*]] = fdiv fast float 0x7FF8000000000000, [[X:%.*]]
-; CHECK-NEXT:    ret float [[R]]
+; CHECK-NEXT:    ret float 0x7FF8000000000000
 ;
   %r = fdiv fast float 0x7FF8000000000000, %x
   ret float %r
 }
 
 define float @fdiv_nan_op1_nnan(float %x) {
 ; CHECK-LABEL: @fdiv_nan_op1_nnan(
-; CHECK-NEXT:    [[R:%.*]] = fdiv nnan float [[X:%.*]], 0x7FF8000000000000
-; CHECK-NEXT:    ret float [[R]]
+; CHECK-NEXT:    ret float 0x7FF8000000000000
 ;
   %r = fdiv nnan float %x, 0x7FF8000000000000
   ret float %r
 }
 
 define float @frem_nan_op0_nnan(float %x) {
 ; CHECK-LABEL: @frem_nan_op0_nnan(
-; CHECK-NEXT:    [[R:%.*]] = frem nnan float 0x7FF8000000000000, [[X:%.*]]
-; CHECK-NEXT:    ret float [[R]]
+; CHECK-NEXT:    ret float 0x7FF8000000000000
 ;
   %r = frem nnan float 0x7FF8000000000000, %x
   ret float %r
 }
 
 define float @frem_nan_op1_fast(float %x) {
 ; CHECK-LABEL: @frem_nan_op1_fast(
-; CHECK-NEXT:    [[R:%.*]] = frem fast float [[X:%.*]], 0x7FF8000000000000
-; CHECK-NEXT:    ret float [[R]]
+; CHECK-NEXT:    ret float 0x7FF8000000000000
 ;
   %r = frem fast float %x, 0x7FF8000000000000
   ret float %r
 }