[WebAssembly] Added initial AsmParser implementation.

[aardappel]

Summary

It uses the MC framework and the tablegen matcher to do the
heavy lifting. Can handle both explicit and implicit locals
(-disable-wasm-explicit-locals). Comes with a small regression
test.

This is a first basic implementation that can parse most llvm .s
output and round-trips most instructions succesfully, but in order
to keep the commit small, does not address all issues.

There are a fair number of mismatches between what MC / assembly
matcher think a "CPU" should look like and what WASM provides,
some already have workarounds in this commit (e.g. the way it
deals with register operands) and some that require further work.
Some of that further work may involve changing what the
Disassembler outputs (and what s2wasm parses), so are probably
best left to followups.

Some known things missing:

• Many directives are ignored and not emitted.
• Vararg calls are parsed but extra args not emitted.
• Loop signatures are likely incorrect.
• $drop= is not emitted.
• Disassembler does not output SIMD types correctly, so assembler can't test them.

[aardappel]

Fixed out of date comments in WebAssemblyParser.cpp

[jgravelle-google]

WIP review, read up through WebAssemblyAsmParser::ParseInstruction

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

35

Nit: I feel this should be "wasm-asm-parser"? The other targets define this as:

lib/Target/ARM/AsmParser/ARMAsmParser.cpp:#define DEBUG_TYPE "asm-parser"
lib/Target/Mips/AsmParser/MipsAsmParser.cpp:#define DEBUG_TYPE "mips-asm-parser"
lib/Target/AVR/AsmParser/AVRAsmParser.cpp:#define DEBUG_TYPE "avr-asm-parser"
lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp:#define DEBUG_TYPE "mcasmparser"

so it probably doesn't really matter.

83

The repetition here makes me think something is odd, but I'm not convinced that other designs would be better.

One thing that might reduce the conceptual repetition is changing SMLoc Start, SMLoc End to AsmToken Tok, and just calling Tok.getLoc()/Tok.getEndLoc() from here, instead of at each callsite.

118

Nit: "not" -> "Not", for consistent capitalization

285

Typo: should be ParseSingleInteger?

291

Wait, is truthiness here used to represent failure? That's... confusing.
Oh, that's overridden from MCTargetAsmParser::ParseInstruction, cool.

320

... I feel like this sort of thing might be cleaner with a #define ERR_IF(x) if(x) { return true; } macro, but I may be in the minority there.

[aardappel]

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

83

There is one call-site (for one instance of TokOp) where no token is available, so the best I can do is make all of em use Tok and then still have one at that has 2 SMLoc's. Not sure if that is much cleaner in total.

291

Yup, just following along with what LLVM does here.

320

I'd just swap the truthyness. Since the rest of the code doesn't use such a macro, there's little point I'm afraid.

[aardappel]

Minor changes due to @jgravelle-google's review.

[dschuff]

looking pretty good overall, here are a couple of high-level comments.

lib/MC/MCExpr.cpp

402

Wow, is it just me or did the diff engine really screw this file up :/

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

215

There are a couple of confusing things to me about this. First, the SIMD proposal has only one value type (v128) and the wasm backend has a corresponding register class (V128) into which all the SIMD MVTs (v4f32 et al) can go. But in the assembly language the scalar instructions use the value type name in their mnemonic and the SIMD instructions use the lane division interpretation names. So that's a bit of inherent weirdness that will have to be reflected in this code somewhere. But the other thing is that this function is named ParseRegType which to me would indicate the type of register (i.e. register class which in C++ code would be e.g. WebAssembly::I32RegClass), but what it returns is actually a physical register number. What we maybe actually want is to reflect either a wasm value type (although it looks like that's maybe not actually even reflected directly in the MIR, just in the binary format) or an MVT (e.g. MVT::i32 or MVT::v4f32).

... ok actually looking at the way these reg types are used I now actually understand the comment you wrote in WebAssemblyOperand::RegOp. Not sure I have a better idea right now. I guess it's because the generated matcher expects the reg operand to be one of the physical registers and validates that?

249

Up until now, the stack "reg" numbers on the "$push" and "$pop" tokens were really just annotations for readability, (because of course the operands push and pop on the stack in a defined order). So far nothing has actually depended on those notations, and this seems to be adding that dependence. Not that we absolutely can't do that; but it would be nice if we didn't have to. It looks like it might make this code more awkward though, because it appears that we are just getting the lexer tokens in order, and we'd maybe have to buffer them or something before processing them in right-to-left order. Am I understanding this correctly?

291

There are a lot of places in LLVM backends that return true for failure and false for success ¯\_(ツ)_/¯
edit: actually there doesn't appear to be a failure path in this function, but its caller below clearly expects that possibility?

[aardappel]

lib/MC/MCExpr.cpp

402

whatever diff this uses seems generally much worse than github/gerrit/critique..

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

35

I'll change it anyway, seems more logical to have a -

215

Yes, this was originally to please the generated matcher. Though looking at the code, it seems the different v128 layouts are only needed for emitParam / emitLocal, whereas the matcher would be fine with generic registers. I can try splitting these up and reverting to a single physical register type, and see if it still works.

249

The generated matcher does need registers in pretty much the same locations as these, so thats why it seemed natural to follow along. Certainly the number part is non-essential, since I am essentially re-using the assignment from the disassembler, though to accept code that does not have these numbers, I presume I would have to track a stack to able to assign them myself. That's not hard, but also not entirely trivial, so that may be a nice thing to do for a followup. In fact, I think it be nice to be able to not require these at all, and completely skip them on parse, and have a mode (initially for the non-elf path) that makes the dissassembler not output them either. Opinions welcome.

291

I'm guessing this originally had code that could fail parsing in it.. I'll make it void.

[sbc100]

lib/Target/WebAssembly/CMakeLists.txt

10

This diff looks message up to. How did you generate/upload this diff? arc diff?

55

And this one..

[dschuff]

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

249

Yeah, that was sort of what I was getting at. s2wasm ignores the numbers entirely and tracks the stack itself. I do think it would be nice to not need them at all.

I think It sort of comes down to what we want the assembly language to look like. The non-ELF path will soon be the only path, so we don't need to worry about it for the long term. I think my preference for the language would be to keep it simpler and not require the numbers. This would require the assembler to track the stack, but even if it used the numbers, it would probably need to validate them anyway so overall it wouldn't be much different. I do actually like having the numbers as an annotation though (it makes the asm easier to read), and there is a way to attach annotations to assembly output, so maybe we should use it for that.

[aardappel]

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

249

agreed. I think it should be an option for the dissassembler (I personally would prefer to read the code without them), and the assemble should permit but ignore them.

Tracking the stack myself may be a bit more interesting than usual, since the current assembler code has no idea of instruction semantics, it leaves all of that to the table-gen matcher. So I'd need to at least dip into the table-gen to extract information on instruction signature if I want to avoid hard-coding any of that.

lib/Target/WebAssembly/CMakeLists.txt

10

git format-patch, as recommended by https://llvm.org/docs/Phabricator.html. I'll try arc for my next PR.

[jgravelle-google]

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

249

To throw my own opinions in the mix,
Design goals I think are important:

1. the .s syntax should be easy to read
2. it should support inline asm fairly easily

To that end we could take and existing (wasm-elf) .s:

i32.const $push3=, 0
i32.load  $push2=, __stack_pointer($pop3)
i32.const $push4=, 16
i32.sub   $1=, $pop2, $pop4

and write it as

i32.const 0
i32.load  offset=__stack_pointer
i32.const 16
i32.sub
set_local 1

which is generally identical to .wat. We (in principle) can do this because the push/pop annotations are essentially cosmetic: we know them statically on a per-opcode basis. (This is almost certainly less the case for function calls.)
This should be the easiest thing to write inline asm for, and map most directly to the official text format, which should help the learning curve.

As a secondary idea, we keep the numbers, but observe that we can reuse virtual registers / stack slots after popping. Then the number refers to the depth of the stack at any given point. This also serves as a proxy for register pressure in the engines.

i32.const $push0=, 0
i32.load  $push0=, __stack_pointer($pop0)
i32.const $push1=, 16
i32.sub   $1=, $pop0, $pop1

[dschuff]

I think i'd be in favor of letting this patch go in as it is for now, since it uses our existing syntax, and then have a separate discussion of how to change it on tool-conventions.

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

249

Yeah, when formatted as an annotation the push/pop labels would probably end up looking something like this, when using explicit locals:

i32.const 0   #  push3
i32.load  offset=__stack_pointer    #  pop3
i32.const 16  #  push4
i32.sub    # pop4, pop3, push4
set_local 1 # pop5

Without explicit locals it gets more interesting because the actual parsed syntax is different from the spec (and of course we have to parse it). In that case it might make more sense to also explicitly print/parse pop operations.

But anyway we shouldn't be having this discussion here, an issue on tool-conventions probably makes more sense.

[aardappel]

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

215

Refactored how register types and layout are handled, and reverted to a single SIMD register in the latest patch.

249

Agreed. I'm fine either making them optional and ignored (in wasm mode, not elf), or comments, or omitted all-together. I am assuming this will be in a follow-up though. I can start a conversation on tool-conventions to include everyone.

[aardappel]

Addressing all comments so far, except for the removal of $push etc annotations.

[dschuff]

LGTM.

[sbc100]

Want to land this @dschuff ? Or I can if you prefer.

lib/Target/WebAssembly/WebAssemblyRegisterInfo.td

39–44

"used a" -> "used as"

lib/MC/MCExpr.cpp

return StringSwitch<VariantKind>(Name.lower())
     .Case("dtprel@higher", VK_PPC_DTPREL_HIGHER)
     .Case("dtprel@highera", VK_PPC_DTPREL_HIGHERA)
     .Case("dtprel@highest", VK_PPC_DTPREL_HIGHEST)
     .Case("dtprel@highesta", VK_PPC_DTPREL_HIGHESTA)
     .Case("got@tprel", VK_PPC_GOT_TPREL)
     .Case("got@tprel@l", VK_PPC_GOT_TPREL_LO)
     .Case("got@tprel@h", VK_PPC_GOT_TPREL_HI)
     .Case("got@tprel@ha", VK_PPC_GOT_TPREL_HA)
-    .Case("got@dtprel", VK_PPC_GOT_DTPREL)
-    .Case("got@dtprel@l", VK_PPC_GOT_DTPREL_LO)
-    .Case("got@dtprel@h", VK_PPC_GOT_DTPREL_HI)
-    .Case("got@dtprel@ha", VK_PPC_GOT_DTPREL_HA)
-    .Case("got@tlsgd", VK_PPC_GOT_TLSGD)
-    .Case("got@tlsgd@l", VK_PPC_GOT_TLSGD_LO)
-    .Case("got@tlsgd@h", VK_PPC_GOT_TLSGD_HI)
-    .Case("got@tlsgd@ha", VK_PPC_GOT_TLSGD_HA)
-    .Case("got@tlsld", VK_PPC_GOT_TLSLD)
-    .Case("got@tlsld@l", VK_PPC_GOT_TLSLD_LO)
-    .Case("got@tlsld@h", VK_PPC_GOT_TLSLD_HI)
-    .Case("got@tlsld@ha", VK_PPC_GOT_TLSLD_HA)
-    .Case("gdgot", VK_Hexagon_GD_GOT)
-    .Case("gdplt", VK_Hexagon_GD_PLT)
-    .Case("iegot", VK_Hexagon_IE_GOT)
-    .Case("ie", VK_Hexagon_IE)
-    .Case("ldgot", VK_Hexagon_LD_GOT)
-    .Case("ldplt", VK_Hexagon_LD_PLT)
-    .Case("pcrel", VK_Hexagon_PCREL)
-    .Case("none", VK_ARM_NONE)
-    .Case("got_prel", VK_ARM_GOT_PREL)
-    .Case("target1", VK_ARM_TARGET1)
-    .Case("target2", VK_ARM_TARGET2)
-    .Case("prel31", VK_ARM_PREL31)
-    .Case("sbrel", VK_ARM_SBREL)
-    .Case("tlsldo", VK_ARM_TLSLDO)
-    .Case("lo8", VK_AVR_LO8)
-    .Case("hi8", VK_AVR_HI8)
-    .Case("hlo8", VK_AVR_HLO8)
+    .Case("got@dtprel", VK_PPC_GOT_DTPREL)
+    .Case("got@dtprel@l", VK_PPC_GOT_DTPREL_LO)
+    .Case("got@dtprel@h", VK_PPC_GOT_DTPREL_HI)
+    .Case("got@dtprel@ha", VK_PPC_GOT_DTPREL_HA)
+    .Case("got@tlsgd", VK_PPC_GOT_TLSGD)
+    .Case("got@tlsgd@l", VK_PPC_GOT_TLSGD_LO)
+    .Case("got@tlsgd@h", VK_PPC_GOT_TLSGD_HI)
+    .Case("got@tlsgd@ha", VK_PPC_GOT_TLSGD_HA)
+    .Case("got@tlsld", VK_PPC_GOT_TLSLD)
+    .Case("got@tlsld@l", VK_PPC_GOT_TLSLD_LO)
+    .Case("got@tlsld@h", VK_PPC_GOT_TLSLD_HI)
+    .Case("got@tlsld@ha", VK_PPC_GOT_TLSLD_HA)
+    .Case("gdgot", VK_Hexagon_GD_GOT)
+    .Case("gdplt", VK_Hexagon_GD_PLT)
+    .Case("iegot", VK_Hexagon_IE_GOT)
+    .Case("ie", VK_Hexagon_IE)
+    .Case("ldgot", VK_Hexagon_LD_GOT)
+    .Case("ldplt", VK_Hexagon_LD_PLT)
+    .Case("pcrel", VK_Hexagon_PCREL)
+    .Case("none", VK_ARM_NONE)
+    .Case("got_prel", VK_ARM_GOT_PREL)
+    .Case("target1", VK_ARM_TARGET1)
+    .Case("target2", VK_ARM_TARGET2)
+    .Case("prel31", VK_ARM_PREL31)
+    .Case("sbrel", VK_ARM_SBREL)
+    .Case("tlsldo", VK_ARM_TLSLDO)
+    .Case("lo8", VK_AVR_LO8)
+    .Case("hi8", VK_AVR_HI8)
+    .Case("hlo8", VK_AVR_HLO8)
+    .Case("function", VK_WebAssembly_FUNCTION)
+    .Case("typeindex", VK_WebAssembly_TYPEINDEX)
     .Case("gotpcrel32@lo", VK_AMDGPU_GOTPCREL32_LO)
     .Case("gotpcrel32@hi", VK_AMDGPU_GOTPCREL32_HI)
     .Case("rel32@lo", VK_AMDGPU_REL32_LO)
     .Case("rel32@hi", VK_AMDGPU_REL32_HI)
     .Default(VK_Invalid);
 }
 
 void MCSymbolRefExpr::printVariantKind(raw_ostream &OS) const {

lib/Target/WebAssembly/AsmParser/CMakeLists.txt

+add_llvm_library(LLVMWebAssemblyAsmParser
+  WebAssemblyAsmParser.cpp
+  )

lib/Target/WebAssembly/AsmParser/LLVMBuild.txt

+;===-- ./lib/Target/WebAssembly/Disassembler/LLVMBuild.txt -----*- Conf -*--===;
+;
+;                     The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+;   http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = WebAssemblyAsmParser
+parent = WebAssembly
+required_libraries = MC MCParser WebAssemblyInfo Support
+add_to_library_groups = WebAssembly

lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

+//==- WebAssemblyAsmParser.cpp - Assembler for WebAssembly -*- C++ -*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// \brief This file is part of the WebAssembly Assembler.
+///
+/// It contains code to translate a parsed .s file into MCInsts.
+///
+//===----------------------------------------------------------------------===//
+
+#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
+#include "MCTargetDesc/WebAssemblyTargetStreamer.h"
+#include "WebAssembly.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCParser/MCTargetAsmParser.h"
+#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCSymbol.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/Support/Endian.h"
+#include "llvm/Support/TargetRegistry.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "wasm-asmparser"
+
+namespace {
+
+/// WebAssemblyOperand - Instances of this class represent the operands in a
+/// parsed WASM machine instruction.
+struct WebAssemblyOperand : public MCParsedAsmOperand {
+  enum KindTy { Token, Local, Stack, Integer, Float, Symbol } Kind;
+
+  SMLoc StartLoc, EndLoc;
+
+  struct TokOp {
+    StringRef Tok;
+  };
+
+  struct RegOp {
+    // This is a (virtual) local or stack register represented as 0..
+    unsigned RegNo;
+    // This uses the fixed registers enum, because that is what the
+    // generated asm matcher expects when it calls getReg(). This enum cannot
+    // easily represent RegNo since we have an unbounded number of differently
+    // typed registers.
+    // It also calls addRegOperands to generate the MCInst, where we can pass
+    // RegNo instead, ensuring correct code generation.
+    // TODO: This "works", but it would be nice to clean this up further.
+    unsigned RegType;
+  };
+
+  struct IntOp {
+    int64_t Val;
+  };
+
+  struct FltOp {
+    double Val;
+  };
+
+  struct SymOp {
+    const MCExpr *Exp;
+  };
+
+  union {
+    struct TokOp Tok;
+    struct RegOp Reg;
+    struct IntOp Int;
+    struct FltOp Flt;
+    struct SymOp Sym;
+  };
+
+  WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, TokOp T)
+    : Kind(K), StartLoc(Start), EndLoc(End), Tok(T) {}
+  WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, RegOp R)
+    : Kind(K), StartLoc(Start), EndLoc(End), Reg(R) {}
+  WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, IntOp I)
+    : Kind(K), StartLoc(Start), EndLoc(End), Int(I) {}
+  WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, FltOp F)
+    : Kind(K), StartLoc(Start), EndLoc(End), Flt(F) {}
+  WebAssemblyOperand(KindTy K, SMLoc Start, SMLoc End, SymOp S)
+    : Kind(K), StartLoc(Start), EndLoc(End), Sym(S) {}
+
+  bool isToken() const override { return Kind == Token; }
+  bool isImm() const override { return Kind == Integer ||
+                                       Kind == Float ||
+                                       Kind == Symbol; }
+  bool isReg() const override { return Kind == Local || Kind == Stack; }
+  bool isMem() const override { return false; }
+
+  unsigned getReg() const override {
+    assert(isReg());
+    // This is called from the tablegen matcher (MatchInstructionImpl)
+    // where it expects to match the type of register, see RegOp above.
+    return Reg.RegType;
+  }
+
+  StringRef getToken() const {
+    assert(isToken());
+    return Tok.Tok;
+  }
+
+  SMLoc getStartLoc() const override { return StartLoc; }
+  SMLoc getEndLoc() const override { return EndLoc; }
+
+  void addRegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    assert(isReg() && "not a register operand!");
+    // This is called from the tablegen matcher (MatchInstructionImpl)
+    // where it expects to output the actual register index, see RegOp above.
+    unsigned R = Reg.RegNo;
+    if (Kind == Stack) {
+      // A stack register is represented as a large negative number.
+      // See WebAssemblyRegNumbering::runOnMachineFunction and
+      // getWARegStackId for why this | is needed.
+      R |= INT32_MIN;
+    }
+    Inst.addOperand(MCOperand::createReg(R));
+  }
+
+  void addImmOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    if (Kind == Integer)
+      Inst.addOperand(MCOperand::createImm(Int.Val));
+    else if (Kind == Float)
+      Inst.addOperand(MCOperand::createFPImm(Flt.Val));
+    else if (Kind == Symbol)
+      Inst.addOperand(MCOperand::createExpr(Sym.Exp));
+    else
+      llvm_unreachable("Should be immediate or symbol!");
+  }
+
+  void print(raw_ostream &OS) const override {
+    switch (Kind) {
+    case Token:
+      OS << "Tok:" << Tok.Tok;
+      break;
+    case Local:
+      OS << "Loc:" << Reg.RegNo << ":" << Reg.RegType;
+      break;
+    case Stack:
+      OS << "Stk:" << Reg.RegNo << ":" << Reg.RegType;
+      break;
+    case Integer:
+      OS << "Int:" << Int.Val;
+      break;
+    case Float:
+      OS << "Flt:" << Flt.Val;
+      break;
+    case Symbol:
+      OS << "Sym:" << Sym.Exp;
+      break;
+    }
+  }
+};
+
+class WebAssemblyAsmParser final : public MCTargetAsmParser {
+  MCAsmParser &Parser;
+  MCAsmLexer &Lexer;
+  // These are for the current function being parsed:
+  // These are vectors since register assignments are so far non-sparse.
+  // Replace by map if necessary.
+  std::vector<unsigned> LocalTypes;
+  std::vector<unsigned> StackTypes;
+  MCSymbol *LastLabel;
+
+public:
+  WebAssemblyAsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
+                       const MCInstrInfo &mii, const MCTargetOptions &Options)
+      : MCTargetAsmParser(Options, sti, mii), Parser(Parser),
+        Lexer(Parser.getLexer()), LastLabel(nullptr) {
+  }
+
+#define GET_ASSEMBLER_HEADER
+#include "WebAssemblyGenAsmMatcher.inc"
+
+  // TODO: This is required to be implemented, but appears unused.
+  bool ParseRegister(unsigned &/*RegNo*/, SMLoc &/*StartLoc*/,
+                     SMLoc &/*EndLoc*/) override {
+    llvm_unreachable("ParseRegister is not implemented.");
+  }
+
+  bool Error(const StringRef &msg, const AsmToken &tok) {
+    return Parser.Error(tok.getLoc(), msg + tok.getString());
+  }
+
+  bool IsNext(AsmToken::TokenKind Kind) {
+    auto ok = Lexer.is(Kind);
+    if (ok) Parser.Lex();
+    return ok;
+  }
+
+  bool Expect(AsmToken::TokenKind Kind, const char *KindName) {
+    if (!IsNext(Kind))
+      return Error(std::string("Expected ") + KindName + ", instead got: ",
+                   Lexer.getTok());
+    return false;
+  }
+
+  unsigned ParseRegType(const StringRef &RegType) {
+    // Derive type from .param .local decls, or the instruction itself.
+    return StringSwitch<unsigned>(RegType)
+        .Case("i32", WebAssembly::I32_0)
+        .Case("i64", WebAssembly::I64_0)
+        .Case("f32", WebAssembly::F32_0)
+        .Case("f64", WebAssembly::F64_0)
+        .Case("i8x16", WebAssembly::V16I8_0)
+        .Case("i16x8", WebAssembly::V8I16_0)
+        .Case("i32x4", WebAssembly::V4I32_0)
+        .Case("f32x4", WebAssembly::V4F32_0)
+        .Default(WebAssembly::NoRegister);
+  }
+
+  unsigned &GetType(std::vector<unsigned> &Types, size_t i) {
+    Types.resize(std::max(i + 1, Types.size()), WebAssembly::NoRegister);
+    return Types[i];
+  }
+
+  bool ParseReg(OperandVector &Operands, StringRef TypePrefix) {
+    if (Lexer.is(AsmToken::Integer)) {
+      auto &Local = Lexer.getTok();
+      // This is a reference to a local, turn it into a virtual register.
+      auto LocalNo = static_cast<unsigned>(Local.getIntVal());
+      Operands.push_back(make_unique<WebAssemblyOperand>(
+                           WebAssemblyOperand::Local, Local.getLoc(),
+                           Local.getEndLoc(),
+                           WebAssemblyOperand::RegOp{LocalNo,
+                               GetType(LocalTypes, LocalNo)}));
+      Parser.Lex();
+    } else if (Lexer.is(AsmToken::Identifier)) {
+      auto &StackRegTok = Lexer.getTok();
+      // These are push/pop/drop pseudo stack registers, which we turn
+      // into virtual registers also. The stackify pass will later turn them
+      // back into implicit stack references if possible.
+      auto StackReg = StackRegTok.getString();
+      auto StackOp = StackReg.take_while([](char c) { return isalpha(c); });
+      auto Reg = StackReg.drop_front(StackOp.size());
+      unsigned long long ParsedRegNo = 0;
+      if (!Reg.empty() && getAsUnsignedInteger(Reg, 10, ParsedRegNo))
+        return Error("Cannot parse stack register index: ", StackRegTok);
+      unsigned RegNo = static_cast<unsigned>(ParsedRegNo);
+      if (StackOp == "push") {
+        // This defines a result, record register type.
+        auto RegType = ParseRegType(TypePrefix);
+        GetType(StackTypes, RegNo) = RegType;
+        Operands.push_back(make_unique<WebAssemblyOperand>(
+                             WebAssemblyOperand::Stack,
+                             StackRegTok.getLoc(),
+                             StackRegTok.getEndLoc(),
+                             WebAssemblyOperand::RegOp{RegNo, RegType}));
+      } else if (StackOp == "pop") {
+        // This uses a previously defined stack value.
+        auto RegType = GetType(StackTypes, RegNo);
+        Operands.push_back(make_unique<WebAssemblyOperand>(
+                             WebAssemblyOperand::Stack,
+                             StackRegTok.getLoc(),
+                             StackRegTok.getEndLoc(),
+                             WebAssemblyOperand::RegOp{RegNo, RegType}));
+      } else if (StackOp == "drop") {
+        // This operand will be dropped, since it is part of an instruction
+        // whose result is void.
+      } else {
+        return Error("Unknown stack register prefix: ", StackRegTok);
+      }
+      Parser.Lex();
+    } else {
+      return Error(
+            "Expected identifier/integer following $, instead got: ",
+            Lexer.getTok());
+    }
+    IsNext(AsmToken::Equal);
+    return false;
+  }
+
+  bool ParserSingleInteger(bool IsNegative, OperandVector &Operands) {
+    auto &Int = Lexer.getTok();
+    int64_t Val = Int.getIntVal();
+    if (IsNegative) Val = -Val;
+    Operands.push_back(make_unique<WebAssemblyOperand>(
+                         WebAssemblyOperand::Integer, Int.getLoc(),
+                         Int.getEndLoc(), WebAssemblyOperand::IntOp{Val}));
+    Parser.Lex();
+    return false;
+  }
+
+  bool ParseOperandStartingWithInteger(bool IsNegative,
+                                       OperandVector &Operands,
+                                       StringRef InstType) {
+    if (ParserSingleInteger(IsNegative, Operands))
+      return true;
+    if (Lexer.is(AsmToken::LParen)) {
+      // Parse load/store operands of the form: offset($reg)align
+      auto &LParen = Lexer.getTok();
+      Operands.push_back(
+            make_unique<WebAssemblyOperand>(WebAssemblyOperand::Token,
+                                            LParen.getLoc(),
+                                            LParen.getEndLoc(),
+                                            WebAssemblyOperand::TokOp{
+                                              LParen.getString()}));
+      Parser.Lex();
+      if (Expect(AsmToken::Dollar, "register")) return true;
+      if (ParseReg(Operands, InstType)) return true;
+      auto &RParen = Lexer.getTok();
+      Operands.push_back(
+            make_unique<WebAssemblyOperand>(WebAssemblyOperand::Token,
+                                            RParen.getLoc(),
+                                            RParen.getEndLoc(),
+                                            WebAssemblyOperand::TokOp{
+                                              RParen.getString()}));
+      if (Expect(AsmToken::RParen, ")")) return true;
+      if (Lexer.is(AsmToken::Integer)) {
+        if (ParserSingleInteger(false, Operands))
+          return true;
+      } else {
+        // Alignment not specified.
+        // FIXME: correctly derive a default from the instruction.
+        Operands.push_back(make_unique<WebAssemblyOperand>(
+                             WebAssemblyOperand::Integer, RParen.getLoc(),
+                             RParen.getEndLoc(), WebAssemblyOperand::IntOp{0}));
+      }
+    }
+    return false;
+  }
+
+  bool ParseInstruction(ParseInstructionInfo &/*Info*/, StringRef Name,
+                        SMLoc NameLoc, OperandVector &Operands) override {
+    Operands.push_back(
+          make_unique<WebAssemblyOperand>(WebAssemblyOperand::Token, NameLoc,
+                                          SMLoc::getFromPointer(
+                                            NameLoc.getPointer() + Name.size()),
+                                          WebAssemblyOperand::TokOp{
+                                            StringRef(NameLoc.getPointer(),
+                                                    Name.size())}));
+    auto NamePair = Name.split('.');
+    // If no '.', there is no type prefix.
+    if (NamePair.second.empty()) std::swap(NamePair.first, NamePair.second);
+    while (Lexer.isNot(AsmToken::EndOfStatement)) {
+      auto &Tok = Lexer.getTok();
+      switch (Tok.getKind()) {
+      case AsmToken::Dollar: {
+        Parser.Lex();
+        if (ParseReg(Operands, NamePair.first)) return true;
+        break;
+      }
+      case AsmToken::Identifier: {
+        auto &Id = Lexer.getTok();
+        const MCExpr *Val;
+        SMLoc End;
+        if (Parser.parsePrimaryExpr(Val, End))
+          return Error("Cannot parse symbol: ", Lexer.getTok());
+        Operands.push_back(make_unique<WebAssemblyOperand>(
+                             WebAssemblyOperand::Symbol, Id.getLoc(),
+                             Id.getEndLoc(), WebAssemblyOperand::SymOp{Val}));
+        break;
+      }
+      case AsmToken::Minus:
+        Parser.Lex();
+        if (Lexer.isNot(AsmToken::Integer))
+          return Error("Expected integer instead got: ", Lexer.getTok());
+        if (ParseOperandStartingWithInteger(true, Operands, NamePair.first))
+          return true;
+        break;
+      case AsmToken::Integer:
+        if (ParseOperandStartingWithInteger(false, Operands, NamePair.first))
+          return true;
+        break;
+      case AsmToken::Real: {
+        double Val;
+        if (Tok.getString().getAsDouble(Val, false))
+          return Error("Cannot parse real: ", Tok);
+        Operands.push_back(make_unique<WebAssemblyOperand>(
+                             WebAssemblyOperand::Float, Tok.getLoc(),
+                             Tok.getEndLoc(), WebAssemblyOperand::FltOp{Val}));
+        Parser.Lex();
+        break;
+      }
+      default:
+        return Error("Unexpected token in operand: ", Tok);
+      }
+      if (Lexer.isNot(AsmToken::EndOfStatement)) {
+        if (Expect(AsmToken::Comma, ",")) return true;
+      }
+    }
+    Parser.Lex();
+    // Call instructions are vararg, but the tablegen matcher doesn't seem to
+    // support that, so for now we strip these extra operands.
+    // This is problematic if these arguments are not simple $pop stack
+    // registers, since e.g. a local register would get lost, so we check for
+    // this. This can be the case when using -disable-wasm-explicit-locals
+    // which currently s2wasm requires.
+    // TODO: Instead, we can move this code to MatchAndEmitInstruction below and
+    // actually generate get_local instructions on the fly.
+    // Or even better, improve the matcher to support vararg?
+    auto IsIndirect = NamePair.second == "call_indirect";
+    if (IsIndirect || NamePair.second == "call") {
+      // Figure out number of fixed operands from the instruction.
+      size_t CallOperands = 1;  // The name token.
+      if (!IsIndirect) CallOperands++;  // The function index.
+      if (!NamePair.first.empty()) CallOperands++;  // The result register.
+      if (Operands.size() > CallOperands) {
+        // Ensure operands we drop are all $pop.
+        for (size_t I = CallOperands; I < Operands.size(); I++) {
+          auto Operand =
+              reinterpret_cast<WebAssemblyOperand *>(Operands[I].get());
+          if (Operand->Kind != WebAssemblyOperand::Stack)
+            Parser.Error(NameLoc,
+              "Call instruction has non-stack arguments, if this code was "
+              "generated with -disable-wasm-explicit-locals please remove it");
+        }
+        // Drop unneeded operands.
+        Operands.resize(CallOperands);
+      }
+    }
+    // Block instructions require a signature index, but these are missing in
+    // assembly, so we add a dummy one explicitly (since we have no control
+    // over signature tables here, we assume these will be regenerated when
+    // the wasm module is generated).
+    if (NamePair.second == "block" || NamePair.second == "loop") {
+      Operands.push_back(make_unique<WebAssemblyOperand>(
+                           WebAssemblyOperand::Integer, NameLoc,
+                           NameLoc, WebAssemblyOperand::IntOp{-1}));
+    }
+    // These don't specify the type, which has to derived from the local index.
+    if (NamePair.second == "get_local" || NamePair.second == "tee_local") {
+      if (Operands.size() >= 3 && Operands[1]->isReg() &&
+          Operands[2]->isImm()) {
+        auto Op1 = reinterpret_cast<WebAssemblyOperand *>(Operands[1].get());
+        auto Op2 = reinterpret_cast<WebAssemblyOperand *>(Operands[2].get());
+        auto Type = GetType(LocalTypes, static_cast<size_t>(Op2->Int.Val));
+        Op1->Reg.RegType = Type;
+        GetType(StackTypes, Op1->Reg.RegNo) = Type;
+      }
+    }
+    return false;
+  }
+
+  void onLabelParsed(MCSymbol *Symbol) override {
+    LastLabel = Symbol;
+  }
+
+  MVT::SimpleValueType RegTypeToMVT(unsigned RegType) {
+    switch(RegType) {
+      case WebAssembly::I32_0: return MVT::i32;
+      case WebAssembly::I64_0: return MVT::i64;
+      case WebAssembly::F32_0: return MVT::f32;
+      case WebAssembly::F64_0: return MVT::f64;
+      case WebAssembly::V16I8_0: return MVT::v16i8;
+      case WebAssembly::V8I16_0: return MVT::v8i16;
+      case WebAssembly::V4I32_0: return MVT::v4i32;
+      case WebAssembly::V4F32_0: return MVT::v4f32;
+      default: return MVT::INVALID_SIMPLE_VALUE_TYPE;
+    }
+  }
+
+  bool ParseDirective(AsmToken DirectiveID) override {
+    assert(DirectiveID.getKind() == AsmToken::Identifier);
+    auto &Out = getStreamer();
+    auto &TOut = reinterpret_cast<WebAssemblyTargetStreamer &>(
+                   *Out.getTargetStreamer());
+    // TODO: we're just parsing the subset of directives we're interested in,
+    // and ignoring ones we don't recognise. We should ideally verify
+    // all directives here.
+    if (DirectiveID.getString() == ".type") {
+      // This could be the start of a function, check if followed by
+      // "label,@function"
+      if (!(IsNext(AsmToken::Identifier) &&
+            IsNext(AsmToken::Comma) &&
+            IsNext(AsmToken::At) &&
+            Lexer.is(AsmToken::Identifier)))
+        return Error("Expected label,@type declaration, got: ", Lexer.getTok());
+      if (Lexer.getTok().getString() == "function") {
+        // Track locals from start of function.
+        LocalTypes.clear();
+        StackTypes.clear();
+      }
+      Parser.Lex();
+      //Out.EmitSymbolAttribute(??, MCSA_ELF_TypeFunction);
+    } else if (DirectiveID.getString() == ".param" ||
+               DirectiveID.getString() == ".local") {
+      // Track the number of locals, needed for correct virtual register
+      // assignment elsewhere.
+      // Also output a directive to the streamer.
+      std::vector<MVT> Params;
+      std::vector<MVT> Locals;
+      while (Lexer.is(AsmToken::Identifier)) {
+        auto RegType = ParseRegType(Lexer.getTok().getString());
+        if (RegType == WebAssembly::NoRegister) return true;
+        LocalTypes.push_back(RegType);
+        if (DirectiveID.getString() == ".param") {
+          Params.push_back(MVT(RegTypeToMVT(RegType)));
+        } else {
+          Locals.push_back(MVT(RegTypeToMVT(RegType)));
+        }
+        Parser.Lex();
+        if (!IsNext(AsmToken::Comma)) break;
+      }
+      assert(LastLabel);
+      TOut.emitParam(LastLabel, Params);
+      TOut.emitLocal(Locals);
+    } else {
+      // For now, ignore anydirective we don't recognize:
+      while (Lexer.isNot(AsmToken::EndOfStatement)) Parser.Lex();
+    }
+    return Expect(AsmToken::EndOfStatement, "EOL");
+  }
+
+  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &/*Opcode*/,
+                               OperandVector &Operands,
+                               MCStreamer &Out, uint64_t &ErrorInfo,
+                               bool MatchingInlineAsm) override {
+    MCInst Inst;
+    unsigned MatchResult =
+        MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
+    switch (MatchResult) {
+    case Match_Success: {
+      Out.EmitInstruction(Inst, getSTI());
+      return false;
+    }
+    case Match_MissingFeature:
+      return Parser.Error(IDLoc,
+          "instruction requires a WASM feature not currently enabled");
+    case Match_MnemonicFail:
+      return Parser.Error(IDLoc, "invalid instruction");
+    case Match_NearMisses:
+      return Parser.Error(IDLoc, "ambiguous instruction");
+    case Match_InvalidTiedOperand:
+    case Match_InvalidOperand: {
+      SMLoc ErrorLoc = IDLoc;
+      if (ErrorInfo != ~0ULL) {
+        if (ErrorInfo >= Operands.size())
+          return Parser.Error(IDLoc, "too few operands for instruction");
+        ErrorLoc = Operands[ErrorInfo]->getStartLoc();
+        if (ErrorLoc == SMLoc())
+          ErrorLoc = IDLoc;
+      }
+      return Parser.Error(ErrorLoc, "invalid operand for instruction");
+    }
+    }
+    llvm_unreachable("Implement any new match types added!");
+  }
+};
+} // end anonymous namespace
+
+// Force static initialization.
+extern "C" void LLVMInitializeWebAssemblyAsmParser() {
+  RegisterMCAsmParser<WebAssemblyAsmParser> X(getTheWebAssemblyTarget32());
+  RegisterMCAsmParser<WebAssemblyAsmParser> Y(getTheWebAssemblyTarget64());
+}
+
+#define GET_REGISTER_MATCHER
+#define GET_MATCHER_IMPLEMENTATION
+#include "WebAssemblyGenAsmMatcher.inc"

lib/Target/WebAssembly/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS WebAssembly.td)
 
 tablegen(LLVM WebAssemblyGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM WebAssemblyGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM WebAssemblyGenFastISel.inc -gen-fast-isel)
 tablegen(LLVM WebAssemblyGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM WebAssemblyGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM WebAssemblyGenRegisterInfo.inc -gen-register-info)
-tablegen(LLVM WebAssemblyGenSubtargetInfo.inc -gen-subtarget)
+tablegen(LLVM WebAssemblyGenSubtargetInfo.inc -gen-subtarget)
+tablegen(LLVM WebAssemblyGenAsmMatcher.inc -gen-asm-matcher)
 add_public_tablegen_target(WebAssemblyCommonTableGen)
 
 add_llvm_target(WebAssemblyCodeGen
   WebAssemblyArgumentMove.cpp
   WebAssemblyAsmPrinter.cpp
   WebAssemblyCallIndirectFixup.cpp
   WebAssemblyCFGStackify.cpp
   WebAssemblyCFGSort.cpp
add_llvm_target(WebAssemblyCodeGen
   WebAssemblySetP2AlignOperands.cpp
   WebAssemblyStoreResults.cpp
   WebAssemblySubtarget.cpp
   WebAssemblyTargetMachine.cpp
   WebAssemblyTargetObjectFile.cpp
   WebAssemblyTargetTransformInfo.cpp
   WebAssemblyUtilities.cpp
 
-  DEPENDS
-  intrinsics_gen
-)
-
+  DEPENDS
+  intrinsics_gen
+)
+
+add_subdirectory(AsmParser)
 add_subdirectory(Disassembler)
 add_subdirectory(InstPrinter)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(TargetInfo)

lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp

void WebAssemblyInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
   printAnnotation(OS, Annot);
 
   if (CommentStream) {
     // Observe any effects on the control flow stack, for use in annotating
     // control flow label references.
     switch (MI->getOpcode()) {
     default:
       break;
-    case WebAssembly::LOOP: {
-      printAnnotation(OS, "label" + utostr(ControlFlowCounter) + ':');
-      ControlFlowStack.push_back(std::make_pair(ControlFlowCounter++, true));
-      break;
-    }
-    case WebAssembly::BLOCK:
-      ControlFlowStack.push_back(std::make_pair(ControlFlowCounter++, false));
-      break;
-    case WebAssembly::END_LOOP:
-      ControlFlowStack.pop_back();
+    case WebAssembly::LOOP: {
+      printAnnotation(OS, "label" + utostr(ControlFlowCounter) + ':');
+      ControlFlowStack.push_back(std::make_pair(ControlFlowCounter++, true));
+      break;
+    }
+    case WebAssembly::BLOCK:
+      ControlFlowStack.push_back(std::make_pair(ControlFlowCounter++, false));
+      break;
+    case WebAssembly::END_LOOP:
+      // Have to guard against an empty stack, in case of mismatched pairs
+      // in assembly parsing.
+      if (!ControlFlowStack.empty()) ControlFlowStack.pop_back();
       break;
     case WebAssembly::END_BLOCK:
-      printAnnotation(
+      if (!ControlFlowStack.empty()) printAnnotation(
           OS, "label" + utostr(ControlFlowStack.pop_back_val().first) + ':');
       break;
     }
 
     // Annotate any control flow label references.
     unsigned NumFixedOperands = Desc.NumOperands;
     SmallSet<uint64_t, 8> Printed;
     for (unsigned i = 0, e = MI->getNumOperands(); i < e; ++i) {

lib/Target/WebAssembly/LLVMBuild.txt

 ; This is an LLVMBuild description file for the components in this subdirectory.
 ;
 ; For more information on the LLVMBuild system, please see:
 ;
 ;   http://llvm.org/docs/LLVMBuild.html
 ;
 ;===------------------------------------------------------------------------===;
 
-[common]
-subdirectories = Disassembler InstPrinter MCTargetDesc TargetInfo
+[common]
+subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo
 
 [component_0]
 type = TargetGroup
-name = WebAssembly
-parent = Target
+name = WebAssembly
+parent = Target
+has_asmparser = 1
 has_asmprinter = 1
 has_disassembler = 1
 
 [component_1]
 type = Library
 name = WebAssemblyCodeGen
 parent = WebAssembly
 required_libraries = Analysis AsmPrinter CodeGen Core MC Scalar SelectionDAG Support Target TransformUtils WebAssemblyAsmPrinter WebAssemblyDesc WebAssemblyInfo
 add_to_library_groups = WebAssembly

lib/Target/WebAssembly/WebAssemblyRegisterInfo.td

 // Registers
 //===----------------------------------------------------------------------===//
 
 // Special registers used as the frame and stack pointer.
 //
 // WebAssembly may someday supports mixed 32-bit and 64-bit heaps in the same
 // application, which requires separate width FP and SP.
 def FP32 : WebAssemblyReg<"%FP32">;
-def FP64 : WebAssemblyReg<"%FP64">;
-def SP32 : WebAssemblyReg<"%SP32">;
-def SP64 : WebAssemblyReg<"%SP64">;
-
-// The register allocation framework requires register classes have at least
-// one register, so we define a few for the floating point register classes
-// since we otherwise don't need a physical register in those classes.
-def F32_0 : WebAssemblyReg<"%f32.0">;
-def F64_0 : WebAssemblyReg<"%f64.0">;
-def V128_0: WebAssemblyReg<"%v128">;
+def FP64 : WebAssemblyReg<"%FP64">;
+def SP32 : WebAssemblyReg<"%SP32">;
+def SP64 : WebAssemblyReg<"%SP64">;
+
+// The register allocation framework requires register classes have at least
+// one register, so we define a few for the integer / floating point register
+// classes since we otherwise don't need a physical register in those classes.
+// These are also used a "types" in the generated assembly matcher.
+def I32_0 : WebAssemblyReg<"%i32.0">;
+def I64_0 : WebAssemblyReg<"%i64.0">;
+def F32_0 : WebAssemblyReg<"%f32.0">;
+def F64_0 : WebAssemblyReg<"%f64.0">;
+
+def V4F32_0: WebAssemblyReg<"%v4f32">;
+def V4I32_0: WebAssemblyReg<"%v4i32">;
+def V16I8_0: WebAssemblyReg<"%v16i8">;
+def V8I16_0: WebAssemblyReg<"%v8i16">;
+
 def EXCEPT_REF_0 : WebAssemblyReg<"%except_ref.0">;
 
 // The value stack "register". This is an opaque entity which serves to order
 // uses and defs that must remain in LIFO order.
 def VALUE_STACK : WebAssemblyReg<"STACK">;
 
-// The incoming arguments "register". This is an opaque entity which serves to
-// order the ARGUMENT instructions that are emulating live-in registers and
+// The incoming arguments "register". This is an opaque entity which serves to
+// order the ARGUMENT instructions that are emulating live-in registers and
 // must not be scheduled below other instructions.
 def ARGUMENTS : WebAssemblyReg<"ARGUMENTS">;
-
-//===----------------------------------------------------------------------===//
-//  Register classes
-//===----------------------------------------------------------------------===//
-
-def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32)>;
-def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64)>;
-def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
-def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;
-def V128 : WebAssemblyRegClass<[v4f32, v4i32, v16i8, v8i16], 128, (add V128_0)>;
-def EXCEPT_REF : WebAssemblyRegClass<[ExceptRef], 0, (add EXCEPT_REF_0)>;
+
+//===----------------------------------------------------------------------===//
+//  Register classes
+//===----------------------------------------------------------------------===//
+
+def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32, I32_0)>;
+def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>;
+def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
+def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;
+def V128 : WebAssemblyRegClass<[v4f32, v4i32, v16i8, v8i16], 128,
+                               (add V4F32_0, V4I32_0, V16I8_0, V8I16_0)>;
+def EXCEPT_REF : WebAssemblyRegClass<[ExceptRef], 0, (add EXCEPT_REF_0)>;
+

test/MC/WebAssembly/basic-assembly.s

+# RUN: llvm-mc -arch=wasm32 < %s | FileCheck %s
+
+    .text
+    .type    test0,@function
+test0:
+    # Test all types:
+    .param      i32, i64
+    .local      f32, f64  #, i8x16, i16x8, i32x4, f32x4
+    # Explicit getlocal/setlocal:
+    get_local   $push0=, 2
+    set_local   2, $pop0=
+    # Implicit locals & immediates:
+    i32.const   $0=, -1
+    f64.const   $3=, 0x1.999999999999ap1
+    # Indirect addressing:
+    get_local   $push1=, 0
+    f64.store   0($pop1), $3
+    # Loops, conditionals, binary ops, calls etc:
+    block
+    i32.const   $push2=, 1
+    get_local   $push7=, 0
+    i32.ge_s    $push0=, $pop2, $pop7
+    br_if       0, $pop0        # 0: down to label0
+.LBB0_1:
+    loop             # label1:
+    call        $drop=, something1@FUNCTION
+    i64.const   $push10=, 1234
+    i32.call    $push8=, something2@FUNCTION, $pop10
+    i32.const   $push11=, 0
+    call_indirect $pop11
+    i32.const   $push5=, 1
+    i32.add     $push4=, $pop8, $pop5
+    tee_local   $push3=, 0, $pop4
+    get_local   $push9=, 0
+    i32.lt_s    $push1=, $pop3, $pop9
+    br_if       0, $pop1        # 0: up to label1
+.LBB0_2:
+    end_loop
+    end_block                       # label0:
+    end_function
+
+
+# CHECK:           .text
+# CHECK-LABEL: test0:
+# CHECK-NEXT:      .param      i32, i64
+# CHECK-NEXT:      .local      f32, f64
+# CHECK-NEXT:      get_local   $push0=, 2
+# CHECK-NEXT:      set_local   2, $pop0
+# CHECK-NEXT:      i32.const   $0=, -1
+# CHECK-NEXT:      f64.const   $3=, 0x1.999999999999ap1
+# CHECK-NEXT:      get_local   $push1=, 0
+# CHECK-NEXT:      f64.store   0($pop1):p2align=0, $3
+# CHECK-NEXT:      block
+# CHECK-NEXT:      i32.const   $push2=, 1
+# CHECK-NEXT:      get_local   $push7=, 0
+# CHECK-NEXT:      i32.ge_s    $push0=, $pop2, $pop7
+# CHECK-NEXT:      br_if 0,    $pop0        # 0: down to label0
+# CHECK-NEXT:  .LBB0_1:
+# CHECK-NEXT:      loop        i32             # label1:
+# CHECK-NEXT:      call        something1@FUNCTION
+# CHECK-NEXT:      i64.const   $push10=, 1234
+# CHECK-NEXT:      i32.call    $push8=, something2@FUNCTION
+# CHECK-NEXT:      i32.const   $push11=, 0
+# CHECK-NEXT:      call_indirect
+# CHECK-NEXT:      i32.const   $push5=, 1
+# CHECK-NEXT:      i32.add     $push4=, $pop8, $pop5
+# CHECK-NEXT:      tee_local   $push3=, 0, $pop4
+# CHECK-NEXT:      get_local   $push9=, 0
+# CHECK-NEXT:      i32.lt_s    $push1=, $pop3, $pop9
+# CHECK-NEXT:      br_if 0,    $pop1        # 0: up to label1
+# CHECK-NEXT:  .LBB0_2:
+# CHECK-NEXT:      end_loop
+# CHECK-NEXT:      end_block                       # label0:
+# CHECK-NEXT:      end_function