[mips] Split out ASEPredicate from InsnPredicates (NFC)

[sdardis]

Summary

This simplifies tagging instructions with the correct ISA and ASE, albeit making
instruction definitions a bit more verbose.

[sdardis]

Minor update, incorrect predicates for (s|l)w(l|r)e, fixed the ASE_EVA class overwriting the InsnPredicates instead of the ASEPredicates.

[atanasyan]

LGTM

llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td

 //===-- MicroMipsDSPInstrFormats.td - Instruction Formats --*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 class MMDSPInst<string opstr = "">
     : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
-  let InsnPredicates = [HasDSP];
+  let ASEPredicate = [HasDSP];
   let AdditionalPredicates = [InMicroMips];
   string BaseOpcode = opstr;
   string Arch = "mmdsp";
   let DecoderNamespace = "MicroMips";
 }
 
 class MMDSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
     : InstAlias<Asm, Result, Emit>, PredicateControl {
-  let InsnPredicates = [HasDSP];
+  let ASEPredicate = [HasDSP];
   let AdditionalPredicates = [InMicroMips];
 }
 
 class POOL32A_3R_FMT<string opstr, bits<11> op> : MMDSPInst<opstr> {
   bits<5> rd;
   bits<5> rs;
   bits<5> rt;
 

llvm/trunk/lib/Target/Mips/Mips.td

class PredicateControl {
   // Predicates for the encoding scheme in use such as HasStdEnc
   list<Predicate> EncodingPredicates = [];
   // Predicates for the GPR size such as IsGP64bit
   list<Predicate> GPRPredicates = [];
   // Predicates for the PTR size such as IsPTR64bit
   list<Predicate> PTRPredicates = [];
   // Predicates for the FGR size and layout such as IsFP64bit
   list<Predicate> FGRPredicates = [];
-  // Predicates for the instruction group membership such as ISA's and ASE's
+  // Predicates for the instruction group membership such as ISA's.
   list<Predicate> InsnPredicates = [];
+  // Predicate for the ASE that an instruction belongs to.
+  list<Predicate> ASEPredicate = [];
   // Predicate for marking the instruction as usable in hard-float mode only.
   list<Predicate> HardFloatPredicate = [];
   // Predicates for anything else
   list<Predicate> AdditionalPredicates = [];
   list<Predicate> Predicates = !listconcat(EncodingPredicates,
                                            GPRPredicates,
                                            PTRPredicates,
                                            FGRPredicates,
                                            InsnPredicates,
                                            HardFloatPredicate,
+                                           ASEPredicate,
                                            AdditionalPredicates);
 }
 
 // Like Requires<> but for the AdditionalPredicates list
 class AdditionalRequires<list<Predicate> preds> {
   list<Predicate> AdditionalPredicates = preds;
 }
 

llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td

 def HasDSP : Predicate<"Subtarget->hasDSP()">,
              AssemblerPredicate<"FeatureDSP">;
 def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
                AssemblerPredicate<"FeatureDSPR2">;
 def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
                AssemblerPredicate<"FeatureDSPR3">;
 
 class ISA_DSPR2 {
-  list<Predicate> InsnPredicates = [HasDSPR2];
+  list<Predicate> ASEPredicate = [HasDSPR2];
 }
 
 class ISA_DSPR3 {
-  list<Predicate> InsnPredicates = [HasDSPR3];
+  list<Predicate> ASEPredicate = [HasDSPR3];
 }
 
 // Fields.
 class Field6<bits<6> val> {
   bits<6> V = val;
 }
 
 def SPECIAL3_OPCODE : Field6<0b011111>;
 def REGIMM_OPCODE : Field6<0b000001>;
 
 class DSPInst<string opstr = "">
     : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
-  let InsnPredicates = [HasDSP];
+  let ASEPredicate = [HasDSP];
   string BaseOpcode = opstr;
   string Arch = "dsp";
 }
 
 class PseudoDSP<dag outs, dag ins, list<dag> pattern,
                 InstrItinClass itin = IIPseudo>
     : MipsPseudo<outs, ins, pattern, itin> {
-  let InsnPredicates = [HasDSP];
+  let ASEPredicate = [HasDSP];
 }
 
 class DSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
     : InstAlias<Asm, Result, Emit>, PredicateControl {
-  let InsnPredicates = [HasDSP];
+  let ASEPredicate = [HasDSP];
 }
 
 // ADDU.QB sub-class format.
 class ADDU_QB_FMT<bits<5> op> : DSPInst {
   bits<5> rd;
   bits<5> rs;
   bits<5> rt;
 

llvm/trunk/lib/Target/Mips/MipsEVAInstrInfo.td

 
 //===----------------------------------------------------------------------===//
 //
 // Instruction definitions
 //
 //===----------------------------------------------------------------------===//
 
 /// Load and Store EVA Instructions
-def LBE     : MMRel, LBE_ENC, LBE_DESC, INSN_EVA;
-def LBuE    : MMRel, LBuE_ENC, LBuE_DESC, INSN_EVA;
-def LHE     : MMRel, LHE_ENC, LHE_DESC, INSN_EVA;
-def LHuE    : MMRel, LHuE_ENC, LHuE_DESC, INSN_EVA;
+def LBE     : MMRel, LBE_ENC, LBE_DESC, ASE_EVA;
+def LBuE    : MMRel, LBuE_ENC, LBuE_DESC, ASE_EVA;
+def LHE     : MMRel, LHE_ENC, LHE_DESC, ASE_EVA;
+def LHuE    : MMRel, LHuE_ENC, LHuE_DESC, ASE_EVA;
 let AdditionalPredicates = [NotInMicroMips] in {
-def LWE     : MMRel, LWE_ENC, LWE_DESC, INSN_EVA;
+def LWE     : MMRel, LWE_ENC, LWE_DESC, ASE_EVA;
 }
-def SBE     : MMRel, SBE_ENC, SBE_DESC, INSN_EVA;
-def SHE     : MMRel, SHE_ENC, SHE_DESC, INSN_EVA;
+def SBE     : MMRel, SBE_ENC, SBE_DESC, ASE_EVA;
+def SHE     : MMRel, SHE_ENC, SHE_DESC, ASE_EVA;
 let AdditionalPredicates = [NotInMicroMips] in {
-def SWE     : MMRel, SWE_ENC, SWE_DESC, INSN_EVA;
+def SWE     : MMRel, SWE_ENC, SWE_DESC, ASE_EVA;
 }
 
 /// load/store left/right EVA
 let AdditionalPredicates = [NotInMicroMips] in {
-def LWLE    : LWLE_ENC, LWLE_DESC, INSN_EVA_NOT_32R6_64R6;
-def LWRE    : LWRE_ENC, LWRE_DESC, INSN_EVA_NOT_32R6_64R6;
-def SWLE    : SWLE_ENC, SWLE_DESC, INSN_EVA_NOT_32R6_64R6;
-def SWRE    : SWRE_ENC, SWRE_DESC, INSN_EVA_NOT_32R6_64R6;
+def LWLE    : LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+def LWRE    : LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+def SWLE    : SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+def SWRE    : SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
 }
 
 /// Load-linked EVA, Store-conditional EVA
 let AdditionalPredicates = [NotInMicroMips] in {
-def LLE     : MMRel, LLE_ENC, LLE_DESC, INSN_EVA;
-def SCE     : MMRel, SCE_ENC, SCE_DESC, INSN_EVA;
+def LLE     : MMRel, LLE_ENC, LLE_DESC, ASE_EVA;
+def SCE     : MMRel, SCE_ENC, SCE_DESC, ASE_EVA;
 }
 
 let AdditionalPredicates = [NotInMicroMips] in {
-  def TLBINV  : TLBINV_ENC, TLBINV_DESC, INSN_EVA;
-  def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, INSN_EVA;
+  def TLBINV  : TLBINV_ENC, TLBINV_DESC, ASE_EVA;
+  def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ASE_EVA;
 }
 
-def CACHEE  : MMRel, CACHEE_ENC, CACHEE_DESC, INSN_EVA;
-def PREFE   : MMRel, PREFE_ENC, PREFE_DESC, INSN_EVA;
+def CACHEE  : MMRel, CACHEE_ENC, CACHEE_DESC, ASE_EVA;
+def PREFE   : MMRel, PREFE_ENC, PREFE_DESC, ASE_EVA;

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

 class ISA_MICROMIPS64R6 {
   list<Predicate> InsnPredicates = [HasMips64r6];
   list<Predicate> EncodingPredicates = [InMicroMips];
 }
 class ISA_MICROMIPS32_NOT_MIPS32R6 {
   list<Predicate> InsnPredicates = [NotMips32r6];
   list<Predicate> EncodingPredicates = [InMicroMips];
 }
-class INSN_EVA { list<Predicate> InsnPredicates = [HasEVA]; }
-class INSN_EVA_NOT_32R6_64R6 {
-  list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA];
-}
+class ASE_EVA { list<Predicate> ASEPredicate = [HasEVA]; }
 
 // The portions of MIPS-III that were also added to MIPS32
 class INSN_MIPS3_32 {
   list<Predicate> InsnPredicates = [HasMips3_32];
   list<Predicate> EncodingPredicates = [HasStdEnc];
 }
 
 // The portions of MIPS-III that were also added to MIPS32 but were removed in

 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
 // MIPS32r6 and MIPS64r6.
 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
   list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
   list<Predicate> EncodingPredicates = [HasStdEnc];
 }
 
 class ASE_CNMIPS {
-  list<Predicate> InsnPredicates = [HasCnMips];
+  list<Predicate> ASEPredicate = [HasCnMips];
 }
 
 class NOT_ASE_CNMIPS {
-  list<Predicate> InsnPredicates = [NotCnMips];
+  list<Predicate> ASEPredicate = [NotCnMips];
 }
 
 class ASE_MIPS64_CNMIPS {
-  list<Predicate> InsnPredicates = [HasMips64, HasCnMips];
+  list<Predicate> ASEPredicate = [HasMips64, HasCnMips];
 }
 
 class ASE_MSA {
-  list<Predicate> InsnPredicates = [HasMSA];
+  list<Predicate> ASEPredicate = [HasMSA];
 }
 
 class ASE_MSA_NOT_MSA64 {
-  list<Predicate> InsnPredicates = [HasMSA, NotMips64];
+  list<Predicate> ASEPredicate = [HasMSA, NotMips64];
 }
 
 class ASE_MSA64 {
-  list<Predicate> InsnPredicates = [HasMSA, HasMips64];
+  list<Predicate> ASEPredicate = [HasMSA, HasMips64];
 }
 
 class ASE_MT {
-  list <Predicate> InsnPredicates = [HasMT];
+  list <Predicate> ASEPredicate = [HasMT];
 }
 
 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
 // It can be used only on instructions that doesn't inherit PredicateControl.
 class ISA_MICROMIPS_NOT_32R6 : PredicateControl {
   let InsnPredicates = [NotMips32r6];
   let EncodingPredicates = [InMicroMips];
 }
 
 class ASE_NOT_DSP {
-  list<Predicate> InsnPredicates = [NotDSP];
+  list<Predicate> ASEPredicate = [NotDSP];
 }
 
 class MADD4 {
   list<Predicate> AdditionalPredicates = [HasMadd4];
 }
 
 // Classses used for separating expansions that differ based on the ABI in
 // use.