[mips] Add support for CRC ASE

[vstefanovic]

Summary

Instructions: crc32b, crc32h, crc32w, crc32d,

crc32cb, crc32ch, crc32cw, crc32cd

Assembler directives: .set crc, .set nocrc, .module crc, .module nocrc
Attribute: crc
.MIPS.abiflags: CRC (0x8000)

[sdardis]

This looks mostly ok. There's only some small changes required, and they are somewhat minor. The recurring change is that for test cases, when there is a run-on line with '\', then the continuation of the command line should be indented by two spaces.

See my inlined comments.

lib/Target/Mips/Mips.td

176 ↗

(On Diff #137274)

As the CRC ASE is only defined for R6, you can drop the brackets.

lib/Target/Mips/Mips32r6InstrFormats.td

587–588 ↗

(On Diff #137274)

Rather than "simplifying" the encoding layout, can you transcribe it directly so that bits 15 to 11 are zeros, and the direction field is a three bit parameter?

lib/Target/Mips/Mips32r6InstrInfo.td

949–955 ↗

(On Diff #137274)

This needs ISA_MIPS32R6 for these instructions. The ASE_CRC adjective comes after the ISA adjective.

lib/Target/Mips/Mips64r6InstrInfo.td

42 ↗

(On Diff #137274)

Nit: align the ':' of this line with the one below. It will look a bit odd w.r.t. the line above, but most of these lines should align w.r.t. ';', but that's a cosmetic nit for another day.

182–183 ↗

(On Diff #137274)

This needs ISA_MIPS64R6 for these instructions, ISA adjectives come first, then the ASE adjectives.

lib/Target/Mips/MipsInstrInfo.td

249–252 ↗

(On Diff #137274)

Can you remove FeatureMipsXXr6 from these assembler predicates? It's my view that ASE and ISA level adjectives/predicates should be separated, such that both can be applied to an instruction without overlap.

test/MC/Disassembler/Mips/crc/valid-32r6-el.txt

2 ↗

(On Diff #137274)

Indent the -mattr=+crc by two spaces here.

test/MC/Disassembler/Mips/crc/valid-32r6.txt

2 ↗

(On Diff #137274)

Indent the -mattr=+crc by two spaces here.

test/MC/Disassembler/Mips/crc/valid-64r6-el.txt

2 ↗

(On Diff #137274)

Indent the -mattr=+crc by two spaces here.

test/MC/Disassembler/Mips/crc/valid-64r6.txt

2 ↗

(On Diff #137274)

Indent the -mattr=+crc by two spaces here.

test/MC/Mips/crc/invalid.s

1 ↗

(On Diff #137274)

Can you also add an invalid-wrong-isa.s test file which uses .set mipsXX * .set micromips to show that we correctly reject the instruction for pre-R6 ISAs?

test/MC/Mips/crc/module-crc.s

2 ↗

(On Diff #137274)

Indent the FileCheck command here by two spaces.

5–7 ↗

(On Diff #137274)

Indent these lines by two spaces.

[vstefanovic]

lib/Target/Mips/Mips32r6InstrInfo.td

949–955 ↗

(On Diff #137274)

This:

def CRC32CW : R6MMR6Rel, CRC32CW_ENC, CRC32CW_DESC, ISA_MIPS32R6, ASE_CRC;

ends up being the same as this:

def CRC32CW : R6MMR6Rel, CRC32CW_ENC, CRC32CW_DESC, ASE_CRC;

because (I think) ISA_MIPS32R6's InsnPredicates get overridden by ASE_CRC's InsnPredicates.
We could do:

class ASE_CRC {
  list <Predicate> InsnPredicates = [HasCRC, HasMips32r6];
}

Btw, we might want to improve this with other ASEs too (in a separate patch), for example this MT case goes without a warning or error:

.set mt
.set mips2
yield $4

[sdardis]

lib/Target/Mips/Mips32r6InstrInfo.td

949–955 ↗

(On Diff #137274)

Good point. I have a posted patch which includes creating an additional field in PredicateControl which seperates ASEs from the other instruction predicates.

I'll factor it out of that patch and include some other refactoring I have in my local copy and commit that.

If we're getting no error from that assembly fragment you've posted, we can solve that in general and you can disregard my requested change for testing that .set correctly rejects the crc instructions.

[vstefanovic]

test/MC/Mips/crc/invalid.s

1 ↗

(On Diff #137274)

I have invalid-wrong-isa.s locally now, if we want to add it later.

[sdardis]

If you look at the dependency, you'll see the way I've separated out the ISA level from the ASEs.

[vstefanovic]

Updated the code to use ASEPRedicate from D44299.

[sdardis]

LGTM with inline nits addressed.

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

1136 ↗

(On Diff #138064)

Newline before and after what you've added here.

lib/Target/Mips/Mips64r6InstrInfo.td

119 ↗

(On Diff #138064)

Nit: New line before and after this hunk.

test/MC/Disassembler/Mips/crc/valid-64r6-el.txt

1 ↗

(On Diff #138064)

Triple here should be mips64el-unknown-linux-gnu.

test/MC/Disassembler/Mips/crc/valid-64r6.txt

1 ↗

(On Diff #138064)

Triple here should be mips64-unknown-linux-gnu.

test/MC/Mips/crc/invalid64.s

3 ↗

(On Diff #138064)

Triple here should be mips64-unknown-linux-gnu.

test/MC/Mips/crc/module-crc.s

1 ↗

(On Diff #138064)

Triple here should be mips-unknown-linux-gnu.

4 ↗

(On Diff #138064)

Triple here should be mips-unknown-linux-gnu.

test/MC/Mips/crc/set-nocrc-directive.s

4 ↗

(On Diff #138064)

Triple here should be mips64-unknown-linux-gnu.

test/MC/Mips/crc/valid.s

3 ↗

(On Diff #138064)

Triple here should be mips64-unknown-linux-gnu.

test/MC/Mips/crc/valid64.s

1 ↗

(On Diff #138064)

Triple here should be mips64-unknown-linux-gnu.

[vstefanovic]

Addressed nits.

llvm/trunk/include/llvm/Support/MipsABIFlags.h

enum AFL_ASE {
   AFL_ASE_MDMX = 0x00000010,      // MDMX ASE
   AFL_ASE_MIPS3D = 0x00000020,    // MIPS-3D ASE
   AFL_ASE_MT = 0x00000040,        // MT ASE
   AFL_ASE_SMARTMIPS = 0x00000080, // SmartMIPS ASE
   AFL_ASE_VIRT = 0x00000100,      // VZ ASE
   AFL_ASE_MSA = 0x00000200,       // MSA ASE
   AFL_ASE_MIPS16 = 0x00000400,    // MIPS16 ASE
   AFL_ASE_MICROMIPS = 0x00000800, // MICROMIPS ASE
-  AFL_ASE_XPA = 0x00001000        // XPA ASE
+  AFL_ASE_XPA = 0x00001000,       // XPA ASE
+  AFL_ASE_CRC = 0x00008000        // CRC ASE
 };
 
 // Values for the isa_ext word of an ABI flags structure.
 enum AFL_EXT {
   AFL_EXT_NONE = 0,         // None
   AFL_EXT_XLR = 1,          // RMI Xlr instruction
   AFL_EXT_OCTEON2 = 2,      // Cavium Networks Octeon2
   AFL_EXT_OCTEONP = 3,      // Cavium Networks OcteonP

llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

#include "MipsGenAsmMatcher.inc"
   bool parseSetOddSPRegDirective();
   bool parseSetNoOddSPRegDirective();
   bool parseSetPopDirective();
   bool parseSetPushDirective();
   bool parseSetSoftFloatDirective();
   bool parseSetHardFloatDirective();
   bool parseSetMtDirective();
   bool parseSetNoMtDirective();
+  bool parseSetNoCRCDirective();
 
   bool parseSetAssignment();
 
   bool parseDataDirective(unsigned Size, SMLoc L);
   bool parseDirectiveGpWord();
   bool parseDirectiveGpDWord();
   bool parseDirectiveDtpRelWord();
   bool parseDirectiveDtpRelDWord();
#undef GET_OPERAND_DIAGNOSTIC_TYPES
 
   bool useSoftFloat() const {
     return getSTI().getFeatureBits()[Mips::FeatureSoftFloat];
   }
   bool hasMT() const {
     return getSTI().getFeatureBits()[Mips::FeatureMT];
   }
 
+  bool hasCRC() const {
+    return getSTI().getFeatureBits()[Mips::FeatureCRC];
+  }
+
   /// Warn if RegIndex is the same as the current AT.
   void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
 
   void warnIfNoMacro(SMLoc Loc);
 
   bool isLittle() const { return IsLittleEndian; }
 
   const MCExpr *createTargetUnaryExpr(const MCExpr *E,
case Mips::DEXTU: {
     assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
            "Operands must be immediates for dextm/dextu!");
     const signed Pos = Inst.getOperand(2).getImm();
     const signed Size = Inst.getOperand(3).getImm();
     if ((32 > (Pos + Size)) || ((Pos + Size) > 64))
       return Match_RequiresPosSizeRange33_64;
     return Match_Success;
   }
+  case Mips::CRC32B: case Mips::CRC32CB:
+  case Mips::CRC32H: case Mips::CRC32CH:
+  case Mips::CRC32W: case Mips::CRC32CW:
+  case Mips::CRC32D: case Mips::CRC32CD:
+    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg())
+      return Match_RequiresSameSrcAndDst;
+    return Match_Success;
   }
 
   uint64_t TSFlags = getInstDesc(Inst.getOpcode()).TSFlags;
   if ((TSFlags & MipsII::HasFCCRegOperand) &&
       (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters())
     return Match_NoFCCRegisterForCurrentISA;
 
   return Match_Success;
bool MipsAsmParser::parseSetNoMtDirective() {
 
   clearFeatureBits(Mips::FeatureMT, "mt");
 
   getTargetStreamer().emitDirectiveSetNoMt();
   Parser.Lex(); // Consume the EndOfStatement.
   return false;
 }
 
+bool MipsAsmParser::parseSetNoCRCDirective() {
+  MCAsmParser &Parser = getParser();
+  Parser.Lex(); // Eat "nocrc".
+
+  // If this is not the end of the statement, report an error.
+  if (getLexer().isNot(AsmToken::EndOfStatement)) {
+    reportParseError("unexpected token, expected end of statement");
+    return false;
+  }
+
+  clearFeatureBits(Mips::FeatureCRC, "crc");
+
+  getTargetStreamer().emitDirectiveSetNoCRC();
+  Parser.Lex(); // Consume the EndOfStatement.
+  return false;
+}
+
 bool MipsAsmParser::parseSetPopDirective() {
   MCAsmParser &Parser = getParser();
   SMLoc Loc = getLexer().getLoc();
 
   Parser.Lex();
   if (getLexer().isNot(AsmToken::EndOfStatement))
     return reportParseError("unexpected token, expected end of statement");
 
bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
   case Mips::FeatureMips64r5:
     selectArch("mips64r5");
     getTargetStreamer().emitDirectiveSetMips64R5();
     break;
   case Mips::FeatureMips64r6:
     selectArch("mips64r6");
     getTargetStreamer().emitDirectiveSetMips64R6();
     break;
+  case Mips::FeatureCRC:
+    setFeatureBits(Mips::FeatureCRC, "crc");
+    getTargetStreamer().emitDirectiveSetCRC();
+    break;
   }
   return false;
 }
 
 bool MipsAsmParser::eatComma(StringRef ErrorStr) {
   MCAsmParser &Parser = getParser();
   if (getLexer().isNot(AsmToken::Comma)) {
     SMLoc Loc = getLexer().getLoc();
bool MipsAsmParser::parseDirectiveSet() {
   } else if (Tok.getString() == "mt") {
     return parseSetMtDirective();
   } else if (Tok.getString() == "nomt") {
     return parseSetNoMtDirective();
   } else if (Tok.getString() == "softfloat") {
     return parseSetSoftFloatDirective();
   } else if (Tok.getString() == "hardfloat") {
     return parseSetHardFloatDirective();
+  } else if (Tok.getString() == "crc") {
+    return parseSetFeature(Mips::FeatureCRC);
+  } else if (Tok.getString() == "nocrc") {
+    return parseSetNoCRCDirective();
   } else {
     // It is just an identifier, look for an assignment.
     parseSetAssignment();
     return false;
   }
 
   return true;
 }

 
 /// parseDirectiveModule
 ///  ::= .module oddspreg
 ///  ::= .module nooddspreg
 ///  ::= .module fp=value
 ///  ::= .module softfloat
 ///  ::= .module hardfloat
 ///  ::= .module mt
+///  ::= .module crc
+///  ::= .module nocrc
 bool MipsAsmParser::parseDirectiveModule() {
   MCAsmParser &Parser = getParser();
   MCAsmLexer &Lexer = getLexer();
   SMLoc L = Lexer.getLoc();
 
   if (!getTargetStreamer().isModuleDirectiveAllowed()) {
     // TODO : get a better message.
     reportParseError(".module directive must appear before any code");
if (Option == "oddspreg") {
 
     // If this is not the end of the statement, report an error.
     if (getLexer().isNot(AsmToken::EndOfStatement)) {
       reportParseError("unexpected token, expected end of statement");
       return false;
     }
 
     return false; // parseDirectiveModule has finished successfully.
+  } else if (Option == "crc") {
+    setModuleFeatureBits(Mips::FeatureCRC, "crc");
+
+    // Synchronize the ABI Flags information with the FeatureBits information we
+    // updated above.
+    getTargetStreamer().updateABIInfo(*this);
+
+    // If printing assembly, use the recently updated ABI Flags information.
+    // If generating ELF, don't do anything (the .MIPS.abiflags section gets
+    // emitted later).
+    getTargetStreamer().emitDirectiveModuleCRC();
+
+    // If this is not the end of the statement, report an error.
+    if (getLexer().isNot(AsmToken::EndOfStatement)) {
+      reportParseError("unexpected token, expected end of statement");
+      return false;
+    }
+
+    return false; // parseDirectiveModule has finished successfully.
+  } else if (Option == "nocrc") {
+    clearModuleFeatureBits(Mips::FeatureCRC, "crc");
+
+    // Synchronize the ABI Flags information with the FeatureBits information we
+    // updated above.
+    getTargetStreamer().updateABIInfo(*this);
+
+    // If printing assembly, use the recently updated ABI Flags information.
+    // If generating ELF, don't do anything (the .MIPS.abiflags section gets
+    // emitted later).
+    getTargetStreamer().emitDirectiveModuleNoCRC();
+
+    // If this is not the end of the statement, report an error.
+    if (getLexer().isNot(AsmToken::EndOfStatement)) {
+      reportParseError("unexpected token, expected end of statement");
+      return false;
+    }
+
+    return false; // parseDirectiveModule has finished successfully.
   } else {
     return Error(L, "'" + Twine(Option) + "' is not a valid .module option.");
   }
 }
 
 /// parseDirectiveModuleFP
 ///  ::= =32
 ///  ::= =xx

llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

 template <typename InsnType>
 static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
                                const void *Decoder);
 
 template <typename InsnType>
 static DecodeStatus DecodeDEXT(MCInst &MI, InsnType Insn, uint64_t Address,
                                const void *Decoder);
 
+template <typename InsnType>
+static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
+                              const void *Decoder);
+
 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
                                          uint64_t Address,
                                          const void *Decoder);
 
 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
                                            uint64_t Address,
                                            const void *Decoder);
 
static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
   MI.setOpcode(Mips::DINS);
   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
   MI.addOperand(MCOperand::createImm(Pos));
   MI.addOperand(MCOperand::createImm(Size));
 
   return MCDisassembler::Success;
 }
+
+// Auto-generated decoder wouldn't add the third operand for CRC32*.
+template <typename InsnType>
+static DecodeStatus DecodeCRC(MCInst &MI, InsnType Insn, uint64_t Address,
+                              const void *Decoder) {
+  InsnType Rs = fieldFromInstruction(Insn, 21, 5);
+  InsnType Rt = fieldFromInstruction(Insn, 16, 5);
+  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
+                                     Rt)));
+  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
+                                     Rs)));
+  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
+                                     Rt)));
+  return MCDisassembler::Success;
+}
+
 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 /// according to the given endianness.
 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
                                       uint64_t &Size, uint32_t &Insn,
                                       bool IsBigEndian) {
   // We want to read exactly 2 Bytes of data.
   if (Bytes.size() < 2) {
     Size = 0;

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h

void setASESetFromPredicates(const PredicateLibrary &P) {
     if (P.hasMSA())
       ASESet |= Mips::AFL_ASE_MSA;
     if (P.inMicroMipsMode())
       ASESet |= Mips::AFL_ASE_MICROMIPS;
     if (P.inMips16Mode())
       ASESet |= Mips::AFL_ASE_MIPS16;
     if (P.hasMT())
       ASESet |= Mips::AFL_ASE_MT;
+    if (P.hasCRC())
+      ASESet |= Mips::AFL_ASE_CRC;
   }
 
   template <class PredicateLibrary>
   void setFpAbiFromPredicates(const PredicateLibrary &P) {
     Is32BitABI = P.isABI_O32();
 
     FpABI = FpABIKind::ANY;
     if (P.useSoftFloat())

llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMt() {}
 void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
+void MipsTargetStreamer::emitDirectiveSetCRC() {}
+void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
   forbidModuleDirective();
 }
 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
 void MipsTargetStreamer::emitDirectiveAbiCalls() {}

 
 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
   if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
     report_fatal_error("+nooddspreg is only valid for O32");
 }
 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
 void MipsTargetStreamer::emitDirectiveModuleMT() {}
+void MipsTargetStreamer::emitDirectiveModuleCRC() {}
+void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
 void MipsTargetStreamer::emitDirectiveSetFp(
     MipsABIFlagsSection::FpABIKind Value) {
   forbidModuleDirective();
 }
 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
   forbidModuleDirective();
 }
void MipsTargetAsmStreamer::emitDirectiveSetMt() {
   MipsTargetStreamer::emitDirectiveSetMt();
 }
 
 void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
   OS << "\t.set\tnomt\n";
   MipsTargetStreamer::emitDirectiveSetNoMt();
 }
 
+void MipsTargetAsmStreamer::emitDirectiveSetCRC() {
+  OS << "\t.set\tcrc\n";
+  MipsTargetStreamer::emitDirectiveSetCRC();
+}
+
+void MipsTargetAsmStreamer::emitDirectiveSetNoCRC() {
+  OS << "\t.set\tnocrc\n";
+  MipsTargetStreamer::emitDirectiveSetNoCRC();
+}
+
 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
   OS << "\t.set\tat\n";
   MipsTargetStreamer::emitDirectiveSetAt();
 }
 
 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);

 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
   OS << "\t.module\thardfloat\n";
 }
 
 void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
   OS << "\t.module\tmt\n";
 }
 
+void MipsTargetAsmStreamer::emitDirectiveModuleCRC() {
+  OS << "\t.module\tcrc\n";
+}
+
+void MipsTargetAsmStreamer::emitDirectiveModuleNoCRC() {
+  OS << "\t.module\tnocrc\n";
+}
+
 // This part is for ELF object output.
 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
                                              const MCSubtargetInfo &STI)
     : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
   MCAssembler &MCA = getStreamer().getAssembler();
 
   // It's possible that MCObjectFileInfo isn't fully initialized at this point
   // due to an initialization order problem where LLVMTargetMachine creates the

llvm/trunk/lib/Target/Mips/Mips.td

 def FeatureDSPR3
     : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
                        [ FeatureDSP, FeatureDSPR2 ]>;
 
 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
 
 def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
 
+def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Mips R6 CRC ASE">;
+
 def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
                                          "microMips mode">;
 
 def FeatureCnMips     : SubtargetFeature<"cnmips", "HasCnMips",
                                 "true", "Octeon cnMIPS Support",
                                 [FeatureMips64r2]>;
 
 def FeatureUseTCCInDIV : SubtargetFeature<

llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td

class COP2LDST_FM<OPCODE5 Operation> : MipsR6Inst {
   bits<32> Inst;
 
   let Inst{31-26} = OPGROUP_COP2LDST.Value;
   let Inst{25-21} = Operation.Value;
   let Inst{20-16} = rt;
   let Inst{15-11} = base;
   let Inst{10-0}  = offset;
 }
+
+class SPECIAL3_2R_SZ_CRC<bits<2> sz, bits<3> direction> : MipsR6Inst {
+  bits<5> rs;
+  bits<5> rt;
+
+  let Inst{31-26} = OPGROUP_SPECIAL3.Value;
+  let Inst{25-21} = rs;
+  let Inst{20-16} = rt;
+  let Inst{15-11} = 0b00000;
+  let Inst{10-8} = direction;
+  let Inst{7-6} = sz;
+  let Inst{5-0} = 0b001111;
+
+  string DecoderMethod = "DecodeCRC";
+}

llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td

 class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>;
 class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>;
 
 class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>;
 class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>;
 
 class SDBBP_R6_ENC : SPECIAL_SDBBP_FM;
 
+class CRC32B_ENC  : SPECIAL3_2R_SZ_CRC<0,0>;
+class CRC32H_ENC  : SPECIAL3_2R_SZ_CRC<1,0>;
+class CRC32W_ENC  : SPECIAL3_2R_SZ_CRC<2,0>;
+class CRC32CB_ENC : SPECIAL3_2R_SZ_CRC<0,1>;
+class CRC32CH_ENC : SPECIAL3_2R_SZ_CRC<1,1>;
+class CRC32CW_ENC : SPECIAL3_2R_SZ_CRC<2,1>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Multiclasses
 //
 //===----------------------------------------------------------------------===//
 
 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
                           RegisterOperand FGROpnd,
class SDBBP_R6_DESC {
   dag OutOperandList = (outs);
   dag InOperandList = (ins uimm20:$code_);
   string AsmString = "sdbbp\t$code_";
   list<dag> Pattern = [];
   bit isCTI = 1;
   InstrItinClass Itinerary = II_SDBBP;
 }
 
+class CRC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
+                    InstrItinClass itin> : MipsR6Arch<instr_asm> {
+  dag OutOperandList = (outs GPROpnd:$rd);
+  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
+  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = itin;
+}
+
+class CRC32B_DESC : CRC_DESC_BASE<"crc32b", GPR32Opnd, II_CRC32B>;
+class CRC32H_DESC : CRC_DESC_BASE<"crc32h", GPR32Opnd, II_CRC32H>;
+class CRC32W_DESC : CRC_DESC_BASE<"crc32w", GPR32Opnd, II_CRC32W>;
+class CRC32CB_DESC : CRC_DESC_BASE<"crc32cb", GPR32Opnd, II_CRC32CB>;
+class CRC32CH_DESC : CRC_DESC_BASE<"crc32ch", GPR32Opnd, II_CRC32CH>;
+class CRC32CW_DESC : CRC_DESC_BASE<"crc32cw", GPR32Opnd, II_CRC32CW>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
 def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
   def SELNEZ_S : R6MMR6Rel, SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6,
                  HARDFLOAT;
   def SEL_D : R6MMR6Rel, SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
   def SEL_S : R6MMR6Rel, SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
   def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
   def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
 }
 
+let AdditionalPredicates = [NotInMicroMips] in {
+  def CRC32B : R6MMR6Rel, CRC32B_ENC, CRC32B_DESC, ISA_MIPS32R6, ASE_CRC;
+  def CRC32H : R6MMR6Rel, CRC32H_ENC, CRC32H_DESC, ISA_MIPS32R6, ASE_CRC;
+  def CRC32W : R6MMR6Rel, CRC32W_ENC, CRC32W_DESC, ISA_MIPS32R6, ASE_CRC;
+  def CRC32CB : R6MMR6Rel, CRC32CB_ENC, CRC32CB_DESC, ISA_MIPS32R6, ASE_CRC;
+  def CRC32CH : R6MMR6Rel, CRC32CH_ENC, CRC32CH_DESC, ISA_MIPS32R6, ASE_CRC;
+  def CRC32CW : R6MMR6Rel, CRC32CW_ENC, CRC32CW_DESC, ISA_MIPS32R6, ASE_CRC;
+}
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Aliases
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsInstAlias<"dvp", (DVP ZERO), 0>, ISA_MIPS32R6;
 def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6;

llvm/trunk/lib/Target/Mips/Mips64r6InstrInfo.td

 class DMODU_ENC   : SPECIAL_3R_FM<0b00011, 0b011111>;
 class DMUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011100>;
 class DMUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011101>;
 class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
 class DMULU_ENC   : SPECIAL_3R_FM<0b00010, 0b011101>;
 class LDPC_ENC    : PCREL18_FM<OPCODE3_LDPC>;
 class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
 class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
+class CRC32D_ENC  : SPECIAL3_2R_SZ_CRC<3,0>;
+class CRC32CD_ENC : SPECIAL3_2R_SZ_CRC<3,1>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> {
class JR_HB64_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR64Opnd> {
   bit isBranch = 1;
   bit isIndirectBranch = 1;
   bit hasDelaySlot = 1;
   bit isTerminator=1;
   bit isBarrier=1;
   bit isCTI = 1;
   InstrItinClass Itinerary = II_JR_HB;
 }
+
+class CRC32D_DESC  : CRC_DESC_BASE<"crc32d", GPR32Opnd, II_CRC32D>;
+class CRC32CD_DESC : CRC_DESC_BASE<"crc32cd", GPR32Opnd, II_CRC32CD>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let AdditionalPredicates = [NotInMicroMips] in {
   let DecoderMethod = "DecodeDAHIDATI" in {

 def BLTUC64 : BLTUC_ENC, BLTUC64_DESC, ISA_MIPS64R6, GPR_64;
 def BNEC64 : BNEC_ENC, BNEC64_DESC, ISA_MIPS64R6, GPR_64;
 def BNEZC64 : BNEZC_ENC, BNEZC64_DESC, ISA_MIPS64R6, GPR_64;
 }
 let DecoderNamespace = "Mips32r6_64r6_BranchZero" in {
 def BLTZC64 : BLTZC_ENC, BLTZC64_DESC, ISA_MIPS64R6, GPR_64;
 def BGEZC64 : BGEZC_ENC, BGEZC64_DESC, ISA_MIPS64R6, GPR_64;
 }
+let AdditionalPredicates = [NotInMicroMips] in {
+  def CRC32D : R6MMR6Rel, CRC32D_ENC, CRC32D_DESC, ISA_MIPS64R6, ASE_CRC;
+  def CRC32CD : R6MMR6Rel, CRC32CD_ENC, CRC32CD_DESC, ISA_MIPS64R6, ASE_CRC;
+}
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Aliases
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsInstAlias<"jr $rs", (JALR64 ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS64R6;

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

 def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">,
                AssemblerPredicate<"!FeatureMadd4">;
 def HasMT  : Predicate<"Subtarget->hasMT()">,
              AssemblerPredicate<"FeatureMT">;
 def UseIndirectJumpsHazard : Predicate<"Subtarget->useIndirectJumpsHazard()">,
                             AssemblerPredicate<"FeatureUseIndirectJumpsHazard">;
 def NoIndirectJumpGuards : Predicate<"!Subtarget->useIndirectJumpsHazard()">,
                            AssemblerPredicate<"!FeatureUseIndirectJumpsHazard">;
+def HasCRC   : Predicate<"Subtarget->hasCRC()">,
+               AssemblerPredicate<"FeatureCRC">;
 //===----------------------------------------------------------------------===//
 // Mips GPR size adjectives.
 // They are mutually exclusive.
 //===----------------------------------------------------------------------===//
 
 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
 

 class ASE_MSA64 {
   list<Predicate> ASEPredicate = [HasMSA, HasMips64];
 }
 
 class ASE_MT {
   list <Predicate> ASEPredicate = [HasMT];
 }
 
+class ASE_CRC {
+  list <Predicate> ASEPredicate = [HasCRC];
+}
+
 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
 // It can be used only on instructions that doesn't inherit PredicateControl.
 class ISA_MICROMIPS_NOT_32R6 : PredicateControl {
   let InsnPredicates = [NotMips32r6];
   let EncodingPredicates = [InMicroMips];
 }
 
 class ASE_NOT_DSP {

llvm/trunk/lib/Target/Mips/MipsSchedule.td

 def II_BCCZALS          : InstrItinClass; // bgezals and bltzals
 def II_BCCZC            : InstrItinClass; // beqzc, bnezc
 def II_BITSWAP          : InstrItinClass;
 def II_CEIL             : InstrItinClass;
 def II_CFC1             : InstrItinClass;
 def II_CFC2             : InstrItinClass;
 def II_CLO              : InstrItinClass;
 def II_CLZ              : InstrItinClass;
+def II_CRC32B           : InstrItinClass;
+def II_CRC32CB          : InstrItinClass;
+def II_CRC32CD          : InstrItinClass;
+def II_CRC32CH          : InstrItinClass;
+def II_CRC32CW          : InstrItinClass;
+def II_CRC32D           : InstrItinClass;
+def II_CRC32H           : InstrItinClass;
+def II_CRC32W           : InstrItinClass;
 def II_CTC1             : InstrItinClass;
 def II_CTC2             : InstrItinClass;
 def II_CVT              : InstrItinClass;
 def II_C_CC_D           : InstrItinClass; // Any c.<cc>.d instruction
 def II_C_CC_S           : InstrItinClass; // Any c.<cc>.s instruction
 def II_CMP_CC_D         : InstrItinClass; // Any cmp.<cc>.d instruction
 def II_CMP_CC_S         : InstrItinClass; // Any cmp.<cc>.s instruction
 def II_CLASS_D          : InstrItinClass;
def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
   InstrItinData<II_TLBINV          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_TLBINVF         , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_LLE             , [InstrStage<3,  [ALU]>]>,
   InstrItinData<II_SCE             , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_WRPGPR          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_RDPGPR          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_DVP             , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_EVP             , [InstrStage<1,  [ALU]>]>,
-  InstrItinData<II_YIELD           , [InstrStage<5,  [ALU]>]>
+  InstrItinData<II_YIELD           , [InstrStage<5,  [ALU]>]>,
+  InstrItinData<II_CRC32B          , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_CRC32H          , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_CRC32W          , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_CRC32D          , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_CRC32CB         , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_CRC32CH         , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_CRC32CW         , [InstrStage<1,  [ALU]>]>,
+  InstrItinData<II_CRC32CD         , [InstrStage<1,  [ALU]>]>
 ]>;

llvm/trunk/lib/Target/Mips/MipsSubtarget.h

class MipsSubtarget : public MipsGenSubtargetInfo {
  
   // nomadd4 - disables generation of 4-operand madd.s, madd.d and
   // related instructions.
   bool DisableMadd4;
 
   // HasMT -- support MT ASE.
   bool HasMT;
 
+  // HasCRC -- supports R6 CRC ASE
+  bool HasCRC;
+
   // Use hazard variants of the jump register instructions for indirect
   // function calls and jump tables.
   bool UseIndirectJumpsHazard;
 
   // Disable use of the `jal` instruction.
   bool UseLongCalls = false;
 
   /// The minimum alignment known to hold of the stack frame on
public:
   bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
   bool hasDSP() const { return HasDSP; }
   bool hasDSPR2() const { return HasDSPR2; }
   bool hasDSPR3() const { return HasDSPR3; }
   bool hasMSA() const { return HasMSA; }
   bool disableMadd4() const { return DisableMadd4; }
   bool hasEVA() const { return HasEVA; }
   bool hasMT() const { return HasMT; }
+  bool hasCRC() const { return HasCRC; }
   bool useIndirectJumpsHazard() const {
     return UseIndirectJumpsHazard && hasMips32r2();
   }
   bool useSmallSection() const { return UseSmallSection; }
 
   bool hasStandardEncoding() const { return !inMips16Mode(); }
 
   bool useSoftFloat() const { return IsSoftFloat; }

llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp

: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
       IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
       NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
       IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
       HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
       HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
       InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
       HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
       Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
-      HasEVA(false), DisableMadd4(false), HasMT(false),
+      HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
       UseIndirectJumpsHazard(false), StackAlignOverride(StackAlignOverride),
       TM(TM), TargetTriple(TT), TSInfo(),
       InstrInfo(
           MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
       FrameLowering(MipsFrameLowering::create(*this)),
       TLInfo(MipsTargetLowering::create(TM, *this)) {
 
   if (MipsArchVersion == MipsDefault)

llvm/trunk/lib/Target/Mips/MipsTargetStreamer.h

public:
   virtual void emitDirectiveSetReorder();
   virtual void emitDirectiveSetNoReorder();
   virtual void emitDirectiveSetMacro();
   virtual void emitDirectiveSetNoMacro();
   virtual void emitDirectiveSetMsa();
   virtual void emitDirectiveSetNoMsa();
   virtual void emitDirectiveSetMt();
   virtual void emitDirectiveSetNoMt();
+  virtual void emitDirectiveSetCRC();
+  virtual void emitDirectiveSetNoCRC();
   virtual void emitDirectiveSetAt();
   virtual void emitDirectiveSetAtWithArg(unsigned RegNo);
   virtual void emitDirectiveSetNoAt();
   virtual void emitDirectiveEnd(StringRef Name);
 
   virtual void emitDirectiveEnt(const MCSymbol &Symbol);
   virtual void emitDirectiveAbiCalls();
   virtual void emitDirectiveNaN2008();
public:
   virtual void emitDirectiveModuleFP();
   virtual void emitDirectiveModuleOddSPReg();
   virtual void emitDirectiveModuleSoftFloat();
   virtual void emitDirectiveModuleHardFloat();
   virtual void emitDirectiveModuleMT();
   virtual void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value);
   virtual void emitDirectiveSetOddSPReg();
   virtual void emitDirectiveSetNoOddSPReg();
+  virtual void emitDirectiveModuleCRC();
+  virtual void emitDirectiveModuleNoCRC();
 
   void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
              const MCSubtargetInfo *STI);
   void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
               const MCSubtargetInfo *STI);
   void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
               const MCSubtargetInfo *STI);
   void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
public:
   void emitDirectiveSetReorder() override;
   void emitDirectiveSetNoReorder() override;
   void emitDirectiveSetMacro() override;
   void emitDirectiveSetNoMacro() override;
   void emitDirectiveSetMsa() override;
   void emitDirectiveSetNoMsa() override;
   void emitDirectiveSetMt() override;
   void emitDirectiveSetNoMt() override;
+  void emitDirectiveSetCRC() override;
+  void emitDirectiveSetNoCRC() override;
   void emitDirectiveSetAt() override;
   void emitDirectiveSetAtWithArg(unsigned RegNo) override;
   void emitDirectiveSetNoAt() override;
   void emitDirectiveEnd(StringRef Name) override;
 
   void emitDirectiveEnt(const MCSymbol &Symbol) override;
   void emitDirectiveAbiCalls() override;
   void emitDirectiveNaN2008() override;
void emitDirectiveCpreturn(unsigned SaveLocation,
                              bool SaveLocationIsRegister) override;
 
   // FP abiflags directives
   void emitDirectiveModuleFP() override;
   void emitDirectiveModuleOddSPReg() override;
   void emitDirectiveModuleSoftFloat() override;
   void emitDirectiveModuleHardFloat() override;
   void emitDirectiveModuleMT() override;
+  void emitDirectiveModuleCRC() override;
+  void emitDirectiveModuleNoCRC() override;
   void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value) override;
   void emitDirectiveSetOddSPReg() override;
   void emitDirectiveSetNoOddSPReg() override;
 };
 
 // This part is for ELF object output
 class MipsTargetELFStreamer : public MipsTargetStreamer {
   bool MicroMipsEnabled;

llvm/trunk/test/MC/Disassembler/Mips/crc/valid-32r6-el.txt

+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux-gnu \
+# RUN:   -mcpu=mips32r6 -mattr=+crc | FileCheck %s
+
+0x0f 0x00 0x41 0x7c  # CHECK: crc32b $1, $2, $1
+0x4f 0x00 0xa4 0x7c  # CHECK: crc32h $4, $5, $4
+0x8f 0x00 0x07 0x7d  # CHECK: crc32w $7, $8, $7
+0x0f 0x01 0x41 0x7c  # CHECK: crc32cb $1, $2, $1
+0x4f 0x01 0xa4 0x7c  # CHECK: crc32ch $4, $5, $4
+0x8f 0x01 0x07 0x7d  # CHECK: crc32cw $7, $8, $7

llvm/trunk/test/MC/Disassembler/Mips/crc/valid-32r6.txt

+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux-gnu \
+# RUN:   -mcpu=mips32r6 -mattr=+crc | FileCheck %s
+
+0x7c 0x41 0x00 0x0f  # CHECK: crc32b $1, $2, $1
+0x7c 0xa4 0x00 0x4f  # CHECK: crc32h $4, $5, $4
+0x7d 0x07 0x00 0x8f  # CHECK: crc32w $7, $8, $7
+0x7c 0x41 0x01 0x0f  # CHECK: crc32cb $1, $2, $1
+0x7c 0xa4 0x01 0x4f  # CHECK: crc32ch $4, $5, $4
+0x7d 0x07 0x01 0x8f  # CHECK: crc32cw $7, $8, $7

llvm/trunk/test/MC/Disassembler/Mips/crc/valid-64r6-el.txt

+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux-gnu \
+# RUN:   -mcpu=mips64r6 -mattr=+crc | FileCheck %s
+
+0x0f 0x00 0x41 0x7c  # CHECK: crc32b $1, $2, $1
+0x4f 0x00 0xa4 0x7c  # CHECK: crc32h $4, $5, $4
+0x8f 0x00 0x07 0x7d  # CHECK: crc32w $7, $8, $7
+0xcf 0x00 0x6a 0x7d  # CHECK: crc32d $10, $11, $10
+0x0f 0x01 0x41 0x7c  # CHECK: crc32cb $1, $2, $1
+0x4f 0x01 0xa4 0x7c  # CHECK: crc32ch $4, $5, $4
+0x8f 0x01 0x07 0x7d  # CHECK: crc32cw $7, $8, $7
+0xcf 0x01 0x6a 0x7d  # CHECK: crc32cd $10, $11, $10

llvm/trunk/test/MC/Disassembler/Mips/crc/valid-64r6.txt

+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux-gnu \
+# RUN:   -mcpu=mips64r6 -mattr=+crc | FileCheck %s
+
+0x7c 0x41 0x00 0x0f  # CHECK: crc32b $1, $2, $1
+0x7c 0xa4 0x00 0x4f  # CHECK: crc32h $4, $5, $4
+0x7d 0x07 0x00 0x8f  # CHECK: crc32w $7, $8, $7
+0x7d 0x6a 0x00 0xcf  # CHECK: crc32d $10, $11, $10
+0x7c 0x41 0x01 0x0f  # CHECK: crc32cb $1, $2, $1
+0x7c 0xa4 0x01 0x4f  # CHECK: crc32ch $4, $5, $4
+0x7d 0x07 0x01 0x8f  # CHECK: crc32cw $7, $8, $7
+0x7d 0x6a 0x01 0xcf  # CHECK: crc32cd $10, $11, $10

llvm/trunk/test/MC/Mips/crc/invalid.s

+# Instructions that are invalid.
+#
+# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+crc 2>%t1
+# RUN: FileCheck %s < %t1
+# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 -mattr=+crc 2>%t1
+# RUN: FileCheck %s < %t1
+
+  .set noat
+  crc32b  $1, $2, $2      # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32b  $1, $2, $3      # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32b  $1, $2, 2       # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+  crc32b  $1, 2, $2       # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+  crc32b  1, $2, $2       # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  crc32b  $1, $2          # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32b  $1              # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32b  $1, $2, 0($2)   # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+
+  crc32h  $1, $2, $2      # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32h  $1, $2, $3      # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32h  $1, $2, 2       # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+  crc32h  $1, 2, $2       # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+  crc32h  1, $2, $2       # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  crc32h  $1, $2          # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32h  $1              # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32h  $1, $2, 0($2)   # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+
+  crc32w  $1, $2, $2      # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32w  $1, $2, $3      # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32w  $1, $2, 2       # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+  crc32w  $1, 2, $2       # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+  crc32w  1, $2, $2       # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  crc32w  $1, $2          # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32w  $1              # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32w  $1, $2, 0($2)   # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+
+  crc32cb  $1, $2, $2     # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32cb  $1, $2, $3     # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32cb  $1, $2, 2      # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
+  crc32cb  $1, 2, $2      # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+  crc32cb  1, $2, $2      # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+  crc32cb  $1, $2         # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32cb  $1             # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32cb  $1, $2, 0($2)  # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
+
+  crc32ch  $1, $2, $2     # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32ch  $1, $2, $3     # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32ch  $1, $2, 2      # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
+  crc32ch  $1, 2, $2      # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+  crc32ch  1, $2, $2      # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+  crc32ch  $1, $2         # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32ch  $1             # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32ch  $1, $2, 0($2)  # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
+
+  crc32cw  $1, $2, $2     # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32cw  $1, $2, $3     # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32cw  $1, $2, 2      # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
+  crc32cw  $1, 2, $2      # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+  crc32cw  1, $2, $2      # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+  crc32cw  $1, $2         # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32cw  $1             # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32cw  $1, $2, 0($2)  # CHECK: :[[@LINE]]:20: error: invalid operand for instruction
+
+  crc32 $1, $2, $2        # CHECK: :[[@LINE]]:3: error: unknown instruction
+  crcb $1, $2, $2         # CHECK: :[[@LINE]]:3: error: unknown instruction
+  crc $1, $2, $2          # CHECK: :[[@LINE]]:3: error: unknown instruction

llvm/trunk/test/MC/Mips/crc/invalid64.s

+# Instructions that are invalid.
+#
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux-gnu -mcpu=mips64r6 \
+# RUN:     -mattr=+crc 2>%t1
+# RUN: FileCheck %s < %t1
+
+  .set noat
+  crc32d $1, $2, $2       # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32d $1, $2, $3       # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32d $1, $2, 2        # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
+  crc32d $1, 2, $2        # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+  crc32d 1, $2, $2        # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+  crc32d $1, $2           # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32d $1               # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32d $1, $2, 0($2)    # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
+
+  crc32cd $1, $2, $2      # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32cd $1, $2, $3      # CHECK: :[[@LINE]]:3: error: source and destination must match
+  crc32cd $1, $2, 2       # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+  crc32cd $1, 2, $2       # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+  crc32cd 1, $2, $2       # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  crc32cd $1, $2          # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32cd $1              # CHECK: :[[@LINE]]:3: error: too few operands for instruction
+  crc32cd $1, $2, 0($2)   # CHECK: :[[@LINE]]:19: error: invalid operand for instruction

llvm/trunk/test/MC/Mips/crc/module-crc.s

+# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -mcpu=mips32r6 | \
+# RUN:   FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -mcpu=mips32r6 \
+# RUN:   -filetype=obj -o - | \
+# RUN:   llvm-readobj -mips-abi-flags - | \
+# RUN:   FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module crc
+
+# Check if the MIPS.abiflags section was correctly emitted:
+# CHECK-OBJ: MIPS ABI Flags {
+# CHECK-OBJ:   ASEs [ (0x8000)
+# CHECK-OBJ:     CRC (0x8000)
+# CHECK-OBJ: }
+
+  .module crc
+  crc32b $2,$3,$2
+
+# FIXME: Test should include gnu_attributes directive when implemented.
+#        An explicit .gnu_attribute must be checked against the effective
+#        command line options and any inconsistencies reported via a warning.

llvm/trunk/test/MC/Mips/crc/module-nocrc.s

+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+crc | \
+# RUN:   FileCheck %s -check-prefix=CHECK-ASM
+#
+# RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -filetype=obj -o - -mattr=+crc | \
+# RUN:   llvm-readobj -mips-abi-flags - | \
+# RUN:   FileCheck %s -check-prefix=CHECK-OBJ
+
+# CHECK-ASM: .module nocrc
+
+# Check that MIPS.abiflags has no CRC flag.
+# CHECK-OBJ: MIPS ABI Flags {
+# CHECK-OBJ:   ASEs [ (0x0)
+# CHECK-OBJ-NOT:   ASEs [ (0x8000)
+# CHECK-OBJ-NOT:     CRC (0x8000)
+# CHECK-OBJ: }
+
+  .module nocrc
+
+# FIXME: Test should include gnu_attributes directive when implemented.
+#        An explicit .gnu_attribute must be checked against the effective
+#        command line options and any inconsistencies reported via a warning.

llvm/trunk/test/MC/Mips/crc/set-crc-directive.s

+# RUN: llvm-mc %s -show-encoding -triple=mips-unknown-linux-gnu \
+# RUN:   -mcpu=mips32r6 | FileCheck %s
+# RUN: llvm-mc %s -show-encoding -triple=mips64-unknown-linux-gnu \
+# RUN:   -mcpu=mips64r6 | FileCheck %s
+
+  .set crc
+  crc32b  $1, $2, $1  # CHECK: crc32b $1, $2, $1 # encoding: [0x7c,0x41,0x00,0x0f]

llvm/trunk/test/MC/Mips/crc/set-nocrc-directive.s

+# RUN: not llvm-mc %s -triple=mips-unknown-linux-gnu -show-encoding \
+# RUN:     -mcpu=mips32r6 -mattr=+crc 2>%t1
+# RUN: FileCheck %s < %t1
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux-gnu -show-encoding \
+# RUN:     -mcpu=mips64r6 -mattr=+crc 2>%t1
+# RUN: FileCheck %s < %t1
+
+  .set nocrc
+  crc32b  $1, $2, $1  # CHECK: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/crc/valid.s

+# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -show-encoding \
+# RUN:   -mcpu=mips32r6 -mattr=+crc | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux-gnu -show-encoding \
+# RUN:   -mcpu=mips64r6 -mattr=+crc | FileCheck %s
+
+  .set noat
+  crc32b $1, $2, $1      # CHECK: crc32b $1, $2, $1   # encoding: [0x7c,0x41,0x00,0x0f]
+  crc32h $4, $5, $4      # CHECK: crc32h $4, $5, $4   # encoding: [0x7c,0xa4,0x00,0x4f]
+  crc32w $7, $8, $7      # CHECK: crc32w $7, $8, $7   # encoding: [0x7d,0x07,0x00,0x8f]
+  crc32cb $1, $2, $1     # CHECK: crc32cb $1, $2, $1  # encoding: [0x7c,0x41,0x01,0x0f]
+  crc32ch $4, $5, $4     # CHECK: crc32ch $4, $5, $4  # encoding: [0x7c,0xa4,0x01,0x4f]
+  crc32cw $7, $8, $7     # CHECK: crc32cw $7, $8, $7  # encoding: [0x7d,0x07,0x01,0x8f]

llvm/trunk/test/MC/Mips/crc/valid64.s

+# RUN: llvm-mc %s -triple=mips64-unknown-linux-gnu -show-encoding \
+# RUN:   -mcpu=mips64r6 -mattr=+crc | FileCheck %s
+
+  .set noat
+  crc32d $10, $11, $10   # CHECK: crc32d  $10, $11, $10  # encoding: [0x7d,0x6a,0x00,0xcf]
+  crc32cd $10, $11, $10  # CHECK: crc32cd $10, $11, $10  # encoding: [0x7d,0x6a,0x01,0xcf]

llvm/trunk/tools/llvm-readobj/ELFDumper.cpp

static const EnumEntry<unsigned> ElfMipsASEFlags[] = {
   {"MDMX",               Mips::AFL_ASE_MDMX},
   {"MIPS-3D",            Mips::AFL_ASE_MIPS3D},
   {"MT",                 Mips::AFL_ASE_MT},
   {"SmartMIPS",          Mips::AFL_ASE_SMARTMIPS},
   {"VZ",                 Mips::AFL_ASE_VIRT},
   {"MSA",                Mips::AFL_ASE_MSA},
   {"MIPS16",             Mips::AFL_ASE_MIPS16},
   {"microMIPS",          Mips::AFL_ASE_MICROMIPS},
-  {"XPA",                Mips::AFL_ASE_XPA}
+  {"XPA",                Mips::AFL_ASE_XPA},
+  {"CRC",                Mips::AFL_ASE_CRC},
 };
 
 static const EnumEntry<unsigned> ElfMipsFpABIType[] = {
   {"Hard or soft float",                  Mips::Val_GNU_MIPS_ABI_FP_ANY},
   {"Hard float (double precision)",       Mips::Val_GNU_MIPS_ABI_FP_DOUBLE},
   {"Hard float (single precision)",       Mips::Val_GNU_MIPS_ABI_FP_SINGLE},
   {"Soft float",                          Mips::Val_GNU_MIPS_ABI_FP_SOFT},
   {"Hard float (MIPS32r2 64-bit FPU 12 callee-saved)",