Propagate flags to SDValue in SplitVecOp_VECREDUCE

[sabuasal]

Summary

This patch is a proposed fix for 36642.

While legalizing long vector types, make sure the smaller types get the
flags of the wider type.

[spatel]

Does D37686 handle this problem too?

[aemerson]

Please add a test.

[sabuasal]

@spatel

Thanks for the review. I tried to apply the patch on tip, it applies cleanly but it doesn't compile, I think it is out of date.

[sabuasal]

@aemerson

Test case added.

Thanks for the review!

[sabuasal]

updated test name.

[aemerson]

LGTM, can you also make the test name a little more specific, e.g. 'vecreduce-propagate-sd-flags.ll'?

test/CodeGen/AArch64/propagate-sdvalue-flags.ll

1

You will also need a REQUIRES: asserts since you use the -debug-only option.

[sabuasal]

committed in @327079

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

case ISD::VECREDUCE_FMIN:
     CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINNAN;
     break;
   default:
     llvm_unreachable("Unexpected reduce ISD node");
   }
 
   // Use the appropriate scalar instruction on the split subvectors before
   // reducing the now partially reduced smaller vector.
-  SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi);
-  return DAG.getNode(N->getOpcode(), dl, ResVT, Partial);
+  SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags());
+  return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags());
 }
 
 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
   // The result has a legal vector type, but the input needs splitting.
   EVT ResVT = N->getValueType(0);
   SDValue Lo, Hi;
   SDLoc dl(N);
   GetSplitVector(N->getOperand(0), Lo, Hi);

test/CodeGen/AArch64/propagate-sdvalue-flags.ll

+; REQUIRES: arm-registered-target
+; RUN: llc %s -debug-only=legalize-types 2>&1 | FileCheck %s
+
+; This test check that when v4f64 gets broken down to two v2f64 it maintains
+; the "nnan" flags.
+
+; CHECK: Legalizing node: [[VFOUR:t.*]]: v4f64 = BUILD_VECTOR
+; CHECK-NEXT: Analyzing result type: v4f64
+; CHECK-NEXT: Split node result: [[VFOUR]]: v4f64 = BUILD_VECTOR
+
+; CHECK: Legalizing node: [[VTWO:t.*]]: v2f64 = BUILD_VECTOR
+; CHECK: Legally typed node: [[VTWO]]: v2f64 = BUILD_VECTOR
+; CHECK: Legalizing node: t26: v2f64 = fmaxnum nnan [[VTWO]], [[VTWO]]
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnu"
+
+
+; Function Attrs: norecurse nounwind
+define fastcc double @test() unnamed_addr #1 {
+entry:
+ %0 = insertelement <4 x double> undef, double 1.0, i32 0
+ %1 = insertelement <4 x double> %0, double 1.0, i32 1
+ %2 = insertelement <4 x double> %1, double 1.0, i32 2
+ %3 = insertelement <4 x double> %2, double 1.0, i32 3
+ %4 = call nnan double @llvm.experimental.vector.reduce.fmax.f64.v4f64(<4 x double> %3)
+ ret double %4
+}
+
+declare double @llvm.experimental.vector.reduce.fmax.f64.v4f64(<4 x double>)