[mips] Fix the definitions of the EVA instructions

[sdardis]

Summary

Correct their availability to their respective ISAs.

[sdardis]

Based on my comments on D44176, I'm preparing another patch which is the splitting out of the ASEPredicate from InsnPredicates in PredicateControl.

[sdardis]

Update to account for splitting out one of the changes into D44299.

[atanasyan]

LGTM

[sdardis]

lib/Target/Mips/MicroMipsInstrInfo.td

965–992

This change crept in from the next patch in the series, I'll remove it from this one.

lib/Target/Mips/MipsInstrInfo.td

2070

As did this.

test/MC/Mips/micromips/valid.s

166–188

And this.

[sdardis]

Update to remove unrelated changes to trap instructions.

[atanasyan]

Anyway LGTM :)

lib/Target/Mips/MicroMipsInstrInfo.td

let DecoderMethod = "DecodeMemMMImm16" in {
     def LW_MM  : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>;
     def SB_MM  : Store<"sb", GPR32Opnd, null_frag, II_SB>, MMRel,
                  LW_FM_MM<0x6>;
     def SH_MM  : Store<"sh", GPR32Opnd, null_frag, II_SH>, MMRel,
                  LW_FM_MM<0xe>;
     def SW_MM  : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel,
                  LW_FM_MM<0x3e>;
   }
-
+}
+let DecoderNamespace = "MicroMips" in {
   let DecoderMethod = "DecodeMemMMImm9" in {
     def LBE_MM  : MMRel, Load<"lbe", GPR32Opnd, null_frag, II_LBE>,
-                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
+                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>, ISA_MICROMIPS, ASE_EVA;
     def LBuE_MM : MMRel, Load<"lbue", GPR32Opnd, null_frag, II_LBUE>,
-                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
-    def LHE_MM  : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9,
-                                    null_frag, II_LHE>,
-                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
-    def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9,
-                                    null_frag, II_LHUE>,
-                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
-    def LWE_MM  : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9,
-                                     null_frag, II_LWE>,
-                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
-    def SBE_MM  : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9,
-                                     null_frag, II_SBE>,
-                  POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
-    def SHE_MM  : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9,
-                                     null_frag, II_SHE>,
-                  POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
-    def SWE_MM  : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9,
-                                     null_frag, II_SWE>,
-                  POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
+                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>, ISA_MICROMIPS, ASE_EVA;
+    def LHE_MM  : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9, null_frag,
+                                    II_LHE>,
+                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>, ISA_MICROMIPS, ASE_EVA;
+    def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag,
+                                    II_LHUE>,
+                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>, ISA_MICROMIPS, ASE_EVA;
+    def LWE_MM  : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag,
+                                    II_LWE>,
+                  POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>, ISA_MICROMIPS, ASE_EVA;
+    def SBE_MM  : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9, null_frag,
+                                     II_SBE>,
+                  POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>, ISA_MICROMIPS, ASE_EVA;
+    def SHE_MM  : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9, null_frag,
+                                     II_SHE>,
+                  POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>, ISA_MICROMIPS, ASE_EVA;
+    def SWE_MM  : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9, null_frag,
+                                     II_SWE>,
+                  POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>, ISA_MICROMIPS, ASE_EVA;
+    def LWLE_MM : MMRel, LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9,
+                                         II_LWLE>,
+                  POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>,
+                  ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
+    def LWRE_MM : MMRel, LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9,
+                                         II_LWRE>,
+                  POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>,
+                  ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
+    def SWLE_MM : MMRel, StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9,
+                                          II_SWLE>,
+                  POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>,
+                  ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
+    def SWRE_MM : MMRel, StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9,
+                                          II_SWRE>,
+                  POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>,
+                  ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
   }
-
+}
+let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
 
   /// Load and Store Instructions - unaligned
   def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12, II_LWL>,
                LWL_FM_MM<0x0>;
   def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12, II_LWR>,
                LWL_FM_MM<0x1>;
   def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12, II_SWL>,
                LWL_FM_MM<0x8>;
   def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12, II_SWR>,
                LWL_FM_MM<0x9>;
-  let DecoderMethod = "DecodeMemMMImm9" in {
-    def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9,
-                                  II_LWLE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>;
-    def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9,
-                                  II_LWRE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>;
-    def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9,
-                                   II_SWLE>,
-                  POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>;
-    def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9,
-                                   II_SWRE>,
-                  POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6;
-  }
 
   /// Load and Store Instructions - multiple
   def SWM32_MM  : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>;
   def LWM32_MM  : LoadMultMM<"lwm32", II_LWM>, LWM_FM_MM<0x5>;
 
   /// Load and Store Pair Instructions
   def SWP_MM  : StorePairMM<"swp">, LWM_FM_MM<0x9>;
   def LWP_MM  : LoadPairMM<"lwp">, LWM_FM_MM<0x1>;
let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   def WAIT_MM    : WaitMM<"wait">, WAIT_FM_MM;
   def ERET_MM    : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>;
   def DERET_MM   : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>;
   def EI_MM      : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>,
                    ISA_MIPS32R2;
   def DI_MM      : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>,
                    ISA_MIPS32R2;
 
   /// Trap Instructions
   def TEQ_MM  : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>;
   def TGE_MM  : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4, II_TGE>, TEQ_FM_MM<0x08>;
   def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4, II_TGEU>,
                 TEQ_FM_MM<0x10>;
   def TLT_MM  : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4, II_TLT>, TEQ_FM_MM<0x20>;
   def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4, II_TLTU>,
                 TEQ_FM_MM<0x28>;
   def TNE_MM  : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4, II_TNE>, TEQ_FM_MM<0x30>;
 
   def TEQI_MM  : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM_MM<0x0e>;
   def TGEI_MM  : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM_MM<0x09>;
   def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>,
                  TEQI_FM_MM<0x0b>;
   def TLTI_MM  : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM_MM<0x08>;
   def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>,
                  TEQI_FM_MM<0x0a>;
   def TNEI_MM  : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM_MM<0x0c>;
 
   /// Load-linked, Store-conditional
   def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
   def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
-
-  def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>;
-  def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>;
-
+}
+let DecoderNamespace = "MicroMips" in {
+  def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>,
+               ISA_MICROMIPS, ASE_EVA;
+  def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>,
+               ISA_MICROMIPS, ASE_EVA;
+}
+let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   let DecoderMethod = "DecodeCacheOpMM" in {
   def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,
                  CACHE_PREF_FM_MM<0x08, 0x6>;
   def PREF_MM  : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>,
                  CACHE_PREF_FM_MM<0x18, 0x2>;
   }
-
+}
+let DecoderNamespace = "MicroMips" in {
   let DecoderMethod = "DecodePrefeOpMM" in {
     def PREFE_MM  : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>,
-                    CACHE_PREFE_FM_MM<0x18, 0x2>;
+                    CACHE_PREFE_FM_MM<0x18, 0x2>, ISA_MICROMIPS, ASE_EVA;
     def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>,
-                    CACHE_PREFE_FM_MM<0x18, 0x3>;
+                    CACHE_PREFE_FM_MM<0x18, 0x3>, ISA_MICROMIPS, ASE_EVA;
   }
+}
+let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
   def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>;
   def EHB_MM   : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>;
   def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>;
 
   def TLBP_MM : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM_MM<0x0d>;
   def TLBR_MM : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM_MM<0x4d>;
   def TLBWI_MM : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM_MM<0x8d>;
   def TLBWR_MM : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM_MM<0xcd>;

lib/Target/Mips/MipsEVAInstrInfo.td

 // Load/Store Left/Right EVA descriptions
 class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
                                     InstrItinClass itin = NoItinerary> {
   dag OutOperandList = (outs GPROpnd:$rt);
   dag InOperandList = (ins mem_simm9:$addr, GPROpnd:$src);
   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   list<dag> Pattern = [];
   string DecoderMethod = "DecodeMemEVA";
+  string BaseOpcode = instr_asm;
   string Constraints = "$src = $rt";
   bit canFoldAsLoad = 1;
   InstrItinClass Itinerary = itin;
 }
 
 class LWLE_DESC  : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwle",  GPR32Opnd, II_LWLE>;
 class LWRE_DESC  : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwre",  GPR32Opnd, II_LWRE>;
 
 class STORE_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
                                      InstrItinClass itin = NoItinerary> {
   dag OutOperandList = (outs);
   dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   list<dag> Pattern = [];
   string DecoderMethod = "DecodeMemEVA";
+  string BaseOpcode = instr_asm;
   InstrItinClass Itinerary = itin;
 }
 
 class SWLE_DESC  : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"swle",  GPR32Opnd, II_SWLE>;
 class SWRE_DESC  : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"swre",  GPR32Opnd, II_SWRE>;
 
 // Load-linked EVA, Store-conditional EVA descriptions
 class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,

 class PREFE_DESC   : CACHEE_DESC_BASE<"prefe", mem_simm9, II_PREFE>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction definitions
 //
 //===----------------------------------------------------------------------===//
 
-/// Load and Store EVA Instructions
-def LBE     : MMRel, LBE_ENC, LBE_DESC, ASE_EVA;
-def LBuE    : MMRel, LBuE_ENC, LBuE_DESC, ASE_EVA;
-def LHE     : MMRel, LHE_ENC, LHE_DESC, ASE_EVA;
-def LHuE    : MMRel, LHuE_ENC, LHuE_DESC, ASE_EVA;
 let AdditionalPredicates = [NotInMicroMips] in {
-def LWE     : MMRel, LWE_ENC, LWE_DESC, ASE_EVA;
-}
-def SBE     : MMRel, SBE_ENC, SBE_DESC, ASE_EVA;
-def SHE     : MMRel, SHE_ENC, SHE_DESC, ASE_EVA;
-let AdditionalPredicates = [NotInMicroMips] in {
-def SWE     : MMRel, SWE_ENC, SWE_DESC, ASE_EVA;
-}
+  /// Load and Store EVA Instructions
+  def LBE     : MMRel, LBE_ENC, LBE_DESC, ISA_MIPS32R2, ASE_EVA;
+  def LBuE    : MMRel, LBuE_ENC, LBuE_DESC, ISA_MIPS32R2, ASE_EVA;
+  def LHE     : MMRel, LHE_ENC, LHE_DESC, ISA_MIPS32R2, ASE_EVA;
+  def LHuE    : MMRel, LHuE_ENC, LHuE_DESC, ISA_MIPS32R2, ASE_EVA;
+  def LWE     : MMRel, LWE_ENC, LWE_DESC, ISA_MIPS32R2, ASE_EVA;
+  def SBE     : MMRel, SBE_ENC, SBE_DESC, ISA_MIPS32R2, ASE_EVA;
+  def SHE     : MMRel, SHE_ENC, SHE_DESC, ISA_MIPS32R2, ASE_EVA;
+  def SWE     : MMRel, SWE_ENC, SWE_DESC, ISA_MIPS32R2, ASE_EVA;
 
   /// load/store left/right EVA
-let AdditionalPredicates = [NotInMicroMips] in {
-def LWLE    : LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
-def LWRE    : LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
-def SWLE    : SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
-def SWRE    : SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
-}
+  def LWLE    : MMRel, LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+  def LWRE    : MMRel, LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+  def SWLE    : MMRel, SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
+  def SWRE    : MMRel, SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA;
 
   /// Load-linked EVA, Store-conditional EVA
-let AdditionalPredicates = [NotInMicroMips] in {
-def LLE     : MMRel, LLE_ENC, LLE_DESC, ASE_EVA;
-def SCE     : MMRel, SCE_ENC, SCE_DESC, ASE_EVA;
-}
+  def LLE     : MMRel, LLE_ENC, LLE_DESC, ISA_MIPS32R2, ASE_EVA;
+  def SCE     : MMRel, SCE_ENC, SCE_DESC, ISA_MIPS32R2, ASE_EVA;
 
-let AdditionalPredicates = [NotInMicroMips] in {
-  def TLBINV  : TLBINV_ENC, TLBINV_DESC, ASE_EVA;
-  def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ASE_EVA;
+  /// TLB invalidate instructions
+  def TLBINV  : TLBINV_ENC, TLBINV_DESC, ISA_MIPS32R2, ASE_EVA;
+  def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ISA_MIPS32R2, ASE_EVA;
+
+  /// EVA versions of cache and pref
+  def CACHEE  : MMRel, CACHEE_ENC, CACHEE_DESC, ISA_MIPS32R2, ASE_EVA;
+  def PREFE   : MMRel, PREFE_ENC, PREFE_DESC, ISA_MIPS32R2, ASE_EVA;
 }
-
-def CACHEE  : MMRel, CACHEE_ENC, CACHEE_DESC, ASE_EVA;
-def PREFE   : MMRel, PREFE_ENC, PREFE_DESC, ASE_EVA;

lib/Target/Mips/MipsInstrInfo.td

def InMicroMips    :  Predicate<"Subtarget->inMicroMipsMode()">,
                       AssemblerPredicate<"FeatureMicroMips">;
 def NotInMicroMips :  Predicate<"!Subtarget->inMicroMipsMode()">,
                       AssemblerPredicate<"!FeatureMicroMips">;
 def IsLE           :  Predicate<"Subtarget->isLittle()">;
 def IsBE           :  Predicate<"!Subtarget->isLittle()">;
 def IsNotNaCl    :    Predicate<"!Subtarget->isTargetNaCl()">;
 def UseTCCInDIV    :  AssemblerPredicate<"FeatureUseTCCInDIV">;
 def HasEVA       :    Predicate<"Subtarget->hasEVA()">,
-                      AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
+                      AssemblerPredicate<"FeatureEVA">;
 def HasMSA : Predicate<"Subtarget->hasMSA()">,
              AssemblerPredicate<"FeatureMSA">;
 def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">,
                AssemblerPredicate<"!FeatureMadd4">;
 def HasMT  : Predicate<"Subtarget->hasMT()">,
              AssemblerPredicate<"FeatureMT">;
 def UseIndirectJumpsHazard : Predicate<"Subtarget->useIndirectJumpsHazard()">,
                             AssemblerPredicate<"FeatureUseIndirectJumpsHazard">;

 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>, TEQI_FM<0x9>,
            ISA_MIPS2_NOT_32R6_64R6;
 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM<0xa>,
            ISA_MIPS2_NOT_32R6_64R6;
 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>, TEQI_FM<0xb>,
            ISA_MIPS2_NOT_32R6_64R6;
 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM<0xe>,
            ISA_MIPS2_NOT_32R6_64R6;
 
 let AdditionalPredicates = [NotInMicroMips] in {
 def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>;
 def SYSCALL : MMRel, SYS_FT<"syscall", uimm20, II_SYSCALL>, SYS_FM<0xc>;
 }
 def TRAP : TrapBase<BREAK>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20, II_SDBBP>, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
 }

test/CodeGen/Mips/micromips-eva.mir

 # RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips -start-after=expand-isel-pseudos \
-# RUN:     -filetype obj %s -o - | llvm-objdump -d - | FileCheck %s
+# RUN:     -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s
 
 --- |
 
   @wArray = global [13 x i32] zeroinitializer, align 4
   @hArray = global [13 x i16] zeroinitializer, align 2
   @bArray = global [13 x i8] zeroinitializer, align 1
 
   ; Function Attrs: noinline nounwind optnone

test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

-# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mattr=micromips \
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mattr=micromips,eva \
 # RUN: | FileCheck %s
 
 0xf9 0x4f # CHECK: addiusp -16
 0xff 0x4f # CHECK: addiusp -1028
 0xfd 0x4f # CHECK: addiusp -1032
 0x01 0x4c # CHECK: addiusp 1024
 0x03 0x4c # CHECK: addiusp 1028
 0x29 0x2c # CHECK: andi16 $16, $2, 31

test/MC/Disassembler/Mips/micromips32r3/valid.txt

-# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mattr=micromips \
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mattr=micromips,eva \
 # RUN: | FileCheck %s
 
 0x4f 0xf9 # CHECK: addiusp -16
 0x4f 0xff # CHECK: addiusp -1028
 0x4f 0xfd # CHECK: addiusp -1032
 0x4c 0x01 # CHECK: addiusp 1024
 0x4c 0x03 # CHECK: addiusp 1028
 0x2c 0x29 # CHECK: andi16 $16, $2, 31

test/MC/Disassembler/Mips/micromips32r6/valid.txt

-# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips,eva | FileCheck %s
 
 0x6f 0x83 # CHECK: addiur1sp $7, 4
 0x6f 0x7e # CHECK: addiur2 $6, $7, -1
 0x6f 0x76 # CHECK: addiur2 $6, $7, 12
 0x4c 0xfc # CHECK: addius5 $7, -2
 0x4f 0xff # CHECK: addiusp -1028
 0x4f 0xfd # CHECK: addiusp -1032
 0x4c 0x01 # CHECK: addiusp 1024

test/MC/Mips/micromips-control-instructions.s

 # CHECK-EL:    ei                         # encoding: [0x00,0x00,0x7c,0x57]
 # CHECK-EL:    ei  $10                    # encoding: [0x0a,0x00,0x7c,0x57]
 # CHECK-EL:    wait                       # encoding: [0x00,0x00,0x7c,0x93]
 # CHECK-EL:    wait 17                    # encoding: [0x11,0x00,0x7c,0x93]
 # CHECK-EL:    tlbp                       # encoding: [0x00,0x00,0x7c,0x03]
 # CHECK-EL:    tlbr                       # encoding: [0x00,0x00,0x7c,0x13]
 # CHECK-EL:    tlbwi                      # encoding: [0x00,0x00,0x7c,0x23]
 # CHECK-EL:    tlbwr                      # encoding: [0x00,0x00,0x7c,0x33]
-# CHECK-EL:    prefe 1, 8($5)             # encoding: [0x25,0x60,0x08,0xa4]
-# CHECK-EL:    cachee 1, 8($5)            # encoding: [0x25,0x60,0x08,0xa6]
 # CHECK-EL:    prefx 1, $3($5)            # encoding: [0x65,0x54,0xa0,0x09]
-# CHECK-EL:    swre $24, 5($3)            # encoding: [0x03,0x63,0x05,0xa2]
-# CHECK-EL:    swle $24, 5($3)            # encoding: [0x03,0x63,0x05,0xa0]
-# CHECK-EL:    lwre $24, 5($3)            # encoding: [0x03,0x63,0x05,0x66]
-# CHECK-EL:    lwle $24, 2($4)            # encoding: [0x04,0x63,0x02,0x64]
-# CHECK-EL:    lle $2, 8($4)              # encoding: [0x44,0x60,0x08,0x6c]
-# CHECK-EL:    sce $2, 8($4)              # encoding: [0x44,0x60,0x08,0xac]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
 # CHECK-EB:   sdbbp                       # encoding: [0x00,0x00,0xdb,0x7c]
 # CHECK-EB:   sdbbp 34                    # encoding: [0x00,0x22,0xdb,0x7c]
 # CHECK-EB-NOT:    .set push
 # CHECK-EB-NOT:    .set mips32r2
 # CHECK-EB:   rdhwr $5, $29               # encoding: [0x00,0xbd,0x6b,0x3c]

 # CHECK-EB:   ei                          # encoding: [0x00,0x00,0x57,0x7c]
 # CHECK-EB:   ei  $10                     # encoding: [0x00,0x0a,0x57,0x7c]
 # CHECK-EB:   wait                        # encoding: [0x00,0x00,0x93,0x7c]
 # CHECK-EB:   wait 17                     # encoding: [0x00,0x11,0x93,0x7c]
 # CHECK-EB:   tlbp                        # encoding: [0x00,0x00,0x03,0x7c]
 # CHECK-EB:   tlbr                        # encoding: [0x00,0x00,0x13,0x7c]
 # CHECK-EB:   tlbwi                       # encoding: [0x00,0x00,0x23,0x7c]
 # CHECK-EB:   tlbwr                       # encoding: [0x00,0x00,0x33,0x7c]
-# CHECK-EB:   prefe 1, 8($5)              # encoding: [0x60,0x25,0xa4,0x08]
-# CHECK-EB:   cachee 1, 8($5)             # encoding: [0x60,0x25,0xa6,0x08]
 # CHECK-EB:   prefx 1, $3($5)             # encoding: [0x54,0x65,0x09,0xa0]
-# CHECK-EB:   swre $24, 5($3)             # encoding: [0x63,0x03,0xa2,0x05]
-# CHECK-EB:   swle $24, 5($3)             # encoding: [0x63,0x03,0xa0,0x05]
-# CHECK-EB:   lwre $24, 5($3)             # encoding: [0x63,0x03,0x66,0x05]
-# CHECK-EB:   lwle $24, 2($4)             # encoding: [0x63,0x04,0x64,0x02]
-# CHECK-EB:   lle $2, 8($4)               # encoding: [0x60,0x44,0x6c,0x08]
-# CHECK-EB:   sce $2, 8($4)               # encoding: [0x60,0x44,0xac,0x08]
 
     sdbbp
     sdbbp 34
     rdhwr $5, $29
     cache 1, 8($5)
     pref 1, 8($5)
     ssnop
     ehb
# CHECK-EB:   prefx 1, $3($5)             # encoding: [0x54,0x65,0x09,0xa0]
     ei $0
     ei $10
     wait
     wait 17
     tlbp
     tlbr
     tlbwi
     tlbwr
-    prefe 1, 8($5)
-    cachee 1, 8($5)
     prefx 1, $3($5)
-    swre $24, 5($3)
-    swle $24, 5($3)
-    lwre $24, 5($3)
-    lwle $24, 2($4)
-    lle $2, 8($4)
-    sce $2, 8($4)
+

test/MC/Mips/micromips-eva.s

+# RUN: llvm-mc %s -triple=mipsel -show-encoding -show-inst -mcpu=mips32r2 \
+# RUN:   -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EL %s
+# RUN: llvm-mc %s -triple=mips -show-encoding -show-inst -mcpu=mips32r2 \
+# RUN:   -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EB %s
+# Check that the assembler can handle the documented syntax
+# for EVA instructions.
+#------------------------------------------------------------------------------
+# microMIPS EVA Instructions
+#------------------------------------------------------------------------------
+# Little endian
+#------------------------------------------------------------------------------
+# CHECK-EL:    prefe 1, 8($5)             # encoding: [0x25,0x60,0x08,0xa4]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} PREFE_MM
+# CHECK-EL:    cachee 1, 8($5)            # encoding: [0x25,0x60,0x08,0xa6]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} CACHEE_MM
+# CHECK-EL:    lle $2, 8($4)              # encoding: [0x44,0x60,0x08,0x6c]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LLE_MM
+# CHECK-EL:    sce $2, 8($4)              # encoding: [0x44,0x60,0x08,0xac]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} SCE_MM
+# CHECK-EL:    swre $24, 5($3)            # encoding: [0x03,0x63,0x05,0xa2]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} SWRE_MM
+# CHECK-EL:    swle $24, 5($3)            # encoding: [0x03,0x63,0x05,0xa0]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} SWLE_MM
+# CHECK-EL:    lwre $24, 5($3)            # encoding: [0x03,0x63,0x05,0x66]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LWRE_MM
+# CHECK-EL:    lwle $24, 2($4)            # encoding: [0x04,0x63,0x02,0x64]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LWLE_MM
+# CHECK-EL: lhue   $4, 8($2)              # encoding: [0x82,0x60,0x08,0x62]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LHuE_M
+# CHECK-EL: lbe    $4, 8($2)              # encoding: [0x82,0x60,0x08,0x68]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LBE_MM
+# CHECK-EL: lbue   $4, 8($2)              # encoding: [0x82,0x60,0x08,0x60]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LBuE_MM
+# CHECK-EL: lhe    $4, 8($2)              # encoding: [0x82,0x60,0x08,0x6a]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LHE_MM
+# CHECK-EL: lwe    $4, 8($2)              # encoding: [0x82,0x60,0x08,0x6e]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LWE_MM
+# CHECK-EL: sbe    $5, 8($4)              # encoding: [0xa4,0x60,0x08,0xa8]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} SBE_MM
+# CHECK-EL: she    $5, 8($4)              # encoding: [0xa4,0x60,0x08,0xaa]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} SHE_MM
+# CHECK-EL: swe    $5, 8($4)              # encoding: [0xa4,0x60,0x08,0xae]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} SWE_MM
+#------------------------------------------------------------------------------
+# Big endian
+#------------------------------------------------------------------------------
+# CHECK-EB:   prefe 1, 8($5)              # encoding: [0x60,0x25,0xa4,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} PREFE_MM
+# CHECK-EB:   cachee 1, 8($5)             # encoding: [0x60,0x25,0xa6,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} CACHEE_MM
+# CHECK-EB:   lle $2, 8($4)               # encoding: [0x60,0x44,0x6c,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LLE_MM
+# CHECK-EB:   sce $2, 8($4)               # encoding: [0x60,0x44,0xac,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} SCE_MM
+# CHECK-EB:   swre $24, 5($3)             # encoding: [0x63,0x03,0xa2,0x05]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} SWRE_MM
+# CHECK-EB:   swle $24, 5($3)             # encoding: [0x63,0x03,0xa0,0x05]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} SWLE_MM
+# CHECK-EB:   lwre $24, 5($3)             # encoding: [0x63,0x03,0x66,0x05]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LWRE_MM
+# CHECK-EB:   lwle $24, 2($4)             # encoding: [0x63,0x04,0x64,0x02]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LWLE_MM
+# CHECK-EB: lhue   $4, 8($2)              # encoding: [0x60,0x82,0x62,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LHuE_MM
+# CHECK-EB: lbe    $4, 8($2)              # encoding: [0x60,0x82,0x68,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LBE_MM
+# CHECK-EB: lbue   $4, 8($2)              # encoding: [0x60,0x82,0x60,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LBuE_MM
+# CHECK-EB: lhe    $4, 8($2)              # encoding: [0x60,0x82,0x6a,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LHE_MM
+# CHECK-EB: lwe    $4, 8($2)              # encoding: [0x60,0x82,0x6e,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LWE_MM
+# CHECK-EB: sbe    $5, 8($4)              # encoding: [0x60,0xa4,0xa8,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} SBE_MM
+# CHECK-EB: she    $5, 8($4)              # encoding: [0x60,0xa4,0xaa,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} SHE_MM
+# CHECK-EB: swe    $5, 8($4)              # encoding: [0x60,0xa4,0xae,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} SWE_MM
+
+    prefe 1, 8($5)
+    cachee 1, 8($5)
+    lle $2, 8($4)
+    sce $2, 8($4)
+    swre $24, 5($3)
+    swle $24, 5($3)
+    lwre $24, 5($3)
+    lwle $24, 2($4)
+    lhue   $4, 8($2)
+    lbe    $4, 8($2)
+    lbue   $4, 8($2)
+    lhe    $4, 8($2)
+    lwe    $4, 8($2)
+    sbe    $5, 8($4)
+    she    $5, 8($4)
+    swe    $5, 8($4)
+

test/MC/Mips/micromips-loadstore-instructions.s

 # CHECK-EL: lwm32  $16, $17, $ra, 8($4)       # encoding: [0x44,0x22,0x08,0x50]
 # CHECK-EL: lwm32  $16, $17, 8($sp)           # encoding: [0x5d,0x20,0x08,0x50]
 # CHECK-EL: swm16  $16, $17, $ra, 8($sp)      # encoding: [0x52,0x45]
 # CHECK-EL: swm32  $16, $17, $ra, 64($sp)     # encoding: [0x5d,0x22,0x40,0xd0]
 # CHECK-EL: swm32  $16, $17, $ra, 8($4)       # encoding: [0x44,0x22,0x08,0xd0]
 # CHECK-EL: swm32  $16, $17, 8($sp)           # encoding: [0x5d,0x20,0x08,0xd0]
 # CHECK-EL: swp    $16, 8($4)                 # encoding: [0x04,0x22,0x08,0x90]
 # CHECK-EL: lwp    $16, 8($4)                 # encoding: [0x04,0x22,0x08,0x10]
-# CHECK-EL: lhue   $4, 8($2)                  # encoding: [0x82,0x60,0x08,0x62]
-# CHECK-EL: lbe    $4, 8($2)                  # encoding: [0x82,0x60,0x08,0x68]
-# CHECK-EL: lbue   $4, 8($2)                  # encoding: [0x82,0x60,0x08,0x60]
-# CHECK-EL: lhe    $4, 8($2)                  # encoding: [0x82,0x60,0x08,0x6a]
-# CHECK-EL: lwe    $4, 8($2)                  # encoding: [0x82,0x60,0x08,0x6e]
-# CHECK-EL: sbe    $5, 8($4)                  # encoding: [0xa4,0x60,0x08,0xa8]
-# CHECK-EL: she    $5, 8($4)                  # encoding: [0xa4,0x60,0x08,0xaa]
-# CHECK-EL: swe    $5, 8($4)                  # encoding: [0xa4,0x60,0x08,0xae]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
 # CHECK-EB: lb     $5, 8($4)                 # encoding: [0x1c,0xa4,0x00,0x08]
 # CHECK-EB: lbu    $6, 8($4)                 # encoding: [0x14,0xc4,0x00,0x08]
 # CHECK-EB: lh     $2, 8($4)                 # encoding: [0x3c,0x44,0x00,0x08]
 # CHECK-EB: lhu    $4, 8($2)                 # encoding: [0x34,0x82,0x00,0x08]
 # CHECK-EB: lw     $6, 4($5)                 # encoding: [0xfc,0xc5,0x00,0x04]

 # CHECK-EB: lwm32  $16, $17, $ra, 8($4)      # encoding: [0x22,0x44,0x50,0x08]
 # CHECK-EB: lwm32  $16, $17, 8($sp)          # encoding: [0x20,0x5d,0x50,0x08]
 # CHECK-EB: swm16  $16, $17, $ra, 8($sp)     # encoding: [0x45,0x52]
 # CHECK-EB: swm32  $16, $17, $ra, 64($sp)    # encoding: [0x22,0x5d,0xd0,0x40]
 # CHECK-EB: swm32  $16, $17, $ra, 8($4)      # encoding: [0x22,0x44,0xd0,0x08]
 # CHECK-EB: swm32  $16, $17, 8($sp)          # encoding: [0x20,0x5d,0xd0,0x08]
 # CHECK-EB: swp    $16, 8($4)                # encoding: [0x22,0x04,0x90,0x08]
 # CHECK-EB: lwp    $16, 8($4)                # encoding: [0x22,0x04,0x10,0x08]
-# CHECK-EB: lhue   $4, 8($2)                 # encoding: [0x60,0x82,0x62,0x08]
-# CHECK-EB: lbe    $4, 8($2)                 # encoding: [0x60,0x82,0x68,0x08]
-# CHECK-EB: lbue   $4, 8($2)                 # encoding: [0x60,0x82,0x60,0x08]
-# CHECK-EB: lhe    $4, 8($2)                 # encoding: [0x60,0x82,0x6a,0x08]
-# CHECK-EB: lwe    $4, 8($2)                 # encoding: [0x60,0x82,0x6e,0x08]
-# CHECK-EB: sbe    $5, 8($4)                 # encoding: [0x60,0xa4,0xa8,0x08]
-# CHECK-EB: she    $5, 8($4)                 # encoding: [0x60,0xa4,0xaa,0x08]
-# CHECK-EB: swe    $5, 8($4)                 # encoding: [0x60,0xa4,0xae,0x08]
      lb     $5, 8($4)
      lbu    $6, 8($4)
      lh     $2, 8($4)
      lhu    $4, 8($2)
      lw     $6, 4($5)
      lw     $6, 123($sp)
      sb     $5, 8($4)
      sh     $2, 8($4)
# CHECK-EB: lwp    $16, 8($4)                # encoding: [0x22,0x04,0x10,0x08]
      lwm    $16, $17, $ra, 8($4)
      lwm    $16, $17, 8($sp)
      swm    $16, $17, $ra, 8($sp)
      swm    $16, $17, $ra, 64($sp)
      swm    $16, $17, $ra, 8($4)
      swm    $16, $17, 8($sp)
      swp    $16, 8($4)
      lwp    $16, 8($4)
-     lhue   $4, 8($2)
-     lbe    $4, 8($2)
-     lbue   $4, 8($2)
-     lhe    $4, 8($2)
-     lwe    $4, 8($2)
-     sbe    $5, 8($4)
-     she    $5, 8($4)
-     swe    $5, 8($4)
+

test/MC/Mips/micromips/invalid.s

-# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1
+# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips,eva 2>%t1
 # RUN: FileCheck %s < %t1
 
   addiur1sp $7, 260   # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
   addiur1sp $7, 241   # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
   addiur1sp $8, 240   # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
   addius5 $2, -9      # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
   addius5 $2, 8       # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
   break -1            # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate

test/MC/Mips/micromips/valid.s

-# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mattr=micromips | FileCheck %s
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mattr=micromips,eva | FileCheck %s
 
 .set noat
 addiusp -16                 # CHECK: addiusp -16        # encoding: [0x4f,0xf9]
 addiusp -1028               # CHECK: addiusp -1028      # encoding: [0x4f,0xff]
 addiusp -1032               # CHECK: addiusp -1032      # encoding: [0x4f,0xfd]
 addiusp 1024                # CHECK: addiusp 1024       # encoding: [0x4c,0x01]
 addiusp 1028                # CHECK: addiusp 1028       # encoding: [0x4c,0x03]
 andi16 $16, $2, 31          # CHECK: andi16 $16, $2, 31 # encoding: [0x2c,0x29]

 bgez $6, 1332               # CHECK: bgez $6, 1332          # encoding: [0x40,0x46,0x02,0x9a]
 bgezal $6, 1332             # CHECK: bgezal $6, 1332        # encoding: [0x40,0x66,0x02,0x9a]
 bltzal $6, 1332             # CHECK: bltzal $6, 1332        # encoding: [0x40,0x26,0x02,0x9a]
 bgtz $6, 1332               # CHECK: bgtz $6, 1332          # encoding: [0x40,0xc6,0x02,0x9a]
 blez $6, 1332               # CHECK: blez $6, 1332          # encoding: [0x40,0x86,0x02,0x9a]
 bne $9, $6, 1332            # CHECK: bne $9, $6, 1332       # encoding: [0xb4,0xc9,0x02,0x9a]
 bltz $6, 1332               # CHECK: bltz $6, 1332          # encoding: [0x40,0x06,0x02,0x9a]
 teq $8, $9                  # CHECK: teq $8, $9             # encoding: [0x01,0x28,0x00,0x3c]
 tge $8, $9                  # CHECK: tge $8, $9             # encoding: [0x01,0x28,0x02,0x3c]
 tgeu $8, $9                 # CHECK: tgeu $8, $9            # encoding: [0x01,0x28,0x04,0x3c]
 tlt $8, $9                  # CHECK: tlt $8, $9             # encoding: [0x01,0x28,0x08,0x3c]
 tltu $8, $9                 # CHECK: tltu $8, $9            # encoding: [0x01,0x28,0x0a,0x3c]
 tne $8, $9                  # CHECK: tne $8, $9             # encoding: [0x01,0x28,0x0c,0x3c]
 teqi $9, 17767              # CHECK: teqi $9, 17767         # encoding: [0x41,0xc9,0x45,0x67]
 tgei $9, 17767              # CHECK: tgei $9, 17767         # encoding: [0x41,0x29,0x45,0x67]
 tgeiu $9, 17767             # CHECK: tgeiu $9, 17767        # encoding: [0x41,0x69,0x45,0x67]
 tlti $9, 17767              # CHECK: tlti $9, 17767         # encoding: [0x41,0x09,0x45,0x67]
 tltiu $9, 17767             # CHECK: tltiu $9, 17767        # encoding: [0x41,0x49,0x45,0x67]
 tnei $9, 17767              # CHECK: tnei $9, 17767         # encoding: [0x41,0x89,0x45,0x67]
 cache 1, 8($5)              # CHECK: cache 1, 8($5)         # encoding: [0x20,0x25,0x60,0x08]
 pref 1, 8($5)               # CHECK: pref 1, 8($5)          # encoding: [0x60,0x25,0x20,0x08]
 ssnop                       # CHECK: ssnop                  # encoding: [0x00,0x00,0x08,0x00]
 ehb                         # CHECK: ehb                    # encoding: [0x00,0x00,0x18,0x00]
 pause                       # CHECK: pause                  # encoding: [0x00,0x00,0x28,0x00]
 ll $2, 8($4)                # CHECK: ll $2, 8($4)           # encoding: [0x60,0x44,0x30,0x08]
 sc $2, 8($4)                # CHECK: sc $2, 8($4)           # encoding: [0x60,0x44,0xb0,0x08]
 lwxs $2, $3($4)             # CHECK: lwxs $2, $3($4)        # encoding: [0x00,0x64,0x11,0x18]
 bgezals $6, 1332            # CHECK: bgezals $6, 1332       # encoding: [0x42,0x66,0x02,0x9a]
 bltzals $6, 1332            # CHECK: bltzals $6, 1332       # encoding: [0x42,0x26,0x02,0x9a]
 beqzc $9, 1332              # CHECK: beqzc $9, 1332         # encoding: [0x40,0xe9,0x02,0x9a]
 bnezc $9, 1332              # CHECK: bnezc $9, 1332         # encoding: [0x40,0xa9,0x02,0x9a]
 jals 1328                   # CHECK: jals 1328              # encoding: [0x74,0x00,0x02,0x98]
 jalrs $ra, $6               # CHECK: jalrs $ra, $6          # encoding: [0x03,0xe6,0x4f,0x3c]
 lwm32 $16, $17, 8($4)       # CHECK: lwm32 $16, $17, 8($4)  # encoding: [0x20,0x44,0x50,0x08]
 lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)   # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)  # encoding: [0x21,0x3b,0x59,0x84]
 swm32 $16, $17, 8($4)       # CHECK: swm32 $16, $17, 8($4)  # encoding: [0x20,0x44,0xd0,0x08]
 swp $16, 8($4)              # CHECK: swp $16, 8($4)         # encoding: [0x22,0x04,0x90,0x08]
 lwp $16, 8($4)              # CHECK: lwp $16, 8($4)         # encoding: [0x22,0x04,0x10,0x08]
 nop                         # CHECK: nop                    # encoding: [0x00,0x00,0x00,0x00]

test/MC/Mips/micromips32r6-eva.s

+# RUN: llvm-mc %s -triple=mipsel -show-encoding -show-inst -mcpu=mips32r6 \
+# RUN:   -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EL %s
+# RUN: llvm-mc %s -triple=mips -show-encoding -show-inst -mcpu=mips32r6 \
+# RUN:   -mattr=+micromips,+eva | FileCheck -check-prefix=CHECK-EB %s
+# Check that the assembler can handle the documented syntax
+# for EVA instructions.
+#------------------------------------------------------------------------------
+# microMIPS EVA Instructions
+#------------------------------------------------------------------------------
+# Little endian
+#------------------------------------------------------------------------------
+# CHECK-EL:    prefe 1, 8($5)             # encoding: [0x25,0x60,0x08,0xa4]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} PREFE_MM
+# CHECK-EL:    cachee 1, 8($5)            # encoding: [0x25,0x60,0x08,0xa6]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} CACHEE_MM
+# CHECK-EL:    lle $2, 8($4)              # encoding: [0x44,0x60,0x08,0x6c]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LLE_MM
+# CHECK-EL:    sce $2, 8($4)              # encoding: [0x44,0x60,0x08,0xac]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} SCE_MM
+# CHECK-EL: lhue   $4, 8($2)              # encoding: [0x82,0x60,0x08,0x62]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LHuE_M
+# CHECK-EL: lbe    $4, 8($2)              # encoding: [0x82,0x60,0x08,0x68]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LBE_MM
+# CHECK-EL: lbue   $4, 8($2)              # encoding: [0x82,0x60,0x08,0x60]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LBuE_MM
+# CHECK-EL: lhe    $4, 8($2)              # encoding: [0x82,0x60,0x08,0x6a]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LHE_MM
+# CHECK-EL: lwe    $4, 8($2)              # encoding: [0x82,0x60,0x08,0x6e]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} LWE_MM
+# CHECK-EL: sbe    $5, 8($4)              # encoding: [0xa4,0x60,0x08,0xa8]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} SBE_MM
+# CHECK-EL: she    $5, 8($4)              # encoding: [0xa4,0x60,0x08,0xaa]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} SHE_MM
+# CHECK-EL: swe    $5, 8($4)              # encoding: [0xa4,0x60,0x08,0xae]
+# CHECK-EL-NEXT:                          # <MCInst #{{[0-9]+}} SWE_MM
+#------------------------------------------------------------------------------
+# Big endian
+#------------------------------------------------------------------------------
+# CHECK-EB:   prefe 1, 8($5)              # encoding: [0x60,0x25,0xa4,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} PREFE_MM
+# CHECK-EB:   cachee 1, 8($5)             # encoding: [0x60,0x25,0xa6,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} CACHEE_MM
+# CHECK-EB:   lle $2, 8($4)               # encoding: [0x60,0x44,0x6c,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LLE_MM
+# CHECK-EB:   sce $2, 8($4)               # encoding: [0x60,0x44,0xac,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} SCE_MM
+# CHECK-EB: lhue   $4, 8($2)              # encoding: [0x60,0x82,0x62,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LHuE_MM
+# CHECK-EB: lbe    $4, 8($2)              # encoding: [0x60,0x82,0x68,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LBE_MM
+# CHECK-EB: lbue   $4, 8($2)              # encoding: [0x60,0x82,0x60,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LBuE_MM
+# CHECK-EB: lhe    $4, 8($2)              # encoding: [0x60,0x82,0x6a,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LHE_MM
+# CHECK-EB: lwe    $4, 8($2)              # encoding: [0x60,0x82,0x6e,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} LWE_MM
+# CHECK-EB: sbe    $5, 8($4)              # encoding: [0x60,0xa4,0xa8,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} SBE_MM
+# CHECK-EB: she    $5, 8($4)              # encoding: [0x60,0xa4,0xaa,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} SHE_MM
+# CHECK-EB: swe    $5, 8($4)              # encoding: [0x60,0xa4,0xae,0x08]
+# CHECK-EB-NEXT:                          # <MCInst #{{[0-9]+}} SWE_MM
+
+    prefe 1, 8($5)
+    cachee 1, 8($5)
+    lle $2, 8($4)
+    sce $2, 8($4)
+    lhue   $4, 8($2)
+    lbe    $4, 8($2)
+    lbue   $4, 8($2)
+    lhe    $4, 8($2)
+    lwe    $4, 8($2)
+    sbe    $5, 8($4)
+    she    $5, 8($4)
+    swe    $5, 8($4)
+

test/MC/Mips/micromips32r6/invalid.s

-# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1
+# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=+micromips,+eva 2>%t1
 # RUN: FileCheck %s < %t1
 
   addiur1sp $7, 260        # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
   addiur1sp $7, 241        # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
   addiur1sp $8, 240        # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
   addiur2 $9, $7, -1       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   addiur2 $6, $7, 10       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   addius5 $2, -9           # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate

test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   jialc $5, 256            # CHECK: jialc $5, 256       # encoding: [0x80,0x05,0x01,0x00]
   jic   $5, 256            # CHECK: jic $5, 256         # encoding: [0xa0,0x05,0x01,0x00]
   jrc16 $9                 # CHECK: jrc16 $9            # encoding: [0x45,0x23]
   jrcaddiusp 20            # CHECK: jrcaddiusp 20       # encoding: [0x44,0xb3]
   lapc $4, 100             # CHECK: lapc $4, 100        # encoding: [0x78,0x80,0x00,0x19]
   lapc $7, 1048572         # CHECK: lapc $7, 1048572    # encoding: [0x78,0xe3,0xff,0xff]
   lapc $7, -1048576        # CHECK: lapc $7, -1048576   # encoding: [0x78,0xe4,0x00,0x00]
   lh $2, 8($4)             # CHECK: lh $2, 8($4)        # encoding: [0x3c,0x44,0x00,0x08]
-  lhe $4, 8($2)            # CHECK: lhe $4, 8($2)       # encoding: [0x60,0x82,0x6a,0x08]
   lhu $4, 8($2)            # CHECK: lhu $4, 8($2)       # encoding: [0x34,0x82,0x00,0x08]
-  lhue $4, 8($2)           # CHECK: lhue $4, 8($2)      # encoding: [0x60,0x82,0x62,0x08]
   lsa $2, $3, $4, 3        # CHECK: lsa  $2, $3, $4, 3  # encoding: [0x00,0x43,0x24,0x0f]
   lwpc    $2,268           # CHECK: lwpc $2, 268        # encoding: [0x78,0x48,0x00,0x43]
   lwm $16, $17, $ra, 8($sp)   # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
   lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
   ll $2, 8($4)                    # CHECK: ll $2, 8($4)                    # encoding: [0x60,0x44,0x30,0x08]
   lwm32 $16, $17, 8($4)           # CHECK: lwm32 $16, $17, 8($4)           # encoding: [0x20,0x44,0x50,0x08]
   lwm32 $16, $17, 8($sp)          # CHECK: lwm32 $16, $17, 8($sp)          # encoding: [0x20,0x5d,0x50,0x08]
   lwm32 $16, $17, $ra, 8($4)      # CHECK: lwm32 $16, $17, $ra, 8($4)      # encoding: [0x22,0x44,0x50,0x08]
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   sync 17                  # CHECK: sync 17             # encoding: [0x00,0x11,0x6b,0x7c]
   synci 8($5)              # CHECK: synci 8($5)         # encoding: [0x41,0x85,0x00,0x08]
   rdpgpr $3, $9            # CHECK: $3, $9              # encoding: [0x00,0x69,0xe1,0x7c]
   sdbbp                    # CHECK: sdbbp               # encoding: [0x00,0x00,0xdb,0x7c]
   sdbbp 34                 # CHECK: sdbbp 34            # encoding: [0x00,0x22,0xdb,0x7c]
   xor $3, $4, $5           # CHECK: xor $3, $4, $5      # encoding: [0x00,0xa4,0x1b,0x10]
   xori $3, $4, 1234        # CHECK: xori $3, $4, 1234   # encoding: [0x70,0x64,0x04,0xd2]
   sw $5, 4($6)             # CHECK: sw $5, 4($6)        # encoding: [0xf8,0xa6,0x00,0x04]
-  swe $5, 8($4)            # CHECK: swe $5, 8($4)       # encoding: [0x60,0xa4,0xae,0x08]
   add.s $f3, $f4, $f5      # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30]
   add.d $f2, $f4, $f6      # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30]
                            # CHECK-NEXT:                # <MCInst #{{[0-9]+}} FADD_D64_MM
   sub.s $f3, $f4, $f5      # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70]
   sub.d $f2, $f4, $f6      # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70]
                            # CHECK-NEXT:                # <MCInst #{{[0-9]+}} FSUB_D64_MM
   mul.s $f3, $f4, $f5      # CHECK: mul.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xb0]
   mul.d $f2, $f4, $f6      # CHECK: mul.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xb0]
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   lw $3, 24($sp)           # CHECK: lw $3, 24($sp)      # encoding: [0x48,0x66]
   lw $3, 124($sp)          # CHECK: lw $3, 124($sp)     # encoding: [0x48,0x7f]
   lw $3, 128($sp)          # CHECK: lw $3, 128($sp)     # encoding: [0xfc,0x7d,0x00,0x80]
   lw16 $4, 8($17)          # CHECK: lw16 $4, 8($17)     # encoding: [0x6a,0x12]
   lhu16 $3, 4($16)         # CHECK: lhu16 $3, 4($16)    # encoding: [0x29,0x82]
   lbu16 $3, 4($17)         # CHECK: lbu16 $3, 4($17)    # encoding: [0x09,0x94]
   lbu16 $3, -1($17)        # CHECK: lbu16 $3, -1($17)   # encoding: [0x09,0x9f]
   sb  $4, 6($5)            # CHECK: sb  $4, 6($5)       # encoding: [0x18,0x85,0x00,0x06]
-  sbe $4, 6($5)            # CHECK: sbe $4, 6($5)       # encoding: [0x60,0x85,0xa8,0x06]
-  sce $4, 6($5)            # CHECK: sce $4, 6($5)       # encoding: [0x60,0x85,0xac,0x06]
   sh $4, 6($5)             # CHECK: sh $4, 6($5)        # encoding: [0x38,0x85,0x00,0x06]
-  she $4, 6($5)            # CHECK: she $4, 6($5)       # encoding: [0x60,0x85,0xaa,0x06]
-  lle $4, 6($5)            # CHECK: lle $4, 6($5)       # encoding: [0x60,0x85,0x6c,0x06]
-  lwe $4, 6($5)            # CHECK: lwe $4, 6($5)       # encoding: [0x60,0x85,0x6e,0x06]
   lw $4, 6($5)             # CHECK: lw $4, 6($5)        # encoding: [0xfc,0x85,0x00,0x06]
   lui $6, 17767            # CHECK: lui $6, 17767       # encoding: [0x10,0xc0,0x45,0x67]
   addu16 $6, $17, $4       # CHECK: addu16 $6, $17, $4  # encoding: [0x04,0xcc]
   and16 $16, $2            # CHECK: and16 $16, $2       # encoding: [0x44,0x21]
   andi16 $4, $5, 8         # CHECK: andi16 $4, $5, 8    # encoding: [0x2e,0x56]
   not16 $4, $7             # CHECK: not16 $4, $7        # encoding: [0x46,0x70]
   or16 $3, $7              # CHECK: or16 $3, $7         # encoding: [0x45,0xf9]
   sll16 $3, $6, 8          # CHECK: sll16 $3, $6, 8     # encoding: [0x25,0xe0]
   srl16 $3, $6, 8          # CHECK: srl16 $3, $6, 8     # encoding: [0x25,0xe1]
-  prefe 1, 8($5)           # CHECK: prefe 1, 8($5)      # encoding: [0x60,0x25,0xa4,0x08]
-  cachee 1, 8($5)          # CHECK: cachee 1, 8($5)     # encoding: [0x60,0x25,0xa6,0x08]
   teq $8, $9               # CHECK: teq $8, $9          # encoding: [0x01,0x28,0x00,0x3c]
   teq $5, $7, 15           # CHECK: teq $5, $7, 15      # encoding: [0x00,0xe5,0xf0,0x3c]
   tge $7, $10              # CHECK: tge $7, $10         # encoding: [0x01,0x47,0x02,0x3c]
   tge $7, $19, 15          # CHECK: tge $7, $19, 15     # encoding: [0x02,0x67,0xf2,0x3c]
   tgeu $22, $gp            # CHECK: tgeu $22, $gp       # encoding: [0x03,0x96,0x04,0x3c]
   tgeu $20, $14, 15        # CHECK: tgeu $20, $14, 15   # encoding: [0x01,0xd4,0xf4,0x3c]
   tlt $15, $13             # CHECK: tlt $15, $13        # encoding: [0x01,0xaf,0x08,0x3c]
   tlt $2, $19, 15          # CHECK: tlt $2, $19, 15     # encoding: [0x02,0x62,0xf8,0x3c]
   tltu $11, $16            # CHECK: tltu $11, $16       # encoding: [0x02,0x0b,0x0a,0x3c]
   tltu $16, $sp, 15        # CHECK: tltu $16, $sp, 15   # encoding: [0x03,0xb0,0xfa,0x3c]
   tne $6, $17              # CHECK: tne $6, $17         # encoding: [0x02,0x26,0x0c,0x3c]
   tne $7, $8, 15           # CHECK: tne $7, $8, 15      # encoding: [0x01,0x07,0xfc,0x3c]
   break16 8                # CHECK: break16 8           # encoding: [0x46,0x1b]
   li16 $3, -1              # CHECK: li16 $3, -1         # encoding: [0xed,0xff]
   move16 $3, $5            # CHECK: move16 $3, $5       # encoding: [0x0c,0x65]
   sdbbp16 8                # CHECK: sdbbp16 8           # encoding: [0x46,0x3b]
   subu16 $5, $16, $3       # CHECK: subu16 $5, $16, $3  # encoding: [0x04,0x3b]
   xor16 $17, $5            # CHECK: xor16 $17, $5       # encoding: [0x44,0xd8]
   lb $4, 8($5)             # CHECK: lb $4, 8($5)        # encoding: [0x1c,0x85,0x00,0x08]
   lbu $4, 8($5)            # CHECK: lbu $4, 8($5)       # encoding: [0x14,0x85,0x00,0x08]
-  lbe $4, 8($5)            # CHECK: lbe $4, 8($5)       # encoding: [0x60,0x85,0x68,0x08]
-  lbue $4, 8($5)           # CHECK: lbue $4, 8($5)      # encoding: [0x60,0x85,0x60,0x08]
   recip.s $f2, $f4         # CHECK: recip.s $f2, $f4    # encoding: [0x54,0x44,0x12,0x3b]
   recip.d $f2, $f4         # CHECK: recip.d $f2, $f4    # encoding: [0x54,0x44,0x52,0x3b]
   rint.s $f2, $f4          # CHECK: rint.s $f2, $f4     # encoding: [0x54,0x82,0x00,0x20]
   rint.d $f2, $f4          # CHECK: rint.d $f2, $f4     # encoding: [0x54,0x82,0x02,0x20]
   round.l.s $f2, $f4       # CHECK: round.l.s $f2, $f4  # encoding: [0x54,0x44,0x33,0x3b]
   round.l.d $f2, $f4       # CHECK: round.l.d $f2, $f4  # encoding: [0x54,0x44,0x73,0x3b]
   round.w.s $f2, $f4       # CHECK: round.w.s $f2, $f4  # encoding: [0x54,0x44,0x3b,0x3b]
   round.w.d $f2, $f4       # CHECK: round.w.d $f2, $f4  # encoding: [0x54,0x44,0x7b,0x3b]