This is an archive of the discontinued LLVM Phabricator instance.

Differential D44145

AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELT
ClosedPublic

Authored by arsenm on Mar 6 2018, 5:55 AM.

Details

Reviewers
tstellar
nhaehnle
rampitec

Diff Detail

Event Timeline

arsenm created this revision.Mar 6 2018, 5:55 AM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptMar 6 2018, 5:55 AM
nhaehnle added inline comments.Mar 7 2018, 1:45 AM
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
459–460

What happens if the index operand is in an SGPR?

479–480

Same here, what if IdxOp is in an SGPR?

arsenm added inline comments.Mar 7 2018, 11:24 AM
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
459–460

As implemented today, indirect addressing is only done on VGPRs. Someday we could implement SGPR indexing, but right now the register type of the index doesn't really matter

nhaehnle accepted this revision.Mar 9 2018, 2:34 AM

Okay, makes sense.

This revision is now accepted and ready to land.Mar 9 2018, 2:34 AM
arsenm closed this revision.Mar 12 2018, 6:39 AM

r327269

Revision Contents

Diff 137176

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo() {
// G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer // G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer
// operands. In assert builds, the instruction selector will assert // operands. In assert builds, the instruction selector will assert
// if it sees a generic instruction which isn't legal, so we need to // if it sees a generic instruction which isn't legal, so we need to
// tell it that scalar types are legal for pointer operands // tell it that scalar types are legal for pointer operands
setAction({G_GEP, S64}, Legal); setAction({G_GEP, S64}, Legal);
setAction({G_LOAD, 1, S64}, Legal); setAction({G_LOAD, 1, S64}, Legal);
setAction({G_STORE, 1, S64}, Legal); setAction({G_STORE, 1, S64}, Legal);
for (unsigned Op : {G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT}) {
getActionDefinitionsBuilder(Op)
.legalIf([=](const LegalityQuery &Query) {
const LLT &VecTy = Query.Types[1];
const LLT &IdxTy = Query.Types[2];
return VecTy.getSizeInBits() % 32 == 0 &&
VecTy.getSizeInBits() <= 512 &&
IdxTy.getSizeInBits() == 32;
});
}
// FIXME: Doesn't handle extract of illegal sizes. // FIXME: Doesn't handle extract of illegal sizes.
getActionDefinitionsBuilder(G_EXTRACT) getActionDefinitionsBuilder(G_EXTRACT)
.unsupportedIf([=](const LegalityQuery &Query) { .unsupportedIf([=](const LegalityQuery &Query) {
return Query.Types[0].getSizeInBits() >= Query.Types[1].getSizeInBits(); return Query.Types[0].getSizeInBits() >= Query.Types[1].getSizeInBits();
}) })
.legalIf([=](const LegalityQuery &Query) { .legalIf([=](const LegalityQuery &Query) {
const LLT &Ty0 = Query.Types[0]; const LLT &Ty0 = Query.Types[0];
const LLT &Ty1 = Query.Types[1]; const LLT &Ty1 = Query.Types[1];
Show All 33 Lines

lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 LinesAMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI)
assert(&RBSGPR == &AMDGPU::SGPRRegBank); assert(&RBSGPR == &AMDGPU::SGPRRegBank);
const RegisterBank &RBVGPR = getRegBank(AMDGPU::VGPRRegBankID); const RegisterBank &RBVGPR = getRegBank(AMDGPU::VGPRRegBankID);
(void)RBVGPR; (void)RBVGPR;
assert(&RBVGPR == &AMDGPU::VGPRRegBank); assert(&RBVGPR == &AMDGPU::VGPRRegBank);
} }
static bool isConstant(const MachineOperand &MO, int64_t &C) {
const MachineFunction *MF = MO.getParent()->getParent()->getParent();
const MachineRegisterInfo &MRI = MF->getRegInfo();
const MachineInstr *Def = MRI.getVRegDef(MO.getReg());
if (!Def)
return false;
if (Def->getOpcode() == AMDGPU::G_CONSTANT) {
C = Def->getOperand(1).getCImm()->getSExtValue();
return true;
}
if (Def->getOpcode() == AMDGPU::COPY)
return isConstant(Def->getOperand(1), C);
return false;
}
unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst, unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
const RegisterBank &Src, const RegisterBank &Src,
unsigned Size) const { unsigned Size) const {
if (Dst.getID() == AMDGPU::SGPRRegBankID && if (Dst.getID() == AMDGPU::SGPRRegBankID &&
Src.getID() == AMDGPU::VGPRRegBankID) Src.getID() == AMDGPU::VGPRRegBankID)
return std::numeric_limits<unsigned>::max(); return std::numeric_limits<unsigned>::max();
// SGPRRegBank with size 1 is actually vcc or another 64-bit sgpr written by // SGPRRegBank with size 1 is actually vcc or another 64-bit sgpr written by
▲ Show 20 Lines • Show All 364 Lines • ▼ Show 20 Lines unsigned Op0Bank = Op2Bank == AMDGPU::SGPRRegBankID &&
Op3Bank == AMDGPU::SGPRRegBankID ? Op3Bank == AMDGPU::SGPRRegBankID ?
AMDGPU::SCCRegBankID : AMDGPU::VGPRRegBankID; AMDGPU::SCCRegBankID : AMDGPU::VGPRRegBankID;
OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, 1); OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, 1);
OpdsMapping[1] = nullptr; // Predicate Operand. OpdsMapping[1] = nullptr; // Predicate Operand.
OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size); OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size); OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size);
break; break;
} }
case AMDGPU::G_EXTRACT_VECTOR_ELT: {
unsigned IdxOp = 2;
int64_t Imm;
// XXX - Do we really need to fully handle these? The constant case should
// be legalized away before RegBankSelect?
unsigned OutputBankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
nhaehnleUnsubmitted
Not Done
ReplyInline Actions

What happens if the index operand is in an SGPR?

nhaehnle: What happens if the index operand is in an SGPR?
arsenmAuthorUnsubmitted
Not Done
ReplyInline Actions

As implemented today, indirect addressing is only done on VGPRs. Someday we could implement SGPR indexing, but right now the register type of the index doesn't really matter

arsenm: As implemented today, indirect addressing is only done on VGPRs. Someday we could implement…
unsigned VecBank = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
unsigned IdxBank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(0).getReg()).getSizeInBits());
OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(1).getReg()).getSizeInBits());
// The index can be either if the source vector is VGPR.
OpdsMapping[2] = AMDGPU::getValueMapping(IdxBank, MRI.getType(MI.getOperand(2).getReg()).getSizeInBits());
break;
}
case AMDGPU::G_INSERT_VECTOR_ELT: {
// XXX - Do we really need to fully handle these? The constant case should
// be legalized away before RegBankSelect?
int64_t Imm;
unsigned VecOp = 0;
unsigned IdxOp = MI.getOpcode() == AMDGPU::G_EXTRACT_VECTOR_ELT ? 2 : 3;
unsigned BankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
nhaehnleUnsubmitted
Not Done
ReplyInline Actions

Same here, what if IdxOp is in an SGPR?

nhaehnle: Same here, what if IdxOp is in an SGPR?
// TODO: Can do SGPR indexing, which would obviate the need for the
// isConstant check.
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
OpdsMapping[i] = AMDGPU::getValueMapping(BankID, Size);
}
break;
}
case AMDGPU::G_INTRINSIC: { case AMDGPU::G_INTRINSIC: {
switch(MI.getOperand(1).getIntrinsicID()) { switch(MI.getOperand(1).getIntrinsicID()) {
default: default:
return getInvalidInstructionMapping(); return getInvalidInstructionMapping();
case Intrinsic::maxnum: case Intrinsic::maxnum:
case Intrinsic::minnum: case Intrinsic::minnum:
case Intrinsic::amdgcn_cvt_pkrtz: case Intrinsic::amdgcn_cvt_pkrtz:
return getDefaultMappingVOP(MI); return getDefaultMappingVOP(MI);
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
---
name: extract_vector_elt_0_v2i32
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: extract_vector_elt_0_v2i32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 0
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
$vgpr0 = COPY %2
...
---
name: extract_vector_elt_0_v3i32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2
; CHECK-LABEL: name: extract_vector_elt_0_v3i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<3 x s32>), [[C]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_CONSTANT i32 0
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
$vgpr0 = COPY %2
...
---
name: extract_vector_elt_0_v4i32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-LABEL: name: extract_vector_elt_0_v4i32
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = G_CONSTANT i32 0
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
$vgpr0 = COPY %2
...
---
name: extract_vector_elt_0_v5i32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: extract_vector_elt_0_v5i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[MV:%[0-9]+]]:_(<5 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<5 x s32>), [[C]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<5 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0
%2:_(s32) = G_CONSTANT i32 0
%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
$vgpr0 = COPY %3
...
---
name: extract_vector_elt_0_v6i32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: extract_vector_elt_0_v6i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[MV:%[0-9]+]]:_(<6 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<6 x s32>), [[C]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<6 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0, %0
%2:_(s32) = G_CONSTANT i32 0
%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
$vgpr0 = COPY %3
...
---
name: extract_vector_elt_0_v7i32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: extract_vector_elt_0_v7i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[MV:%[0-9]+]]:_(<7 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<7 x s32>), [[C]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<7 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0, %0, %0
%2:_(s32) = G_CONSTANT i32 0
%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
$vgpr0 = COPY %3
...
---
name: extract_vector_elt_0_v8i32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: extract_vector_elt_0_v8i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[MV:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<8 x s32>), [[C]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<8 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0, %0, %0, %0
%2:_(s32) = G_CONSTANT i32 0
%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
$vgpr0 = COPY %3
...
---
name: extract_vector_elt_0_v16i32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: extract_vector_elt_0_v16i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[MV:%[0-9]+]]:_(<16 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<16 x s32>), [[C]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<16 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0
%2:_(s32) = G_CONSTANT i32 0
%3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
$vgpr0 = COPY %3
...
---
name: extract_vector_elt_var_v2i32
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-LABEL: name: extract_vector_elt_var_v2i32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
$vgpr0 = COPY %2
...
---
name: extract_vector_elt_var_v8i32
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; CHECK-LABEL: name: extract_vector_elt_var_v8i32
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<8 x s32>), [[COPY1]](s32)
; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:_(s32) = COPY $vgpr2
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
$vgpr0 = COPY %2
...

test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
---
name: insert_vector_elt_0_v2i32
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-LABEL: name: insert_vector_elt_0_v2i32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[C]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[IVEC]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s32) = G_CONSTANT i32 0
%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
$vgpr0_vgpr1 = COPY %3
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir

  • This file was added.
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
---
name: extract_vector_elt_0_v2i32_s
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
%0:_(<2 x s32>) = COPY $sgpr0_sgpr1
%1:_(s32) = G_CONSTANT i32 0
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
$vgpr0 = COPY %2
...
---
name: extract_vector_elt_0_v4i32_s
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
%1:_(s32) = G_CONSTANT i32 0
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
$vgpr0 = COPY %2
...

test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
---
name: insert_vector_elt_v4i32_s_s_k
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5
; CHECK-LABEL: name: insert_vector_elt_v4i32_s_s_k
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[IVEC:%[0-9]+]]:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[C]](s32)
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
%1:_(s32) = COPY $sgpr5
%2:_(s32) = G_CONSTANT i32 0
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
...
---
name: insert_vector_elt_v4i32_v_s_k
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr5
; CHECK-LABEL: name: insert_vector_elt_v4i32_v_s_k
; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY2]](s32), [[COPY3]](s32)
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $sgpr5
%2:_(s32) = G_CONSTANT i32 0
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
...
---
name: insert_vector_elt_v4i32_s_v_k
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr5
; CHECK-LABEL: name: insert_vector_elt_v4i32_s_v_k
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[COPY2:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY2]], [[COPY1]](s32), [[COPY3]](s32)
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
%1:_(s32) = COPY $vgpr2
%2:_(s32) = G_CONSTANT i32 0
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
...
---
name: insert_vector_elt_var_v4i32_s_s_s
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, $sgpr6
; CHECK-LABEL: name: insert_vector_elt_var_v4i32_s_s_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY4]](s32), [[COPY5]](s32)
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
%1:_(s32) = COPY $sgpr5
%2:_(s32) = COPY $sgpr6
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
...
---
name: insert_vector_elt_var_v4i32_s_s_v
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, $vgpr6
; CHECK-LABEL: name: insert_vector_elt_var_v4i32_s_s_v
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY4]](s32), [[COPY2]](s32)
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
%1:_(s32) = COPY $sgpr5
%2:_(s32) = COPY $vgpr6
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
...
---
name: insert_vector_elt_var_v4i32_v_s_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr5, $vgpr6
; CHECK-LABEL: name: insert_vector_elt_var_v4i32_v_s_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY3]](s32), [[COPY2]](s32)
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $sgpr5
%2:_(s32) = COPY $vgpr6
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
...
---
name: insert_vector_elt_var_v4i32_v_v_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr5, $vgpr6
; CHECK-LABEL: name: insert_vector_elt_var_v4i32_v_v_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr5
%2:_(s32) = COPY $vgpr6
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...