See bug 36558: https://bugs.llvm.org/show_bug.cgi?id=36558
The change requires LDS bit in BUFFER_STORE_LDS_DWORD. This looks incorrect. LDS bit affects only MUBUF reads.
The change disallows TFE for BUFFER_STORE_LDS instructions as well as buffer loads to LDS. However, ISA manual disallows the latter case only: it says that it is illegal to set the instruction’s TFE bit for loads to LDS.
I believe that both LDS and TFE do not affect buffer stores. Perhaps it is worth to issue a warning or error in such cases. That's up to you.
AMD documentation explicitly states:
"MUBUF Instruction: BUFFER_STORE_LDS_DWORD LDS = 1 IDXEN = 0 OFFEN = 0 ..."
See Gfx9_Shader_Programming, Section 3.9.8 "LDS_DMA : LDS to Memory buffer without VGPRs".
Regarding TFE, documentation says that TFE is valid for "fetch" instructions only. By design, TFE is useless with stores.
I believe this instruction is not a "fetch".
Sure. However, there is a difference between "invalid" and "useless". Let's decide which approach we like and use it consistently.
Right now TFE is not disabled in "conventional" buffer stores (I just checked that), but this patch disallows it in LDS stores.
This can be done in a separate patch, but let's not forget that.
Thanks. So we require LDS and disallow both idxen and offen.
LGTM provided that now we stay on the same page.
|775 ↗||(On Diff #136544)|
It seems strange that this is not "NOSICI: error: instruction not supported on this GPU"
|899 ↗||(On Diff #136544)|
This isn't a separate opcode according to the documentation? Isn't this just a modifier bit? i.e. this would be BUFFER_STORE_DWORD_lds and not have a separate string name either