[compiler-rt, RISCV] Support builtins for RISC-V

[kito-cheng]

Summary

Support builtins for RISC-V, RV32 and RV64.

[kito-cheng]

clean up some useless check code.

[apazos]

Thanks Kito, with this change plus lib/Basic/Targets/RISCV.h change in clang to return true for hasInt128Type() and disabling fPIC we can build compiler rt for RISCV. We will test it next. But we need to decide if we want to go this route or implement int128_t with int64_t.

[apazos]

Kito, do you plan to add a test case for the new added function?

[kito-cheng]

Hi Ana:

Sure, I am working on add test case for that, I'll update this in next days.

[kito-cheng]

Changes:

• Add testcase.
• Remove muldi3 support for RV64 in lib/builtins/riscv/mul3.S, because compiler-rt already provide a general version for muldi3.
• Rename lib/builtins/riscv/mul3.S to lib/builtins/riscv/mulsi3.S for matching compiler-rt's naming convention.

[mgrang]

LGTM.

cmake/Modules/CompilerRTUtils.cmake

macro(detect_target_arch)
   check_symbol_exists(__arm__ "" __ARM)
   check_symbol_exists(__aarch64__ "" __AARCH64)
   check_symbol_exists(__x86_64__ "" __X86_64)
   check_symbol_exists(__i386__ "" __I386)
   check_symbol_exists(__mips__ "" __MIPS)
   check_symbol_exists(__mips64__ "" __MIPS64)
   check_symbol_exists(__powerpc64__ "" __PPC64)
   check_symbol_exists(__powerpc64le__ "" __PPC64LE)
+  check_symbol_exists(__riscv "" __RISCV)
   check_symbol_exists(__s390x__ "" __S390X)
   check_symbol_exists(__wasm32__ "" __WEBASSEMBLY32)
   check_symbol_exists(__wasm64__ "" __WEBASSEMBLY64)
   if(__ARM)
     add_default_target_arch(arm)
   elseif(__AARCH64)
     add_default_target_arch(aarch64)
   elseif(__X86_64)
     add_default_target_arch(x86_64)
   elseif(__I386)
     add_default_target_arch(i386)
   elseif(__MIPS64) # must be checked before __MIPS
     add_default_target_arch(mips64)
   elseif(__MIPS)
     add_default_target_arch(mips)
   elseif(__PPC64)
     add_default_target_arch(powerpc64)
   elseif(__PPC64LE)
     add_default_target_arch(powerpc64le)
+  elseif(__RISCV32)
+    add_default_target_arch(riscv32)
+  elseif(__RISCV64)
+    add_default_target_arch(riscv64)
+  elseif(__RISCV)
+    check_type_size("long" XLEN)
+    if(XLEN EQUAL "4")
+      add_default_target_arch(riscv32)
+    elseif(XLEN EQUAL "8")
+      add_default_target_arch(riscv64)
+    else()
+      message(FATAL_ERROR "Unsupport XLEN for RISC-V")
+    endif()
   elseif(__S390X)
     add_default_target_arch(s390x)
   elseif(__WEBASSEMBLY32)
     add_default_target_arch(wasm32)
   elseif(__WEBASSEMBLY64)
     add_default_target_arch(wasm64)
   endif()
 endmacro()

cmake/base-config-ix.cmake

elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "arm")
         test_target_arch(arm "" "-march=armv7-a" "-mfloat-abi=soft")
         test_target_arch(armhf "" "-march=armv7-a" "-mfloat-abi=hard")
         test_target_arch(armv6m "" "-march=armv6m" "-mfloat-abi=soft")
       endif()
     elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "aarch32")
       test_target_arch(aarch32 "" "-march=armv8-a")
     elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "aarch64")
       test_target_arch(aarch64 "" "-march=armv8-a")
+    elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "riscv32")
+      test_target_arch(riscv32 "" "")
+    elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "riscv64")
+      test_target_arch(riscv64 "" "")
     elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "wasm32")
       test_target_arch(wasm32 "" "--target=wasm32-unknown-unknown")
     elseif("${COMPILER_RT_DEFAULT_TARGET_ARCH}" MATCHES "wasm64")
       test_target_arch(wasm64 "" "--target=wasm64-unknown-unknown")
     endif()
     set(COMPILER_RT_OS_SUFFIX "")
   endif()
 endmacro()

cmake/builtin-config-ix.cmake

 
 set(ARM64 aarch64)
 set(ARM32 arm armhf armv6m armv7m armv7em armv7 armv7s armv7k)
 set(X86 i386)
 set(X86_64 x86_64)
 set(MIPS32 mips mipsel)
 set(MIPS64 mips64 mips64el)
 set(PPC64 powerpc64 powerpc64le)
+set(RISCV32 riscv32)
+set(RISCV64 riscv64)
 set(WASM32 wasm32)
 set(WASM64 wasm64)
 
 if(APPLE)
   set(ARM64 arm64)
   set(ARM32 armv7 armv7k armv7s)
   set(X86_64 x86_64 x86_64h)
 endif()
 
 set(ALL_BUILTIN_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64}
-    ${MIPS32} ${MIPS64} ${PPC64} ${WASM32} ${WASM64})
+    ${MIPS32} ${MIPS64} ${PPC64} ${RISCV32} ${RISCV64} ${WASM32} ${WASM64})
 
 include(CompilerRTUtils)
 include(CompilerRTDarwinUtils)
 
 if(APPLE)
 
   find_darwin_sdk_dir(DARWIN_osx_SYSROOT macosx)
   find_darwin_sdk_dir(DARWIN_iossim_SYSROOT iphonesimulator)

cmake/config-ix.cmake

 
 set(ARM64 aarch64)
 set(ARM32 arm armhf)
 set(X86 i386)
 set(X86_64 x86_64)
 set(MIPS32 mips mipsel)
 set(MIPS64 mips64 mips64el)
 set(PPC64 powerpc64 powerpc64le)
+set(RISCV32 riscv32)
+set(RISCV64 riscv64)
 set(S390X s390x)
 set(WASM32 wasm32)
 set(WASM64 wasm64)
 
 if(APPLE)
   set(ARM64 arm64)
   set(ARM32 armv7 armv7s armv7k)
   set(X86_64 x86_64 x86_64h)

lib/builtins/CMakeLists.txt

set(powerpc64_SOURCES
   ppc/gcc_qadd.c
   ppc/gcc_qdiv.c
   ppc/gcc_qmul.c
   ppc/gcc_qsub.c
   ppc/multc3.c
   ${GENERIC_SOURCES})
 set(powerpc64le_SOURCES ${powerpc64_SOURCES})
 
+set(riscv_SOURCES riscv/mul3.S ${GENERIC_SOURCES} ${GENERIC_TF_SOURCES})
+set(riscv32_SOURCES ${riscv_SOURCES})
+set(riscv64_SOURCES ${riscv_SOURCES})
+
 set(wasm32_SOURCES
   ${GENERIC_TF_SOURCES}
   ${GENERIC_SOURCES})
 set(wasm64_SOURCES
   ${GENERIC_TF_SOURCES}
   ${GENERIC_SOURCES})
 
 add_custom_target(builtins)

lib/builtins/int_types.h

#if _YUGA_LITTLE_ENDIAN
         su_int high;
 #else
         su_int high;
         su_int low;
 #endif /* _YUGA_LITTLE_ENDIAN */
     }s;
 } udwords;
 
-#if (defined(__LP64__) || defined(__wasm__) || defined(__mips64))
+#if (defined(__LP64__) || defined(__wasm__) || defined(__mips64)) || defined(__riscv)
 #define CRT_HAS_128BIT
 #endif
 
 #ifdef CRT_HAS_128BIT
 typedef int      ti_int __attribute__ ((mode (TI)));
 typedef unsigned tu_int __attribute__ ((mode (TI)));
 
 typedef union

lib/builtins/riscv/mul3.S

+//===--- mul3.S - Integer multiplication routines routines ---===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is dual licensed under the MIT and the University of Illinois Open
+// Source Licenses. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef __riscv_mul
+  .text
+  .align 2
+
+#if __riscv_xlen == 32
+/* Our RV64 64-bit routine is equivalent to our RV32 32-bit routine.  */
+# define __muldi3 __mulsi3
+#endif
+
+  .globl __muldi3
+  .type  __muldi3, @function
+__muldi3:
+  mv     a2, a0
+  mv     a0, zero
+.L1:
+  andi   a3, a1, 1
+  beqz   a3, .L2
+  add    a0, a0, a2
+.L2:
+  srli   a1, a1, 1
+  slli   a2, a2, 1
+  bnez   a1, .L1
+  ret
+#endif