[ARM] Armv8.2-A FP16 code generation (part 3/3)

[SjoerdMeijer]

Summary

This adds most of the FP16 codegen support, but these areas need further work:

• FP16 literals and immediates are not properly supported yet (e.g. literal pool needs work),
• instructions that are generated from intrinsics (e.g. vabs) haven't been added.

This will be addressed in follow-up patches.

[SjoerdMeijer]

Added T32 tests.

[olista01]

LGTM with a few nits (see inline comments), but please give 24 hours for other time zones to comment before committing.

lib/Target/ARM/ARMInstrVFP.td

531

The AHuI class already has the HasFullFP16 predicate, so is this needed?

(same question many more times in this file)

782

Output should be SPR?

1380

Should this copy to the SPR regclass, since the input is 32-bit?

test/CodeGen/ARM/fp16-instructions.ll

99

It might be better to write these tests as loading/storing the fp16 values, rather than doing all of this bit-casting, to simplify the tests. However, if you're going to do native support for fp16 args/returns in the backend soon, I'd be fine with committing these as-is for now knowing that they'll be simplified even further by that.

[SjoerdMeijer]

Thanks for the review!
Nits addressed, so this is the diff I will commit tomorrow.

It might be better to write these tests as loading/storing the fp16 values,
rather than doing all of this bit-casting, to simplify the tests. However, if
you're going to do native support for fp16 args/returns in the backend soon,
I'd be fine with committing these as-is for now knowing that they'll be
simplified even further by that.

Yes, that was exactly my plan: when we have proper fp16 args/return support, I
will update these tests to reflect that. For now I would like to keep the IR
and tests like they are at the moment, because that's the IR that we currently
generate from source code.

lib/Target/ARM/ARMISelLowering.h

EVT getOptimalMemOpType(uint64_t Size,
                             unsigned DstAlign, unsigned SrcAlign,
                             bool IsMemset, bool ZeroMemset,
                             bool MemcpyStrSrc,
                             MachineFunction &MF) const override;
 
     bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
     bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
     bool isZExtFree(SDValue Val, EVT VT2) const override;
+    bool isFNegFree(EVT VT) const override;
 
     bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
 
     bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
 
 
     /// isLegalAddressingMode - Return true if the addressing mode represented
     /// by AM is legal for this target, for a load/store of the specified type.

lib/Target/ARM/ARMISelLowering.cpp

ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
   setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
   setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
   setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
   if (Subtarget->useSjLjEH())
     setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
 
   setOperationAction(ISD::SETCC,     MVT::i32, Expand);
+  setOperationAction(ISD::SETCC,     MVT::f16, Expand);
   setOperationAction(ISD::SETCC,     MVT::f32, Expand);
   setOperationAction(ISD::SETCC,     MVT::f64, Expand);
   setOperationAction(ISD::SELECT,    MVT::i32, Custom);
   setOperationAction(ISD::SELECT,    MVT::f32, Custom);
   setOperationAction(ISD::SELECT,    MVT::f64, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
   case MVT::i16:
     // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
     return true;
   }
 
   return false;
 }
 
+bool ARMTargetLowering::isFNegFree(EVT VT) const {
+  if (!VT.isSimple())
+    return false;
+
+  // There are quite a few FP16 instructions (e.g. VNMLA, VNMLS, etc.) that
+  // negate values directly (fneg is free). So, we don't want to let the DAG
+  // combiner rewrite fneg into xors and some other instructions.  For f16 and
+  // FullFP16 argument passing, some bitcast nodes may be introduced,
+  // triggering this DAG combine rewrite, so we are avoiding that with this.
+  switch (VT.getSimpleVT().SimpleTy) {
+  default: break;
+  case MVT::f16:
+    return Subtarget->hasFullFP16();
+  }
+
+  return false;
+}
+
 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
   EVT VT = ExtVal.getValueType();
 
   if (!isTypeLegal(VT))
     return false;
 
   // Don't create a loadext if we can fold the extension into a wide/long
   // instruction.

 }
 
 /// isFPImmLegal - Returns true if the target can instruction select the
 /// specified FP immediate natively. If false, the legalizer will
 /// materialize the FP immediate as a load from a constant pool.
 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
   if (!Subtarget->hasVFP3())
     return false;
+  if (VT == MVT::f16 && Subtarget->hasFullFP16())
+    return ARM_AM::getFP16Imm(Imm) != -1;
   if (VT == MVT::f32)
     return ARM_AM::getFP32Imm(Imm) != -1;
   if (VT == MVT::f64 && !Subtarget->isFPOnlySP())
     return ARM_AM::getFP64Imm(Imm) != -1;
   return false;
 }
 
 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as

lib/Target/ARM/ARMInstrVFP.td

 def VDIVS  : ASbI<0b11101, 0b00, 0, 0,
                   (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
                   IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
                   [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>,
              Sched<[WriteFPDIV32]>;
 
 let TwoOperandAliasConstraint = "$Sn = $Sd" in
 def VDIVH  : AHbI<0b11101, 0b00, 0, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
+                  (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
                   IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm",
-                  []>,
+                  [(set HPR:$Sd, (fdiv HPR:$Sn, HPR:$Sm))]>,
              Sched<[WriteFPDIV32]>;
 
 let TwoOperandAliasConstraint = "$Dn = $Dd" in
 def VMULD  : ADbI<0b11100, 0b10, 0, 0,
                   (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
                   IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
                   [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>,
              Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>;
 
 let TwoOperandAliasConstraint = "$Sn = $Sd" in
 def VMULS  : ASbIn<0b11100, 0b10, 0, 0,
                    (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
                    IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
                    [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>,
             Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> {
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines on A8.
   let D = VFPNeonA8Domain;
 }
 
 let TwoOperandAliasConstraint = "$Sn = $Sd" in
 def VMULH  : AHbI<0b11100, 0b10, 0, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
+                  (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
                   IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm",
-                  []>,
+                  [(set HPR:$Sd, (fmul HPR:$Sn, HPR:$Sm))]>,
              Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>;
 
 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
                   (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
                   IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
                   [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>,
              Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>;
 
 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
                   (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
                   IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
                   [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>,
             Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> {
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines on A8.
   let D = VFPNeonA8Domain;
 }
 
 def VNMULH : AHbI<0b11100, 0b10, 1, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
+                  (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
                   IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",
-                  []>,
+                  [(set HPR:$Sd, (fneg (fmul HPR:$Sn, HPR:$Sm)))]>,
              Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>;
 
 multiclass vsel_inst<string op, bits<2> opc, int CC> {
   let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
       Uses = [CPSR], AddedComplexity = 4 in {
     def H : AHbInp<0b11100, opc, 0,
                    (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
                    NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"),
def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
                   IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
                   [(arm_cmpfp SPR:$Sd, SPR:$Sm, (i32 1))]> {
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines on A8.
   let D = VFPNeonA8Domain;
 }
 
 def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0,
-                  (outs), (ins SPR:$Sd, SPR:$Sm),
+                  (outs), (ins HPR:$Sd, HPR:$Sm),
                   IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm",
-                  []>;
+                  [(arm_cmpfp HPR:$Sd, HPR:$Sm, (i32 1))]>;
 
 def VCMPD  : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
                   (outs), (ins DPR:$Dd, DPR:$Dm),
                   IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
                   [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm), (i32 0))]>;
 
 def VCMPS  : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
                   (outs), (ins SPR:$Sd, SPR:$Sm),
                   IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
                   [(arm_cmpfp SPR:$Sd, SPR:$Sm, (i32 0))]> {
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines on A8.
   let D = VFPNeonA8Domain;
 }
 
 def VCMPH  : AHuI<0b11101, 0b11, 0b0100, 0b01, 0,
-                  (outs), (ins SPR:$Sd, SPR:$Sm),
+                  (outs), (ins HPR:$Sd, HPR:$Sm),
                   IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm",
-                  []>;
+                  [(arm_cmpfp HPR:$Sd, HPR:$Sm, (i32 0))]>;
 } // Defs = [FPSCR_NZCV]
 
 //===----------------------------------------------------------------------===//
 // FP Unary Operations.
 //
 
 def VABSD  : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
                   (outs DPR:$Dd), (ins DPR:$Dm),

 
 def : FP16Pat<(f64 (f16_to_fp GPR:$a)),
               (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
 
 multiclass vcvt_inst<string opc, bits<2> rm,
                      SDPatternOperator node = null_frag> {
   let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
     def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0,
-                    (outs SPR:$Sd), (ins SPR:$Sm),
+                    (outs SPR:$Sd), (ins HPR:$Sm),
                     NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"),
                     []>,
                     Requires<[HasFullFP16]> {
       let Inst{17-16} = rm;
     }
 
     def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0,
-                    (outs SPR:$Sd), (ins SPR:$Sm),
+                    (outs SPR:$Sd), (ins HPR:$Sm),
                     NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"),
                     []>,
                     Requires<[HasFullFP16]> {
       let Inst{17-16} = rm;
     }
 
     def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
                     (outs SPR:$Sd), (ins SPR:$Sm),
def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
       // Encode instruction operands
       let Inst{3-0}  = Dm{3-0};
       let Inst{5}    = Dm{4};
       let Inst{8} = 1;
     }
   }
 
   let Predicates = [HasFPARMv8] in {
+    let Predicates = [HasFullFP16] in {
+    def : Pat<(i32 (fp_to_sint (node HPR:$a))),
+              (COPY_TO_REGCLASS
+                (!cast<Instruction>(NAME#"SH") HPR:$a),
+                GPR)>;
+
+    def : Pat<(i32 (fp_to_uint (node HPR:$a))),
+              (COPY_TO_REGCLASS
+                (!cast<Instruction>(NAME#"UH") HPR:$a),
+                GPR)>;
+    }
     def : Pat<(i32 (fp_to_sint (node SPR:$a))),
               (COPY_TO_REGCLASS
                 (!cast<Instruction>(NAME#"SS") SPR:$a),
                 GPR)>;
     def : Pat<(i32 (fp_to_uint (node SPR:$a))),
               (COPY_TO_REGCLASS
                 (!cast<Instruction>(NAME#"US") SPR:$a),
                 GPR)>;
def VNEGS  : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
                    IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
                    [(set SPR:$Sd, (fneg SPR:$Sm))]> {
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines on A8.
   let D = VFPNeonA8Domain;
 }
 
 def VNEGH  : AHuI<0b11101, 0b11, 0b0001, 0b01, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sm),
+                  (outs HPR:$Sd), (ins HPR:$Sm),
                   IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm",
-                  []>;
+                  [(set HPR:$Sd, (fneg HPR:$Sm))]>;
 
 multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
   def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0,
                (outs SPR:$Sd), (ins SPR:$Sm),
                NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm",
                []>,
                Requires<[HasFullFP16]> {
     let Inst{7} = op2;

 
 def : VFPNoNEONPat<(f32 (sint_to_fp GPR:$a)),
                    (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
 
 def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))),
                    (VSITOS (VLDRS addrmode5:$a))>;
 
 def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
-                               (outs SPR:$Sd), (ins SPR:$Sm),
+                               (outs HPR:$Sd), (ins SPR:$Sm),
                                IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm",
                                []>,
              Sched<[WriteFPCVT]> {
   let Inst{7} = 1; // s32
 }
 
+def : VFPNoNEONPat<(f16 (sint_to_fp GPR:$a)),
+                   (VSITOH (COPY_TO_REGCLASS GPR:$a, SPR))>;
+
 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
                                (outs DPR:$Dd), (ins SPR:$Sm),
                                IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
                                []>,
              Sched<[WriteFPCVT]> {
   let Inst{7} = 0; // u32
 }
 

 
 def : VFPNoNEONPat<(f32 (uint_to_fp GPR:$a)),
                    (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
 
 def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))),
                    (VUITOS (VLDRS addrmode5:$a))>;
 
 def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
-                                (outs SPR:$Sd), (ins SPR:$Sm),
+                                (outs HPR:$Sd), (ins SPR:$Sm),
                                 IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm",
                                 []>,
              Sched<[WriteFPCVT]> {
   let Inst{7} = 0; // u32
 }
 
+def : VFPNoNEONPat<(f16 (uint_to_fp GPR:$a)),
+                   (VUITOH (COPY_TO_REGCLASS GPR:$a, SPR))>;
+
 // FP -> Int:
 
 class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
                         bits<4> opcod4, dag oops, dag iops,
                         InstrItinClass itin, string opc, string asm,
                         list<dag> pattern>
   : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
              pattern> {

 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
                    (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
 
 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
                                    addrmode5:$ptr),
                    (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
 
 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
-                                 (outs SPR:$Sd), (ins SPR:$Sm),
+                                 (outs SPR:$Sd), (ins HPR:$Sm),
                                  IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm",
                                  []>,
               Sched<[WriteFPCVT]> {
   let Inst{7} = 1; // Z bit
 }
 
+def : VFPNoNEONPat<(i32 (fp_to_sint HPR:$a)),
+                   (COPY_TO_REGCLASS (VTOSIZH HPR:$a), GPR)>;
+
 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
                                (outs SPR:$Sd), (ins DPR:$Dm),
                                IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
                                []>,
               Sched<[WriteFPCVT]> {
   let Inst{7} = 1; // Z bit
 }
 

 def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
                    (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
 
 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
                                    addrmode5:$ptr),
                   (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
 
 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
-                                 (outs SPR:$Sd), (ins SPR:$Sm),
+                                 (outs SPR:$Sd), (ins HPR:$Sm),
                                  IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm",
                                  []>,
               Sched<[WriteFPCVT]> {
   let Inst{7} = 1; // Z bit
 }
 
+def : VFPNoNEONPat<(i32 (fp_to_uint HPR:$a)),
+                   (COPY_TO_REGCLASS (VTOUIZH HPR:$a), GPR)>;
+
 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
 let Uses = [FPSCR] in {
 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
                                 (outs SPR:$Sd), (ins DPR:$Dm),
                                 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
                                 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>,
               Sched<[WriteFPCVT]> {
   let Inst{7} = 0; // Z bit
def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
               Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>,
               Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines on A8.
   let D = VFPNeonA8Domain;
 }
 
 def VMLAH : AHbI<0b11100, 0b00, 0, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
+                  (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
                   IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm",
-                  []>,
+                  [(set HPR:$Sd, (fadd_mlx (fmul_su HPR:$Sn, HPR:$Sm),
+                                           HPR:$Sdin))]>,
               RegConstraint<"$Sdin = $Sd">,
               Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;
 
 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
           (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
           Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
           (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
           Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
+def : Pat<(fadd_mlx HPR:$dstin, (fmul_su HPR:$a, HPR:$b)),
+          (VMLAH HPR:$dstin, HPR:$a, HPR:$b)>,
+          Requires<[HasFullFP16,DontUseNEONForFP, UseFPVMLx,DontUseFusedMAC]>;
+
 
 def VMLSD : ADbI<0b11100, 0b00, 1, 0,
                  (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
                  IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
                  [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
                                           (f64 DPR:$Ddin)))]>,
               RegConstraint<"$Ddin = $Dd">,
               Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>,
               Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;
 
 def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
                   (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
                   IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
                   [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
                                            SPR:$Sdin))]>,
               RegConstraint<"$Sdin = $Sd">,
               Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>,
               Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines on A8.
   let D = VFPNeonA8Domain;
 }
 
 def VMLSH : AHbI<0b11100, 0b00, 1, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
+                  (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
                   IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm",
-                  []>,
+                  [(set HPR:$Sd, (fadd_mlx (fneg (fmul_su HPR:$Sn, HPR:$Sm)),
+                                           HPR:$Sdin))]>,
               RegConstraint<"$Sdin = $Sd">,
               Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;
 
 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
           (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
           Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
           (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
           Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
+def : Pat<(fsub_mlx HPR:$dstin, (fmul_su HPR:$a, HPR:$b)),
+          (VMLSH HPR:$dstin, HPR:$a, HPR:$b)>,
+          Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
 
 def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
                   (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
                   IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
                   [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
                                           (f64 DPR:$Ddin)))]>,
                 RegConstraint<"$Ddin = $Dd">,
                 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>,
                 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;
 
 def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
                   (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
                   IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
                   [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
                                            SPR:$Sdin))]>,
                 RegConstraint<"$Sdin = $Sd">,
                 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>,
                 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines on A8.
   let D = VFPNeonA8Domain;
 }
 
 def VNMLAH : AHbI<0b11100, 0b01, 1, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
+                  (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
                   IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm",
-                  []>,
+                  [(set HPR:$Sd, (fsub_mlx (fneg (fmul_su HPR:$Sn, HPR:$Sm)),
+                                           HPR:$Sdin))]>,
                 RegConstraint<"$Sdin = $Sd">,
                 Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;
 
 // (-(a * b) - dst) -> -(dst + (a * b))
 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
           (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
           Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
           (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
           Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
+def : Pat<(fsub_mlx (fneg (fmul_su HPR:$a, HPR:$b)), HPR:$dstin),
+          (VNMLAH HPR:$dstin, HPR:$a, HPR:$b)>,
+          Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
 
 // (-dst - (a * b)) -> -(dst + (a * b))
 def : Pat<(fsub_mlx (fneg DPR:$dstin), (fmul_su DPR:$a, (f64 DPR:$b))),
           (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
           Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
 def : Pat<(fsub_mlx (fneg SPR:$dstin), (fmul_su SPR:$a, SPR:$b)),
           (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
           Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
+def : Pat<(fsub_mlx (fneg HPR:$dstin), (fmul_su HPR:$a, HPR:$b)),
+          (VNMLAH HPR:$dstin, HPR:$a, HPR:$b)>,
+          Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
 
 def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
                   (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
                   IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
                   [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
                                            (f64 DPR:$Ddin)))]>,
                RegConstraint<"$Ddin = $Dd">,
                Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>,
                Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;
 
 def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
                   (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
                   IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
              [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
                          RegConstraint<"$Sdin = $Sd">,
                 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>,
              Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines on A8.
   let D = VFPNeonA8Domain;
 }
 
 def VNMLSH : AHbI<0b11100, 0b01, 0, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
+                  (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
                   IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm",
-             []>,
+             [(set HPR:$Sd, (fsub_mlx (fmul_su HPR:$Sn, HPR:$Sm), HPR:$Sdin))]>,
                          RegConstraint<"$Sdin = $Sd">,
                 Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;
 
 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
           (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
           Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
           (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
           Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
+def : Pat<(fsub_mlx (fmul_su HPR:$a, HPR:$b), HPR:$dstin),
+          (VNMLSH HPR:$dstin, HPR:$a, HPR:$b)>,
+          Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx,DontUseFusedMAC]>;
 
 //===----------------------------------------------------------------------===//
 // Fused FP Multiply-Accumulate Operations.
 //
 def VFMAD : ADbI<0b11101, 0b10, 0, 0,
                  (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
                  IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
                  [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
def VFMAS : ASbIn<0b11101, 0b10, 0, 0,
               RegConstraint<"$Sdin = $Sd">,
               Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>,
             Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines.
 }
 
 def VFMAH : AHbI<0b11101, 0b10, 0, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
+                  (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
                   IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm",
-                  []>,
+                  [(set HPR:$Sd, (fadd_mlx (fmul_su HPR:$Sn, HPR:$Sm),
+                                           HPR:$Sdin))]>,
               RegConstraint<"$Sdin = $Sd">,
               Requires<[HasFullFP16,UseFusedMAC]>,
             Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;
 
 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
           (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
           Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
           (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
           Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
+def : Pat<(fadd_mlx HPR:$dstin, (fmul_su HPR:$a, HPR:$b)),
+          (VFMAH HPR:$dstin, HPR:$a, HPR:$b)>,
+          Requires<[HasFullFP16,DontUseNEONForFP,UseFusedMAC]>;
 
 // Match @llvm.fma.* intrinsics
 // (fma x, y, z) -> (vfms z, x, y)
 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
           (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
       Requires<[HasVFP4,HasDPVFP]>;
 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
           (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
def VFMSS : ASbIn<0b11101, 0b10, 1, 0,
               RegConstraint<"$Sdin = $Sd">,
               Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>,
               Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines.
 }
 
 def VFMSH : AHbI<0b11101, 0b10, 1, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
+                  (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
                   IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm",
-                  []>,
+                  [(set HPR:$Sd, (fadd_mlx (fneg (fmul_su HPR:$Sn, HPR:$Sm)),
+                                           HPR:$Sdin))]>,
               RegConstraint<"$Sdin = $Sd">,
               Requires<[HasFullFP16,UseFusedMAC]>,
               Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;
 
 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
           (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
           Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
           (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
           Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>;
+def : Pat<(fsub_mlx HPR:$dstin, (fmul_su HPR:$a, HPR:$b)),
+          (VFMSH HPR:$dstin, HPR:$a, HPR:$b)>,
+          Requires<[HasFullFP16,DontUseNEONForFP,UseFusedMAC]>;
 
 // Match @llvm.fma.* intrinsics
 // (fma (fneg x), y, z) -> (vfms z, x, y)
 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
           (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
       Requires<[HasVFP4,HasDPVFP]>;
 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
           (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
def VFNMAS : ASbI<0b11101, 0b01, 1, 0,
                 RegConstraint<"$Sdin = $Sd">,
                 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>,
                 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines.
 }
 
 def VFNMAH : AHbI<0b11101, 0b01, 1, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
+                  (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
                   IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm",
-                  []>,
+                  [(set HPR:$Sd, (fsub_mlx (fneg (fmul_su HPR:$Sn, HPR:$Sm)),
+                                           HPR:$Sdin))]>,
                 RegConstraint<"$Sdin = $Sd">,
                 Requires<[HasFullFP16,UseFusedMAC]>,
                 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;
 
 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
           (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
           Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
def VFNMSS : ASbI<0b11101, 0b01, 0, 0,
                          RegConstraint<"$Sdin = $Sd">,
                   Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>,
                   Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> {
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines.
 }
 
 def VFNMSH : AHbI<0b11101, 0b01, 0, 0,
-                  (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
+                  (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
                   IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm",
-             []>,
+             [(set HPR:$Sd, (fsub_mlx (fmul_su HPR:$Sn, HPR:$Sm), HPR:$Sdin))]>,
                          RegConstraint<"$Sdin = $Sd">,
                   Requires<[HasFullFP16,UseFusedMAC]>,
                   Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>;
 
 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
           (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
           Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),

test/CodeGen/ARM/fp16-instructions.ll

 ; SOFT:
 ; RUN: llc < %s -mtriple=arm-none-eabi -float-abi=soft     | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT
+; RUN: llc < %s -mtriple=thumb-none-eabi -float-abi=soft   | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT
 
 ; SOFTFP:
 ; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp3        | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-VFP3
 ; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp4        | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FP16
 ; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+fullfp16    | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FULLFP16
 
+; RUN: llc < %s -mtriple=thumbv7-none-eabi -mattr=+vfp3        | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-VFP3
+; RUN: llc < %s -mtriple=thumbv7-none-eabi -mattr=+vfp4        | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FP16
+; RUN: llc < %s -mtriple=thumbv7-none-eabi -mattr=+fullfp16    | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FULLFP16
+
 ; HARD:
 ; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp3      | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-VFP3
 ; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp4      | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FP16
 ; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+fullfp16  | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FULLFP16
 
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mattr=+vfp3      | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-VFP3
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mattr=+vfp4      | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FP16
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mattr=+fullfp16  | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FULLFP16
+
+; FP-CONTRACT=FAST
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+fullfp16 -fp-contract=fast | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FULLFP16-FAST
+; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mattr=+fullfp16 -fp-contract=fast | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FULLFP16-FAST
+
 
-define float @RetValBug(float %A.coerce) local_unnamed_addr {
+define float @RetValBug(float %A.coerce) {
 entry:
   ret float undef
-; This expression is optimised away due to the undef value. Check that
-; LowerReturn can handle undef nodes (i.e. nodes which do not have any
-; operands) when FullFP16 is enabled.
+; Check thatLowerReturn can handle undef nodes (i.e. nodes which do not have
+; any operands) when FullFP16 is enabled.
 ;
 ; CHECK-LABEL:            RetValBug:
-; CHECK-HARDFP-FULLFP16:  mov pc, lr
+; CHECK-HARDFP-FULLFP16:  {{.*}} lr
 }
 
-define float @Add(float %a.coerce, float %b.coerce) local_unnamed_addr {
+; 1. VABS: TODO
+
+; 2. VADD
+define float @Add(float %a.coerce, float %b.coerce) {
 entry:
   %0 = bitcast float %a.coerce to i32
   %tmp.0.extract.trunc = trunc i32 %0 to i16
   %1 = bitcast i16 %tmp.0.extract.trunc to half
   %2 = bitcast float %b.coerce to i32
   %tmp1.0.extract.trunc = trunc i32 %2 to i16
   %3 = bitcast i16 %tmp1.0.extract.trunc to half
   %add = fadd half %1, %3

 ; CHECK-SOFTFP-FP16:  vadd.f32      [[S0]], [[S0]], [[S2]]
 ; CHECK-SOFTFP-FP16:  vcvtb.f16.f32 [[S0]], [[S0]]
 ; CHECK-SOFTFP-FP16:  vmov  r0, s0
 
 ; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S0:s[0-9]]], r1
 ; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S2:s[0-9]]], r0
 ; CHECK-SOFTFP-FULLFP16:       vadd.f16  [[S0]], [[S2]], [[S0]]
 ; CHECK-SOFTFP-FULLFP16-NEXT:  vmov.f16  r0, s0
-; CHECK-SOFTFP-FULLFP16-NEXT:  mov       pc, lr
 
 ; CHECK-HARDFP-VFP3:  vmov r{{.}}, s0
 ; CHECK-HARDFP-VFP3:  vmov{{.*}}, s1
 ; CHECK-HARDFP-VFP3:  bl  __aeabi_h2f
 ; CHECK-HARDFP-VFP3:  bl  __aeabi_h2f
 ; CHECK-HARDFP-VFP3:  vadd.f32
 ; CHECK-HARDFP-VFP3:  bl  __aeabi_f2h
 ; CHECK-HARDFP-VFP3:  vmov  s0, r0
 
 ; CHECK-HARDFP-FP16:  vcvtb.f32.f16 [[S2:s[0-9]]], s1
 ; CHECK-HARDFP-FP16:  vcvtb.f32.f16 [[S0:s[0-9]]], s0
 ; CHECK-HARDFP-FP16:  vadd.f32  [[S0]], [[S0]], [[S2]]
 ; CHECK-HARDFP-FP16:  vcvtb.f16.f32 [[S0]], [[S0]]
 
 ; CHECK-HARDFP-FULLFP16:       vadd.f16  s0, s0, s1
-; CHECK-HARDFP-FULLFP16-NEXT:  mov pc, lr
+}
+
+; 3. VCMP
+define zeroext i1 @VCMP(float %F.coerce, float %G.coerce) {
+entry:
+  %0 = bitcast float %F.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %G.coerce to i32
+  %tmp1.0.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp1.0.extract.trunc to half
+  %cmp = fcmp ogt half %1, %3
+  ret i1 %cmp
+
+; CHECK-LABEL:            VCMP:
+
+; CHECK-SOFT:             bl  __aeabi_fcmpgt
+
+; CHECK-SOFTFP-VFP3:      bl  __aeabi_h2f
+; CHECK-SOFTFP-VFP3:      bl  __aeabi_h2f
+; CHECK-SOFTFP-VFP3:      vcmpe.f32 s{{.}}, s{{.}}
+
+; CHECK-SOFTFP-FP16:      vcvtb.f32.f16 s{{.}}, s{{.}}
+; CHECK-SOFTFP-FP16:      vcvtb.f32.f16 s{{.}}, s{{.}}
+; CHECK-SOFTFP-FP16:      vcmpe.f32 s{{.}}, s{{.}}
+
+; CHECK-SOFTFP-FULLFP16:  vmov.f16  [[S2:s[0-9]]], r0
+; CHECK-SOFTFP-FULLFP16:  vmov.f16 [[S0:s[0-9]]], r1
+; CHECK-SOFTFP-FULLFP16:  vcmpe.f16 [[S2]], [[S0]]
+
+; CHECK-SOFTFP-FULLFP16-NOT:  vmov.f16  s{{.}}, r0
+; CHECK-SOFTFP-FULLFP16-NOT:  vmov.f16  s{{.}}, r1
+; CHECK-HARDFP-FULLFP16:      vcmpe.f16  s0, s1
+}
+
+; 4. VCMPE
+
+; FIXME: enable when constant pool is fixed
+;
+;define i32 @VCMPE_IMM(float %F.coerce) {
+;entry:
+;  %0 = bitcast float %F.coerce to i32
+;  %tmp.0.extract.trunc = trunc i32 %0 to i16
+;  %1 = bitcast i16 %tmp.0.extract.trunc to half
+;  %tmp = fcmp olt half %1, 1.000000e+00
+;  %tmp1 = zext i1 %tmp to i32
+;  ret i32 %tmp1
+;}
+
+define i32 @VCMPE(float %F.coerce, float %G.coerce) {
+entry:
+  %0 = bitcast float %F.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %G.coerce to i32
+  %tmp.1.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp.1.extract.trunc to half
+  %tmp = fcmp olt half %1, %3
+  %tmp1 = zext i1 %tmp to i32
+  ret i32 %tmp1
+
+; CHECK-LABEL:  VCMPE:
+}
+
+; 5. VCVT (between floating-point and fixed-point)
+; Only assembly/disassembly support
+
+; 6. VCVT (between floating-point and integer, both directions)
+define i32 @fptosi(i32 %A.coerce) {
+entry:
+  %tmp.0.extract.trunc = trunc i32 %A.coerce to i16
+  %0 = bitcast i16 %tmp.0.extract.trunc to half
+  %conv = fptosi half %0 to i32
+  ret i32 %conv
+
+; CHECK-LABEL:                 fptosi:
+
+; CHECK-HARDFP-FULLFP16:       vmov.f16  s0, r0
+; CHECK-HARDFP-FULLFP16-NEXT:  vcvt.s32.f16  s0, s0
+; CHECK-HARDFP-FULLFP16-NEXT:  vmov  r0, s0
+}
+
+define i32 @fptoui(i32 %A.coerce) {
+entry:
+  %tmp.0.extract.trunc = trunc i32 %A.coerce to i16
+  %0 = bitcast i16 %tmp.0.extract.trunc to half
+  %conv = fptoui half %0 to i32
+  ret i32 %conv
+
+; CHECK-HARDFP-FULLFP16:       vcvt.u32.f16  s0, s0
+; CHECK-HARDFP-FULLFP16-NEXT:  vmov  r0, s0
+}
+
+define float @UintToH(i32 %a, i32 %b) {
+entry:
+  %0 = uitofp i32 %a to half
+  %1 = bitcast half %0 to i16
+  %tmp0.insert.ext = zext i16 %1 to i32
+  %2 = bitcast i32 %tmp0.insert.ext to float
+  ret float %2
+
+; CHECK-LABEL:                 UintToH:
+
+; CHECK-HARDFP-FULLFP16:       vmov  s0, r0
+; CHECK-HARDFP-FULLFP16-NEXT:  vcvt.f16.u32  s0, s0
+}
+
+define float @SintToH(i32 %a, i32 %b) {
+entry:
+  %0 = sitofp i32 %a to half
+  %1 = bitcast half %0 to i16
+  %tmp0.insert.ext = zext i16 %1 to i32
+  %2 = bitcast i32 %tmp0.insert.ext to float
+  ret float %2
+
+; CHECK-LABEL:                 SintToH:
+
+; CHECK-HARDFP-FULLFP16:       vmov  s0, r0
+; CHECK-HARDFP-FULLFP16-NEXT:  vcvt.f16.s32  s0, s0
+}
+
+; TODO:
+; 7.  VCVTA
+; 8.  VCVTM
+; 9.  VCVTN
+; 10. VCVTP
+; 11. VCVTR
+
+; 12. VDIV
+define float @Div(float %a.coerce, float %b.coerce) {
+entry:
+  %0 = bitcast float %a.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %b.coerce to i32
+  %tmp1.0.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp1.0.extract.trunc to half
+  %add = fdiv half %1, %3
+  %4 = bitcast half %add to i16
+  %tmp4.0.insert.ext = zext i16 %4 to i32
+  %5 = bitcast i32 %tmp4.0.insert.ext to float
+  ret float %5
+
+; CHECK-LABEL:  Div:
+
+; CHECK-SOFT:  bl  __aeabi_h2f
+; CHECK-SOFT:  bl  __aeabi_h2f
+; CHECK-SOFT:  bl  __aeabi_fdiv
+; CHECK-SOFT:  bl  __aeabi_f2h
+
+; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
+; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
+; CHECK-SOFTFP-VFP3:  vdiv.f32
+; CHECK-SOFTFP-VFP3:  bl  __aeabi_f2h
+
+; CHECK-SOFTFP-FP16:  vmov          [[S2:s[0-9]]], r1
+; CHECK-SOFTFP-FP16:  vmov          [[S0:s[0-9]]], r0
+; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S2]], [[S2]]
+; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16:  vdiv.f32      [[S0]], [[S0]], [[S2]]
+; CHECK-SOFTFP-FP16:  vcvtb.f16.f32 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16:  vmov  r0, s0
+
+; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S0:s[0-9]]], r1
+; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S2:s[0-9]]], r0
+; CHECK-SOFTFP-FULLFP16:       vdiv.f16  [[S0]], [[S2]], [[S0]]
+; CHECK-SOFTFP-FULLFP16-NEXT:  vmov.f16  r0, s0
+
+; CHECK-HARDFP-VFP3:  vmov r{{.}}, s0
+; CHECK-HARDFP-VFP3:  vmov{{.*}}, s1
+; CHECK-HARDFP-VFP3:  bl  __aeabi_h2f
+; CHECK-HARDFP-VFP3:  bl  __aeabi_h2f
+; CHECK-HARDFP-VFP3:  vdiv.f32
+; CHECK-HARDFP-VFP3:  bl  __aeabi_f2h
+; CHECK-HARDFP-VFP3:  vmov  s0, r0
+
+; CHECK-HARDFP-FP16:  vcvtb.f32.f16 [[S2:s[0-9]]], s1
+; CHECK-HARDFP-FP16:  vcvtb.f32.f16 [[S0:s[0-9]]], s0
+; CHECK-HARDFP-FP16:  vdiv.f32  [[S0]], [[S0]], [[S2]]
+; CHECK-HARDFP-FP16:  vcvtb.f16.f32 [[S0]], [[S0]]
+
+; CHECK-HARDFP-FULLFP16:       vdiv.f16  s0, s0, s1
+}
+
+; 13. VFMA
+define float @VFMA(float %a.coerce, float %b.coerce, float %c.coerce) {
+entry:
+  %0 = bitcast float %a.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %b.coerce to i32
+  %tmp1.0.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp1.0.extract.trunc to half
+  %4 = bitcast float %c.coerce to i32
+  %tmp2.0.extract.trunc = trunc i32 %4 to i16
+  %5 = bitcast i16 %tmp2.0.extract.trunc to half
+  %mul = fmul half %1, %3
+  %add = fadd half %mul, %5
+  %6 = bitcast half %add to i16
+  %tmp4.0.insert.ext = zext i16 %6 to i32
+  %7 = bitcast i32 %tmp4.0.insert.ext to float
+  ret float %7
+
+; CHECK-LABEL:                      VFMA:
+; CHECK-HARDFP-FULLFP16-FAST:       vfma.f16  s2, s0, s1
+; CHECK-HARDFP-FULLFP16-FAST-NEXT:  vmov.f32  s0, s2
+}
+
+; 14. VFMS
+define float @VFMS(float %a.coerce, float %b.coerce, float %c.coerce) {
+entry:
+  %0 = bitcast float %a.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %b.coerce to i32
+  %tmp1.0.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp1.0.extract.trunc to half
+  %4 = bitcast float %c.coerce to i32
+  %tmp2.0.extract.trunc = trunc i32 %4 to i16
+  %5 = bitcast i16 %tmp2.0.extract.trunc to half
+  %mul = fmul half %1, %3
+  %sub = fsub half %5, %mul
+  %6 = bitcast half %sub to i16
+  %tmp4.0.insert.ext = zext i16 %6 to i32
+  %7 = bitcast i32 %tmp4.0.insert.ext to float
+  ret float %7
+
+; CHECK-LABEL:                      VFMS:
+; CHECK-HARDFP-FULLFP16-FAST:       vfms.f16  s2, s0, s1
+; CHECK-HARDFP-FULLFP16-FAST-NEXT:  vmov.f32  s0, s2
+}
+
+; 15. VFNMA
+define float @VFNMA(float %a.coerce, float %b.coerce, float %c.coerce) {
+entry:
+  %0 = bitcast float %a.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %b.coerce to i32
+  %tmp1.0.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp1.0.extract.trunc to half
+  %4 = bitcast float %c.coerce to i32
+  %tmp2.0.extract.trunc = trunc i32 %4 to i16
+  %5 = bitcast i16 %tmp2.0.extract.trunc to half
+  %mul = fmul half %1, %3
+  %sub = fsub half -0.0, %mul
+  %sub2 = fsub half %sub, %5
+  %6 = bitcast half %sub2 to i16
+  %tmp4.0.insert.ext = zext i16 %6 to i32
+  %7 = bitcast i32 %tmp4.0.insert.ext to float
+  ret float %7
+
+; CHECK-LABEL:                      VFNMA:
+; CHECK-HARDFP-FULLFP16-FAST:       vfnma.f16  s2, s0, s1
+; CHECK-HARDFP-FULLFP16-FAST-NEXT:  vmov.f32  s0, s2
+}
+
+; 16. VFNMS
+define float @VFNMS(float %a.coerce, float %b.coerce, float %c.coerce) {
+entry:
+  %0 = bitcast float %a.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %b.coerce to i32
+  %tmp1.0.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp1.0.extract.trunc to half
+  %4 = bitcast float %c.coerce to i32
+  %tmp2.0.extract.trunc = trunc i32 %4 to i16
+  %5 = bitcast i16 %tmp2.0.extract.trunc to half
+  %mul = fmul half %1, %3
+  %sub2 = fsub half %mul, %5
+  %6 = bitcast half %sub2 to i16
+  %tmp4.0.insert.ext = zext i16 %6 to i32
+  %7 = bitcast i32 %tmp4.0.insert.ext to float
+  ret float %7
+
+; CHECK-LABEL:                      VFNMS:
+; CHECK-HARDFP-FULLFP16-FAST:       vfnms.f16  s2, s0, s1
+; CHECK-HARDFP-FULLFP16-FAST-NEXT:  vmov.f32  s0, s2
+}
+
+; TODO:
+; 17. VMAXNM
+; 18. VMINNM
+
+; 19. VMLA
+define float @VMLA(float %a.coerce, float %b.coerce, float %c.coerce) {
+entry:
+  %0 = bitcast float %a.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %b.coerce to i32
+  %tmp1.0.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp1.0.extract.trunc to half
+  %4 = bitcast float %c.coerce to i32
+  %tmp2.0.extract.trunc = trunc i32 %4 to i16
+  %5 = bitcast i16 %tmp2.0.extract.trunc to half
+  %mul = fmul half %1, %3
+  %add = fadd half %5, %mul
+  %6 = bitcast half %add to i16
+  %tmp4.0.insert.ext = zext i16 %6 to i32
+  %7 = bitcast i32 %tmp4.0.insert.ext to float
+  ret float %7
+
+; CHECK-LABEL:                 VMLA:
+; CHECK-HARDFP-FULLFP16:       vmla.f16  s2, s0, s1
+; CHECK-HARDFP-FULLFP16-NEXT:  vmov.f32  s0, s2
+}
+
+; 20. VMLS
+define float @VMLS(float %a.coerce, float %b.coerce, float %c.coerce) {
+entry:
+  %0 = bitcast float %a.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %b.coerce to i32
+  %tmp1.0.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp1.0.extract.trunc to half
+  %4 = bitcast float %c.coerce to i32
+  %tmp2.0.extract.trunc = trunc i32 %4 to i16
+  %5 = bitcast i16 %tmp2.0.extract.trunc to half
+  %mul = fmul half %1, %3
+  %add = fsub half %5, %mul
+  %6 = bitcast half %add to i16
+  %tmp4.0.insert.ext = zext i16 %6 to i32
+  %7 = bitcast i32 %tmp4.0.insert.ext to float
+  ret float %7
+
+; CHECK-LABEL:                 VMLS:
+; CHECK-HARDFP-FULLFP16:       vmls.f16  s2, s0, s1
+; CHECK-HARDFP-FULLFP16-NEXT:  vmov.f32  s0, s2
+}
+
+; TODO: fix immediates.
+; 21. VMOV (between general-purpose register and half-precision register)
+; 22. VMOV (immediate)
+
+; 23. VMUL
+define float @Mul(float %a.coerce, float %b.coerce) {
+entry:
+  %0 = bitcast float %a.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %b.coerce to i32
+  %tmp1.0.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp1.0.extract.trunc to half
+  %add = fmul half %1, %3
+  %4 = bitcast half %add to i16
+  %tmp4.0.insert.ext = zext i16 %4 to i32
+  %5 = bitcast i32 %tmp4.0.insert.ext to float
+  ret float %5
+
+; CHECK-LABEL:  Mul:
+
+; CHECK-SOFT:  bl  __aeabi_h2f
+; CHECK-SOFT:  bl  __aeabi_h2f
+; CHECK-SOFT:  bl  __aeabi_fmul
+; CHECK-SOFT:  bl  __aeabi_f2h
+
+; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
+; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
+; CHECK-SOFTFP-VFP3:  vmul.f32
+; CHECK-SOFTFP-VFP3:  bl  __aeabi_f2h
+
+; CHECK-SOFTFP-FP16:  vmov          [[S2:s[0-9]]], r1
+; CHECK-SOFTFP-FP16:  vmov          [[S0:s[0-9]]], r0
+; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S2]], [[S2]]
+; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16:  vmul.f32      [[S0]], [[S0]], [[S2]]
+; CHECK-SOFTFP-FP16:  vcvtb.f16.f32 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16:  vmov  r0, s0
+
+; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S0:s[0-9]]], r1
+; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S2:s[0-9]]], r0
+; CHECK-SOFTFP-FULLFP16:       vmul.f16  [[S0]], [[S2]], [[S0]]
+; CHECK-SOFTFP-FULLFP16-NEXT:  vmov.f16  r0, s0
+
+; CHECK-HARDFP-VFP3:  vmov r{{.}}, s0
+; CHECK-HARDFP-VFP3:  vmov{{.*}}, s1
+; CHECK-HARDFP-VFP3:  bl  __aeabi_h2f
+; CHECK-HARDFP-VFP3:  bl  __aeabi_h2f
+; CHECK-HARDFP-VFP3:  vmul.f32
+; CHECK-HARDFP-VFP3:  bl  __aeabi_f2h
+; CHECK-HARDFP-VFP3:  vmov  s0, r0
+
+; CHECK-HARDFP-FP16:  vcvtb.f32.f16 [[S2:s[0-9]]], s1
+; CHECK-HARDFP-FP16:  vcvtb.f32.f16 [[S0:s[0-9]]], s0
+; CHECK-HARDFP-FP16:  vmul.f32  [[S0]], [[S0]], [[S2]]
+; CHECK-HARDFP-FP16:  vcvtb.f16.f32 [[S0]], [[S0]]
+
+; CHECK-HARDFP-FULLFP16:       vmul.f16  s0, s0, s1
+}
+
+; 24. VNEG
+define float @Neg(float %a.coerce) {
+entry:
+  %0 = bitcast float %a.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = fsub half -0.000000e+00, %1
+  %3 = bitcast half %2 to i16
+  %tmp4.0.insert.ext = zext i16 %3 to i32
+  %4 = bitcast i32 %tmp4.0.insert.ext to float
+  ret float %4
+
+; CHECK-LABEL:                 Neg:
+; CHECK-HARDFP-FULLFP16:       vneg.f16  s0, s0
+}
+
+; 25. VNMLA
+define float @VNMLA(float %a.coerce, float %b.coerce, float %c.coerce) {
+entry:
+  %0 = bitcast float %a.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %b.coerce to i32
+  %tmp1.0.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp1.0.extract.trunc to half
+  %4 = bitcast float %c.coerce to i32
+  %tmp2.0.extract.trunc = trunc i32 %4 to i16
+  %5 = bitcast i16 %tmp2.0.extract.trunc to half
+  %add = fmul half %1, %3
+  %add2 = fsub half -0.000000e+00, %add
+  %add3 = fsub half %add2, %5
+  %6 = bitcast half %add3 to i16
+  %tmp4.0.insert.ext = zext i16 %6 to i32
+  %7 = bitcast i32 %tmp4.0.insert.ext to float
+  ret float %7
+
+; CHECK-LABEL:            VNMLA:
+; CHECK-HARDFP-FULLFP16:  vnmla.f16 s2, s0, s1
+; CHECK-HARDFP-FULLFP16:  vmov.f32  s0, s2
+}
+
+; 26. VNMLS
+define float @VNMLS(float %a.coerce, float %b.coerce, float %c.coerce) {
+entry:
+  %0 = bitcast float %a.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %b.coerce to i32
+  %tmp1.0.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp1.0.extract.trunc to half
+  %4 = bitcast float %c.coerce to i32
+  %tmp2.0.extract.trunc = trunc i32 %4 to i16
+  %5 = bitcast i16 %tmp2.0.extract.trunc to half
+  %add = fmul half %1, %3
+  %add2 = fsub half %add, %5
+  %6 = bitcast half %add2 to i16
+  %tmp4.0.insert.ext = zext i16 %6 to i32
+  %7 = bitcast i32 %tmp4.0.insert.ext to float
+  ret float %7
+
+; CHECK-LABEL:            VNMLS:
+; CHECK-HARDFP-FULLFP16:  vnmls.f16 s2, s0, s1
+; CHECK-HARDFP-FULLFP16:  vmov.f32  s0, s2
+}
+
+; 27. VNMUL
+define float @NMul(float %a.coerce, float %b.coerce) {
+entry:
+  %0 = bitcast float %a.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %b.coerce to i32
+  %tmp1.0.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp1.0.extract.trunc to half
+  %add = fmul half %1, %3
+  %add2 = fsub half -0.0, %add
+  %4 = bitcast half %add2 to i16
+  %tmp4.0.insert.ext = zext i16 %4 to i32
+  %5 = bitcast i32 %tmp4.0.insert.ext to float
+  ret float %5
+
+; CHECK-LABEL:                 NMul:
+; CHECK-HARDFP-FULLFP16:       vnmul.f16  s0, s0, s1
+}
+
+; 28. VRINTA
+; 29. VRINTM
+; 30. VRINTN
+; 31. VRINTP
+; 32. VRINTR
+; 33. VRINTX
+; 34. VRINTZ
+; 35. VSELEQ
+; 36. VSELGE
+; 37. VSELGT
+; 38. VSELVS
+; 39. VSQRT
+
+; 40. VSUB
+define float @Sub(float %a.coerce, float %b.coerce) {
+entry:
+  %0 = bitcast float %a.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %2 = bitcast float %b.coerce to i32
+  %tmp1.0.extract.trunc = trunc i32 %2 to i16
+  %3 = bitcast i16 %tmp1.0.extract.trunc to half
+  %add = fsub half %1, %3
+  %4 = bitcast half %add to i16
+  %tmp4.0.insert.ext = zext i16 %4 to i32
+  %5 = bitcast i32 %tmp4.0.insert.ext to float
+  ret float %5
+
+; CHECK-LABEL:  Sub:
+
+; CHECK-SOFT:  bl  __aeabi_h2f
+; CHECK-SOFT:  bl  __aeabi_h2f
+; CHECK-SOFT:  bl  __aeabi_fsub
+; CHECK-SOFT:  bl  __aeabi_f2h
+
+; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
+; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
+; CHECK-SOFTFP-VFP3:  vsub.f32
+; CHECK-SOFTFP-VFP3:  bl  __aeabi_f2h
+
+; CHECK-SOFTFP-FP16:  vmov          [[S2:s[0-9]]], r1
+; CHECK-SOFTFP-FP16:  vmov          [[S0:s[0-9]]], r0
+; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S2]], [[S2]]
+; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16:  vsub.f32      [[S0]], [[S0]], [[S2]]
+; CHECK-SOFTFP-FP16:  vcvtb.f16.f32 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16:  vmov  r0, s0
+
+; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S0:s[0-9]]], r1
+; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S2:s[0-9]]], r0
+; CHECK-SOFTFP-FULLFP16:       vsub.f16  [[S0]], [[S2]], [[S0]]
+; CHECK-SOFTFP-FULLFP16-NEXT:  vmov.f16  r0, s0
+
+; CHECK-HARDFP-VFP3:  vmov r{{.}}, s0
+; CHECK-HARDFP-VFP3:  vmov{{.*}}, s1
+; CHECK-HARDFP-VFP3:  bl  __aeabi_h2f
+; CHECK-HARDFP-VFP3:  bl  __aeabi_h2f
+; CHECK-HARDFP-VFP3:  vsub.f32
+; CHECK-HARDFP-VFP3:  bl  __aeabi_f2h
+; CHECK-HARDFP-VFP3:  vmov  s0, r0
+
+; CHECK-HARDFP-FP16:  vcvtb.f32.f16 [[S2:s[0-9]]], s1
+; CHECK-HARDFP-FP16:  vcvtb.f32.f16 [[S0:s[0-9]]], s0
+; CHECK-HARDFP-FP16:  vsub.f32  [[S0]], [[S0]], [[S2]]
+; CHECK-HARDFP-FP16:  vcvtb.f16.f32 [[S0]], [[S0]]
+
+; CHECK-HARDFP-FULLFP16:       vsub.f16  s0, s0, s1
 }