This is an archive of the discontinued LLVM Phabricator instance.

Differential D42679

[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.
ClosedPublic

Authored by craig.topper on Jan 30 2018, 1:16 AM.

Details

Reviewers
RKSimon
tra
sfertile
Commits
rGe7ca6f5456a3: [DAGCombiner] When combining zero_extend of a truncate, only mask before…
rL326500: [DAGCombiner] When combining zero_extend of a truncate, only mask before…
Summary

Masking first, prevents the extend from being combine with loads. Its also interfering with some vXi1 extraction code.

Not sure if the other targets here are good or bad. Or if there's some other changes that could be made to recover any loss.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 30 2018, 1:16 AM
Herald added subscribers: javed.absar, nemanjai, jholewinski. · View Herald TranscriptJan 30 2018, 1:16 AM
craig.topper added a reviewer: RKSimon.Jan 30 2018, 1:16 AM
Harbormaster completed remote builds in B14382: Diff 131932.Jan 30 2018, 1:16 AM
RKSimon added a reviewer: jholewinski.Jan 30 2018, 3:56 AM
RKSimon added inline comments.
test/CodeGen/NVPTX/param-load-store.ll
28

This looks like the only regression - I think cvt.u32.u16 effectively acts as "ZERO_EXTEND_INREG" in this case (which we don't have).

@jholewinski any thoughts?

RKSimon edited reviewers, added: tra, sfertile; removed: jholewinski.Jan 30 2018, 3:57 AM
craig.topper added inline comments.Jan 30 2018, 11:34 PM
test/CodeGen/NVPTX/param-load-store.ll
28

Looks like we are able to do fold (zext (and/or/xor (zextload x), cst)) -> (and/or/xor (zextload x), (zext cst)) when the load has multiple uses, but we can't do (zext (zextload x)) -> (zextload x) when there is an additional use.

craig.topper mentioned this in D42783: [DAGCombiner] When folding fold (sext/zext (and/or/xor (sextload/zextload x), cst)) -> (and/or/xor (sextload/zextload x), (sext/zext cst)) make sure we check the legality of the full extended load..Feb 3 2018, 12:19 PM
craig.topper updated this revision to Diff 134506.Feb 15 2018, 2:09 PM

Rebase after D43063

The NVPTX test got weirder now. The setp.eq.b16instruction was always there, but not part of the CHECKs. The and.b32 is new.

tra added a comment.Feb 15 2018, 2:35 PM
In D42679#1009331, @craig.topper wrote:

Rebase after D43063

The NVPTX test got weirder now. The setp.eq.b16instruction was always there, but not part of the CHECKs. The and.b32 is new.

That setp should not be there to start with. AFAICT it's result is not used by anything. I'll take a look at what's going on.

craig.topper added a comment.Feb 22 2018, 3:51 PM

@tra, did you figure out what was going on?

tra added a comment.Feb 23 2018, 10:44 AM
In D42679#1016635, @craig.topper wrote:

@tra, did you figure out what was going on?

Some of it. Something weird is going on during lowering or i1 arguments in NVPTX and we end up with CopyToReg on a chain, but with no other uses. I've found references to what looks like a similar issue in PPC code (ANDIGlueBug), so it may not be a new issue. It certainly has nothing to do with your patch.

LGTM as far as NVPTX is concerned.

tra added a comment.Feb 27 2018, 9:58 AM
In D42679#1017544, @tra wrote:
In D42679#1016635, @craig.topper wrote:

@tra, did you figure out what was going on?

Some of it. Something weird is going on during lowering or i1 arguments in NVPTX and we end up with CopyToReg on a chain, but with no other uses. I've found references to what looks like a similar issue in PPC code (ANDIGlueBug), so it may not be a new issue. It certainly has nothing to do with your patch.

That unused setp is an artifact of -O0. Without it (or with any other -O level) NVPTX generates more sensible code (with or without this patch):

	ld.param.u8 	%r1, [test_i1_param_0];
	and.b32  	%r2, %r1, 1;
	st.param.b32 	[func_retval0+0], %r2;
	ret;
craig.topper added a comment.Mar 1 2018, 12:22 PM

@RKSimon, are you ok with this patch then?

RKSimon accepted this revision.Mar 1 2018, 1:04 PM

LGTM

This revision is now accepted and ready to land.Mar 1 2018, 1:04 PM
Closed by commit rL326500: [DAGCombiner] When combining zero_extend of a truncate, only mask before… (authored by ctopper). · Explain WhyMar 1 2018, 2:35 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
CodeGen/
SelectionDAG/
2 lines
test/
CodeGen/
AArch64/
12 lines
3 lines
4 lines
NVPTX/
6 lines
PowerPC/
8 lines
SystemZ/
4 lines
X86/
1 line
1 line
2 lines
90 lines
4 lines
2 lines
8 lines
5 lines
8 lines
DebugInfo/
X86/
2 lines

Diff 134506

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,855 Lines • ▼ Show 20 Lines if (SDValue NarrowLoad = ReduceLoadWidth(N0.getNode())) {
return SDValue(N, 0); // Return N so it doesn't get rechecked! return SDValue(N, 0); // Return N so it doesn't get rechecked!
} }
EVT SrcVT = N0.getOperand(0).getValueType(); EVT SrcVT = N0.getOperand(0).getValueType();
EVT MinVT = N0.getValueType(); EVT MinVT = N0.getValueType();
// Try to mask before the extension to avoid having to generate a larger mask, // Try to mask before the extension to avoid having to generate a larger mask,
// possibly over several sub-vectors. // possibly over several sub-vectors.
if (SrcVT.bitsLT(VT)) { if (SrcVT.bitsLT(VT) && VT.isVector()) {
if (!LegalOperations || (TLI.isOperationLegal(ISD::AND, SrcVT) && if (!LegalOperations || (TLI.isOperationLegal(ISD::AND, SrcVT) &&
TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) { TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) {
SDValue Op = N0.getOperand(0); SDValue Op = N0.getOperand(0);
Op = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType()); Op = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType());
AddToWorklist(Op.getNode()); AddToWorklist(Op.getNode());
SDValue ZExtOrTrunc = DAG.getZExtOrTrunc(Op, SDLoc(N), VT); SDValue ZExtOrTrunc = DAG.getZExtOrTrunc(Op, SDLoc(N), VT);
// Transfer the debug info; the new node is equivalent to N0. // Transfer the debug info; the new node is equivalent to N0.
DAG.transferDbgValues(N0, ZExtOrTrunc); DAG.transferDbgValues(N0, ZExtOrTrunc);
▲ Show 20 Lines • Show All 9,930 Lines • Show Last 20 Lines

test/CodeGen/AArch64/arm64-aapcs.ll

Show All 23 Lines
@var64 = global i64 0, align 8 @var64 = global i64 0, align 8
; Check stack slots are 64-bit at all times. ; Check stack slots are 64-bit at all times.
define void @test_stack_slots([8 x i32], i1 %bool, i8 %char, i16 %short, define void @test_stack_slots([8 x i32], i1 %bool, i8 %char, i16 %short,
i32 %int, i64 %long) { i32 %int, i64 %long) {
%ext_bool = zext i1 %bool to i64 %ext_bool = zext i1 %bool to i64
store volatile i64 %ext_bool, i64* @var64, align 8 store volatile i64 %ext_bool, i64* @var64, align 8
; CHECK: ldrb w[[EXT:[0-9]+]], [sp]
; Part of last store. Blasted scheduler. ; Part of last store. Blasted scheduler.
; CHECK: ldr [[LONG:x[0-9]+]], [sp, #32] ; CHECK: ldr [[LONG:x[0-9]+]], [sp, #32]
; CHECK: ldrb w[[EXT:[0-9]+]], [sp]
; CHECK: and x[[EXTED:[0-9]+]], x[[EXT]], #0x1 ; CHECK: and x[[EXTED:[0-9]+]], x[[EXT]], #0x1
; CHECK: str x[[EXTED]], [{{x[0-9]+}}, :lo12:var64] ; CHECK: str x[[EXTED]], [{{x[0-9]+}}, :lo12:var64]
%ext_char = zext i8 %char to i64 %ext_char = zext i8 %char to i64
store volatile i64 %ext_char, i64* @var64, align 8 store volatile i64 %ext_char, i64* @var64, align 8
; CHECK: ldrb w[[EXT:[0-9]+]], [sp, #8] ; CHECK: ldrb w[[EXT:[0-9]+]], [sp, #8]
; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64] ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
Show All 14 Lines
} }
; Make sure the callee does extensions (in the absence of zext/sext ; Make sure the callee does extensions (in the absence of zext/sext
; keyword on args) while we're here. ; keyword on args) while we're here.
define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) { define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) {
%ext_bool = zext i1 %bool to i64 %ext_bool = zext i1 %bool to i64
store volatile i64 %ext_bool, i64* @var64 store volatile i64 %ext_bool, i64* @var64
; CHECK: and w[[EXT:[0-9]+]], w0, #0x1 ; CHECK: and [[EXT:x[0-9]+]], x0, #0x1
; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64] ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
%ext_char = sext i8 %char to i64 %ext_char = sext i8 %char to i64
store volatile i64 %ext_char, i64* @var64 store volatile i64 %ext_char, i64* @var64
; CHECK: sxtb [[EXT:x[0-9]+]], w1 ; CHECK: sxtb [[EXT:x[0-9]+]], w1
; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64] ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
%ext_short = zext i16 %short to i64 %ext_short = zext i16 %short to i64
store volatile i64 %ext_short, i64* @var64 store volatile i64 %ext_short, i64* @var64
; CHECK: and w[[EXT:[0-9]+]], w2, #0xffff ; CHECK: and [[EXT:x[0-9]+]], x2, #0xffff
; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64] ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
%ext_int = zext i32 %int to i64 %ext_int = zext i32 %int to i64
store volatile i64 %ext_int, i64* @var64 store volatile i64 %ext_int, i64* @var64
; CHECK: mov w[[EXT:[0-9]+]], w3 ; CHECK: mov w[[EXT:[0-9]+]], w3
; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64] ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
ret void ret void
} }
▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines

test/CodeGen/AArch64/arm64-arith.ll

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines; CHECK: ret
%d = shl i32 %c, 2 %d = shl i32 %c, 2
%e = add i32 %x, %d %e = add i32 %x, %d
ret i32 %e ret i32 %e
} }
define i64 @t14(i16 %a, i64 %x) nounwind ssp { define i64 @t14(i16 %a, i64 %x) nounwind ssp {
entry: entry:
; CHECK-LABEL: t14: ; CHECK-LABEL: t14:
; CHECK: and w8, w0, #0xffff ; CHECK: add x0, x1, w0, uxth #3
; CHECK: add x0, x1, w8, uxtw #3
; CHECK: ret ; CHECK: ret
%c = zext i16 %a to i64 %c = zext i16 %a to i64
%d = shl i64 %c, 3 %d = shl i64 %c, 3
%e = add i64 %x, %d %e = add i64 %x, %d
ret i64 %e ret i64 %e
} }
; rdar://9160598 ; rdar://9160598
▲ Show 20 Lines • Show All 136 Lines • Show Last 20 Lines

test/CodeGen/AArch64/bitfield.ll

Show All 25 Lines; CHECK-LABEL: test_extendb64:
store volatile i64 %sxt64, i64* @var64 store volatile i64 %sxt64, i64* @var64
; CHECK: sxtb {{x[0-9]+}}, {{w[0-9]+}} ; CHECK: sxtb {{x[0-9]+}}, {{w[0-9]+}}
; N.b. this doesn't actually produce a bitfield instruction at the ; N.b. this doesn't actually produce a bitfield instruction at the
; moment, but it's still a good test to have and the semantics are ; moment, but it's still a good test to have and the semantics are
; correct. ; correct.
%uxt64 = zext i8 %var to i64 %uxt64 = zext i8 %var to i64
store volatile i64 %uxt64, i64* @var64 store volatile i64 %uxt64, i64* @var64
; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xff ; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xff
ret void ret void
} }
define void @test_extendh32(i16 %var) { define void @test_extendh32(i16 %var) {
; CHECK-LABEL: test_extendh32: ; CHECK-LABEL: test_extendh32:
%sxt32 = sext i16 %var to i32 %sxt32 = sext i16 %var to i32
store volatile i32 %sxt32, i32* @var32 store volatile i32 %sxt32, i32* @var32
Show All 15 Lines; CHECK-LABEL: test_extendh64:
store volatile i64 %sxt64, i64* @var64 store volatile i64 %sxt64, i64* @var64
; CHECK: sxth {{x[0-9]+}}, {{w[0-9]+}} ; CHECK: sxth {{x[0-9]+}}, {{w[0-9]+}}
; N.b. this doesn't actually produce a bitfield instruction at the ; N.b. this doesn't actually produce a bitfield instruction at the
; moment, but it's still a good test to have and the semantics are ; moment, but it's still a good test to have and the semantics are
; correct. ; correct.
%uxt64 = zext i16 %var to i64 %uxt64 = zext i16 %var to i64
store volatile i64 %uxt64, i64* @var64 store volatile i64 %uxt64, i64* @var64
; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, #0xffff ; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xffff
ret void ret void
} }
define void @test_extendw(i32 %var) { define void @test_extendw(i32 %var) {
; CHECK-LABEL: test_extendw: ; CHECK-LABEL: test_extendw:
%sxt64 = sext i32 %var to i64 %sxt64 = sext i32 %var to i64
store volatile i64 %sxt64, i64* @var64 store volatile i64 %sxt64, i64* @var64
▲ Show 20 Lines • Show All 158 Lines • Show Last 20 Lines

test/CodeGen/NVPTX/param-load-store.ll

Show All 19 Lines
; All scalar parameters must be at least 32 bits in size. ; All scalar parameters must be at least 32 bits in size.
; i1 is loaded/stored as i8. ; i1 is loaded/stored as i8.
; CHECK: .func (.param .b32 func_retval0) ; CHECK: .func (.param .b32 func_retval0)
; CHECK-LABEL: test_i1( ; CHECK-LABEL: test_i1(
; CHECK-NEXT: .param .b32 test_i1_param_0 ; CHECK-NEXT: .param .b32 test_i1_param_0
; CHECK: ld.param.u8 [[A8:%rs[0-9]+]], [test_i1_param_0]; ; CHECK: ld.param.u8 [[A8:%rs[0-9]+]], [test_i1_param_0];
; CHECK: and.b16 [[A:%rs[0-9]+]], [[A8]], 1; ; CHECK: and.b16 [[A:%rs[0-9]+]], [[A8]], 1;
; CHECK: cvt.u32.u16 [[B:%r[0-9]+]], [[A]] ; CHECK: setp.eq.b16 %p1, [[A]], 1
RKSimonUnsubmitted
Not Done
ReplyInline Actions

This looks like the only regression - I think cvt.u32.u16 effectively acts as "ZERO_EXTEND_INREG" in this case (which we don't have).

@jholewinski any thoughts?

RKSimon: This looks like the only regression - I think cvt.u32.u16 effectively acts as…
craig.topperAuthorUnsubmitted
Not Done
ReplyInline Actions

Looks like we are able to do fold (zext (and/or/xor (zextload x), cst)) -> (and/or/xor (zextload x), (zext cst)) when the load has multiple uses, but we can't do (zext (zextload x)) -> (zextload x) when there is an additional use.

craig.topper: Looks like we are able to do fold (zext (and/or/xor (zextload x), cst)) -> (and/or/xor…
; CHECK: cvt.u32.u16 [[B:%r[0-9]+]], [[A8]]
; CHECK: and.b32 [[C:%r[0-9]+]], [[B]], 1;
; CHECK: .param .b32 param0; ; CHECK: .param .b32 param0;
; CHECK: st.param.b32 [param0+0], [[B]] ; CHECK: st.param.b32 [param0+0], [[C]]
; CHECK: .param .b32 retval0; ; CHECK: .param .b32 retval0;
; CHECK: call.uni ; CHECK: call.uni
; CHECK-NEXT: test_i1, ; CHECK-NEXT: test_i1,
; CHECK: ld.param.b32 [[R8:%r[0-9]+]], [retval0+0]; ; CHECK: ld.param.b32 [[R8:%r[0-9]+]], [retval0+0];
; CHECK: and.b32 [[R:%r[0-9]+]], [[R8]], 1; ; CHECK: and.b32 [[R:%r[0-9]+]], [[R8]], 1;
; CHECK: st.param.b32 [func_retval0+0], [[R]]; ; CHECK: st.param.b32 [func_retval0+0], [[R]];
; CHECK: ret; ; CHECK: ret;
define i1 @test_i1(i1 %a) { define i1 @test_i1(i1 %a) {
▲ Show 20 Lines • Show All 902 Lines • Show Last 20 Lines

test/CodeGen/PowerPC/vec_extract_p9_2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE
define zeroext i8 @test_add1(<16 x i8> %a, i32 signext %index, i8 zeroext %c) { define zeroext i8 @test_add1(<16 x i8> %a, i32 signext %index, i8 zeroext %c) {
; CHECK-LE-LABEL: test_add1: ; CHECK-LE-LABEL: test_add1:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: vextubrx 3, 5, 2 ; CHECK-LE-NEXT: vextubrx 3, 5, 2
; CHECK-LE-NEXT: add 3, 3, 6 ; CHECK-LE-NEXT: add 3, 3, 6
; CHECK-LE-NEXT: rlwinm 3, 3, 0, 24, 31 ; CHECK-LE-NEXT: clrldi 3, 3, 56
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; CHECK-BE-LABEL: test_add1: ; CHECK-BE-LABEL: test_add1:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vextublx 3, 5, 2 ; CHECK-BE-NEXT: vextublx 3, 5, 2
; CHECK-BE-NEXT: add 3, 3, 6 ; CHECK-BE-NEXT: add 3, 3, 6
; CHECK-BE-NEXT: rlwinm 3, 3, 0, 24, 31 ; CHECK-BE-NEXT: clrldi 3, 3, 56
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <16 x i8> %a, i32 %index %vecext = extractelement <16 x i8> %a, i32 %index
%conv = zext i8 %vecext to i32 %conv = zext i8 %vecext to i32
%conv1 = zext i8 %c to i32 %conv1 = zext i8 %c to i32
%add = add nuw nsw i32 %conv, %conv1 %add = add nuw nsw i32 %conv, %conv1
%conv2 = trunc i32 %add to i8 %conv2 = trunc i32 %add to i8
ret i8 %conv2 ret i8 %conv2
Show All 22 Lines
} }
define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c) { define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c) {
; CHECK-LE-LABEL: test_add3: ; CHECK-LE-LABEL: test_add3:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30
; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2
; CHECK-LE-NEXT: add 3, 3, 6 ; CHECK-LE-NEXT: add 3, 3, 6
; CHECK-LE-NEXT: rlwinm 3, 3, 0, 16, 31 ; CHECK-LE-NEXT: clrldi 3, 3, 48
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; CHECK-BE-LABEL: test_add3: ; CHECK-BE-LABEL: test_add3:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30
; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2
; CHECK-BE-NEXT: add 3, 3, 6 ; CHECK-BE-NEXT: add 3, 3, 6
; CHECK-BE-NEXT: rlwinm 3, 3, 0, 16, 31 ; CHECK-BE-NEXT: clrldi 3, 3, 48
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <8 x i16> %a, i32 %index %vecext = extractelement <8 x i16> %a, i32 %index
%conv = zext i16 %vecext to i32 %conv = zext i16 %vecext to i32
%conv1 = zext i16 %c to i32 %conv1 = zext i16 %c to i32
%add = add nuw nsw i32 %conv, %conv1 %add = add nuw nsw i32 %conv, %conv1
%conv2 = trunc i32 %add to i16 %conv2 = trunc i32 %add to i16
ret i16 %conv2 ret i16 %conv2
▲ Show 20 Lines • Show All 178 Lines • Show Last 20 Lines

test/CodeGen/SystemZ/insert-05.ll

Show First 20 Lines • Show All 208 Lines • ▼ Show 20 Lines; CHECK: br %r14
%ext = zext i32 %mul to i64 %ext = zext i32 %mul to i64
%or = or i64 4294967296, %ext %or = or i64 4294967296, %ext
ret i64 %or ret i64 %or
} }
; The truncation here isn't free; we need an explicit zero extension. ; The truncation here isn't free; we need an explicit zero extension.
define i64 @f19(i32 %a) { define i64 @f19(i32 %a) {
; CHECK-LABEL: f19: ; CHECK-LABEL: f19:
; CHECK: llcr %r2, %r2 ; CHECK: llgcr %r2, %r2
; CHECK: iihf %r2, 1 ; CHECK: oihl %r2, 1
; CHECK: br %r14 ; CHECK: br %r14
%trunc = trunc i32 %a to i8 %trunc = trunc i32 %a to i8
%ext = zext i8 %trunc to i64 %ext = zext i8 %trunc to i64
%or = or i64 %ext, 4294967296 %or = or i64 %ext, 4294967296
ret i64 %or ret i64 %or
} }

test/CodeGen/X86/3addr-or.ll

Show All 14 Lines
} }
; This test no longer requires or to be converted to 3 addr form because we are ; This test no longer requires or to be converted to 3 addr form because we are
; are able to use a zero extend instead of an 'and' which gives the register ; are able to use a zero extend instead of an 'and' which gives the register
; allocator freedom. ; allocator freedom.
define i64 @test2(i8 %A, i8 %B) nounwind { define i64 @test2(i8 %A, i8 %B) nounwind {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NEXT: shll $4, %edi ; CHECK-NEXT: shll $4, %edi
; CHECK-NEXT: andl $48, %edi ; CHECK-NEXT: andl $48, %edi
; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: movzbl %sil, %eax
; CHECK-NEXT: shrq $4, %rax ; CHECK-NEXT: shrq $4, %rax
; CHECK-NEXT: orq %rdi, %rax ; CHECK-NEXT: orq %rdi, %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%C = zext i8 %A to i64 %C = zext i8 %A to i64
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

test/CodeGen/X86/avx512cd-intrinsics-upgrade.ll

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%res = call <16 x i32> @llvm.x86.avx512.broadcastmw.512(i16 %a0) %res = call <16 x i32> @llvm.x86.avx512.broadcastmw.512(i16 %a0)
ret <16 x i32> %res ret <16 x i32> %res
} }
declare <16 x i32> @llvm.x86.avx512.broadcastmw.512(i16) declare <16 x i32> @llvm.x86.avx512.broadcastmw.512(i16)
define <8 x i64> @test_x86_broadcastmb_512(i8 %a0) { define <8 x i64> @test_x86_broadcastmb_512(i8 %a0) {
; CHECK-LABEL: test_x86_broadcastmb_512: ; CHECK-LABEL: test_x86_broadcastmb_512:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: ## kill: def $edi killed $edi def $rdi
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: vpbroadcastq %rax, %zmm0 ; CHECK-NEXT: vpbroadcastq %rax, %zmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <8 x i64> @llvm.x86.avx512.broadcastmb.512(i8 %a0) %res = call <8 x i64> @llvm.x86.avx512.broadcastmb.512(i8 %a0)
ret <8 x i64> %res ret <8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.broadcastmb.512(i8) declare <8 x i64> @llvm.x86.avx512.broadcastmb.512(i8)

test/CodeGen/X86/avx512cdvl-intrinsics-upgrade.ll

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%res = call <4 x i32> @llvm.x86.avx512.broadcastmw.128(i16 %a0) ; %res = call <4 x i32> @llvm.x86.avx512.broadcastmw.128(i16 %a0) ;
ret <4 x i32> %res ret <4 x i32> %res
} }
declare <4 x i32> @llvm.x86.avx512.broadcastmw.128(i16) declare <4 x i32> @llvm.x86.avx512.broadcastmw.128(i16)
define <4 x i64> @test_x86_broadcastmb_256(i8 %a0) { define <4 x i64> @test_x86_broadcastmb_256(i8 %a0) {
; CHECK-LABEL: test_x86_broadcastmb_256: ; CHECK-LABEL: test_x86_broadcastmb_256:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: ## kill: def $edi killed $edi def $rdi
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: vpbroadcastq %rax, %ymm0 ; CHECK-NEXT: vpbroadcastq %rax, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <4 x i64> @llvm.x86.avx512.broadcastmb.256(i8 %a0) ; %res = call <4 x i64> @llvm.x86.avx512.broadcastmb.256(i8 %a0) ;
ret <4 x i64> %res ret <4 x i64> %res
} }
declare <4 x i64> @llvm.x86.avx512.broadcastmb.256(i8) declare <4 x i64> @llvm.x86.avx512.broadcastmb.256(i8)
define <2 x i64> @test_x86_broadcastmb_128(i8 %a0) { define <2 x i64> @test_x86_broadcastmb_128(i8 %a0) {
; CHECK-LABEL: test_x86_broadcastmb_128: ; CHECK-LABEL: test_x86_broadcastmb_128:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: ## kill: def $edi killed $edi def $rdi
; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: vpbroadcastq %rax, %xmm0 ; CHECK-NEXT: vpbroadcastq %rax, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call <2 x i64> @llvm.x86.avx512.broadcastmb.128(i8 %a0) ; %res = call <2 x i64> @llvm.x86.avx512.broadcastmb.128(i8 %a0) ;
ret <2 x i64> %res ret <2 x i64> %res
} }
declare <2 x i64> @llvm.x86.avx512.broadcastmb.128(i8) declare <2 x i64> @llvm.x86.avx512.broadcastmb.128(i8)

test/CodeGen/X86/avx512vl-vec-masked-cmp.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,205 Lines • ▼ Show 20 Lines
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v4i1_mask: ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v4i1_mask:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%1 = bitcast <2 x i64> %__b to <2 x i64> %1 = bitcast <2 x i64> %__b to <2 x i64>
%2 = icmp eq <2 x i64> %0, %1 %2 = icmp eq <2 x i64> %0, %1
%3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%4 = bitcast <4 x i1> %3 to i4 %4 = bitcast <4 x i1> %3 to i4
Show All 10 Lines
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v4i1_mask_mem: ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v4i1_mask_mem:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vmovdqa (%rdi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rdi), %xmm1
; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load <2 x i64>, <2 x i64>* %__b %load = load <2 x i64>, <2 x i64>* %__b
%1 = bitcast <2 x i64> %load to <2 x i64> %1 = bitcast <2 x i64> %load to <2 x i64>
%2 = icmp eq <2 x i64> %0, %1 %2 = icmp eq <2 x i64> %0, %1
%3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
Show All 13 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%1 = bitcast <2 x i64> %__b to <2 x i64> %1 = bitcast <2 x i64> %__b to <2 x i64>
%2 = icmp eq <2 x i64> %0, %1 %2 = icmp eq <2 x i64> %0, %1
%3 = bitcast i8 %__u to <8 x i1> %3 = bitcast i8 %__u to <8 x i1>
%extract.i = shufflevector <8 x i1> %3, <8 x i1> undef, <2 x i32> <i32 0, i32 1> %extract.i = shufflevector <8 x i1> %3, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
Show All 15 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vmovdqa (%rsi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rsi), %xmm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load <2 x i64>, <2 x i64>* %__b %load = load <2 x i64>, <2 x i64>* %__b
%1 = bitcast <2 x i64> %load to <2 x i64> %1 = bitcast <2 x i64> %load to <2 x i64>
%2 = icmp eq <2 x i64> %0, %1 %2 = icmp eq <2 x i64> %0, %1
%3 = bitcast i8 %__u to <8 x i1> %3 = bitcast i8 %__u to <8 x i1>
Show All 15 Lines
; NoVLX-LABEL: test_vpcmpeqq_v2i1_v4i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpeqq_v2i1_v4i1_mask_mem_b:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1
; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load i64, i64* %__b %load = load i64, i64* %__b
%vec = insertelement <2 x i64> undef, i64 %load, i32 0 %vec = insertelement <2 x i64> undef, i64 %load, i32 0
%1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = icmp eq <2 x i64> %0, %1 %2 = icmp eq <2 x i64> %0, %1
Show All 14 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpeqq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load i64, i64* %__b %load = load i64, i64* %__b
%vec = insertelement <2 x i64> undef, i64 %load, i32 0 %vec = insertelement <2 x i64> undef, i64 %load, i32 0
%1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = icmp eq <2 x i64> %0, %1 %2 = icmp eq <2 x i64> %0, %1
▲ Show 20 Lines • Show All 5,218 Lines • ▼ Show 20 Lines
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v4i1_mask: ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v4i1_mask:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%1 = bitcast <2 x i64> %__b to <2 x i64> %1 = bitcast <2 x i64> %__b to <2 x i64>
%2 = icmp sgt <2 x i64> %0, %1 %2 = icmp sgt <2 x i64> %0, %1
%3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%4 = bitcast <4 x i1> %3 to i4 %4 = bitcast <4 x i1> %3 to i4
Show All 10 Lines
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v4i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v4i1_mask_mem:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vmovdqa (%rdi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load <2 x i64>, <2 x i64>* %__b %load = load <2 x i64>, <2 x i64>* %__b
%1 = bitcast <2 x i64> %load to <2 x i64> %1 = bitcast <2 x i64> %load to <2 x i64>
%2 = icmp sgt <2 x i64> %0, %1 %2 = icmp sgt <2 x i64> %0, %1
%3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
Show All 13 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%1 = bitcast <2 x i64> %__b to <2 x i64> %1 = bitcast <2 x i64> %__b to <2 x i64>
%2 = icmp sgt <2 x i64> %0, %1 %2 = icmp sgt <2 x i64> %0, %1
%3 = bitcast i8 %__u to <8 x i1> %3 = bitcast i8 %__u to <8 x i1>
%extract.i = shufflevector <8 x i1> %3, <8 x i1> undef, <2 x i32> <i32 0, i32 1> %extract.i = shufflevector <8 x i1> %3, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
Show All 15 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vmovdqa (%rsi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rsi), %xmm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load <2 x i64>, <2 x i64>* %__b %load = load <2 x i64>, <2 x i64>* %__b
%1 = bitcast <2 x i64> %load to <2 x i64> %1 = bitcast <2 x i64> %load to <2 x i64>
%2 = icmp sgt <2 x i64> %0, %1 %2 = icmp sgt <2 x i64> %0, %1
%3 = bitcast i8 %__u to <8 x i1> %3 = bitcast i8 %__u to <8 x i1>
Show All 15 Lines
; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v4i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgtq_v2i1_v4i1_mask_mem_b:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1
; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load i64, i64* %__b %load = load i64, i64* %__b
%vec = insertelement <2 x i64> undef, i64 %load, i32 0 %vec = insertelement <2 x i64> undef, i64 %load, i32 0
%1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = icmp sgt <2 x i64> %0, %1 %2 = icmp sgt <2 x i64> %0, %1
Show All 14 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpgtq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load i64, i64* %__b %load = load i64, i64* %__b
%vec = insertelement <2 x i64> undef, i64 %load, i32 0 %vec = insertelement <2 x i64> undef, i64 %load, i32 0
%1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = icmp sgt <2 x i64> %0, %1 %2 = icmp sgt <2 x i64> %0, %1
▲ Show 20 Lines • Show All 5,322 Lines • ▼ Show 20 Lines
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v4i1_mask: ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v4i1_mask:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%1 = bitcast <2 x i64> %__b to <2 x i64> %1 = bitcast <2 x i64> %__b to <2 x i64>
%2 = icmp sge <2 x i64> %0, %1 %2 = icmp sge <2 x i64> %0, %1
%3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%4 = bitcast <4 x i1> %3 to i4 %4 = bitcast <4 x i1> %3 to i4
Show All 10 Lines
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v4i1_mask_mem: ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v4i1_mask_mem:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vmovdqa (%rdi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rdi), %xmm1
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load <2 x i64>, <2 x i64>* %__b %load = load <2 x i64>, <2 x i64>* %__b
%1 = bitcast <2 x i64> %load to <2 x i64> %1 = bitcast <2 x i64> %load to <2 x i64>
%2 = icmp sge <2 x i64> %0, %1 %2 = icmp sge <2 x i64> %0, %1
%3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
Show All 13 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%1 = bitcast <2 x i64> %__b to <2 x i64> %1 = bitcast <2 x i64> %__b to <2 x i64>
%2 = icmp sge <2 x i64> %0, %1 %2 = icmp sge <2 x i64> %0, %1
%3 = bitcast i8 %__u to <8 x i1> %3 = bitcast i8 %__u to <8 x i1>
%extract.i = shufflevector <8 x i1> %3, <8 x i1> undef, <2 x i32> <i32 0, i32 1> %extract.i = shufflevector <8 x i1> %3, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
Show All 15 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vmovdqa (%rsi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rsi), %xmm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load <2 x i64>, <2 x i64>* %__b %load = load <2 x i64>, <2 x i64>* %__b
%1 = bitcast <2 x i64> %load to <2 x i64> %1 = bitcast <2 x i64> %load to <2 x i64>
%2 = icmp sge <2 x i64> %0, %1 %2 = icmp sge <2 x i64> %0, %1
%3 = bitcast i8 %__u to <8 x i1> %3 = bitcast i8 %__u to <8 x i1>
Show All 15 Lines
; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v4i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpsgeq_v2i1_v4i1_mask_mem_b:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load i64, i64* %__b %load = load i64, i64* %__b
%vec = insertelement <2 x i64> undef, i64 %load, i32 0 %vec = insertelement <2 x i64> undef, i64 %load, i32 0
%1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = icmp sge <2 x i64> %0, %1 %2 = icmp sge <2 x i64> %0, %1
Show All 14 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1} ; NoVLX-NEXT: vpcmpleq %zmm0, %zmm1, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load i64, i64* %__b %load = load i64, i64* %__b
%vec = insertelement <2 x i64> undef, i64 %load, i32 0 %vec = insertelement <2 x i64> undef, i64 %load, i32 0
%1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = icmp sge <2 x i64> %0, %1 %2 = icmp sge <2 x i64> %0, %1
▲ Show 20 Lines • Show All 5,342 Lines • ▼ Show 20 Lines
; NoVLX-LABEL: test_vpcmpultq_v2i1_v4i1_mask: ; NoVLX-LABEL: test_vpcmpultq_v2i1_v4i1_mask:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%1 = bitcast <2 x i64> %__b to <2 x i64> %1 = bitcast <2 x i64> %__b to <2 x i64>
%2 = icmp ult <2 x i64> %0, %1 %2 = icmp ult <2 x i64> %0, %1
%3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%4 = bitcast <4 x i1> %3 to i4 %4 = bitcast <4 x i1> %3 to i4
Show All 10 Lines
; NoVLX-LABEL: test_vpcmpultq_v2i1_v4i1_mask_mem: ; NoVLX-LABEL: test_vpcmpultq_v2i1_v4i1_mask_mem:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vmovdqa (%rdi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rdi), %xmm1
; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load <2 x i64>, <2 x i64>* %__b %load = load <2 x i64>, <2 x i64>* %__b
%1 = bitcast <2 x i64> %load to <2 x i64> %1 = bitcast <2 x i64> %load to <2 x i64>
%2 = icmp ult <2 x i64> %0, %1 %2 = icmp ult <2 x i64> %0, %1
%3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
Show All 13 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%1 = bitcast <2 x i64> %__b to <2 x i64> %1 = bitcast <2 x i64> %__b to <2 x i64>
%2 = icmp ult <2 x i64> %0, %1 %2 = icmp ult <2 x i64> %0, %1
%3 = bitcast i8 %__u to <8 x i1> %3 = bitcast i8 %__u to <8 x i1>
%extract.i = shufflevector <8 x i1> %3, <8 x i1> undef, <2 x i32> <i32 0, i32 1> %extract.i = shufflevector <8 x i1> %3, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
Show All 15 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vmovdqa (%rsi), %xmm1 ; NoVLX-NEXT: vmovdqa (%rsi), %xmm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load <2 x i64>, <2 x i64>* %__b %load = load <2 x i64>, <2 x i64>* %__b
%1 = bitcast <2 x i64> %load to <2 x i64> %1 = bitcast <2 x i64> %load to <2 x i64>
%2 = icmp ult <2 x i64> %0, %1 %2 = icmp ult <2 x i64> %0, %1
%3 = bitcast i8 %__u to <8 x i1> %3 = bitcast i8 %__u to <8 x i1>
Show All 15 Lines
; NoVLX-LABEL: test_vpcmpultq_v2i1_v4i1_mask_mem_b: ; NoVLX-LABEL: test_vpcmpultq_v2i1_v4i1_mask_mem_b:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rdi), %xmm1
; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load i64, i64* %__b %load = load i64, i64* %__b
%vec = insertelement <2 x i64> undef, i64 %load, i32 0 %vec = insertelement <2 x i64> undef, i64 %load, i32 0
%1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = icmp ult <2 x i64> %0, %1 %2 = icmp ult <2 x i64> %0, %1
Show All 14 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1 ; NoVLX-NEXT: vpbroadcastq (%rsi), %xmm1
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vpcmpltuq %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x i64> %0 = bitcast <2 x i64> %__a to <2 x i64>
%load = load i64, i64* %__b %load = load i64, i64* %__b
%vec = insertelement <2 x i64> undef, i64 %load, i32 0 %vec = insertelement <2 x i64> undef, i64 %load, i32 0
%1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %vec, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = icmp ult <2 x i64> %0, %1 %2 = icmp ult <2 x i64> %0, %1
▲ Show 20 Lines • Show All 3,742 Lines • ▼ Show 20 Lines
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v4i1_mask: ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v4i1_mask:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x double> %0 = bitcast <2 x i64> %__a to <2 x double>
%1 = bitcast <2 x i64> %__b to <2 x double> %1 = bitcast <2 x i64> %__b to <2 x double>
%2 = fcmp oeq <2 x double> %0, %1 %2 = fcmp oeq <2 x double> %0, %1
%3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%4 = bitcast <4 x i1> %3 to i4 %4 = bitcast <4 x i1> %3 to i4
Show All 10 Lines
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v4i1_mask_mem: ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v4i1_mask_mem:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vmovapd (%rdi), %xmm1 ; NoVLX-NEXT: vmovapd (%rdi), %xmm1
; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x double> %0 = bitcast <2 x i64> %__a to <2 x double>
%load = load <2 x i64>, <2 x i64>* %__b %load = load <2 x i64>, <2 x i64>* %__b
%1 = bitcast <2 x i64> %load to <2 x double> %1 = bitcast <2 x i64> %load to <2 x double>
%2 = fcmp oeq <2 x double> %0, %1 %2 = fcmp oeq <2 x double> %0, %1
%3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %3 = shufflevector <2 x i1> %2, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
Show All 11 Lines
; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v4i1_mask_mem_b: ; NoVLX-LABEL: test_vcmpoeqpd_v2i1_v4i1_mask_mem_b:
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] ; NoVLX-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0]
; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 ; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x double> %0 = bitcast <2 x i64> %__a to <2 x double>
%load = load double, double* %__b %load = load double, double* %__b
%vec = insertelement <2 x double> undef, double %load, i32 0 %vec = insertelement <2 x double> undef, double %load, i32 0
%1 = shufflevector <2 x double> %vec, <2 x double> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x double> %vec, <2 x double> undef, <2 x i32> <i32 0, i32 0>
%2 = fcmp oeq <2 x double> %0, %1 %2 = fcmp oeq <2 x double> %0, %1
Show All 14 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x double> %0 = bitcast <2 x i64> %__a to <2 x double>
%1 = bitcast <2 x i64> %__b to <2 x double> %1 = bitcast <2 x i64> %__b to <2 x double>
%2 = fcmp oeq <2 x double> %0, %1 %2 = fcmp oeq <2 x double> %0, %1
%3 = bitcast i2 %__u to <2 x i1> %3 = bitcast i2 %__u to <2 x i1>
%4 = and <2 x i1> %2, %3 %4 = and <2 x i1> %2, %3
Show All 14 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vmovapd (%rsi), %xmm1 ; NoVLX-NEXT: vmovapd (%rsi), %xmm1
; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x double> %0 = bitcast <2 x i64> %__a to <2 x double>
%load = load <2 x i64>, <2 x i64>* %__b %load = load <2 x i64>, <2 x i64>* %__b
%1 = bitcast <2 x i64> %load to <2 x double> %1 = bitcast <2 x i64> %load to <2 x double>
%2 = fcmp oeq <2 x double> %0, %1 %2 = fcmp oeq <2 x double> %0, %1
%3 = bitcast i2 %__u to <2 x i1> %3 = bitcast i2 %__u to <2 x i1>
Show All 15 Lines
; NoVLX: # %bb.0: # %entry ; NoVLX: # %bb.0: # %entry
; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
; NoVLX-NEXT: kmovw %edi, %k1 ; NoVLX-NEXT: kmovw %edi, %k1
; NoVLX-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] ; NoVLX-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0]
; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1} ; NoVLX-NEXT: vcmpeqpd %zmm1, %zmm0, %k0 {%k1}
; NoVLX-NEXT: kshiftlw $14, %k0, %k0 ; NoVLX-NEXT: kshiftlw $14, %k0, %k0
; NoVLX-NEXT: kshiftrw $14, %k0, %k0 ; NoVLX-NEXT: kshiftrw $14, %k0, %k0
; NoVLX-NEXT: kmovw %k0, %eax ; NoVLX-NEXT: kmovw %k0, %eax
; NoVLX-NEXT: andb $3, %al ; NoVLX-NEXT: andl $3, %eax
; NoVLX-NEXT: movzbl %al, %eax
; NoVLX-NEXT: vzeroupper ; NoVLX-NEXT: vzeroupper
; NoVLX-NEXT: retq ; NoVLX-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__a to <2 x double> %0 = bitcast <2 x i64> %__a to <2 x double>
%load = load double, double* %__b %load = load double, double* %__b
%vec = insertelement <2 x double> undef, double %load, i32 0 %vec = insertelement <2 x double> undef, double %load, i32 0
%1 = shufflevector <2 x double> %vec, <2 x double> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x double> %vec, <2 x double> undef, <2 x i32> <i32 0, i32 0>
%2 = fcmp oeq <2 x double> %0, %1 %2 = fcmp oeq <2 x double> %0, %1
▲ Show 20 Lines • Show All 2,209 Lines • Show Last 20 Lines

test/CodeGen/X86/memset-nonzero.ll

Show First 20 Lines • Show All 189 Lines • ▼ Show 20 Lines
declare i8* @__memset_chk(i8*, i32, i64, i64) declare i8* @__memset_chk(i8*, i32, i64, i64)
; Repeat with a non-constant value for the stores. ; Repeat with a non-constant value for the stores.
define void @memset_16_nonconst_bytes(i8* %x, i8 %c) { define void @memset_16_nonconst_bytes(i8* %x, i8 %c) {
; SSE-LABEL: memset_16_nonconst_bytes: ; SSE-LABEL: memset_16_nonconst_bytes:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: # kill: def $esi killed $esi def $rsi
; SSE-NEXT: movzbl %sil, %eax ; SSE-NEXT: movzbl %sil, %eax
; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101 ; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101
; SSE-NEXT: imulq %rax, %rcx ; SSE-NEXT: imulq %rax, %rcx
; SSE-NEXT: movq %rcx, 8(%rdi) ; SSE-NEXT: movq %rcx, 8(%rdi)
; SSE-NEXT: movq %rcx, (%rdi) ; SSE-NEXT: movq %rcx, (%rdi)
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; SSE2FAST-LABEL: memset_16_nonconst_bytes: ; SSE2FAST-LABEL: memset_16_nonconst_bytes:
Show All 21 Lines
; AVX2-NEXT: retq ; AVX2-NEXT: retq
tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 16, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 16, i1 false)
ret void ret void
} }
define void @memset_32_nonconst_bytes(i8* %x, i8 %c) { define void @memset_32_nonconst_bytes(i8* %x, i8 %c) {
; SSE-LABEL: memset_32_nonconst_bytes: ; SSE-LABEL: memset_32_nonconst_bytes:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: # kill: def $esi killed $esi def $rsi
; SSE-NEXT: movzbl %sil, %eax ; SSE-NEXT: movzbl %sil, %eax
; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101 ; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101
; SSE-NEXT: imulq %rax, %rcx ; SSE-NEXT: imulq %rax, %rcx
; SSE-NEXT: movq %rcx, 24(%rdi) ; SSE-NEXT: movq %rcx, 24(%rdi)
; SSE-NEXT: movq %rcx, 16(%rdi) ; SSE-NEXT: movq %rcx, 16(%rdi)
; SSE-NEXT: movq %rcx, 8(%rdi) ; SSE-NEXT: movq %rcx, 8(%rdi)
; SSE-NEXT: movq %rcx, (%rdi) ; SSE-NEXT: movq %rcx, (%rdi)
; SSE-NEXT: retq ; SSE-NEXT: retq
Show All 27 Lines
; AVX2-NEXT: retq ; AVX2-NEXT: retq
tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 32, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 32, i1 false)
ret void ret void
} }
define void @memset_64_nonconst_bytes(i8* %x, i8 %c) { define void @memset_64_nonconst_bytes(i8* %x, i8 %c) {
; SSE-LABEL: memset_64_nonconst_bytes: ; SSE-LABEL: memset_64_nonconst_bytes:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: # kill: def $esi killed $esi def $rsi
; SSE-NEXT: movzbl %sil, %eax ; SSE-NEXT: movzbl %sil, %eax
; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101 ; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101
; SSE-NEXT: imulq %rax, %rcx ; SSE-NEXT: imulq %rax, %rcx
; SSE-NEXT: movq %rcx, 56(%rdi) ; SSE-NEXT: movq %rcx, 56(%rdi)
; SSE-NEXT: movq %rcx, 48(%rdi) ; SSE-NEXT: movq %rcx, 48(%rdi)
; SSE-NEXT: movq %rcx, 40(%rdi) ; SSE-NEXT: movq %rcx, 40(%rdi)
; SSE-NEXT: movq %rcx, 32(%rdi) ; SSE-NEXT: movq %rcx, 32(%rdi)
; SSE-NEXT: movq %rcx, 24(%rdi) ; SSE-NEXT: movq %rcx, 24(%rdi)
Show All 35 Lines
; AVX2-NEXT: retq ; AVX2-NEXT: retq
tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 64, i1 false) tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 64, i1 false)
ret void ret void
} }
define void @memset_128_nonconst_bytes(i8* %x, i8 %c) { define void @memset_128_nonconst_bytes(i8* %x, i8 %c) {
; SSE-LABEL: memset_128_nonconst_bytes: ; SSE-LABEL: memset_128_nonconst_bytes:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: # kill: def $esi killed $esi def $rsi
; SSE-NEXT: movzbl %sil, %eax ; SSE-NEXT: movzbl %sil, %eax
; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101 ; SSE-NEXT: movabsq $72340172838076673, %rcx # imm = 0x101010101010101
; SSE-NEXT: imulq %rax, %rcx ; SSE-NEXT: imulq %rax, %rcx
; SSE-NEXT: movq %rcx, 120(%rdi) ; SSE-NEXT: movq %rcx, 120(%rdi)
; SSE-NEXT: movq %rcx, 112(%rdi) ; SSE-NEXT: movq %rcx, 112(%rdi)
; SSE-NEXT: movq %rcx, 104(%rdi) ; SSE-NEXT: movq %rcx, 104(%rdi)
; SSE-NEXT: movq %rcx, 96(%rdi) ; SSE-NEXT: movq %rcx, 96(%rdi)
; SSE-NEXT: movq %rcx, 88(%rdi) ; SSE-NEXT: movq %rcx, 88(%rdi)
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

test/CodeGen/X86/pr27591.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -o - -O0 < %s | FileCheck %s ; RUN: llc -o - -O0 < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define void @test1(i32 %x) #0 { define void @test1(i32 %x) #0 {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: cmpl $0, %edi ; CHECK-NEXT: cmpl $0, %edi
; CHECK-NEXT: setne %al ; CHECK-NEXT: setne %al
; CHECK-NEXT: andb $1, %al
; CHECK-NEXT: movzbl %al, %edi ; CHECK-NEXT: movzbl %al, %edi
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: callq callee1 ; CHECK-NEXT: callq callee1
; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%tobool = icmp ne i32 %x, 0 %tobool = icmp ne i32 %x, 0
call void @callee1(i1 zeroext %tobool) call void @callee1(i1 zeroext %tobool)
ret void ret void
} }
Show All 23 Lines

test/CodeGen/X86/pr35763.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-linux-gnu %s -o - | FileCheck %s ; RUN: llc -mtriple=x86_64-linux-gnu %s -o - | FileCheck %s
%struct.S = type <{ i16, i24, [5 x i8], i8, i16, [2 x i8] }> %struct.S = type <{ i16, i24, [5 x i8], i8, i16, [2 x i8] }>
@z = global { i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, [5 x i8] } { i16 -724, i8 94, i8 -18, i8 5, i8 undef, i8 96, i8 104, i8 -24, i8 10, i8 0, [5 x i8] undef }, align 8 @z = global { i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, [5 x i8] } { i16 -724, i8 94, i8 -18, i8 5, i8 undef, i8 96, i8 104, i8 -24, i8 10, i8 0, [5 x i8] undef }, align 8
@tf_3_var_136 = global i64 0, align 8 @tf_3_var_136 = global i64 0, align 8
@.str = private unnamed_addr constant [6 x i8] c"%llu\0A\00", align 1 @.str = private unnamed_addr constant [6 x i8] c"%llu\0A\00", align 1
define void @PR35763() { define void @PR35763() {
; CHECK-LABEL: PR35763: ; CHECK-LABEL: PR35763:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movzwl {{.*}}(%rip), %eax ; CHECK-NEXT: movl {{.*}}(%rip), %eax
; CHECK-NEXT: movzwl z+{{.*}}(%rip), %ecx ; CHECK-NEXT: orl z+{{.*}}(%rip), %eax
; CHECK-NEXT: orl %eax, %ecx ; CHECK-NEXT: movzwl %ax, %eax
; CHECK-NEXT: movq %rcx, {{.*}}(%rip) ; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: movl z+{{.*}}(%rip), %eax ; CHECK-NEXT: movl z+{{.*}}(%rip), %eax
; CHECK-NEXT: movzbl z+{{.*}}(%rip), %ecx ; CHECK-NEXT: movzbl z+{{.*}}(%rip), %ecx
; CHECK-NEXT: shlq $32, %rcx ; CHECK-NEXT: shlq $32, %rcx
; CHECK-NEXT: orq %rax, %rcx ; CHECK-NEXT: orq %rax, %rcx
; CHECK-NEXT: movabsq $1090921758719, %rax # imm = 0xFE0000FFFF ; CHECK-NEXT: movabsq $1090921758719, %rax # imm = 0xFE0000FFFF
; CHECK-NEXT: andq %rcx, %rax ; CHECK-NEXT: andq %rcx, %rax
; CHECK-NEXT: movl %eax, z+{{.*}}(%rip) ; CHECK-NEXT: movl %eax, z+{{.*}}(%rip)
; CHECK-NEXT: shrq $32, %rax ; CHECK-NEXT: shrq $32, %rax
Show All 18 Lines

test/CodeGen/X86/sext-i1.ll

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines; X64-NEXT: retq
ret i32 %sext ret i32 %sext
} }
; sext (xor Bool, -1) --> sub (zext Bool), 1 ; sext (xor Bool, -1) --> sub (zext Bool), 1
define i32 @select_0_or_1s_signext(i1 signext %cond) { define i32 @select_0_or_1s_signext(i1 signext %cond) {
; X32-LABEL: select_0_or_1s_signext: ; X32-LABEL: select_0_or_1s_signext:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: andb $1, %al ; X32-NEXT: andl $1, %eax
; X32-NEXT: movzbl %al, %eax
; X32-NEXT: decl %eax ; X32-NEXT: decl %eax
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: select_0_or_1s_signext: ; X64-LABEL: select_0_or_1s_signext:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: notl %edi ; X64-NEXT: notl %edi
; X64-NEXT: movl %edi, %eax ; X64-NEXT: movl %edi, %eax
; X64-NEXT: retq ; X64-NEXT: retq
%not = xor i1 %cond, 1 %not = xor i1 %cond, 1
%sext = sext i1 %not to i32 %sext = sext i1 %not to i32
ret i32 %sext ret i32 %sext
} }

test/CodeGen/X86/swift-return.ll

Show First 20 Lines • Show All 227 Lines • ▼ Show 20 Lines
declare swiftcc { float, float, float, float } @gen4(float %key) declare swiftcc { float, float, float, float } @gen4(float %key)
define void @consume_i1_ret() { define void @consume_i1_ret() {
; CHECK-LABEL: consume_i1_ret: ; CHECK-LABEL: consume_i1_ret:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq produce_i1_ret ; CHECK-NEXT: callq produce_i1_ret
; CHECK-NEXT: andb $1, %al
; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: movl %eax, {{.*}}(%rip) ; CHECK-NEXT: movl %eax, {{.*}}(%rip)
; CHECK-NEXT: andb $1, %dl
; CHECK-NEXT: movzbl %dl, %eax ; CHECK-NEXT: movzbl %dl, %eax
; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: movl %eax, {{.*}}(%rip) ; CHECK-NEXT: movl %eax, {{.*}}(%rip)
; CHECK-NEXT: andb $1, %cl
; CHECK-NEXT: movzbl %cl, %eax ; CHECK-NEXT: movzbl %cl, %eax
; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: movl %eax, {{.*}}(%rip) ; CHECK-NEXT: movl %eax, {{.*}}(%rip)
; CHECK-NEXT: andb $1, %r8b
; CHECK-NEXT: movzbl %r8b, %eax ; CHECK-NEXT: movzbl %r8b, %eax
; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: movl %eax, {{.*}}(%rip) ; CHECK-NEXT: movl %eax, {{.*}}(%rip)
; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; CHECK-O0-LABEL: consume_i1_ret: ; CHECK-O0-LABEL: consume_i1_ret:
; CHECK-O0: # %bb.0: ; CHECK-O0: # %bb.0:
; CHECK-O0-NEXT: pushq %rax ; CHECK-O0-NEXT: pushq %rax
; CHECK-O0-NEXT: .cfi_def_cfa_offset 16 ; CHECK-O0-NEXT: .cfi_def_cfa_offset 16
▲ Show 20 Lines • Show All 324 Lines • Show Last 20 Lines

test/DebugInfo/X86/sdag-combine.ll

Show All 9 Lines
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 declare void @llvm.dbg.declare(metadata, metadata, metadata) #0
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
define swiftcc void @g() #0 !dbg !5 { define swiftcc void @g() #0 !dbg !5 {
entry: entry:
%0 = alloca %TSb, align 1 %0 = alloca %TSb, align 1
%1 = call swiftcc i1 @f(), !dbg !7 %1 = call swiftcc i1 @f(), !dbg !7
; CHECK: DBG_VALUE debug-use $rax, debug-use $noreg, !8, !DIExpression(), debug-location !7 ; CHECK: DBG_VALUE debug-use $rcx, debug-use $noreg, !8, !DIExpression(), debug-location !7
call void @llvm.dbg.value(metadata i1 %1, metadata !8, metadata !DIExpression()), !dbg !7 call void @llvm.dbg.value(metadata i1 %1, metadata !8, metadata !DIExpression()), !dbg !7
%2 = getelementptr inbounds %TSb, %TSb* %0, i32 0, i32 0, !dbg !7 %2 = getelementptr inbounds %TSb, %TSb* %0, i32 0, i32 0, !dbg !7
store i1 %1, i1* %2, align 1, !dbg !7 store i1 %1, i1* %2, align 1, !dbg !7
%3 = zext i1 %1 to i64, !dbg !7 %3 = zext i1 %1 to i64, !dbg !7
call void asm sideeffect "", "r"(i64 %3), !dbg !7 call void asm sideeffect "", "r"(i64 %3), !dbg !7
ret void, !dbg !7 ret void, !dbg !7
} }
Show All 20 Lines