[DAGCombiner] Add one use check before calling SimplifyDemandedBits on the value in visitStore.

[craig.topper]

Summary

The SimplifyDemandedBits entry point used by DAGCombiner forces the AssumeSingleUse flag to be set to true preventing SimplifyDemandedBits from protecting this itself. Every other caller from DAGCombine pass the node being visited due to SimplifyDemandedBits so this isn't a problem for them.

[craig.topper]

Nevermind apparently I don't know which entry point DAGCombiner actually uses.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue Shorter = DAG.GetDemandedBits(
                                     ST->getMemoryVT().getScalarSizeInBits()));
     AddToWorklist(Value.getNode());
     if (Shorter.getNode())
       return DAG.getTruncStore(Chain, SDLoc(N), Shorter,
                                Ptr, ST->getMemoryVT(), ST->getMemOperand());
 
     // Otherwise, see if we can simplify the operation with
     // SimplifyDemandedBits, which only works if the value has a single use.
-    if (SimplifyDemandedBits(
+    if (Value->hasOneUse() &&
+        SimplifyDemandedBits(
             Value,
             APInt::getLowBitsSet(Value.getScalarValueSizeInBits(),
                                  ST->getMemoryVT().getScalarSizeInBits()))) {
       // Re-visit the store if anything changed and the store hasn't been merged
       // with another node (N is deleted) SimplifyDemandedBits will add Value's
       // node back to the worklist if necessary, but we also need to re-visit
       // the Store node itself.
       if (N->getOpcode() != ISD::DELETED_NODE)

test/CodeGen/ARM/illegal-bitfield-loadstore.ll

 ; LE-NEXT:    orr r2, r2, #49152
 ; LE-NEXT:    orr r1, r1, #384
 ; LE-NEXT:    and r1, r1, r2
 ; LE-NEXT:    strh r1, [r0]
 ; LE-NEXT:    mov pc, lr
 ;
 ; BE-LABEL: i24_and_or:
 ; BE:       @ %bb.0:
-; BE-NEXT:    mov r1, #128
-; BE-NEXT:    strb r1, [r0, #2]
 ; BE-NEXT:    ldrh r1, [r0]
-; BE-NEXT:    orr r1, r1, #1
-; BE-NEXT:    strh r1, [r0]
+; BE-NEXT:    ldrb r2, [r0, #2]
+; BE-NEXT:    orr r1, r2, r1, lsl #8
+; BE-NEXT:    orr r1, r1, #384
+; BE-NEXT:    lsr r2, r1, #8
+; BE-NEXT:    strh r2, [r0]
+; BE-NEXT:    ldr r2, .LCPI1_0
+; BE-NEXT:    and r1, r1, r2
+; BE-NEXT:    strb r1, [r0, #2]
 ; BE-NEXT:    mov pc, lr
+; BE-NEXT:    .p2align 2
+; BE-NEXT:  @ %bb.1:
+; BE-NEXT:  .LCPI1_0:
+; BE-NEXT:    .long 16777088 @ 0xffff80
   %b = load i24, i24* %a, align 1
   %c = and i24 %b, -128
   %d = or i24 %c, 384
   store i24 %d, i24* %a, align 1
   ret void
 }
 
 define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {

 ; LE-NEXT:    str r1, [r0]
 ; LE-NEXT:    mov pc, lr
 ;
 ; BE-LABEL: i56_and_or:
 ; BE:       @ %bb.0:
 ; BE-NEXT:    mov r1, r0
 ; BE-NEXT:    ldr r12, [r0]
 ; BE-NEXT:    ldrh r2, [r1, #4]!
-; BE-NEXT:    mov r3, #128
-; BE-NEXT:    strb r3, [r1, #2]
-; BE-NEXT:    lsl r2, r2, #8
+; BE-NEXT:    ldrb r3, [r1, #2]
+; BE-NEXT:    orr r2, r3, r2, lsl #8
 ; BE-NEXT:    orr r2, r2, r12, lsl #24
 ; BE-NEXT:    orr r2, r2, #384
 ; BE-NEXT:    lsr r3, r2, #8
+; BE-NEXT:    bic r2, r2, #127
 ; BE-NEXT:    strh r3, [r1]
+; BE-NEXT:    strb r2, [r1, #2]
 ; BE-NEXT:    bic r1, r12, #255
 ; BE-NEXT:    orr r1, r1, r2, lsr #24
 ; BE-NEXT:    str r1, [r0]
 ; BE-NEXT:    mov pc, lr
 
   %b = load i56, i56* %a, align 1
   %c = and i56 %b, -128
   %d = or i56 %c, 384

test/CodeGen/X86/norex-subreg.ll

-; RUN: llc -O0 < %s -verify-machineinstrs
-; RUN: llc < %s -verify-machineinstrs
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,FOO
+; RUN: llc < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,BAR
 target triple = "x86_64-apple-macosx10.7"
 
 ; This test case extracts a sub_8bit_hi sub-register:
 ;
 ; %r8b = COPY %bh, implicit killed %ebx
 ; %esi = MOVZX32_NOREXrr8 killed %r8b
 ;
 ; The register allocation above is invalid, %bh can only be encoded without an
 ; REX prefix, so the destination register must be GR8_NOREX.  The code above
 ; triggers an assertion in copyPhysReg.
 ;
 ; <rdar://problem/10248099>
 
 define void @f() nounwind uwtable ssp {
+; FOO-LABEL: f:
+; FOO:       ## %bb.0: ## %entry
+; FOO-NEXT:    ## implicit-def: %rax
+; FOO-NEXT:    ## implicit-def: %cx
+; FOO-NEXT:    movl $15, %edx
+; FOO-NEXT:    ## implicit-def: %rsi
+; FOO-NEXT:    movl (%rsi), %edi
+; FOO-NEXT:    addl $0, %edi
+; FOO-NEXT:    movw %di, %r8w
+; FOO-NEXT:    andw $255, %r8w
+; FOO-NEXT:    andw $255, %r8w
+; FOO-NEXT:    shlw $8, %r8w
+; FOO-NEXT:    movw (%rax), %r9w
+; FOO-NEXT:    andw $255, %r9w
+; FOO-NEXT:    orw %r8w, %r9w
+; FOO-NEXT:    movw %r9w, (%rax)
+; FOO-NEXT:    movw (%rax), %r8w
+; FOO-NEXT:    shrw $8, %r8w
+; FOO-NEXT:    andw $255, %r8w
+; FOO-NEXT:    movzwl %r8w, %edi
+; FOO-NEXT:    movq %rax, -{{[0-9]+}}(%rsp) ## 8-byte Spill
+; FOO-NEXT:    movl %edi, %eax
+; FOO-NEXT:    movl %edx, -{{[0-9]+}}(%rsp) ## 4-byte Spill
+; FOO-NEXT:    cltd
+; FOO-NEXT:    movl -{{[0-9]+}}(%rsp), %edi ## 4-byte Reload
+; FOO-NEXT:    idivl %edi
+; FOO-NEXT:    movw %dx, %r8w
+; FOO-NEXT:    andw $255, %r8w
+; FOO-NEXT:    andw $255, %r8w
+; FOO-NEXT:    shlw $8, %r8w
+; FOO-NEXT:    orw %r8w, %cx
+; FOO-NEXT:    movq -{{[0-9]+}}(%rsp), %rsi ## 8-byte Reload
+; FOO-NEXT:    movw %cx, (%rsi)
+; FOO-NEXT:    retq
+;
+; BAR-LABEL: f:
+; BAR:       ## %bb.0: ## %entry
+; BAR-NEXT:    movw $-1, (%rax)
+; BAR-NEXT:    retq
 entry:
   %0 = load i32, i32* undef, align 4
   %add = add i32 0, %0
   %conv1 = trunc i32 %add to i16
   %bf.value = and i16 %conv1, 255
   %1 = and i16 %bf.value, 255
   %2 = shl i16 %1, 8
   %3 = load i16, i16* undef, align 1

 ;       %2 = COPY %1:sub_8bit_hi; GR8:%2 GR64_ABCD:%1
 ;       TEST8ri %2, 1, implicit-def %eflags; GR8:%2
 ;
 ; %2 must be constrained to GR8_NOREX, or the COPY could become impossible.
 ;
 ; PR11088
 
 define fastcc i32 @g(i64 %FB) nounwind uwtable readnone align 2 {
+; FOO-LABEL: g:
+; FOO:       ## %bb.0: ## %entry
+; FOO-NEXT:    ## implicit-def: %al
+; FOO-NEXT:    ## implicit-def: %ecx
+; FOO-NEXT:    ## implicit-def: %rdx
+; FOO-NEXT:    xorl %esi, %esi
+; FOO-NEXT:    movq %rdi, %r8
+; FOO-NEXT:    andq $256, %r8 ## imm = 0x100
+; FOO-NEXT:    cmpq $0, %r8
+; FOO-NEXT:    movl %ecx, %r9d
+; FOO-NEXT:    cmovel %esi, %r9d
+; FOO-NEXT:    movl %r9d, %esi
+; FOO-NEXT:    orl $4, %esi
+; FOO-NEXT:    cmpq $0, %rdx
+; FOO-NEXT:    cmovel %r9d, %esi
+; FOO-NEXT:    movq %rdi, %rdx
+; FOO-NEXT:    andq $32, %rdx
+; FOO-NEXT:    movl %esi, %r9d
+; FOO-NEXT:    orl $2, %r9d
+; FOO-NEXT:    cmpq $0, %rdx
+; FOO-NEXT:    cmovel %esi, %r9d
+; FOO-NEXT:    movq %rdi, %rdx
+; FOO-NEXT:    andq $8192, %rdx ## imm = 0x2000
+; FOO-NEXT:    movl %r9d, %esi
+; FOO-NEXT:    orl $32, %esi
+; FOO-NEXT:    cmpq $0, %rdx
+; FOO-NEXT:    cmovel %r9d, %esi
+; FOO-NEXT:    movl %esi, %r9d
+; FOO-NEXT:    orl $64, %r9d
+; FOO-NEXT:    testb $1, %al
+; FOO-NEXT:    cmovnel %esi, %r9d
+; FOO-NEXT:    movq %rdi, %rdx
+; FOO-NEXT:    shrq $2, %rdx
+; FOO-NEXT:    movl %edx, %esi
+; FOO-NEXT:    andl $1, %esi
+; FOO-NEXT:    orl %esi, %r9d
+; FOO-NEXT:    andq $128, %rdi
+; FOO-NEXT:    movl %r9d, %esi
+; FOO-NEXT:    orl $8, %esi
+; FOO-NEXT:    cmpq $0, %rdi
+; FOO-NEXT:    cmovel %r9d, %esi
+; FOO-NEXT:    testb $1, %al
+; FOO-NEXT:    cmovnel %ecx, %esi
+; FOO-NEXT:    testb $1, %al
+; FOO-NEXT:    cmovnel %ecx, %esi
+; FOO-NEXT:    movl %esi, %eax
+; FOO-NEXT:    retq
+;
+; BAR-LABEL: g:
+; BAR:       ## %bb.0: ## %entry
+; BAR-NEXT:    retq
 entry:
   %and32 = and i64 %FB, 256
   %cmp33 = icmp eq i64 %and32, 0
   %Features.6.or35 = select i1 %cmp33, i32 0, i32 undef
   %cmp38 = icmp eq i64 undef, 0
   %or40 = or i32 %Features.6.or35, 4
   %Features.8 = select i1 %cmp38, i32 %Features.6.or35, i32 %or40
   %and42 = and i64 %FB, 32