[AArch64] Fix BITCAST lowering crash

[evandro]

Summary

The data type is assumed to be a vector, but sometimes it may not be, leading to an assertion.

Add simple test-case to verify this.

[evandro]

Ping! 🔔

[evandro]

¡Ping! 🔔🔔

[rengolin]

Sorry, I missed a lot of reviews this year (mail issues). The patch LGTM with the nit.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

8716

Nit: I'd add a check to this early-exit here.

[samparker]

LGTM, cheers.

[evandro]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

8716

I'm confused. Isn't this a check yet?

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

static SDValue performBitcastCombine(SDNode *N,
   // For example,
   //    (v4i16 (bitconvert
   //             (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
   //  becomes
   //    (extract_subvector ((v8i16 ...), (i64 4)))
 
   // Only interested in 64-bit vectors as the ultimate result.
   EVT VT = N->getValueType(0);
   if (!VT.isVector())
     return SDValue();
   if (VT.getSimpleVT().getSizeInBits() != 64)
     return SDValue();
   // Is the operand an extract_subvector starting at the beginning or halfway
   // point of the vector? A low half may also come through as an
   // EXTRACT_SUBREG, so look for that, too.
   SDValue Op0 = N->getOperand(0);
   if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
static SDValue performBitcastCombine(SDNode *N,
   }
   // Look through the bitcast of the input to the extract.
   if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
     return SDValue();
   SDValue Source = Op0->getOperand(0)->getOperand(0);
   // If the source type has twice the number of elements as our destination
   // type, we know this is an extract of the high or low half of the vector.
   EVT SVT = Source->getValueType(0);
-  if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
+  if (!SVT.isVector() ||
+      SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
     return SDValue();
 
   DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
 
   // Create the simplified form to just extract the low or high half of the
   // vector directly rather than bothering with the bitcasts.
   SDLoc dl(N);
   unsigned NumElements = VT.getVectorNumElements();

llvm/test/CodeGen/AArch64/strqu.ll

+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-linux-gnu    | FileCheck --check-prefixes=CHECK,NOSPLIT %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64_be-linux-gnu | FileCheck --check-prefixes=CHECK,NOSPLIT %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-linux-gnu    -mcpu=exynos-m1 | FileCheck --check-prefixes=CHECK,NOSPLIT %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64_be-linux-gnu -mcpu=exynos-m1 | FileCheck --check-prefixes=CHECK,SPLIT %s
+
+; CHECK-LABEL: test_split_f:
+; NOSPLIT: str q{{[0-9]+}}, [x{{[0-9]+}}]
+; SPLIT: st1 { v{{[0-9]+}}.2s }, [x{{[0-9]+}}]
+; SPLIT: st1 { v{{[0-9]+}}.2s }, [x{{[0-9]+}}]
+define void @test_split_f(<4 x float> %val, <4 x float>* %addr) {
+  store <4 x float> %val, <4 x float>* %addr, align 8
+  ret void
+}
+
+; CHECK-LABEL: test_split_d:
+; NOSPLIT: str q{{[0-9]+}}, [x{{[0-9]+}}]
+; SPLIT: st1 { v{{[0-9]+}}.2d }, [x{{[0-9]+}}]
+define void @test_split_d(<2 x double> %val, <2 x double>* %addr) {
+  store <2 x double> %val, <2 x double>* %addr, align 8
+  ret void
+}
+
+; CHECK-LABEL: test_split_128:
+; CHECK: str q{{[0-9]+}}, [x{{[0-9]+}}]
+define void @test_split_128(fp128 %val, fp128* %addr) {
+  store fp128 %val, fp128* %addr, align 8
+  ret void
+}
+