[MIR] Add support for addrspace in MIR

[thegameg]

Summary

Add support for printing / parsing the addrspace of a MachineMemOperand.

PR35970

[MatzeB]

LGTM

(+CC AMDGPU so they can veto if they don't like the syntax)

test/CodeGen/MIR/AArch64/addrspace-memoperands.mir

26

Can you add a line that addrspace 0 is correctly parsed (and not printed)

[thegameg]

Add test case with addrspace 0.

[thegameg]

Update some more failing tests.

lib/CodeGen/MIRParser/MILexer.h

enum TokenKind {
     kw_x86_fp80,
     kw_fp128,
     kw_ppc_fp128,
     kw_target_flags,
     kw_volatile,
     kw_non_temporal,
     kw_invariant,
     kw_align,
+    kw_addrspace,
     kw_stack,
     kw_got,
     kw_jump_table,
     kw_constant_pool,
     kw_call_entry,
     kw_liveout,
     kw_address_taken,
     kw_landing_pad,

lib/CodeGen/MIRParser/MILexer.cpp

return StringSwitch<MIToken::TokenKind>(Identifier)
       .Case("fp128", MIToken::kw_fp128)
       .Case("ppc_fp128", MIToken::kw_ppc_fp128)
       .Case("target-flags", MIToken::kw_target_flags)
       .Case("volatile", MIToken::kw_volatile)
       .Case("non-temporal", MIToken::kw_non_temporal)
       .Case("dereferenceable", MIToken::kw_dereferenceable)
       .Case("invariant", MIToken::kw_invariant)
       .Case("align", MIToken::kw_align)
+      .Case("addrspace", MIToken::kw_addrspace)
       .Case("stack", MIToken::kw_stack)
       .Case("got", MIToken::kw_got)
       .Case("jump-table", MIToken::kw_jump_table)
       .Case("constant-pool", MIToken::kw_constant_pool)
       .Case("call-entry", MIToken::kw_call_entry)
       .Case("liveout", MIToken::kw_liveout)
       .Case("address-taken", MIToken::kw_address_taken)
       .Case("landing-pad", MIToken::kw_landing_pad)

lib/CodeGen/MIRParser/MIParser.cpp

public:
   bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
   bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
   bool parseMachineOperand(MachineOperand &Dest,
                            Optional<unsigned> &TiedDefIdx);
   bool parseMachineOperandAndTargetFlags(MachineOperand &Dest,
                                          Optional<unsigned> &TiedDefIdx);
   bool parseOffset(int64_t &Offset);
   bool parseAlignment(unsigned &Alignment);
+  bool parseAddrspace(unsigned &Addrspace);
   bool parseOperandsOffset(MachineOperand &Op);
   bool parseIRValue(const Value *&V);
   bool parseMemoryOperandFlag(MachineMemOperand::Flags &Flags);
   bool parseMemoryPseudoSourceValue(const PseudoSourceValue *&PSV);
   bool parseMachinePointerInfo(MachinePointerInfo &Dest);
   bool parseOptionalScope(LLVMContext &Context, SyncScope::ID &SSID);
   bool parseOptionalAtomicOrdering(AtomicOrdering &Order);
   bool parseMachineMemoryOperand(MachineMemOperand *&Dest);
bool MIParser::parseAlignment(unsigned &Alignment) {
   if (Token.isNot(MIToken::IntegerLiteral) || Token.integerValue().isSigned())
     return error("expected an integer literal after 'align'");
   if (getUnsigned(Alignment))
     return true;
   lex();
   return false;
 }
 
+bool MIParser::parseAddrspace(unsigned &Addrspace) {
+  assert(Token.is(MIToken::kw_addrspace));
+  lex();
+  if (Token.isNot(MIToken::IntegerLiteral) || Token.integerValue().isSigned())
+    return error("expected an integer literal after 'addrspace'");
+  if (getUnsigned(Addrspace))
+    return true;
+  lex();
+  return false;
+}
+
 bool MIParser::parseOperandsOffset(MachineOperand &Op) {
   int64_t Offset = 0;
   if (parseOffset(Offset))
     return true;
   Op.setOffset(Offset);
   return false;
 }
 
bool MIParser::parseMachineMemoryOperand(MachineMemOperand *&Dest) {
   AAMDNodes AAInfo;
   MDNode *Range = nullptr;
   while (consumeIfPresent(MIToken::comma)) {
     switch (Token.kind()) {
     case MIToken::kw_align:
       if (parseAlignment(BaseAlignment))
         return true;
       break;
+    case MIToken::kw_addrspace:
+      if (parseAddrspace(Ptr.AddrSpace))
+        return true;
+      break;
     case MIToken::md_tbaa:
       lex();
       if (parseMDNode(AAInfo.TBAA))
         return true;
       break;
     case MIToken::md_alias_scope:
       lex();
       if (parseMDNode(AAInfo.Scope))
         return true;
       break;
     case MIToken::md_noalias:
       lex();
       if (parseMDNode(AAInfo.NoAlias))
         return true;
       break;
     case MIToken::md_range:
       lex();
       if (parseMDNode(Range))
         return true;
       break;
+
     // TODO: Report an error on duplicate metadata nodes.
     default:
       return error("expected 'align' or '!tbaa' or '!alias.scope' or "
                    "'!noalias' or '!range'");
     }
   }
   if (expectAndConsume(MIToken::rparen))
     return true;

lib/CodeGen/MIRPrinter.cpp

void MIPrinter::print(const LLVMContext &Context, const TargetInstrInfo &TII,
   if (AAInfo.NoAlias) {
     OS << ", !noalias ";
     AAInfo.NoAlias->printAsOperand(OS, MST);
   }
   if (Op.getRanges()) {
     OS << ", !range ";
     Op.getRanges()->printAsOperand(OS, MST);
   }
+  if (unsigned AS = Op.getAddrSpace())
+    OS << ", addrspace " << AS;
+
   OS << ')';
 }
 
 void MIPrinter::printSyncScope(const LLVMContext &Context, SyncScope::ID SSID) {
   switch (SSID) {
   case SyncScope::System: {
     break;
   }

test/CodeGen/MIR/AArch64/addrspace-memoperands.mir

+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
+
+--- |
+
+  define void @addrspace_memoperands() {
+    ret void
+  }
+
+...
+---
+name:            addrspace_memoperands
+body: |
+  bb.0:
+
+    ; CHECK-LABEL: name: addrspace_memoperands
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+    ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8, addrspace 1)
+    ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4, align 2, addrspace 3)
+    ; CHECK: G_STORE [[LOAD]](s64), [[COPY]](p0) :: (store 8, addrspace 1)
+    ; CHECK: G_STORE [[LOAD1]](s32), [[COPY]](p0) :: (store 4, align 2, addrspace 3)
+    ; CHECK: RET_ReallyLR
+    %0:_(p0) = COPY %x0
+    %1:_(s64) = G_LOAD %0(p0) :: (load 8, addrspace 1)
+    %2:_(s32) = G_LOAD %0(p0) :: (load 4, align 2, addrspace 3)
+    G_STORE %1(s64), %0(p0) :: (store 8, addrspace 1)
+    G_STORE %2(s32), %0(p0) :: (store 4, align 2, addrspace 3)
+    RET_ReallyLR
+...