Page MenuHomePhabricator

[AMDGPU][MC] Added validation of image dst/data size (must match dmask and tfe)
ClosedPublic

Authored by dp on Jan 24 2018, 7:51 AM.

Diff Detail

Repository
rL LLVM

Event Timeline

dp created this revision.Jan 24 2018, 7:51 AM
dp updated this revision to Diff 131284.Jan 24 2018, 8:56 AM

Disabled validation of gather4 instructions because they have special rules not described in AMD documents.

Could anybody provide an up-to-date gather4 description?

arsenm added inline comments.Jan 24 2018, 9:11 AM
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
2281 ↗(On Diff #131284)

New line

2284 ↗(On Diff #131284)

New line

2295 ↗(On Diff #131284)

I've been thinking we should probably eventually remove the TFE operands from instructions. Since this changes the register class of the result, so it necessitates another set of instruction definitions

2297 ↗(On Diff #131284)

New line

2307–2308 ↗(On Diff #131284)

New line.

2308 ↗(On Diff #131284)

Checking for atomic this way is a bit suspect but I think this will work

dp marked 4 inline comments as done.Jan 24 2018, 10:06 AM
dp added inline comments.
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
2295 ↗(On Diff #131284)

I thought about adding TFE variants though the whole thing already looks ugly enough.
Also I'm thinking about excluding d16 from validation - looks like these variants have special (badly documented) rules.

2308 ↗(On Diff #131284)

Should I add a new flag for atomics to identify them safely?

dp updated this revision to Diff 131308.Jan 24 2018, 10:21 AM

Corrected typos found by Matt.
Excluded d16 from validation.

artem.tamazov accepted this revision.Jan 25 2018, 7:19 AM
This revision is now accepted and ready to land.Jan 25 2018, 7:19 AM
This revision was automatically updated to reflect the committed changes.