[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

[gberry]

Summary

Move reserveRegisterTuples into AMDGPURegisterInfo and use it in
R600RegisterInfo::getReservedRegs and
R600InstrInfo::reserveIndirectRegisters to ensure that all super
registers of reserved registers are also marked as reserved.

Before this change, under certain circumstances, the registers %t1_x and
%t1_xyzw would be marked as reserved, but %t1_xy and %t1_xyz would not
be, leading to the register allocator sometimes assigning a register to
%t1_xy, which is invalid since %t1_x is reserved.

[arsenm]

LGTM

lib/Target/AMDGPU/R600RegisterInfo.cpp

34–47

I don't think any of these have super registers but it doesn't really matter

[gberry]

Thanks!

lib/Target/AMDGPU/AMDGPURegisterInfo.h

 class TargetInstrInfo;
 
 struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
   AMDGPURegisterInfo();
 
   /// \returns the sub reg enum value for the given \p Channel
   /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
   unsigned getSubRegFromChannel(unsigned Channel) const;
+
+  void reserveRegisterTuples(BitVector &, unsigned Reg) const;
 };
 
 } // End namespace llvm
 
 #endif

lib/Target/AMDGPU/AMDGPURegisterInfo.cpp

static const unsigned SubRegs[] = {
     AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
     AMDGPU::sub15
   };
 
   assert(Channel < array_lengthof(SubRegs));
   return SubRegs[Channel];
 }
 
+void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
+  MCRegAliasIterator R(Reg, this, true);
+
+  for (; R.isValid(); ++R)
+    Reserved.set(*R);
+}
+
 #define GET_REGINFO_TARGET_DESC
 #include "AMDGPUGenRegisterInfo.inc"
 
 // Forced to be here by one .inc
 const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs(
   const MachineFunction *MF) const {
   CallingConv::ID CC = MF->getFunction().getCallingConv();
   switch (CC) {

lib/Target/AMDGPU/R600InstrInfo.h

public:
   unsigned int getInstrLatency(const InstrItineraryData *ItinData,
                                const MachineInstr &MI,
                                unsigned *PredCost = nullptr) const override;
 
   bool expandPostRAPseudo(MachineInstr &MI) const override;
 
   /// \brief Reserve the registers that may be accesed using indirect addressing.
   void reserveIndirectRegisters(BitVector &Reserved,
-                                const MachineFunction &MF) const;
+                                const MachineFunction &MF,
+                                const R600RegisterInfo &TRI) const;
 
   /// Calculate the "Indirect Address" for the given \p RegIndex and
   /// \p Channel
   ///
   /// We model indirect addressing using a virtual address space that can be
   /// accesed with loads and stores.  The "Indirect Address" is the memory
   /// address in this virtual address space that maps to the given \p RegIndex
   /// and \p Channel.

lib/Target/AMDGPU/R600InstrInfo.cpp

buildIndirectWrite(MI.getParent(), MI, MI.getOperand(2).getReg(), // Value
                        RI.getHWRegChan(MI.getOperand(1).getReg()));   // Channel
     break;
   }
   MI.eraseFromParent();
   return true;
 }
 
 void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
-                                             const MachineFunction &MF) const {
+                                             const MachineFunction &MF,
+                                             const R600RegisterInfo &TRI) const {
   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
   const R600FrameLowering *TFL = ST.getFrameLowering();
 
   unsigned StackWidth = TFL->getStackWidth(MF);
   int End = getIndirectIndexEnd(MF);
 
   if (End == -1)
     return;
 
   for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
-    unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
-    Reserved.set(SuperReg);
     for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
       unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
-      Reserved.set(Reg);
+      TRI.reserveRegisterTuples(Reserved, Reg);
     }
   }
 }
 
 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
   return &AMDGPU::R600_TReg32_XRegClass;
 }
 

lib/Target/AMDGPU/R600RegisterInfo.cpp

 }
 
 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
 
   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
   const R600InstrInfo *TII = ST.getInstrInfo();
 
-  Reserved.set(AMDGPU::ZERO);
-  Reserved.set(AMDGPU::HALF);
-  Reserved.set(AMDGPU::ONE);
-  Reserved.set(AMDGPU::ONE_INT);
-  Reserved.set(AMDGPU::NEG_HALF);
-  Reserved.set(AMDGPU::NEG_ONE);
-  Reserved.set(AMDGPU::PV_X);
-  Reserved.set(AMDGPU::ALU_LITERAL_X);
-  Reserved.set(AMDGPU::ALU_CONST);
-  Reserved.set(AMDGPU::PREDICATE_BIT);
-  Reserved.set(AMDGPU::PRED_SEL_OFF);
-  Reserved.set(AMDGPU::PRED_SEL_ZERO);
-  Reserved.set(AMDGPU::PRED_SEL_ONE);
-  Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
+  reserveRegisterTuples(Reserved, AMDGPU::ZERO);
+  reserveRegisterTuples(Reserved, AMDGPU::HALF);
+  reserveRegisterTuples(Reserved, AMDGPU::ONE);
+  reserveRegisterTuples(Reserved, AMDGPU::ONE_INT);
+  reserveRegisterTuples(Reserved, AMDGPU::NEG_HALF);
+  reserveRegisterTuples(Reserved, AMDGPU::NEG_ONE);
+  reserveRegisterTuples(Reserved, AMDGPU::PV_X);
+  reserveRegisterTuples(Reserved, AMDGPU::ALU_LITERAL_X);
+  reserveRegisterTuples(Reserved, AMDGPU::ALU_CONST);
+  reserveRegisterTuples(Reserved, AMDGPU::PREDICATE_BIT);
+  reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_OFF);
+  reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ZERO);
+  reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ONE);
+  reserveRegisterTuples(Reserved, AMDGPU::INDIRECT_BASE_ADDR);
 
   for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
                         E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
-    Reserved.set(*I);
+    reserveRegisterTuples(Reserved, *I);
   }
 
-  TII->reserveIndirectRegisters(Reserved, MF);
+  TII->reserveIndirectRegisters(Reserved, MF, *this);
 
   return Reserved;
 }
 
 // Dummy to not crash RegisterClassInfo.
 static const MCPhysReg CalleeSavedReg = AMDGPU::NoRegister;
 
 const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(

lib/Target/AMDGPU/SIRegisterInfo.h

 private:
   unsigned SGPRSetID;
   unsigned VGPRSetID;
   BitVector SGPRPressureSets;
   BitVector VGPRPressureSets;
   bool SpillSGPRToVGPR;
   bool SpillSGPRToSMEM;
 
-  void reserveRegisterTuples(BitVector &, unsigned Reg) const;
   void classifyPressureSet(unsigned PSetID, unsigned Reg,
                            BitVector &PressureSets) const;
 public:
   SIRegisterInfo(const SISubtarget &ST);
 
   bool spillSGPRToVGPR() const {
     return SpillSGPRToVGPR;
   }

lib/Target/AMDGPU/SIRegisterInfo.cpp

if (isSGPRPressureSet(i) && PressureSetRegUnits[i] > SGPRMax) {
       SGPRMax = PressureSetRegUnits[i];
     }
   }
 
   assert(SGPRSetID < NumRegPressureSets &&
          VGPRSetID < NumRegPressureSets);
 }
 
-void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
-  MCRegAliasIterator R(Reg, this, true);
-
-  for (; R.isValid(); ++R)
-    Reserved.set(*R);
-}
-
 unsigned SIRegisterInfo::reservedPrivateSegmentBufferReg(
   const MachineFunction &MF) const {
 
   const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
   unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), 4) - 4;
   unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
   return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SReg_128RegClass);
 }