[ARM] Fix erroneous availability of SMMLS for Armv7-M

[avieira]

Summary

Currently Armv7-M targets will generate a SMMLS instruction which is only available for Armv7E-M which does have DSP extensions in contrary to Armv7-M.

This patch fixes that and adds a test.

[samparker]

test/CodeGen/ARM/smml.ll

2 ↗

(On Diff #129046)

This duplicates line 6, and why remove the v6 triple? And what about a test that ensures v7E-M works?

[avieira]

test/CodeGen/ARM/smml.ll

2 ↗

(On Diff #129046)

It does indeed, didnt see it. As for v7E-M... that was in the other patch, Ill add one here too. Thanks.

[avieira]

test/CodeGen/ARM/smml.ll

2 ↗

(On Diff #129046)

Right, I was missing my coffee ... line 2 and 6 are for arm and thumb mode respectively. I had another look at the ARM ARM and for arm mode, v6 accepts SMMLS, for thumb only v6T2 accepts it.

I see in ARM.td that FeatureDSP was only added to armv6t2. I have now added it to Armv6.

[samparker]

LGTM, thanks.

llvm/trunk/lib/Target/ARM/ARM.td

 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 
 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 
 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 
 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 
-def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops]>;
+def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops,
+                                                       FeatureDSP]>;
 
 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
                                                        FeatureDSP]>;
 
 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 
 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
                                                        FeatureTrustZone]>;

llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

if (Subtarget->isThumb()) {
                         CurDAG->getRegister(0, MVT::i32) };
       ReplaceNode(N, CurDAG->getMachineNode(
                          Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl,
                          MVT::i32, MVT::i32, Ops));
       return;
     }
   }
   case ARMISD::SUBE: {
-    if (!Subtarget->hasV6Ops())
+    if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
       break;
     // Look for a pattern to match SMMLS
     // (sube a, (smul_loHi a, b), (subc 0, (smul_LOhi(a, b))))
     if (N->getOperand(1).getOpcode() != ISD::SMUL_LOHI ||
         N->getOperand(2).getOpcode() != ARMISD::SUBC ||
         !SDValue(N, 1).use_empty())
       break;
 

llvm/trunk/test/CodeGen/ARM/smml.ll

 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V4
 ; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6
 ; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6
 ; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMB
 ; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6
 ; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6T2
 ; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6T2
+; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V4
+; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6T2
 
 define i32 @Test0(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
 entry:
 ; CHECK-LABEL: Test0
 ; CHECK-NOT: smmls
   %conv4 = zext i32 %a to i64
   %conv1 = sext i32 %b to i64
   %conv2 = sext i32 %c to i64