[AArch64] optimise v4f16 FCMPs to utilise vector instructions

[carwil]

Summary

Improves the code generation for v4f16 FCMP instructions when FullFP16 is not supported by generating FCTVL(s) rather than a longer series of FCVTs.

[SjoerdMeijer]

Thanks, looks good to me. Just a few nits inlined, no need for another review.

lib/Target/AArch64/AArch64ISelLowering.cpp

7304

Nit: perhaps a "TODO remark" here that v8f16 could be optimised as well but is a bit more complicated?

7311

Nit: newline not necessary?

7313

Coding style nit: you don't need the brackets for the else-clause (you can check the coding style with clang-format)

[carwil]

Improved code formatting based on review

[carwil]

Missing colon

lib/Target/AArch64/AArch64ISelLowering.cpp

SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
   if (LHS.getValueType().getVectorElementType().isInteger()) {
     assert(LHS.getValueType() == RHS.getValueType());
     AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
     SDValue Cmp =
         EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG);
     return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType());
   }
 
-  if (LHS.getValueType().getVectorElementType() == MVT::f16)
+  const bool FullFP16 =
+    static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
+
+  // Make v4f16 (only) fcmp operations utilise vector instructions
+  // v8f16 support will be a litle more complicated
+  if (LHS.getValueType().getVectorElementType() == MVT::f16) {
+    if (!FullFP16 && LHS.getValueType().getVectorNumElements() == 4) {
+      LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, LHS);
+      RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, RHS);
+      SDValue NewSetcc = DAG.getSetCC(dl, MVT::v4i16, LHS, RHS, CC);
+      DAG.ReplaceAllUsesWith(Op, NewSetcc);
+      CmpVT = MVT::v4i32;
+    } else
       return SDValue();
+  }
 
   assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
          LHS.getValueType().getVectorElementType() == MVT::f64);
 
   // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
   // clean.  Some of them require two branches to implement.
   AArch64CC::CondCode CC1, CC2;
   bool ShouldInvert;

test/CodeGen/AArch64/fp16-v4-instructions.ll

 ; CHECK-COMMON-NEXT:  xtn    v0.4h, [[REG2]]
 ; CHECK-COMMON-NEXT:  ret
   %1 = fptoui<4 x half> %a to <4 x i16>
   ret <4 x i16> %1
 }
 
 define <4 x i1> @test_fcmp_une(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_une:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm {{.*}}, ne
-; CHECK-CVT-DAG: csetm {{.*}}, ne
-; CHECK-CVT-DAG: csetm {{.*}}, ne
-; CHECK-CVT-DAG: csetm {{.*}}, ne
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmeq
+; CHECK-CVT: mvn
+; CHECK-CVT: xtn
+; CHECK-CVT: ret
 
 ; CHECK-FP16-LABEL: test_fcmp_une:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, ne
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, ne
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, ne
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, ne
 ; CHECK-FP16:       ret
   %1 = fcmp une <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
 define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_ueq:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm [[REG1:w[0-9]+]], eq
-; CHECK-CVT-DAG: csetm [[REG2:w[0-9]+]], eq
-; CHECK-CVT-DAG: csetm [[REG3:w[0-9]+]], eq
-; CHECK-CVT-DAG: csetm [[REG4:w[0-9]+]], eq
-; CHECK-CVT-DAG: csinv {{.*}}, [[REG1]], wzr, vc
-; CHECK-CVT-DAG: csinv {{.*}}, [[REG2]], wzr, vc
-; CHECK-CVT-DAG: csinv {{.*}}, [[REG3]], wzr, vc
-; CHECK-CVT-DAG: csinv {{.*}}, [[REG4]], wzr, vc
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmgt
+; CHECK-CVT: fcmgt
+; CHECK-CVT: orr
+; CHECK-CVT: xtn
+; CHECK-CVT: mvn
+; CHECK-CVT: ret
 
 ; CHECK-FP16-LABEL: test_fcmp_ueq:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, eq
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, eq
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, eq
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, eq
 ; CHECK-FP16:       ret
   %1 = fcmp ueq <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
 define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_ugt:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm {{.*}}, hi
-; CHECK-CVT-DAG: csetm {{.*}}, hi
-; CHECK-CVT-DAG: csetm {{.*}}, hi
-; CHECK-CVT-DAG: csetm {{.*}}, hi
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmge
+; CHECK-CVT: xtn
+; CHECK-CVT: mvn
+; CHECK-CVT: ret
 
 ; CHECK-FP16-LABEL: test_fcmp_ugt:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, hi
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, hi
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, hi
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, hi
 ; CHECK-FP16:       ret
   %1 = fcmp ugt <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
 define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_uge:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm {{.*}}, pl
-; CHECK-CVT-DAG: csetm {{.*}}, pl
-; CHECK-CVT-DAG: csetm {{.*}}, pl
-; CHECK-CVT-DAG: csetm {{.*}}, pl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmgt
+; CHECK-CVT: xtn
+; CHECK-CVT: mvn
+; CHECK-CVT: ret
 
 ; CHECK-FP16-LABEL: test_fcmp_uge:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, pl
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, pl
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, pl
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, pl
 ; CHECK-FP16:       ret
   %1 = fcmp uge <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
 define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_ult:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm {{.*}}, lt
-; CHECK-CVT-DAG: csetm {{.*}}, lt
-; CHECK-CVT-DAG: csetm {{.*}}, lt
-; CHECK-CVT-DAG: csetm {{.*}}, lt
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmge
+; CHECK-CVT: xtn
+; CHECK-CVT: mvn
+; CHECK-CVT: ret
 
 ; CHECK-FP16-LABEL: test_fcmp_ult:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, lt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, lt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, lt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, lt
 ; CHECK-FP16:       ret
   %1 = fcmp ult <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
 define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_ule:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm {{.*}}, le
-; CHECK-CVT-DAG: csetm {{.*}}, le
-; CHECK-CVT-DAG: csetm {{.*}}, le
-; CHECK-CVT-DAG: csetm {{.*}}, le
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmgt
+; CHECK-CVT: xtn
+; CHECK-CVT: mvn
+; CHECK-CVT: ret
 
 ; CHECK-FP16-LABEL: test_fcmp_ule:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, le
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, le
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, le
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, le
 ; CHECK-FP16:       ret
   %1 = fcmp ule <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
 define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_uno:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm {{.*}}, vs
-; CHECK-CVT-DAG: csetm {{.*}}, vs
-; CHECK-CVT-DAG: csetm {{.*}}, vs
-; CHECK-CVT-DAG: csetm {{.*}}, vs
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmge
+; CHECK-CVT: fcmgt
+; CHECK-CVT: orr
+; CHECK-CVT: xtn
+; CHECK-CVT: mvn
+; CHECK-CVT: ret
 
 ; CHECK-FP16-LABEL: test_fcmp_uno:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, vs
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, vs
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, vs
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, vs
 ; CHECK-FP16:       ret
   %1 = fcmp uno <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
 define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_one:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm [[REG1:w[0-9]+]], mi
-; CHECK-CVT-DAG: csetm [[REG2:w[0-9]+]], mi
-; CHECK-CVT-DAG: csetm [[REG3:w[0-9]+]], mi
-; CHECK-CVT-DAG: csetm [[REG4:w[0-9]+]], mi
-; CHECK-CVT-DAG: csinv {{.*}}, [[REG1]], wzr, le
-; CHECK-CVT-DAG: csinv {{.*}}, [[REG2]], wzr, le
-; CHECK-CVT-DAG: csinv {{.*}}, [[REG3]], wzr, le
-; CHECK-CVT-DAG: csinv {{.*}}, [[REG4]], wzr, le
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmgt
+; CHECK-CVT: fcmgt
+; CHECK-CVT: orr
+; CHECK-CVT: xtn
+; CHECK-CVT: ret
 
 ; CHECK-FP16-LABEL: test_fcmp_one:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, mi
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, mi
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, mi
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, mi
 ; CHECK-FP16:       ret
   %1 = fcmp one <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
 define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_oeq:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm {{.*}}, eq
-; CHECK-CVT-DAG: csetm {{.*}}, eq
-; CHECK-CVT-DAG: csetm {{.*}}, eq
-; CHECK-CVT-DAG: csetm {{.*}}, eq
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmeq
+; CHECK-CVT: xtn
+; CHECK-CVT: ret
 
 ; CHECK-FP16-LABEL: test_fcmp_oeq:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, eq
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, eq
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, eq
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, eq
 ; CHECK-FP16:       ret
   %1 = fcmp oeq <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
 define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_ogt:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm {{.*}}, gt
-; CHECK-CVT-DAG: csetm {{.*}}, gt
-; CHECK-CVT-DAG: csetm {{.*}}, gt
-; CHECK-CVT-DAG: csetm {{.*}}, gt
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmgt
+; CHECK-CVT: xtn
+; CHECK-CVT: ret
 
 ; CHECK-FP16-LABEL: test_fcmp_ogt:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, gt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, gt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, gt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, gt
 ; CHECK-FP16:       ret
   %1 = fcmp ogt <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
 define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_oge:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm {{.*}}, ge
-; CHECK-CVT-DAG: csetm {{.*}}, ge
-; CHECK-CVT-DAG: csetm {{.*}}, ge
-; CHECK-CVT-DAG: csetm {{.*}}, ge
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmge
+; CHECK-CVT: xtn
+; CHECK-CVT: ret
 
 ; CHECK-FP16-LABEL: test_fcmp_oge:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, ge
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, ge
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, ge
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, ge
 ; CHECK-FP16:       ret
   %1 = fcmp oge <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
 define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_olt:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm {{.*}}, mi
-; CHECK-CVT-DAG: csetm {{.*}}, mi
-; CHECK-CVT-DAG: csetm {{.*}}, mi
-; CHECK-CVT-DAG: csetm {{.*}}, mi
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmgt
+; CHECK-CVT: xtn
+; CHECK-CVT: ret
 
 ; CHECK-FP16-LABEL: test_fcmp_olt:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, mi
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, mi
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, mi
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, mi
 ; CHECK-FP16:       ret
   %1 = fcmp olt <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
 define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_ole:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm {{.*}}, ls
-; CHECK-CVT-DAG: csetm {{.*}}, ls
-; CHECK-CVT-DAG: csetm {{.*}}, ls
-; CHECK-CVT-DAG: csetm {{.*}}, ls
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmge
+; CHECK-CVT: xtn
+; CHECK-CVT: ret
 
 ; CHECK-FP16-LABEL: test_fcmp_ole:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, ls
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, ls
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, ls
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, ls
 ; CHECK-FP16:       ret
   %1 = fcmp ole <4 x half> %a, %b
   ret <4 x i1> %1
 }
 
 define <4 x i1> @test_fcmp_ord(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-CVT-LABEL: test_fcmp_ord:
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: fcvt
-; CHECK-CVT-DAG: csetm {{.*}}, vc
-; CHECK-CVT-DAG: csetm {{.*}}, vc
-; CHECK-CVT-DAG: csetm {{.*}}, vc
-; CHECK-CVT-DAG: csetm {{.*}}, vc
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcvtl
+; CHECK-CVT: fcmge
+; CHECK-CVT: fcmgt
+; CHECK-CVT: orr
+; CHECK-CVT: xtn
+; CHECK-CVT ret
 
 ; CHECK-FP16-LABEL: test_fcmp_ord:
 ; CHECK-FP16-NOT:   fcvt
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, vc
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}
 ; CHECK-FP16:       csetm {{.*}}, vc
 ; CHECK-FP16:       fcmp  h{{.}}, h{{.}}