[AArch64] CCSIDR2 system register

[samparker]

Summary

Implement the 'Current Cache Size' register that has been introduced as part of the Armv8.3 architecture. I originally missed this, and (hopefully) should be the final patch for assembler support.

[dmgreen]

Looks good to me

lib/Target/AArch64/AArch64SystemOperands.td

 def : ROSysReg<"DBGDTRRX_EL0",       0b10, 0b011, 0b0000, 0b0101, 0b000>;
 def : ROSysReg<"MDRAR_EL1",          0b10, 0b000, 0b0001, 0b0000, 0b000>;
 def : ROSysReg<"OSLSR_EL1",          0b10, 0b000, 0b0001, 0b0001, 0b100>;
 def : ROSysReg<"DBGAUTHSTATUS_EL1",  0b10, 0b000, 0b0111, 0b1110, 0b110>;
 def : ROSysReg<"PMCEID0_EL0",        0b11, 0b011, 0b1001, 0b1100, 0b110>;
 def : ROSysReg<"PMCEID1_EL0",        0b11, 0b011, 0b1001, 0b1100, 0b111>;
 def : ROSysReg<"MIDR_EL1",           0b11, 0b000, 0b0000, 0b0000, 0b000>;
 def : ROSysReg<"CCSIDR_EL1",         0b11, 0b001, 0b0000, 0b0000, 0b000>;
+def : ROSysReg<"CCSIDR2_EL1",        0b11, 0b001, 0b0000, 0b0000, 0b010> {
+  let Requires = [{ {AArch64::HasV8_3aOps} }];
+}
 def : ROSysReg<"CLIDR_EL1",          0b11, 0b001, 0b0000, 0b0000, 0b001>;
 def : ROSysReg<"CTR_EL0",            0b11, 0b011, 0b0000, 0b0000, 0b001>;
 def : ROSysReg<"MPIDR_EL1",          0b11, 0b000, 0b0000, 0b0000, 0b101>;
 def : ROSysReg<"REVIDR_EL1",         0b11, 0b000, 0b0000, 0b0000, 0b110>;
 def : ROSysReg<"AIDR_EL1",           0b11, 0b001, 0b0000, 0b0000, 0b111>;
 def : ROSysReg<"DCZID_EL0",          0b11, 0b011, 0b0000, 0b0000, 0b111>;
 def : ROSysReg<"ID_PFR0_EL1",        0b11, 0b000, 0b0000, 0b0001, 0b000>;
 def : ROSysReg<"ID_PFR1_EL1",        0b11, 0b000, 0b0000, 0b0001, 0b001>;

test/MC/AArch64/arm64-system-encoding.s

 ; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s
+; RUN: not llvm-mc -triple arm64-apple-darwin -mattr=+v8.3a -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK-V83
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 foo:
 
 ;-----------------------------------------------------------------------------
 ; Simple encodings (instructions w/ no operands)
 ;-----------------------------------------------------------------------------
 

   mrs x3, AFSR1_EL1
   mrs x3, AFSR1_EL2
   mrs x3, AFSR1_EL3
   mrs x3, AMAIR_EL1
   mrs x3, AMAIR_EL2
   mrs x3, AMAIR_EL3
   mrs x3, CCSIDR_EL1
   mrs x3, CLIDR_EL1
+  mrs x3, CCSIDR2_EL1
   mrs x3, CNTFRQ_EL0
   mrs x3, CNTHCTL_EL2
   mrs x3, CNTHP_CTL_EL2
   mrs x3, CNTHP_CVAL_EL2
   mrs x3, CNTHP_TVAL_EL2
   mrs x3, CNTKCTL_EL1
   mrs x3, CNTPCT_EL0
   mrs x3, CNTP_CTL_EL0

 ; CHECK: mrs x3, AFSR1_EL1              ; encoding: [0x23,0x51,0x38,0xd5]
 ; CHECK: mrs x3, AFSR1_EL2              ; encoding: [0x23,0x51,0x3c,0xd5]
 ; CHECK: mrs x3, AFSR1_EL3              ; encoding: [0x23,0x51,0x3e,0xd5]
 ; CHECK: mrs x3, AMAIR_EL1              ; encoding: [0x03,0xa3,0x38,0xd5]
 ; CHECK: mrs x3, AMAIR_EL2              ; encoding: [0x03,0xa3,0x3c,0xd5]
 ; CHECK: mrs x3, AMAIR_EL3              ; encoding: [0x03,0xa3,0x3e,0xd5]
 ; CHECK: mrs x3, CCSIDR_EL1             ; encoding: [0x03,0x00,0x39,0xd5]
 ; CHECK: mrs x3, CLIDR_EL1              ; encoding: [0x23,0x00,0x39,0xd5]
+; CHECK-V83: mrs x3, CCSIDR2_EL1        ; encoding: [0x43,0x00,0x39,0xd5]
 ; CHECK: mrs x3, CNTFRQ_EL0             ; encoding: [0x03,0xe0,0x3b,0xd5]
 ; CHECK: mrs x3, CNTHCTL_EL2            ; encoding: [0x03,0xe1,0x3c,0xd5]
 ; CHECK: mrs x3, CNTHP_CTL_EL2          ; encoding: [0x23,0xe2,0x3c,0xd5]
 ; CHECK: mrs x3, CNTHP_CVAL_EL2         ; encoding: [0x43,0xe2,0x3c,0xd5]
 ; CHECK: mrs x3, CNTHP_TVAL_EL2         ; encoding: [0x03,0xe2,0x3c,0xd5]
 ; CHECK: mrs x3, CNTKCTL_EL1            ; encoding: [0x03,0xe1,0x38,0xd5]
 ; CHECK: mrs x3, CNTPCT_EL0             ; encoding: [0x23,0xe0,0x3b,0xd5]
 ; CHECK: mrs x3, CNTP_CTL_EL0           ; encoding: [0x23,0xe2,0x3b,0xd5]

test/MC/AArch64/basic-a64-diagnostics.s

         msr MDCCSR_EL0, x12
         msr DBGDTRRX_EL0, x12
         msr MDRAR_EL1, x12
         msr OSLSR_EL1, x12
         msr DBGAUTHSTATUS_EL1, x12
         msr MIDR_EL1, x12
         msr CCSIDR_EL1, x12
         msr CLIDR_EL1, x12
+        msr CCSIDR2_EL1, x12
         msr CTR_EL0, x12
         msr MPIDR_EL1, x12
         msr REVIDR_EL1, x12
         msr AIDR_EL1, x12
         msr DCZID_EL0, x12
         msr ID_PFR0_EL1, x12
         msr ID_PFR1_EL1, x12
         msr ID_DFR0_EL1, x12

 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr CCSIDR_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr CLIDR_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT:         msr CCSIDR2_EL1, x12
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr CTR_EL0, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr MPIDR_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr REVIDR_EL1, x12
 // CHECK-ERROR-NEXT:             ^

test/MC/Disassembler/AArch64/basic-a64-instructions.txt

 # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s
 # RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8,+fullfp16 -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
+# RUN: llvm-mc -triple=arm64 -mattr=+v8.3a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V83
 
 #------------------------------------------------------------------------------
 # Add/sub (immediate)
 #------------------------------------------------------------------------------
 # CHECK: add      w4, w5, #0
 # CHECK: add      w2, w3, #4095
 # CHECK: add      w30, w29, #1, lsl #12
 # CHECK: add      w13, w5, #4095, lsl #12

 # CHECK: mrs      x9, {{osdlr_el1|OSDLR_EL1}}
 # CHECK: mrs      x9, {{dbgprcr_el1|DBGPRCR_EL1}}
 # CHECK: mrs      x9, {{dbgclaimset_el1|DBGCLAIMSET_EL1}}
 # CHECK: mrs      x9, {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}
 # CHECK: mrs      x9, {{dbgauthstatus_el1|DBGAUTHSTATUS_EL1}}
 # CHECK: mrs      x9, {{midr_el1|MIDR_EL1}}
 # CHECK: mrs      x9, {{ccsidr_el1|CCSIDR_EL1}}
 # CHECK: mrs      x9, {{csselr_el1|CSSELR_EL1}}
+# CHECK-V83: mrs  x9, {{ccsidr2_el1|CCSIDR2_EL1}}
 # CHECK: mrs      x9, {{vpidr_el2|VPIDR_EL2}}
 # CHECK: mrs      x9, {{clidr_el1|CLIDR_EL1}}
 # CHECK: mrs      x9, {{ctr_el0|CTR_EL0}}
 # CHECK: mrs      x9, {{mpidr_el1|MPIDR_EL1}}
 # CHECK: mrs      x9, {{vmpidr_el2|VMPIDR_EL2}}
 # CHECK: mrs      x9, {{revidr_el1|REVIDR_EL1}}
 # CHECK: mrs      x9, {{aidr_el1|AIDR_EL1}}
 # CHECK: mrs      x9, {{dczid_el0|DCZID_EL0}}

 0x89 0x13 0x30 0xd5
 0x89 0x14 0x30 0xd5
 0xc9 0x78 0x30 0xd5
 0xc9 0x79 0x30 0xd5
 0xc9 0x7e 0x30 0xd5
 0x9 0x0 0x38 0xd5
 0x9 0x0 0x39 0xd5
 0x9 0x0 0x3a 0xd5
+0x49 0x0 0x39 0xd5
 0x9 0x0 0x3c 0xd5
 0x29 0x0 0x39 0xd5
 0x29 0x0 0x3b 0xd5
 0xa9 0x0 0x38 0xd5
 0xa9 0x0 0x3c 0xd5
 0xc9 0x0 0x38 0xd5
 0xe9 0x0 0x39 0xd5
 0xe9 0x0 0x3b 0xd5