[AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for AMDGPU

[msearles]

Summary

Turn off MergeConsecutiveStores() before Instruction Selection for AMDGPU. Commit dbbb6c5fc3642987430866dffdf710df4f616ac7 turned on MergeConsecutiveStores() before Instruction Selection for all targets. Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off until the issues can be addressed.

[msearles]

Ran instnamer on memory-legalizer-store-infinite-loop.ll

[rampitec]

test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll

1

Please use -check-prefix=GCN instead of CHECK.

[msearles]

Use -check-prefix=GCN instead of CHECK; add GCN-LABEL

[arsenm]

lib/Target/AMDGPU/AMDGPUISelLowering.h

205

Needs a comment explaining why

[msearles]

Add comment per reviewer request

[arsenm]

LGTM with minor fixes

lib/Target/AMDGPU/AMDGPUISelLowering.h

206

Should refer to the svn revision since that is still the canonical name

test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll

15

Check the stores

16

You can remove weak_odr

[msearles]

Adjust per reviewer comments.

[arsenm]

LGTM

lib/Target/AMDGPU/AMDGPUISelLowering.h

207–208

Just r 319036, the rest is junk

lib/Target/AMDGPU/AMDGPUISelLowering.h

void ReplaceNodeResults(SDNode * N,
                           SelectionDAG &DAG) const override;
 
   SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
                                SDValue RHS, SDValue True, SDValue False,
                                SDValue CC, DAGCombinerInfo &DCI) const;
 
   const char* getTargetNodeName(unsigned Opcode) const override;
 
+  bool mergeStoresAfterLegalization() const override { return false; }
+
   bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
     return true;
   }
   SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
                            int &RefinementSteps, bool &UseOneConstNR,
                            bool Reciprocal) const override;
   SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
                            int &RefinementSteps) const override;
 
   virtual SDNode *PostISelFolding(MachineSDNode *N,

test/CodeGen/AMDGPU/amdgpu.private-memory.ll

entry:
   store i32 %5, i32 addrspace(1)* %out
   ret void
 }
 
 ; FUNC-LABEL: {{^}}char_array:
 
 ; R600: MOVA_INT
 
-; SI-PROMOTE-DAG: buffer_store_short v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ; encoding:
+; SI-PROMOTE-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ; encoding:
+; SI-PROMOTE-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:5 ; encoding:
 
 ; SI-ALLOCA-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ; encoding: [0x04,0x00,0x60,0xe0
 ; SI-ALLOCA-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:5 ; encoding: [0x05,0x00,0x60,0xe0
 define amdgpu_kernel void @char_array(i32 addrspace(1)* %out, i32 %index) #0 {
 entry:
   %0 = alloca [2 x i8]
   %1 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 0
   %2 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 1

test/CodeGen/AMDGPU/memory-legalizer-store-infinite-loop.ll

+; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -verify-machineinstrs < %s | FileCheck %s
+
+; Effectively, check that the compile finishes.
+; In the case of an infinite loop, llc toggles between merging 2 ST4s
+; ( MergeConsecutiveStores() ) and breaking the resulting ST8 apart
+; ( LegalizeStoreOps() )
+
+; Check that code was generated; we know that there will be
+; a s_endpgm, so check for it.
+
+target datalayout = "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
+
+; CHECK: s_endpgm
+define weak_odr amdgpu_kernel void @_Z6brokenPd(double* %arg) {
+bb:
+  %tmp = alloca double, align 8, addrspace(5)
+  %tmp1 = alloca double, align 8, addrspace(5)
+  %tmp2 = load double, double* %arg, align 8
+  br i1 1, label %bb6, label %bb4
+
+bb3:                                             ; No predecessors!
+  br label %bb4
+
+bb4:                                             ; preds = %bb3, %bb
+  %tmp5 = phi double addrspace(5)* [ %tmp1, %bb3 ], [ %tmp, %bb ]
+  store double %tmp2, double addrspace(5)* %tmp5, align 8
+  br label %bb6
+
+bb6:                                             ; preds = %bb4, %bb
+  %tmp7 = phi double [ 0x7FF8123000000000, %bb4 ], [ 0x7FF8000000000000, %bb ]
+  store double %tmp7, double* %arg, align 8
+  ret void
+}