[ARM] Fix endianness of Thumb .inst.w directive

[olista01]

Summary

Wide Thumb2 instructions should be emitted into the object file as pairs of 16-bit words of the appropriate endianness, not one 32-bit word.

[olista01]

Ping.

[fhahn]

Could you provide a pointer to where this behavior is stated?

[olista01]

This is described in the "Instruction endianness" section in the architecture reference manual, which is section A3.3.1 in the latest version of the v7-A/R manual. Here's the relevant bit:

A3.3.1 Instruction endianness

In ARMv7-A, the mapping of instruction memory is always little-endian. In ARMv7-R, instruction endianness can
be controlled at the system level, see Instruction endianness static configuration, ARMv7-R only on page A3-112.

Note: For information about data memory endianness control, see Endianness mapping register, ENDIANSTATE on
page A2-53.

Before ARMv7, the ARM architecture included legacy support for an alternative big-endian memory model,
described as BE-32 and controlled by SCTLR.B bit, bit[7] of the register, see Endian configuration and control on
page AppxL-2516. ARMv7 does not support BE-32 operation, and bit SCTLR[7] is RAZ/SBZP.

Where legacy object code for ARM processors contains instructions with a big-endian byte order, the removal of
support for BE-32 operation requires the instructions in the object files to have their bytes reversed for the code to
be executed on an ARMv7 processor. This means that:

- each Thumb instruction, whether a 32-bit Thumb instruction or a 16-bit Thumb instruction, must have the
  byte order of each halfword of instruction reversed
- each ARM instruction must have the byte order of each word of instruction reversed.

For most situations, this can be handled in the link stage of a tool-flow, provided the object files include sufficient
information to permit this to happen. In practice, this is the situation for all applications with the ARMv7-A profile.

[fhahn]

Thanks for providing the relevant context!

LGTM, according to the spec

lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

case '\0':
 
       break;
     case 'n':
     case 'w':
       Size = (Suffix == 'n' ? 2 : 4);
 
       assert(IsThumb);
       EmitThumbMappingSymbol();
+      // Thumb wide instructions are emitted as a pair of 16-bit words of the
+      // appropriate endianness.
       for (unsigned II = 0, IE = Size; II != IE; II = II + 2) {
-        const unsigned I0 = LittleEndian ? II + 0 : (Size - II - 1);
-        const unsigned I1 = LittleEndian ? II + 1 : (Size - II - 2);
+        const unsigned I0 = LittleEndian ? II + 0 : II + 1;
+        const unsigned I1 = LittleEndian ? II + 1 : II + 0;
         Buffer[Size - II - 2] = uint8_t(Inst >> I0 * CHAR_BIT);
         Buffer[Size - II - 1] = uint8_t(Inst >> I1 * CHAR_BIT);
       }
 
       break;
     default:
       llvm_unreachable("Invalid Suffix");
     }

test/MC/ARM/inst-directive.s

 @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - \
-@ RUN:   | llvm-readobj -s -sd | FileCheck %s
+@ RUN:   | llvm-readobj -s -sd | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
+
+@ RUN: llvm-mc %s -triple=armebv7-linux-gnueabi -filetype=obj -o - \
+@ RUN:   | llvm-readobj -s -sd | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
 
   .syntax unified
 
 @-------------------------------------------------------------------------------
 @ arm_inst
 @-------------------------------------------------------------------------------
   .arm
 
   .section  .inst.arm_inst
 
   .align  2
   .global arm_inst
   .type arm_inst,%function
 arm_inst:
   .inst 0xdefe
 
 @ CHECK: Section {
 @ CHECK:   Name: .inst.arm_inst
 @ CHECK:   SectionData (
-@ CHECK-NEXT:     0000: FEDE0000
+@ CHECK-LE-NEXT:     0000: FEDE0000
+@ CHECK-BE-NEXT:     0000: 0000DEFE
 @ CHECK-NEXT:   )
 
 @-------------------------------------------------------------------------------
 @ thumb_inst_n
 @-------------------------------------------------------------------------------
   .thumb
 
   .section  .inst.thumb_inst_n
 
   .align  2
   .global thumb_inst_n
   .type thumb_inst_n,%function
 thumb_inst_n:
   .inst.n 0xdefe
 
 @ CHECK: Section {
 @ CHECK:   Name: .inst.thumb_inst_n
 @ CHECK:   SectionData (
-@ CHECK-NEXT:     0000: FEDE
+@ CHECK-LE-NEXT:     0000: FEDE
+@ CHECK-BE-NEXT:     0000: DEFE
 @ CHECK-NEXT:   )
 
 @-------------------------------------------------------------------------------
 @ thumb_inst_w
 @-------------------------------------------------------------------------------
   .thumb
 
   .section  .inst.thumb_inst_w
 
   .align  2
   .global thumb_inst_w
   .type thumb_inst_w,%function
 thumb_inst_w:
-  .inst.w 0x00000000
+  .inst.w 0x12345678
 
 @ CHECK: Section {
 @ CHECK:   Name: .inst.thumb_inst_w
 @ CHECK:   SectionData (
-@ CHECK-NEXT:     0000: 00000000
+@ CHECK-LE-NEXT:     0000: 34127856
+@ CHECK-BE-NEXT:     0000: 12345678
 @ CHECK-NEXT:   )
 
 @-------------------------------------------------------------------------------
 @ thumb_inst_w
 @-------------------------------------------------------------------------------
   .thumb
 
   .section  .inst.thumb_inst_inst
 
   .align  2
   .global thumb_inst_inst
   .type thumb_inst_inst,%function
 thumb_inst_inst:
   .inst.w 0xf2400000, 0xf2c00000
 
 @ CHECK: Section {
 @ CHECK:   Name: .inst.thumb_inst_inst
 @ CHECK:   SectionData (
-@ CHECK-NEXT:     0000: 40F20000 C0F20000
+@ CHECK-LE-NEXT:     0000: 40F20000 C0F20000
+@ CHECK-BE-NEXT:     0000: F2400000 F2C00000
 @ CHECK-NEXT:   )