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[X86][AVX512F_128]: Adding full coverage of MC encoding for the AVX512F_128 isa sets.<NFC>
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Authored by tianqing on Dec 13 2017, 5:09 AM.

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Summary

NFC.
Adding MC regressions tests to cover the AVX512F_128 isa sets.
This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952

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rL LLVM

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gadi.haber created this revision.Dec 13 2017, 5:09 AM

What does 128N mean vs 128?

All of the

test/MC/X86/AVX512F_128N-64.s
4

This a VEX encoding which means this is an AVX1 instruction. You'l need to use xmm16-31 to trick it. This applies to lots of instructions in this patcha nd probably the 256 bit patch as well

The AVX512F 128N is a small extension to the AVX512F 128 base which includes the following ifroms:
VEXTRACTPS, VINSERTPS, VMOVD, VMOVHLPS, VMOVHPD, VMOVHPS, VMOVLHPS, VMOVLPD, VMOVLPS, VMOVQ

Is 128N the instructions that don't support masking? Where did this term come from? It's not a distinction made in the SDM as far as I know.

AVX512F 128N are vector instructions which have a GPR or a memory with the size of a scalar as an operand (insert/extract/mov).

tianqing commandeered this revision.Jan 9 2019, 6:07 PM
tianqing added a reviewer: gadi.haber.

@tianqing Are you still looking at this?

@RKSimon Yes, there are some non-EVEX encodings inside, so I'm trying to regenerate it.

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