[AMDGPU] Improve verifier wrt vcc subregs

[rampitec]

Summary

Registers vcc_lo and vcc_hi are added to the checks for constant bus
restriction. This has resulted in two test failures:

1. attr-amdgpu-num-sgpr.ll fails at instructions: %vgpr4<def> = V_MOV_B32_e32 %vcc_lo, ... %vcc<imp-use> %vgpr5<def> = V_MOV_B32_e32 %vcc_hi, ... %vcc<imp-use,kill> ...
   
   We were incorrectly assuming that vcc and vcc_lo uses are distinct.

2. inserted-wait-states.mir fails at the instruction:
   
   %vgpr4<def> = V_WRITELANE_B32 %sgpr4, %vcc_lo
   
   v_writelane_b32 is an exception from constant bus restriction: vsrc0 can be sgpr, const or m0 and lane select sgpr, m0 or inline-const.

Both verifier errors are fixed.

[arsenm]

lib/Target/AMDGPU/SIInstrInfo.cpp

2458

I was trying to clean this up recently to avoid having to list VCC here at all by checking SReg_32/SReg_64 classes instead. I think there's an issue here because implicit really means two different things. This really wants to be checking for the hardware implicit physical register uses from the instruction definition, which only applies to VCC. No instructions implicitly read just vcc_lo or vcc_hi. Implicit can also mean extra operands the compiler added on for modeling other constraints, which should not be verified for constant bus usage.

2473–2474

There aren't any instructions that use these for implicit operands.

In the first test you mentioned, I would hope this would be skipping any of the extra implicit operands beyond the defined exec use since they aren't actually going to be used by the hardware and are just for the compiler internals.

2739

Why would noreg count as a constant bus use? I wouldn't expect to see a noreg operand ever reach here

2740

I'm not sure this is correct. Consider:

v_cndmask_b32_e32 v0, vcc_hi, v1, <implicit vcc>

I'm not sure if this is valid or not.

[rampitec]

lib/Target/AMDGPU/SIInstrInfo.cpp

2739

Is we had no SGPRUsed before it is initialized with NoRegister. Now as we found a used SGPR and it is not the same as was used before we shall record it. It is in fact the same behavior as before, just NoRegister cannot be passed into regsOverlap().

2740

I think it is valid as we are going to read the whole pair in any way.

[arsenm]

Is this still needed?

lib/Target/AMDGPU/SIInstrInfo.cpp

bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
   if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
     return true;
 
   // EXEC register uses the constant bus.
   if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
     return true;
 
   // SGPRs use the constant bus
-  return (MO.getReg() == AMDGPU::VCC || MO.getReg() == AMDGPU::M0 ||
+  return (MO.getReg() == AMDGPU::VCC || MO.getReg() == AMDGPU::VCC_LO ||
+          MO.getReg() == AMDGPU::VCC_HI || MO.getReg() == AMDGPU::M0 ||
           (!MO.isImplicit() &&
            (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
             AMDGPU::SGPR_64RegClass.contains(MO.getReg()))));
 }
 
 static unsigned findImplicitSGPRRead(const MachineInstr &MI) {
   for (const MachineOperand &MO : MI.implicit_operands()) {
     // We only care about reads.
     if (MO.isDef())
       continue;
 
     switch (MO.getReg()) {
     case AMDGPU::VCC:
+    case AMDGPU::VCC_LO:
+    case AMDGPU::VCC_HI:
     case AMDGPU::M0:
     case AMDGPU::FLAT_SCR:
       return MO.getReg();
 
     default:
       break;
     }
   }
if (SGPRUsed != AMDGPU::NoRegister)
       ++ConstantBusCount;
 
     for (int OpIdx : OpIndices) {
       if (OpIdx == -1)
         break;
       const MachineOperand &MO = MI.getOperand(OpIdx);
       if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
         if (MO.isReg()) {
-          if (MO.getReg() != SGPRUsed)
+          if (SGPRUsed == AMDGPU::NoRegister ||
+              !RI.regsOverlap(MO.getReg(), SGPRUsed))
             ++ConstantBusCount;
           SGPRUsed = MO.getReg();
         } else {
           ++ConstantBusCount;
         }
       }
     }
-    if (ConstantBusCount > 1) {
+    // v_writelane_b32 is an exception from constant bus restriction:
+    // vsrc0 can be sgpr, const or m0 and lane select sgpr, m0 or inline-const
+    if (ConstantBusCount > 1 && Opcode != AMDGPU::V_WRITELANE_B32) {
       ErrInfo = "VOP* instruction uses the constant bus more than once";
       return false;
     }
   }
 
   // Verify misc. restrictions on specific instructions.
   if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
       Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {