Fix the MIPS baremetal build

[arichardson]

Summary

Currently sys/cachectl.h is used unconditionally on MIPS although it is
only available on Linux and will fail the build when targetting baremetal

[krytarowski]

Please correct this commit. This header is also present on NetBSD/MIPS.

[petarj]

In D40659#940810, @krytarowski wrote:

Please correct this commit. This header is also present on NetBSD/MIPS.

We can add

|| defined(__NetBSD__)

What about FreeBSD, is it the same?

[arichardson]

I checked Linux, FreeBSD and MacOS and only found it one Linux so I assumed it was Linux specific (especially since the commit that introduced it (r228767) only mentions Linux.
Should I just add || defined(__NetBSD__) or are there any other systems that might have it?

[krytarowski]

In D40659#941310, @petarj wrote:

In D40659#940810, @krytarowski wrote:

Please correct this commit. This header is also present on NetBSD/MIPS.

We can add

|| defined(__NetBSD__)

What about FreeBSD, is it the same?

It's also unclear for me what is 'bare metal' about. FreeBSD should have the same header.

[krytarowski]

It looks like current NetBSD has it as <mips/cachectl.h>, my mistake.

[arichardson]

In D40659#941349, @krytarowski wrote:

In D40659#941310, @petarj wrote:

In D40659#940810, @krytarowski wrote:

Please correct this commit. This header is also present on NetBSD/MIPS.

We can add

|| defined(__NetBSD__)

What about FreeBSD, is it the same?

It's also unclear for me what is 'bare metal' about. FreeBSD should have the same header.

I grepped the FreeBSD source tree for cachectl and the only matches are LLVM and compiler-rt.
By baremetal I mean no operating system and only newlib running on MIPS qemu.

[petarj]

The original change (r228767) was tested on Linux only (including Android). I have never tested this part of the code on any *BSD system.

[krytarowski]

OK, so we can reschedule it for later. Excuse me for noise. It looks like compiler-rt wasn't built (in a while) on NetBSD/evbmips (release engineering machines test x86_64, i386, ppc, sparc, sparc64, arm). Once it will be done, we will address it.

lib/builtins/clear_cache.c

#if defined(__FreeBSD__) && defined(__arm__)
   #include <sys/types.h>
   #include <machine/sysarch.h>
 #endif
 
 #if defined(__NetBSD__) && defined(__arm__)
   #include <machine/sysarch.h>
 #endif
 
-#if defined(__mips__)
+#if defined(__linux__) && defined(__mips__)
   #include <sys/cachectl.h>
   #include <sys/syscall.h>
   #include <unistd.h>
   #if defined(__ANDROID__) && defined(__LP64__)
     /*
      * clear_mips_cache - Invalidates instruction cache for Mips.
      */
     static void clear_mips_cache(const void* Addr, size_t Size) {
#define __ARM_NR_cacheflush 0x0f0002
                           : "r"(syscall_nr), "r"(start_reg), "r"(end_reg),
                             "r"(flags));
          assert(start_reg == 0 && "Cache flush syscall failed.");
     #elif defined(_WIN32)
         FlushInstructionCache(GetCurrentProcess(), start, end - start);
     #else
         compilerrt_abort();
     #endif
-#elif defined(__mips__)
+#elif defined(__linux__) && defined(__mips__)
   const uintptr_t start_int = (uintptr_t) start;
   const uintptr_t end_int = (uintptr_t) end;
     #if defined(__ANDROID__) && defined(__LP64__)
         // Call synci implementation for short address range.
         const uintptr_t address_range_limit = 256;
         if ((end_int - start_int) <= address_range_limit) {
             clear_mips_cache(start, (end_int - start_int));
         } else {