[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output

[thegameg]

Summary

As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities).

As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities).

Basically:

• find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g"
• grep -nr '%vreg' . and fix if needed
• find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g"
• grep -nr 'vreg[0-9]\+' . and fix if needed

[MatzeB]

LGTM with a bunch of nitpicks. Thanks!

lib/CodeGen/DetectDeadLanes.cpp

24

= use should move to the left

lib/CodeGen/PeepholeOptimizer.cpp

1699

maybe use %[0-9]+ instead of just % in the example?

lib/CodeGen/RegisterCoalescer.cpp

1823–1824

rename %X to %physreg_X to make it clear it is not a vreg as %Y.

1832–1834

rename %Y to %physreg_Y to avoid confusion.

lib/CodeGen/SplitKit.cpp

1378–1380

As we are touching this anyway: Rename to %0 and %1 as there is no reason for this to be 827/828 I believe.

lib/Target/AArch64/AArch64InstrInfo.cpp

2833

(unrelated note: Wasn't this renamed to %xzr in your other commit?)

lib/Target/BPF/BPFISelDAGToDAG.cpp

549

Use printReg()?

lib/Target/Hexagon/HexagonPeephole.cpp

16

%166. (Maybe do a round of grep vreg[0-9] through the sourcecode to see if there are other places where people missed the % in front of vreg.

[qcolombet]

This is a personal taste, but I find %0 less obvious than %vreg0.
I.e., I would be against this change and I would rather change the dump of .mir.

[MatzeB]

In D40420#937822, @qcolombet wrote:

This is a personal taste, but I find %0 less obvious than %vreg0.
I.e., I would be against this change and I would rather change the dump of .mir.

I'd propose a compromise here:

1. Switch the debug printing to use the same code as the MIRPrinter today (%[0-9]+)
2. Once we have support for using arbitrary names for vregs we can choose any names when printing vregs. At that point change the debug printer to print %vreg[0-9]+

[nemanjai]

In D40420#937822, @qcolombet wrote:

This is a personal taste, but I find %0 less obvious than %vreg0.
I.e., I would be against this change and I would rather change the dump of .mir.

+1
In addition to being more readable, I use vim and find it useful to place the cursor on a string to search for. It is much more likely that a string like vreg17 will match only what I care about than a string like 17. Of course, I could add the % to the search string but I'm not sure how to do that without requiring manual entry.
So I guess I just find the strings with vreg convenient with my workflow.

[thegameg]

Address comments and rebase.

[thegameg]

lib/CodeGen/PeepholeOptimizer.cpp

1699

I'l just keep %vreg = COPY %physreg.

lib/Target/AArch64/AArch64InstrInfo.cpp

2833

Yep. I fixed some of my misses in lib/ and include/ in the commit (r319187).

lib/Target/BPF/BPFISelDAGToDAG.cpp

549

I am using printReg here in D40421.

[MatzeB]

Still LGTM. For the record: Quentin was fine with the compromise proposal in another email thread.

include/llvm/CodeGen/MachineOperand.h

private:
   /// noop.  See readsReg().
   ///
   /// This is only valid on registers.
   ///
   /// Note that an instruction may have multiple <undef> operands referring to
   /// the same register.  In that case, the instruction may depend on those
   /// operands reading the same dont-care value.  For example:
   ///
-  ///   %vreg1<def> = XOR %vreg2<undef>, %vreg2<undef>
+  ///   %1<def> = XOR %2<undef>, %2<undef>
   ///
-  /// Any register can be used for %vreg2, and its value doesn't matter, but
+  /// Any register can be used for %2, and its value doesn't matter, but
   /// the two operands must be the same register.
   ///
   bool IsUndef : 1;
 
   /// IsInternalRead - True if this operand reads a value that was defined
   /// inside the same instruction or bundle.  This flag can be set on both use
   /// and def operands.  On a sub-register def operand, it refers to the part
   /// of the register that isn't written.  On a full-register def operand, it

include/llvm/CodeGen/TargetRegisterInfo.h

unsigned operator()(unsigned Reg) const {
     return TargetRegisterInfo::virtReg2Index(Reg);
   }
 };
 
 /// Prints virtual and physical registers with or without a TRI instance.
 ///
 /// The format is:
 ///   _               - NoRegister
-///   %vreg5          - a virtual register.
-///   %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
+///   %5              - a virtual register.
+///   %5:sub_8bit     - a virtual register with sub-register index (with TRI).
 ///   %eax            - a physical register
 ///   %physreg17      - a physical register when no TRI instance given.
 ///
 /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
 Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
                    unsigned SubRegIdx = 0);
 
 /// Create Printable object to print register units on a \ref raw_ostream.

lib/CodeGen/DetectDeadLanes.cpp

 /// and instructions that get lowered to a COPY (PHI, REG_SEQUENCE,
 /// INSERT_SUBREG, EXTRACT_SUBREG).
 /// The information is used to detect dead definitions and the usage of
 /// (completely) undefined values and mark the operands as such.
 /// This pass is necessary because the dead/undef status is not obvious anymore
 /// when subregisters are involved.
 ///
 /// Example:
-///    %vreg0 = some definition
-///    %vreg1 = IMPLICIT_DEF
-///    %vreg2 = REG_SEQUENCE %vreg0, sub0, %vreg1, sub1
-///    %vreg3 = EXTRACT_SUBREG %vreg2, sub1
-///           = use %vreg3
-/// The %vreg0 definition is dead and %vreg3 contains an undefined value.
+///    %0 = some definition
+///    %1 = IMPLICIT_DEF
+///    %2 = REG_SEQUENCE %0, sub0, %1, sub1
+///    %3 = EXTRACT_SUBREG %2, sub1
+///           = use %3
+/// The %0 definition is dead and %3 contains an undefined value.
 //
 //===----------------------------------------------------------------------===//
 
 #include <deque>
 #include <vector>
 
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/SetVector.h"

lib/CodeGen/LiveIntervalAnalysis.cpp

for (LiveInterval::const_iterator RI = LI.begin(), RE = LI.end(); RI != RE;
         continue;
       MachineInstr *MI = getInstructionFromIndex(RI->end);
       if (!MI)
         continue;
 
       // Check if any of the regunits are live beyond the end of RI. That could
       // happen when a physreg is defined as a copy of a virtreg:
       //
-      //   %EAX = COPY %vreg5
-      //   FOO %vreg5         <--- MI, cancel kill because %EAX is live.
+      //   %EAX = COPY %5
+      //   FOO %5             <--- MI, cancel kill because %EAX is live.
       //   BAR %EAX<kill>
       //
-      // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
+      // There should be no kill flag on FOO when %5 is rewritten as %EAX.
       for (auto &RUP : RU) {
         const LiveRange &RURange = *RUP.first;
         LiveRange::const_iterator &I = RUP.second;
         if (I == RURange.end())
           continue;
         I = RURange.advanceTo(I, RI->end);
         if (I == RURange.end() || I->start >= RI->end)
           continue;
         // I is overlapping RI.
         goto CancelKill;
       }
 
       if (MRI->subRegLivenessEnabled()) {
         // When reading a partial undefined value we must not add a kill flag.
         // The regalloc might have used the undef lane for something else.
         // Example:
-        //     %vreg1 = ...              ; R32: %vreg1
-        //     %vreg2:high16 = ...       ; R64: %vreg2
-        //        = read %vreg2<kill>    ; R64: %vreg2
-        //        = read %vreg1          ; R32: %vreg1
-        // The <kill> flag is correct for %vreg2, but the register allocator may
-        // assign R0L to %vreg1, and R0 to %vreg2 because the low 32bits of R0
-        // are actually never written by %vreg2. After assignment the <kill>
+        //     %1 = ...                  ; R32: %1
+        //     %2:high16 = ...           ; R64: %2
+        //        = read %2<kill>        ; R64: %2
+        //        = read %1              ; R32: %1
+        // The <kill> flag is correct for %2, but the register allocator may
+        // assign R0L to %1, and R0 to %2 because the low 32bits of R0
+        // are actually never written by %2. After assignment the <kill>
         // flag at the read instruction is invalid.
         LaneBitmask DefinedLanesMask;
         if (!SRs.empty()) {
           // Compute a mask of lanes that are defined.
           DefinedLanesMask = LaneBitmask::getNone();
           for (auto &SRP : SRs) {
             const LiveInterval::SubRange &SR = *SRP.first;
             LiveRange::const_iterator &I = SRP.second;

lib/CodeGen/PeepholeOptimizer.cpp

 //
 // The copy rewriting logic should look at uses as well as defs and be able to
 // eliminate copies across blocks.
 //
 // Later copies that are subregister extracts will also not be eliminated since
 // only the first copy is considered.
 //
 // e.g.
-// %vreg1 = COPY %vreg0
-// %vreg2 = COPY %vreg0:sub1
+// %1 = COPY %0
+// %2 = COPY %0:sub1
 //
-// Should replace %vreg2 uses with %vreg1:sub1
+// Should replace %2 uses with %1:sub1
 bool PeepholeOptimizer::foldRedundantCopy(
     MachineInstr *MI, SmallSet<unsigned, 4> &CopySrcRegs,
     DenseMap<unsigned, MachineInstr *> &CopyMIs) {
   assert(MI->isCopy() && "expected a COPY machine instruction");
 
   unsigned SrcReg = MI->getOperand(1).getReg();
   if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
     return false;

 
 /// \brief Phi instructions will eventually be lowered to copy instructions. If
 /// phi is in a loop header, a recurrence may formulated around the source and
 /// destination of the phi. For such case commuting operands of the instructions
 /// in the recurrence may enable coalescing of the copy instruction generated
 /// from the phi. For example, if there is a recurrence of
 ///
 /// LoopHeader:
-///   %vreg1 = phi(%vreg0, %vreg100)
+///   %1 = phi(%0, %100)
 /// LoopLatch:
-///   %vreg0<def, tied1> = ADD %vreg2<def, tied0>, %vreg1
+///   %0<def, tied1> = ADD %2<def, tied0>, %1
 ///
 /// , the fact that vreg0 and vreg2 are in the same tied operands set makes
 /// the coalescing of copy instruction generated from the phi in
-/// LoopHeader(i.e. %vreg1 = COPY %vreg0) impossible, because %vreg1 and
-/// %vreg2 have overlapping live range. This introduces additional move
-/// instruction to the final assembly. However, if we commute %vreg2 and
-/// %vreg1 of ADD instruction, the redundant move instruction can be
+/// LoopHeader(i.e. %1 = COPY %0) impossible, because %1 and
+/// %2 have overlapping live range. This introduces additional move
+/// instruction to the final assembly. However, if we commute %2 and
+/// %1 of ADD instruction, the redundant move instruction can be
 /// avoided.
 bool PeepholeOptimizer::optimizeRecurrence(MachineInstr &PHI) {
   SmallSet<unsigned, 2> TargetRegs;
   for (unsigned Idx = 1; Idx < PHI.getNumOperands(); Idx += 2) {
     MachineOperand &MO = PHI.getOperand(Idx);
     assert(isVirtualRegisterOperand(MO) && "Invalid PHI instruction");
     TargetRegs.insert(MO.getReg());
   }
for (MachineBasicBlock &MBB : MF) {
     SmallPtrSet<MachineInstr*, 16> LocalMIs;
     SmallSet<unsigned, 4> ImmDefRegs;
     DenseMap<unsigned, MachineInstr*> ImmDefMIs;
     SmallSet<unsigned, 16> FoldAsLoadDefCandidates;
 
     // Track when a non-allocatable physical register is copied to a virtual
     // register so that useless moves can be removed.
     //
-    // %PHYSREG is the map index; MI is the last valid `%vreg = COPY %PHYSREG`
+    // %PHYSREG is the map index; MI is the last valid `% = COPY %PHYSREG`
     // without any intervening re-definition of %PHYSREG.
     DenseMap<unsigned, MachineInstr *> NAPhysToVirtMIs;
 
     // Set of virtual registers that are copied from.
     SmallSet<unsigned, 4> CopySrcRegs;
     DenseMap<unsigned, MachineInstr *> CopySrcMIs;
 
     bool IsLoopHeader = MLI->isLoopHeader(&MBB);

lib/CodeGen/RegisterCoalescer.cpp

class RegisterCoalescer : public MachineFunctionPass,
     /// existing subregister number of the def / use being updated is not zero,
     /// make sure to set it to the correct physical subregister.
     void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
 
     /// If the given machine operand reads only undefined lanes add an undef
     /// flag.
     /// This can happen when undef uses were previously concealed by a copy
     /// which we coalesced. Example:
-    ///    %vreg0:sub0<def,read-undef> = ...
-    ///    %vreg1 = COPY %vreg0       <-- Coalescing COPY reveals undef
-    ///           = use %vreg1:sub1   <-- hidden undef use
+    ///    %0:sub0<def,read-undef> = ...
+    ///    %1 = COPY %0           <-- Coalescing COPY reveals undef
+    ///       = use %1:sub1       <-- hidden undef use
     void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
                       MachineOperand &MO, unsigned SubRegIdx);
 
     /// Handle copies of undef values.
     /// Returns true if @p CopyMI was a copy of an undef value and eliminated.
     bool eliminateUndefCopy(MachineInstr *CopyMI);
 
     /// Check whether or not we should apply the terminal rule on the
bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
   MachineBasicBlock *MBB = CopyMI->getParent();
   MachineBasicBlock::iterator MII =
     std::next(MachineBasicBlock::iterator(CopyMI));
   TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, *DefMI, *TRI);
   MachineInstr &NewMI = *std::prev(MII);
   NewMI.setDebugLoc(DL);
 
   // In a situation like the following:
-  //     %vreg0:subreg = instr              ; DefMI, subreg = DstIdx
-  //     %vreg1        = copy %vreg0:subreg ; CopyMI, SrcIdx = 0
-  // instead of widening %vreg1 to the register class of %vreg0 simply do:
-  //     %vreg1 = instr
+  //     %0:subreg = instr              ; DefMI, subreg = DstIdx
+  //     %1        = copy %0:subreg ; CopyMI, SrcIdx = 0
+  // instead of widening %1 to the register class of %0 simply do:
+  //     %1 = instr
   const TargetRegisterClass *NewRC = CP.getNewRC();
   if (DstIdx != 0) {
     MachineOperand &DefMO = NewMI.getOperand(0);
     if (DefMO.getSubReg() == DstIdx) {
       assert(SrcIdx == 0 && CP.isFlipped()
              && "Shouldn't have SrcIdx+DstIdx at this point");
       const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
       const TargetRegisterClass *CommonRC =
bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
 
   return true;
 }
 
 bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
   // ProcessImpicitDefs may leave some copies of <undef> values, it only removes
   // local variables. When we have a copy like:
   //
-  //   %vreg1 = COPY %vreg2<undef>
+  //   %1 = COPY %2<undef>
   //
-  // We delete the copy and remove the corresponding value number from %vreg1.
+  // We delete the copy and remove the corresponding value number from %1.
   // Any uses of that value number are marked as <undef>.
 
   // Note that we do not query CoalescerPair here but redo isMoveInstr as the
   // CoalescerPair may have a new register class with adjusted subreg indices
   // at this point.
   unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
   isMoveInstr(*TRI, CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
 
bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
   // reserved register.  Also skip merging the live ranges, the reserved
   // register live range doesn't need to be accurate as long as all the
   // defs are there.
 
   // Delete the identity copy.
   MachineInstr *CopyMI;
   if (CP.isFlipped()) {
     // Physreg is copied into vreg
-    //   %vregY = COPY %X
+    //   %Y = COPY %X
     //   ...  //< no other def of %X here
-    //   use %vregY
+    //   use %Y
     // =>
     //   ...
     //   use %X
     CopyMI = MRI->getVRegDef(SrcReg);
   } else {
     // VReg is copied into physreg:
-    //   %vregX = def
+    //   %X = def
     //   ... //< no other def or use of %Y here
-    //   %Y = COPY %vregX
+    //   %Y = COPY %X
     // =>
     //   %Y = def
     //   ...
     if (!MRI->hasOneNonDBGUse(SrcReg)) {
       DEBUG(dbgs() << "\t\tMultiple vreg uses!\n");
       return false;
     }
 

lib/CodeGen/RenameIndependentSubregs.cpp

 //===-- RenameIndependentSubregs.cpp - Live Interval Analysis -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 /// Rename independent subregisters looks for virtual registers with
 /// independently used subregisters and renames them to new virtual registers.
 /// Example: In the following:
-///   %vreg0:sub0<read-undef> = ...
-///   %vreg0:sub1 = ...
-///   use %vreg0:sub0
-///   %vreg0:sub0 = ...
-///   use %vreg0:sub0
-///   use %vreg0:sub1
+///   %0:sub0<read-undef> = ...
+///   %0:sub1 = ...
+///   use %0:sub0
+///   %0:sub0 = ...
+///   use %0:sub0
+///   use %0:sub1
 /// sub0 and sub1 are never used together, and we have two independent sub0
 /// definitions. This pass will rename to:
-///   %vreg0:sub0<read-undef> = ...
-///   %vreg1:sub1<read-undef> = ...
-///   use %vreg1:sub1
-///   %vreg2:sub1<read-undef> = ...
-///   use %vreg2:sub1
-///   use %vreg0:sub0
+///   %0:sub0<read-undef> = ...
+///   %1:sub1<read-undef> = ...
+///   use %1:sub1
+///   %2:sub1<read-undef> = ...
+///   use %2:sub1
+///   use %0:sub0
 //
 //===----------------------------------------------------------------------===//
 
 #include "LiveRangeUtils.h"
 #include "PHIEliminationUtils.h"
 #include "llvm/CodeGen/LiveInterval.h"
 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"

lib/CodeGen/SplitKit.cpp

for (ExtPoint &EP : ExtPoints) {
     unsigned Reg = EP.MO.getReg(), Sub = EP.MO.getSubReg();
     LaneBitmask LM = Sub != 0 ? TRI.getSubRegIndexLaneMask(Sub)
                               : MRI.getMaxLaneMaskForVReg(Reg);
     for (LiveInterval::SubRange &S : LI.subranges()) {
       if ((S.LaneMask & LM).none())
         continue;
       // The problem here can be that the new register may have been created
       // for a partially defined original register. For example:
-      //   %vreg827:subreg_hireg<def,read-undef> = ...
+      //   %827:subreg_hireg<def,read-undef> = ...
       //   ...
-      //   %vreg828<def> = COPY %vreg827
+      //   %828<def> = COPY %827
       if (S.empty())
         continue;
       SubLRC.reset(&VRM.getMachineFunction(), LIS.getSlotIndexes(), &MDT,
                    &LIS.getVNInfoAllocator());
       SmallVector<SlotIndex, 4> Undefs;
       LI.computeSubRangeUndefs(Undefs, S.LaneMask, MRI, *LIS.getSlotIndexes());
       SubLRC.extend(S, EP.Next, 0, Undefs);
     }

lib/CodeGen/TargetRegisterInfo.cpp

 Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI,
                    unsigned SubIdx) {
   return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
     if (!Reg)
       OS << '_';
     else if (TargetRegisterInfo::isStackSlot(Reg))
       OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
     else if (TargetRegisterInfo::isVirtualRegister(Reg))
-      OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
+      OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
     else if (TRI && Reg < TRI->getNumRegs())
       OS << '%' << StringRef(TRI->getName(Reg)).lower();
     else
       OS << "%physreg" << Reg;
     if (SubIdx) {
       if (TRI)
         OS << ':' << TRI->getSubRegIndexName(SubIdx);
       else
return Printable([Unit, TRI](raw_ostream &OS) {
     for (++Roots; Roots.isValid(); ++Roots)
       OS << '~' << TRI->getName(*Roots);
   });
 }
 
 Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
   return Printable([Unit, TRI](raw_ostream &OS) {
     if (TRI && TRI->isVirtualRegister(Unit)) {
-      OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit);
+      OS << '%' << TargetRegisterInfo::virtReg2Index(Unit);
     } else {
       OS << printRegUnit(Unit, TRI);
     }
   });
 }
 
 } // end namespace llvm
 

lib/Target/AArch64/AArch64InstrInfo.cpp

 }
 
 MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
     MachineBasicBlock::iterator InsertPt, int FrameIndex,
     LiveIntervals *LIS) const {
   // This is a bit of a hack. Consider this instruction:
   //
-  //   %vreg0<def> = COPY %SP; GPR64all:%vreg0
+  //   %0<def> = COPY %SP; GPR64all:%0
   //
   // We explicitly chose GPR64all for the virtual register so such a copy might
   // be eliminated by RegisterCoalescer. However, that may not be possible, and
-  // %vreg0 may even spill. We can't spill %SP, and since it is in the GPR64all
+  // %0 may even spill. We can't spill %SP, and since it is in the GPR64all
   // register class, TargetInstrInfo::foldMemoryOperand() is going to try.
   //
-  // To prevent that, we are going to constrain the %vreg0 register class here.
+  // To prevent that, we are going to constrain the %0 register class here.
   //
   // <rdar://problem/11522048>
   //
   if (MI.isFullCopy()) {
     unsigned DstReg = MI.getOperand(0).getReg();
     unsigned SrcReg = MI.getOperand(1).getReg();
     if (SrcReg == AArch64::SP &&
         TargetRegisterInfo::isVirtualRegister(DstReg)) {
       MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass);
       return nullptr;
     }
     if (DstReg == AArch64::SP &&
         TargetRegisterInfo::isVirtualRegister(SrcReg)) {
       MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
       return nullptr;
     }
   }
 
   // Handle the case where a copy is being spilled or filled but the source
   // and destination register class don't match.  For example:
   //
-  //   %vreg0<def> = COPY %XZR; GPR64common:%vreg0
+  //   %0<def> = COPY %XZR; GPR64common:%0
   //
   // In this case we can still safely fold away the COPY and generate the
   // following spill code:
   //
   //   STRXui %XZR, <fi#0>
   //
   // This also eliminates spilled cross register class COPYs (e.g. between x and
   // d regs) of the same size.  For example:
   //
-  //   %vreg0<def> = COPY %vreg1; GPR64:%vreg0, FPR64:%vreg1
+  //   %0<def> = COPY %1; GPR64:%0, FPR64:%1
   //
   // will be filled as
   //
-  //   LDRDui %vreg0, fi<#0>
+  //   LDRDui %0, fi<#0>
   //
   // instead of
   //
-  //   LDRXui %vregTemp, fi<#0>
-  //   %vreg0 = FMOV %vregTemp
+  //   LDRXui %Temp, fi<#0>
+  //   %0 = FMOV %Temp
   //
   if (MI.isCopy() && Ops.size() == 1 &&
       // Make sure we're only folding the explicit COPY defs/uses.
       (Ops[0] == 0 || Ops[0] == 1)) {
     bool IsSpill = Ops[0] == 0;
     bool IsFill = !IsSpill;
     const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
     const MachineRegisterInfo &MRI = MF.getRegInfo();
if (DstMO.getSubReg() == 0 && SrcMO.getSubReg() == 0) {
       else
         loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex,
                              getRegClass(DstReg), &TRI);
       return &*--InsertPt;
     }
 
     // Handle cases like spilling def of:
     //
-    //   %vreg0:sub_32<def,read-undef> = COPY %WZR; GPR64common:%vreg0
+    //   %0:sub_32<def,read-undef> = COPY %WZR; GPR64common:%0
     //
     // where the physical register source can be widened and stored to the full
     // virtual reg destination stack slot, in this case producing:
     //
     //   STRXui %XZR, <fi#0>
     //
     if (IsSpill && DstMO.isUndef() &&
         TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
if (IsSpill && DstMO.isUndef() &&
           storeRegToStackSlot(MBB, InsertPt, WidenedSrcReg, SrcMO.isKill(),
                               FrameIndex, SpillRC, &TRI);
           return &*--InsertPt;
         }
     }
 
     // Handle cases like filling use of:
     //
-    //   %vreg0:sub_32<def,read-undef> = COPY %vreg1; GPR64:%vreg0, GPR32:%vreg1
+    //   %0:sub_32<def,read-undef> = COPY %1; GPR64:%0, GPR32:%1
     //
     // where we can load the full virtual reg source stack slot, into the subreg
     // destination, in this case producing:
     //
-    //   LDRWui %vreg0:sub_32<def,read-undef>, <fi#0>
+    //   LDRWui %0:sub_32<def,read-undef>, <fi#0>
     //
     if (IsFill && SrcMO.getSubReg() == 0 && DstMO.isUndef()) {
       const TargetRegisterClass *FillRC;
       switch (DstMO.getSubReg()) {
       default:
         FillRC = nullptr;
         break;
       case AArch64::sub_32:

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

 //===- SIFixSGPRCopies.cpp - Remove potential VGPR => SGPR copies ---------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
 /// Copies from VGPR to SGPR registers are illegal and the register coalescer
 /// will sometimes generate these illegal copies in situations like this:
 ///
 ///  Register Class <vsrc> is the union of <vgpr> and <sgpr>
 ///
 /// BB0:
-///   %vreg0 <sgpr> = SCALAR_INST
-///   %vreg1 <vsrc> = COPY %vreg0 <sgpr>
+///   %0 <sgpr> = SCALAR_INST
+///   %1 <vsrc> = COPY %0 <sgpr>
 ///    ...
 ///    BRANCH %cond BB1, BB2
 ///  BB1:
-///    %vreg2 <vgpr> = VECTOR_INST
-///    %vreg3 <vsrc> = COPY %vreg2 <vgpr>
+///    %2 <vgpr> = VECTOR_INST
+///    %3 <vsrc> = COPY %2 <vgpr>
 ///  BB2:
-///    %vreg4 <vsrc> = PHI %vreg1 <vsrc>, <BB#0>, %vreg3 <vrsc>, <BB#1>
-///    %vreg5 <vgpr> = VECTOR_INST %vreg4 <vsrc>
+///    %4 <vsrc> = PHI %1 <vsrc>, <BB#0>, %3 <vrsc>, <BB#1>
+///    %5 <vgpr> = VECTOR_INST %4 <vsrc>
 ///
 ///
 /// The coalescer will begin at BB0 and eliminate its copy, then the resulting
 /// code will look like this:
 ///
 /// BB0:
-///   %vreg0 <sgpr> = SCALAR_INST
+///   %0 <sgpr> = SCALAR_INST
 ///    ...
 ///    BRANCH %cond BB1, BB2
 /// BB1:
-///   %vreg2 <vgpr> = VECTOR_INST
-///   %vreg3 <vsrc> = COPY %vreg2 <vgpr>
+///   %2 <vgpr> = VECTOR_INST
+///   %3 <vsrc> = COPY %2 <vgpr>
 /// BB2:
-///   %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <vsrc>, <BB#1>
-///   %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr>
+///   %4 <sgpr> = PHI %0 <sgpr>, <BB#0>, %3 <vsrc>, <BB#1>
+///   %5 <vgpr> = VECTOR_INST %4 <sgpr>
 ///
 /// Now that the result of the PHI instruction is an SGPR, the register
-/// allocator is now forced to constrain the register class of %vreg3 to
+/// allocator is now forced to constrain the register class of %3 to
 /// <sgpr> so we end up with final code like this:
 ///
 /// BB0:
-///   %vreg0 <sgpr> = SCALAR_INST
+///   %0 <sgpr> = SCALAR_INST
 ///    ...
 ///    BRANCH %cond BB1, BB2
 /// BB1:
-///   %vreg2 <vgpr> = VECTOR_INST
-///   %vreg3 <sgpr> = COPY %vreg2 <vgpr>
+///   %2 <vgpr> = VECTOR_INST
+///   %3 <sgpr> = COPY %2 <vgpr>
 /// BB2:
-///   %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <sgpr>, <BB#1>
-///   %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr>
+///   %4 <sgpr> = PHI %0 <sgpr>, <BB#0>, %3 <sgpr>, <BB#1>
+///   %5 <vgpr> = VECTOR_INST %4 <sgpr>
 ///
 /// Now this code contains an illegal copy from a VGPR to an SGPR.
 ///
 /// In order to avoid this problem, this pass searches for PHI instructions
 /// which define a <vsrc> register and constrains its definition class to
 /// <vgpr> if the user of the PHI's definition register is a vector instruction.
 /// If the PHI's definition class is constrained to <vgpr> then the coalescer
 /// will be unable to perform the COPY removal from the above example  which

lib/Target/AMDGPU/SIFoldOperands.cpp

void SIFoldOperands::foldOperand(
   if (UseOp.isReg() && OpToFold.isReg()) {
     if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister)
       return;
 
     // Don't fold subregister extracts into tied operands, only if it is a full
     // copy since a subregister use tied to a full register def doesn't really
     // make sense. e.g. don't fold:
     //
-    // %vreg1 = COPY %vreg0:sub1
-    // %vreg2<tied3> = V_MAC_{F16, F32} %vreg3, %vreg4, %vreg1<tied0>
+    // %1 = COPY %0:sub1
+    // %2<tied3> = V_MAC_{F16, F32} %3, %4, %1<tied0>
     //
     //  into
-    // %vreg2<tied3> = V_MAC_{F16, F32} %vreg3, %vreg4, %vreg0:sub1<tied0>
+    // %2<tied3> = V_MAC_{F16, F32} %3, %4, %0:sub1<tied0>
     if (UseOp.isTied() && OpToFold.getSubReg() != AMDGPU::NoSubRegister)
       return;
   }
 
   // Special case for REG_SEQUENCE: We can't fold literals into
   // REG_SEQUENCE instructions, so we have to fold them into the
   // uses of REG_SEQUENCE.
   if (UseMI->isRegSequence()) {
for (I = MBB->begin(); I != MBB->end(); I = Next) {
 
       if (OpToFold.isReg() &&
           !TargetRegisterInfo::isVirtualRegister(OpToFold.getReg()))
         continue;
 
       // Prevent folding operands backwards in the function. For example,
       // the COPY opcode must not be replaced by 1 in this example:
       //
-      //    %vreg3<def> = COPY %VGPR0; VGPR_32:%vreg3
+      //    %3<def> = COPY %VGPR0; VGPR_32:%3
       //    ...
       //    %VGPR0<def> = V_MOV_B32_e32 1, %EXEC<imp-use>
       MachineOperand &Dst = MI.getOperand(0);
       if (Dst.isReg() &&
           !TargetRegisterInfo::isVirtualRegister(Dst.getReg()))
         continue;
 
       foldInstOperand(MI, OpToFold);
     }
   }
   return false;
 }

lib/Target/AMDGPU/SIPeepholeSDWA.cpp

 //===- SIPeepholeSDWA.cpp - Peephole optimization for SDWA instructions ---===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file This pass tries to apply several peephole SDWA patterns.
 ///
 /// E.g. original:
-///   V_LSHRREV_B32_e32 %vreg0, 16, %vreg1
-///   V_ADD_I32_e32 %vreg2, %vreg0, %vreg3
-///   V_LSHLREV_B32_e32 %vreg4, 16, %vreg2
+///   V_LSHRREV_B32_e32 %0, 16, %1
+///   V_ADD_I32_e32 %2, %0, %3
+///   V_LSHLREV_B32_e32 %4, 16, %2
 ///
 /// Replace:
-///   V_ADD_I32_sdwa %vreg4, %vreg1, %vreg3
+///   V_ADD_I32_sdwa %4, %1, %3
 ///       dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ///
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPU.h"
 #include "AMDGPUSubtarget.h"
 #include "SIDefines.h"
 #include "SIInstrInfo.h"

 }
 
 Optional<int64_t> SIPeepholeSDWA::foldToImm(const MachineOperand &Op) const {
   if (Op.isImm()) {
     return Op.getImm();
   }
 
   // If this is not immediate then it can be copy of immediate value, e.g.:
-  // %vreg1<def> = S_MOV_B32 255;
+  // %1<def> = S_MOV_B32 255;
   if (Op.isReg()) {
     for (const MachineOperand &Def : MRI->def_operands(Op.getReg())) {
       if (!isSameReg(Op, Def))
         continue;
 
       const MachineInstr *DefInst = Def.getParent();
       if (!TII->isFoldableCopy(*DefInst))
         return None;

lib/Target/ARM/ARMBaseInstrInfo.cpp

if (Addr0 != Addr1) {
       MachineInstr *Def1 = MRI->getVRegDef(Addr1);
       // Check if the loaded value, e.g. a constantpool of a global address, are
       // the same.
       if (!produceSameValue(*Def0, *Def1, MRI))
         return false;
     }
 
     for (unsigned i = 3, e = MI0.getNumOperands(); i != e; ++i) {
-      // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:_
+      // %12<def> = PICLDR %11, 0, pred:14, pred:_
       const MachineOperand &MO0 = MI0.getOperand(i);
       const MachineOperand &MO1 = MI1.getOperand(i);
       if (!MO0.isIdenticalTo(MO1))
         return false;
     }
     return true;
   }
 

lib/Target/BPF/BPFISelDAGToDAG.cpp

void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node,
   if (BaseV.getOpcode() != ISD::CopyFromReg)
     return;
 
   const RegisterSDNode *RegN =
       dyn_cast<RegisterSDNode>(BaseV.getNode()->getOperand(1));
   if (!RegN || !TargetRegisterInfo::isVirtualRegister(RegN->getReg()))
     return;
   unsigned AndOpReg = RegN->getReg();
-  DEBUG(dbgs() << "Examine %vreg" << TargetRegisterInfo::virtReg2Index(AndOpReg)
+  DEBUG(dbgs() << "Examine %" << TargetRegisterInfo::virtReg2Index(AndOpReg)
                << '\n');
 
   // Examine the PHI insns in the MachineBasicBlock to found out the
   // definitions of this virtual register. At this stage (DAG2DAG
   // transformation), only PHI machine insns are available in the machine basic
   // block.
   MachineBasicBlock *MBB = FuncInfo->MBB;
   MachineInstr *MII = nullptr;
void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node,
   }
 
   if (MII == nullptr) {
     // No phi definition in this block.
     if (!checkLoadDef(AndOpReg, match_load_op))
       return;
   } else {
     // The PHI node looks like:
-    //   %vreg2<def> = PHI %vreg0, <BB#1>, %vreg1, <BB#3>
-    // Trace each incoming definition, e.g., (%vreg0, BB#1) and (%vreg1, BB#3)
-    // The AND operation can be removed if both %vreg0 in BB#1 and %vreg1 in
+    //   %2<def> = PHI %0, <BB#1>, %1, <BB#3>
+    // Trace each incoming definition, e.g., (%0, BB#1) and (%1, BB#3)
+    // The AND operation can be removed if both %0 in BB#1 and %1 in
     // BB#3 are defined with with a load matching the MaskN.
     DEBUG(dbgs() << "Check PHI Insn: "; MII->dump(); dbgs() << '\n');
     unsigned PrevReg = -1;
     for (unsigned i = 0; i < MII->getNumOperands(); ++i) {
       const MachineOperand &MOP = MII->getOperand(i);
       if (MOP.isReg()) {
         if (MOP.isDef())
           continue;

lib/Target/Hexagon/HexagonBlockRanges.cpp

for (auto &Op : In.operands()) {
         if (BM[PR/32] & (1u << (PR%32)))
           continue;
         RegisterRef R = { PR, 0 };
         if (!Defs.count(R))
           Clobbers.insert(R);
       }
     }
     // Defs and clobbers can overlap, e.g.
-    // %D0<def,dead> = COPY %vreg5, %R0<imp-def>, %R1<imp-def>
+    // %D0<def,dead> = COPY %5, %R0<imp-def>, %R1<imp-def>
     for (RegisterRef R : Defs)
       Clobbers.erase(R);
 
     // Update maps for defs.
     for (RegisterRef S : Defs) {
       // Defs should already be expanded into subregs.
       assert(!TargetRegisterInfo::isPhysicalRegister(S.Reg) ||
              !MCSubRegIterator(S.Reg, &TRI, false).isValid());

lib/Target/Hexagon/HexagonConstPropagation.cpp

default:
       return false;
     case Hexagon::A2_tfrsi:
     case Hexagon::A2_tfrpi:
     case Hexagon::CONST32:
     case Hexagon::CONST64:
     {
       const MachineOperand &VO = MI.getOperand(1);
       // The operand of CONST32 can be a blockaddress, e.g.
-      //   %vreg0<def> = CONST32 <blockaddress(@eat, %L)>
+      //   %0<def> = CONST32 <blockaddress(@eat, %L)>
       // Do this check for all instructions for safety.
       if (!VO.isImm())
         return false;
       int64_t V = MI.getOperand(1).getImm();
       unsigned W = getRegBitWidth(DefR.Reg);
       if (W != 32 && W != 64)
         return false;
       IntegerType *Ty = (W == 32) ? Type::getInt32Ty(CX)

lib/Target/Hexagon/HexagonEarlyIfConv.cpp

 // could be omitted (in case of a triangle, for example).
 // If after conversion of the side block(s) the CFG allows it, the resul-
 // ting blocks may be merged. If the "join" block contained PHI nodes, they
 // will be replaced with MUX (or MUX-like) instructions to maintain the
 // semantics of the PHI.
 //
 // Example:
 //
-//         %vreg40<def> = L2_loadrub_io %vreg39<kill>, 1
-//         %vreg41<def> = S2_tstbit_i %vreg40<kill>, 0
-//         J2_jumpt %vreg41<kill>, <BB#5>, %PC<imp-def,dead>
+//         %40<def> = L2_loadrub_io %39<kill>, 1
+//         %41<def> = S2_tstbit_i %40<kill>, 0
+//         J2_jumpt %41<kill>, <BB#5>, %PC<imp-def,dead>
 //         J2_jump <BB#4>, %PC<imp-def,dead>
 //     Successors according to CFG: BB#4(62) BB#5(62)
 //
 // BB#4: derived from LLVM BB %if.then
 //     Predecessors according to CFG: BB#3
-//         %vreg11<def> = A2_addp %vreg6, %vreg10
-//         S2_storerd_io %vreg32, 16, %vreg11
+//         %11<def> = A2_addp %6, %10
+//         S2_storerd_io %32, 16, %11
 //     Successors according to CFG: BB#5
 //
 // BB#5: derived from LLVM BB %if.end
 //     Predecessors according to CFG: BB#3 BB#4
-//         %vreg12<def> = PHI %vreg6, <BB#3>, %vreg11, <BB#4>
-//         %vreg13<def> = A2_addp %vreg7, %vreg12
-//         %vreg42<def> = C2_cmpeqi %vreg9, 10
-//         J2_jumpf %vreg42<kill>, <BB#3>, %PC<imp-def,dead>
+//         %12<def> = PHI %6, <BB#3>, %11, <BB#4>
+//         %13<def> = A2_addp %7, %12
+//         %42<def> = C2_cmpeqi %9, 10
+//         J2_jumpf %42<kill>, <BB#3>, %PC<imp-def,dead>
 //         J2_jump <BB#6>, %PC<imp-def,dead>
 //     Successors according to CFG: BB#6(4) BB#3(124)
 //
 // would become:
 //
-//         %vreg40<def> = L2_loadrub_io %vreg39<kill>, 1
-//         %vreg41<def> = S2_tstbit_i %vreg40<kill>, 0
-// spec->  %vreg11<def> = A2_addp %vreg6, %vreg10
-// pred->  S2_pstorerdf_io %vreg41, %vreg32, 16, %vreg11
-//         %vreg46<def> = PS_pselect %vreg41, %vreg6, %vreg11
-//         %vreg13<def> = A2_addp %vreg7, %vreg46
-//         %vreg42<def> = C2_cmpeqi %vreg9, 10
-//         J2_jumpf %vreg42<kill>, <BB#3>, %PC<imp-def,dead>
+//         %40<def> = L2_loadrub_io %39<kill>, 1
+//         %41<def> = S2_tstbit_i %40<kill>, 0
+// spec->  %11<def> = A2_addp %6, %10
+// pred->  S2_pstorerdf_io %41, %32, 16, %11
+//         %46<def> = PS_pselect %41, %6, %11
+//         %13<def> = A2_addp %7, %46
+//         %42<def> = C2_cmpeqi %9, 10
+//         J2_jumpf %42<kill>, <BB#3>, %PC<imp-def,dead>
 //         J2_jump <BB#6>, %PC<imp-def,dead>
 //     Successors according to CFG: BB#6 BB#3
 
 #include "Hexagon.h"
 #include "HexagonInstrInfo.h"
 #include "HexagonSubtarget.h"
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/SmallVector.h"

lib/Target/Hexagon/HexagonGenInsert.cpp

if (!DefEx || HasNE) {
     // are empty, so no need to preserve anything.
     LL.clear();
     LL.push_back(std::make_pair(MaxIF, RegisterSet()));
   }
 
   // Now, remove those whose sets of potentially removable registers are
   // contained in another IF candidate for VR. For example, given these
   // candidates for vreg45,
-  //   %vreg45:
-  //     (%vreg44,%vreg41,#9,#8), { %vreg42 }
-  //     (%vreg43,%vreg41,#9,#8), { %vreg42 %vreg44 }
+  //   %45:
+  //     (%44,%41,#9,#8), { %42 }
+  //     (%43,%41,#9,#8), { %42 %44 }
   // remove the first one, since it is contained in the second one.
   for (unsigned i = 0, n = LL.size(); i < n; ) {
     const RegisterSet &RMi = LL[i].second;
     unsigned j = 0;
     while (j < n) {
       if (j != i && LL[j].second.includes(RMi))
         break;
       j++;

lib/Target/Hexagon/HexagonHardwareLoops.cpp

bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
   // Go over all operands to the compare and look for immediate and register
   // operands.  Assume that if the compare has a single register use and a
   // single immediate operand, then the register is being compared with the
   // immediate value.
   for (unsigned i = 0, n = PredDef->getNumOperands(); i < n; ++i) {
     MachineOperand &MO = PredDef->getOperand(i);
     if (MO.isReg()) {
       // Skip all implicit references.  In one case there was:
-      //   %vreg140<def> = FCMPUGT32_rr %vreg138, %vreg139, %USR<imp-use>
+      //   %140<def> = FCMPUGT32_rr %138, %139, %USR<imp-use>
       if (MO.isImplicit())
         continue;
       if (MO.isUse()) {
         if (!isImmediate(MO)) {
           CmpRegs.insert(MO.getReg());
           continue;
         }
         // Consider the register to be the "immediate" operand.

lib/Target/Hexagon/HexagonPeephole.cpp

 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 // This peephole pass optimizes in the following cases.
 // 1. Optimizes redundant sign extends for the following case
 //    Transform the following pattern
-//    %vreg170<def> = SXTW %vreg166
+//    %170<def> = SXTW %166
 //    ...
-//    %vreg176<def> = COPY %vreg170:isub_lo
+//    %176<def> = COPY %170:isub_lo
 //
 //    Into
-//    %vreg176<def> = COPY vreg166
+//    %176<def> = COPY vreg166
 //
 //  2. Optimizes redundant negation of predicates.
-//     %vreg15<def> = CMPGTrr %vreg6, %vreg2
+//     %15<def> = CMPGTrr %6, %2
 //     ...
-//     %vreg16<def> = NOT_p %vreg15<kill>
+//     %16<def> = NOT_p %15<kill>
 //     ...
-//     JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead>
+//     JMP_c %16<kill>, <BB#1>, %PC<imp-def,dead>
 //
 //     Into
-//     %vreg15<def> = CMPGTrr %vreg6, %vreg2;
+//     %15<def> = CMPGTrr %6, %2;
 //     ...
-//     JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>;
+//     JMP_cNot %15<kill>, <BB#1>, %PC<imp-def,dead>;
 //
 // Note: The peephole pass makes the instrucstions like
-// %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
+// %170<def> = SXTW %166 or %16<def> = NOT_p %15<kill>
 // redundant and relies on some form of dead removal instructions, like
 // DCE or DIE to actually eliminate them.
 
 
 //===----------------------------------------------------------------------===//
 
 #include "Hexagon.h"
 #include "HexagonTargetMachine.h"
for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
     PeepholeMap.clear();
     PeepholeDoubleRegsMap.clear();
 
     // Traverse the basic block.
     for (auto I = MBB->begin(), E = MBB->end(), NextI = I; I != E; I = NextI) {
       NextI = std::next(I);
       MachineInstr &MI = *I;
       // Look for sign extends:
-      // %vreg170<def> = SXTW %vreg166
+      // %170<def> = SXTW %166
       if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) {
         assert(MI.getNumOperands() == 2);
         MachineOperand &Dst = MI.getOperand(0);
         MachineOperand &Src = MI.getOperand(1);
         unsigned DstReg = Dst.getReg();
         unsigned SrcReg = Src.getReg();
         // Just handle virtual registers.
         if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
             TargetRegisterInfo::isVirtualRegister(SrcReg)) {
           // Map the following:
-          // %vreg170<def> = SXTW %vreg166
+          // %170<def> = SXTW %166
           // PeepholeMap[170] = vreg166
           PeepholeMap[DstReg] = SrcReg;
         }
       }
 
-      // Look for  %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
-      // %vreg170:DoublRegs, %vreg169:IntRegs
+      // Look for  %170<def> = COMBINE_ir_V4 (0, %169)
+      // %170:DoublRegs, %169:IntRegs
       if (!DisableOptExtTo64 && MI.getOpcode() == Hexagon::A4_combineir) {
         assert(MI.getNumOperands() == 3);
         MachineOperand &Dst = MI.getOperand(0);
         MachineOperand &Src1 = MI.getOperand(1);
         MachineOperand &Src2 = MI.getOperand(2);
         if (Src1.getImm() != 0)
           continue;
         unsigned DstReg = Dst.getReg();
         unsigned SrcReg = Src2.getReg();
         PeepholeMap[DstReg] = SrcReg;
       }
 
       // Look for this sequence below
-      // %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32
-      // %vregIntReg = COPY %vregDoubleReg1:isub_lo.
+      // %DoubleReg1 = LSRd_ri %DoubleReg0, 32
+      // %IntReg = COPY %DoubleReg1:isub_lo.
       // and convert into
-      // %vregIntReg = COPY %vregDoubleReg0:isub_hi.
+      // %IntReg = COPY %DoubleReg0:isub_hi.
       if (MI.getOpcode() == Hexagon::S2_lsr_i_p) {
         assert(MI.getNumOperands() == 3);
         MachineOperand &Dst = MI.getOperand(0);
         MachineOperand &Src1 = MI.getOperand(1);
         MachineOperand &Src2 = MI.getOperand(2);
         if (Src2.getImm() != 32)
           continue;
         unsigned DstReg = Dst.getReg();
         unsigned SrcReg = Src1.getReg();
         PeepholeDoubleRegsMap[DstReg] =
           std::make_pair(*&SrcReg, Hexagon::isub_hi);
       }
 
       // Look for P=NOT(P).
       if (!DisablePNotP && MI.getOpcode() == Hexagon::C2_not) {
         assert(MI.getNumOperands() == 2);
         MachineOperand &Dst = MI.getOperand(0);
         MachineOperand &Src = MI.getOperand(1);
         unsigned DstReg = Dst.getReg();
         unsigned SrcReg = Src.getReg();
         // Just handle virtual registers.
         if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
             TargetRegisterInfo::isVirtualRegister(SrcReg)) {
           // Map the following:
-          // %vreg170<def> = NOT_xx %vreg166
+          // %170<def> = NOT_xx %166
           // PeepholeMap[170] = vreg166
           PeepholeMap[DstReg] = SrcReg;
         }
       }
 
       // Look for copy:
-      // %vreg176<def> = COPY %vreg170:isub_lo
+      // %176<def> = COPY %170:isub_lo
       if (!DisableOptSZExt && MI.isCopy()) {
         assert(MI.getNumOperands() == 2);
         MachineOperand &Dst = MI.getOperand(0);
         MachineOperand &Src = MI.getOperand(1);
 
         // Make sure we are copying the lower 32 bits.
         if (Src.getSubReg() != Hexagon::isub_lo)
           continue;

lib/Target/Hexagon/HexagonStoreWidening.cpp

 //===- HexagonStoreWidening.cpp -------------------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 // Replace sequences of "narrow" stores to adjacent memory locations with
 // a fewer "wide" stores that have the same effect.
 // For example, replace:
-//   S4_storeirb_io  %vreg100, 0, 0   ; store-immediate-byte
-//   S4_storeirb_io  %vreg100, 1, 0   ; store-immediate-byte
+//   S4_storeirb_io  %100, 0, 0   ; store-immediate-byte
+//   S4_storeirb_io  %100, 1, 0   ; store-immediate-byte
 // with
-//   S4_storeirh_io  %vreg100, 0, 0   ; store-immediate-halfword
+//   S4_storeirh_io  %100, 0, 0   ; store-immediate-halfword
 // The above is the general idea.  The actual cases handled by the code
 // may be a bit more complex.
 // The purpose of this pass is to reduce the number of outstanding stores,
 // or as one could say, "reduce store queue pressure".  Also, wide stores
 // mean fewer stores, and since there are only two memory instructions allowed
 // per packet, it also means fewer packets, and ultimately fewer cycles.
 //===---------------------------------------------------------------------===//
 

lib/Target/Hexagon/HexagonSubtarget.cpp

for (unsigned su = 0, e = DAG->SUnits.size(); su != e; ++su) {
     //   5: <call2>
     // The scheduler would often swap 3 and 4, so an additional register is
     // needed. This code inserts a Barrier dependence between 3 & 4 to prevent
     // this. The same applies for %D0 and %V0/%W0, which are also handled.
     else if (SchedRetvalOptimization) {
       const MachineInstr *MI = DAG->SUnits[su].getInstr();
       if (MI->isCopy() && (MI->readsRegister(Hexagon::R0, &TRI) ||
                            MI->readsRegister(Hexagon::V0, &TRI)))  {
-        // %vregX = COPY %R0
+        // %X = COPY %R0
         VRegHoldingRet = MI->getOperand(0).getReg();
         RetRegister = MI->getOperand(1).getReg();
         LastUseOfRet = nullptr;
       } else if (VRegHoldingRet && MI->readsVirtualRegister(VRegHoldingRet))
-        // <use of %vregX>
+        // <use of %X>
         LastUseOfRet = &DAG->SUnits[su];
       else if (LastUseOfRet && MI->definesRegister(RetRegister, &TRI))
         // %R0 = ...
         DAG->SUnits[su].addPred(SDep(LastUseOfRet, SDep::Barrier));
     }
   }
 }
 

lib/Target/NVPTX/NVPTXPeephole.cpp

 // pointer, without this pass the instructions producing alloca'ed address will
 // be based on %SP. NVPTXLowerAlloca tends to help replace store and load on
 // this address with their .local versions, but this may introduce a lot of
 // cvta.to.local instructions. Performance can be improved if we avoid casting
 // address back and forth and directly calculate local address based on %SPL.
 // This peephole pass optimizes these cases, for example
 //
 // It will transform the following pattern
-//    %vreg0<def> = LEA_ADDRi64 %VRFrame, 4
-//    %vreg1<def> = cvta_to_local_yes_64 %vreg0
+//    %0<def> = LEA_ADDRi64 %VRFrame, 4
+//    %1<def> = cvta_to_local_yes_64 %0
 //
 // into
-//    %vreg1<def> = LEA_ADDRi64 %VRFrameLocal, 4
+//    %1<def> = LEA_ADDRi64 %VRFrameLocal, 4
 //
 // %VRFrameLocal is the virtual register name of %SPL
 //
 //===----------------------------------------------------------------------===//
 
 #include "NVPTX.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"

lib/Target/PowerPC/PPCBranchCoalescing.cpp

 ///     %tmp1 = select i1 %test, double %a, double 2.000000e-03
 ///     %tmp2 = select i1 %test, double %b, double 5.000000e-03
 ///
 /// expands to the following machine code:
 ///
 /// BB#0: derived from LLVM BB %entry
 ///    Live Ins: %F1 %F3 %X6
 ///        <SNIP1>
-///        %vreg0<def> = COPY %F1; F8RC:%vreg0
-///        %vreg5<def> = CMPLWI %vreg4<kill>, 0; CRRC:%vreg5 GPRC:%vreg4
-///        %vreg8<def> = LXSDX %ZERO8, %vreg7<kill>, %RM<imp-use>;
-///                    mem:LD8[ConstantPool] F8RC:%vreg8 G8RC:%vreg7
-///        BCC 76, %vreg5, <BB#2>; CRRC:%vreg5
+///        %0<def> = COPY %F1; F8RC:%0
+///        %5<def> = CMPLWI %4<kill>, 0; CRRC:%5 GPRC:%4
+///        %8<def> = LXSDX %ZERO8, %7<kill>, %RM<imp-use>;
+///                    mem:LD8[ConstantPool] F8RC:%8 G8RC:%7
+///        BCC 76, %5, <BB#2>; CRRC:%5
 ///    Successors according to CFG: BB#1(?%) BB#2(?%)
 ///
 /// BB#1: derived from LLVM BB %entry
 ///    Predecessors according to CFG: BB#0
 ///    Successors according to CFG: BB#2(?%)
 ///
 /// BB#2: derived from LLVM BB %entry
 ///    Predecessors according to CFG: BB#0 BB#1
-///        %vreg9<def> = PHI %vreg8, <BB#1>, %vreg0, <BB#0>;
-///                    F8RC:%vreg9,%vreg8,%vreg0
+///        %9<def> = PHI %8, <BB#1>, %0, <BB#0>;
+///                    F8RC:%9,%8,%0
 ///        <SNIP2>
-///        BCC 76, %vreg5, <BB#4>; CRRC:%vreg5
+///        BCC 76, %5, <BB#4>; CRRC:%5
 ///    Successors according to CFG: BB#3(?%) BB#4(?%)
 ///
 /// BB#3: derived from LLVM BB %entry
 ///    Predecessors according to CFG: BB#2
 ///    Successors according to CFG: BB#4(?%)
 ///
 /// BB#4: derived from LLVM BB %entry
 ///    Predecessors according to CFG: BB#2 BB#3
-///        %vreg13<def> = PHI %vreg12, <BB#3>, %vreg2, <BB#2>;
-///                     F8RC:%vreg13,%vreg12,%vreg2
+///        %13<def> = PHI %12, <BB#3>, %2, <BB#2>;
+///                     F8RC:%13,%12,%2
 ///        <SNIP3>
 ///        BLR8 %LR8<imp-use>, %RM<imp-use>, %F1<imp-use>
 ///
 /// When this pattern is detected, branch coalescing will try to collapse
 /// it by moving code in BB#2 to BB#0 and/or BB#4 and removing BB#3.
 ///
 /// If all conditions are meet, IR should collapse to:
 ///
 /// BB#0: derived from LLVM BB %entry
 ///    Live Ins: %F1 %F3 %X6
 ///        <SNIP1>
-///        %vreg0<def> = COPY %F1; F8RC:%vreg0
-///        %vreg5<def> = CMPLWI %vreg4<kill>, 0; CRRC:%vreg5 GPRC:%vreg4
-///        %vreg8<def> = LXSDX %ZERO8, %vreg7<kill>, %RM<imp-use>;
-///                     mem:LD8[ConstantPool] F8RC:%vreg8 G8RC:%vreg7
+///        %0<def> = COPY %F1; F8RC:%0
+///        %5<def> = CMPLWI %4<kill>, 0; CRRC:%5 GPRC:%4
+///        %8<def> = LXSDX %ZERO8, %7<kill>, %RM<imp-use>;
+///                     mem:LD8[ConstantPool] F8RC:%8 G8RC:%7
 ///        <SNIP2>
-///        BCC 76, %vreg5, <BB#4>; CRRC:%vreg5
+///        BCC 76, %5, <BB#4>; CRRC:%5
 ///    Successors according to CFG: BB#1(0x2aaaaaaa / 0x80000000 = 33.33%)
 ///      BB#4(0x55555554 / 0x80000000 = 66.67%)
 ///
 /// BB#1: derived from LLVM BB %entry
 ///    Predecessors according to CFG: BB#0
 ///    Successors according to CFG: BB#4(0x40000000 / 0x80000000 = 50.00%)
 ///
 /// BB#4: derived from LLVM BB %entry
 ///    Predecessors according to CFG: BB#0 BB#1
-///        %vreg9<def> = PHI %vreg8, <BB#1>, %vreg0, <BB#0>;
-///                    F8RC:%vreg9,%vreg8,%vreg0
-///        %vreg13<def> = PHI %vreg12, <BB#1>, %vreg2, <BB#0>;
-///                     F8RC:%vreg13,%vreg12,%vreg2
+///        %9<def> = PHI %8, <BB#1>, %0, <BB#0>;
+///                    F8RC:%9,%8,%0
+///        %13<def> = PHI %12, <BB#1>, %2, <BB#0>;
+///                     F8RC:%13,%12,%2
 ///        <SNIP3>
 ///        BLR8 %LR8<imp-use>, %RM<imp-use>, %F1<imp-use>
 ///
 /// Branch Coalescing does not split blocks, it moves everything in the same
 /// direction ensuring it does not break use/definition semantics.
 ///
 /// PHI nodes and its corresponding use instructions are moved to its successor
 /// block if there are no uses within the successor block PHI nodes.  PHI

lib/Target/PowerPC/PPCInstrInfo.cpp

if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
                            FuncInfo->isLiveInZExt(VReg);
       }
 
       // For a method return value, we check the ZExt/SExt flags in attribute.
       // We assume the following code sequence for method call.
       //   ADJCALLSTACKDOWN 32, %R1<imp-def,dead>, %R1<imp-use>
       //   BL8_NOP <ga:@func>,...
       //   ADJCALLSTACKUP 32, 0, %R1<imp-def,dead>, %R1<imp-use>
-      //   %vreg5<def> = COPY %X3; G8RC:%vreg5
+      //   %5<def> = COPY %X3; G8RC:%5
       if (SrcReg == PPC::X3) {
         const MachineBasicBlock *MBB = MI.getParent();
         MachineBasicBlock::const_instr_iterator II =
           MachineBasicBlock::const_instr_iterator(&MI);
         if (II != MBB->instr_begin() &&
             (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
           const MachineInstr &CallMI = *(--II);
           if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {

lib/Target/PowerPC/PPCMIPeephole.cpp

for (MachineInstr &MI : MBB) {
           NumEliminatedSExt++;
         }
         break;
       }
       case PPC::RLDICL: {
         // We can eliminate RLDICL (e.g. for zero-extension)
         // if all bits to clear are already zero in the input.
         // This code assume following code sequence for zero-extension.
-        //   %vreg6<def> = COPY %vreg5:sub_32; (optional)
-        //   %vreg8<def> = IMPLICIT_DEF;
-        //   %vreg7<def,tied1> = INSERT_SUBREG %vreg8<tied0>, %vreg6, sub_32;
+        //   %6<def> = COPY %5:sub_32; (optional)
+        //   %8<def> = IMPLICIT_DEF;
+        //   %7<def,tied1> = INSERT_SUBREG %8<tied0>, %6, sub_32;
         if (!EnableZExtElimination) break;
 
         if (MI.getOperand(2).getImm() != 0)
           break;
 
         unsigned SrcReg = MI.getOperand(1).getReg();
         if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
           break;
for (MachineInstr &MI : MBB) {
 
         // replace LIs with ADDIs
         MachineInstr *DefPhiMI = getVRegDefOrNull(&Op1, MRI);
         for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) {
           MachineInstr *LiMI = getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI);
           DEBUG(dbgs() << "Optimizing LI to ADDI: ");
           DEBUG(LiMI->dump());
 
-          // There could be repeated registers in the PHI, e.g: %vreg1<def> =
-          // PHI %vreg6, <BB#2>, %vreg8, <BB#3>, %vreg8, <BB#6>; So if we've
+          // There could be repeated registers in the PHI, e.g: %1<def> =
+          // PHI %6, <BB#2>, %8, <BB#3>, %8, <BB#6>; So if we've
           // already replaced the def instruction, skip.
           if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8)
             continue;
 
           assert((LiMI->getOpcode() == PPC::LI ||
                   LiMI->getOpcode() == PPC::LI8) &&
                  "Invalid Opcode!");
           auto LiImm = LiMI->getOperand(1).getImm(); // save the imm of LI

lib/Target/PowerPC/PPCVSXFMAMutate.cpp

bool processBlock(MachineBasicBlock &MBB) {
 
         int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
         if (AltOpc == -1)
           continue;
 
         // This pass is run after register coalescing, and so we're looking for
         // a situation like this:
         //   ...
-        //   %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
-        //   %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
-        //                         %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
+        //   %5<def> = COPY %9; VSLRC:%5,%9
+        //   %5<def,tied1> = XSMADDADP %5<tied0>, %17, %16,
+        //                         %RM<imp-use>; VSLRC:%5,%17,%16
         //   ...
-        //   %vreg9<def,tied1> = XSMADDADP %vreg9<tied0>, %vreg17, %vreg19,
-        //                         %RM<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19
+        //   %9<def,tied1> = XSMADDADP %9<tied0>, %17, %19,
+        //                         %RM<imp-use>; VSLRC:%9,%17,%19
         //   ...
         // Where we can eliminate the copy by changing from the A-type to the
         // M-type instruction. Specifically, for this example, this means:
-        //   %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
-        //                         %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
+        //   %5<def,tied1> = XSMADDADP %5<tied0>, %17, %16,
+        //                         %RM<imp-use>; VSLRC:%5,%17,%16
         // is replaced by:
-        //   %vreg16<def,tied1> = XSMADDMDP %vreg16<tied0>, %vreg18, %vreg9,
-        //                         %RM<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9
-        // and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
+        //   %16<def,tied1> = XSMADDMDP %16<tied0>, %18, %9,
+        //                         %RM<imp-use>; VSLRC:%16,%18,%9
+        // and we remove: %5<def> = COPY %9; VSLRC:%5,%9
 
         SlotIndex FMAIdx = LIS->getInstructionIndex(MI);
 
         VNInfo *AddendValNo =
             LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn();
 
         // This can be null if the register is undef.
         if (!AddendValNo)
bool processBlock(MachineBasicBlock &MBB) {
         // logic below and I suspect it will not occur in any relevant
         // situations.  Additionally, check whether the copy source is killed
         // prior to the fma.  In order to replace the addend here with the
         // source of the copy, it must still be live here.  We can't use
         // interval testing for a physical register, so as long as we're
         // walking the MIs we may as well test liveness here.
         //
         // FIXME: There is a case that occurs in practice, like this:
-        //   %vreg9<def> = COPY %F1; VSSRC:%vreg9
+        //   %9<def> = COPY %F1; VSSRC:%9
         //   ...
-        //   %vreg6<def> = COPY %vreg9; VSSRC:%vreg6,%vreg9
-        //   %vreg7<def> = COPY %vreg9; VSSRC:%vreg7,%vreg9
-        //   %vreg9<def,tied1> = XSMADDASP %vreg9<tied0>, %vreg1, %vreg4; VSSRC:
-        //   %vreg6<def,tied1> = XSMADDASP %vreg6<tied0>, %vreg1, %vreg2; VSSRC:
-        //   %vreg7<def,tied1> = XSMADDASP %vreg7<tied0>, %vreg1, %vreg3; VSSRC:
+        //   %6<def> = COPY %9; VSSRC:%6,%9
+        //   %7<def> = COPY %9; VSSRC:%7,%9
+        //   %9<def,tied1> = XSMADDASP %9<tied0>, %1, %4; VSSRC:
+        //   %6<def,tied1> = XSMADDASP %6<tied0>, %1, %2; VSSRC:
+        //   %7<def,tied1> = XSMADDASP %7<tied0>, %1, %3; VSSRC:
         // which prevents an otherwise-profitable transformation.
         bool OtherUsers = false, KillsAddendSrc = false;
         for (auto J = std::prev(I), JE = MachineBasicBlock::iterator(AddendMI);
              J != JE; --J) {
           if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) {
             OtherUsers = true;
             break;
           }
           if (J->modifiesRegister(AddendSrcReg, TRI) ||
               J->killsRegister(AddendSrcReg, TRI)) {
             KillsAddendSrc = true;
             break;
           }
         }
 
         if (OtherUsers || KillsAddendSrc)
           continue;
 
 
         // The transformation doesn't work well with things like:
-        //    %vreg5 = A-form-op %vreg5, %vreg11, %vreg5;
+        //    %5 = A-form-op %5, %11, %5;
         // unless vreg11 is also a kill, so skip when it is not,
         // and check operand 3 to see it is also a kill to handle the case:
-        //   %vreg5 = A-form-op %vreg5, %vreg5, %vreg11;
+        //   %5 = A-form-op %5, %5, %11;
         // where vreg5 and vreg11 are both kills. This case would be skipped
         // otherwise.
         unsigned OldFMAReg = MI.getOperand(0).getReg();
 
         // Find one of the product operands that is killed by this instruction.
         unsigned KilledProdOp = 0, OtherProdOp = 0;
         unsigned Reg2 = MI.getOperand(2).getReg();
         unsigned Reg3 = MI.getOperand(3).getReg();

lib/Target/X86/X86ISelLowering.cpp

 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
                                          SDValue ExtIdx) {
   int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
   if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
     return Idx;
 
   // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
   // lowered this:
-  //   (extract_vector_elt (v8f32 %vreg1), Constant<6>)
+  //   (extract_vector_elt (v8f32 %1), Constant<6>)
   // to:
   //   (extract_vector_elt (vector_shuffle<2,u,u,u>
-  //                           (extract_subvector (v8f32 %vreg0), Constant<4>),
+  //                           (extract_subvector (v8f32 %0), Constant<4>),
   //                           undef)
   //                       Constant<0>)
   // In this case the vector is the extract_subvector expression and the index
   // is 2, as specified by the shuffle.
   ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
   SDValue ShuffleVec = SVOp->getOperand(0);
   MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
   assert(ShuffleVecVT.getVectorElementType() ==

test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll

 ; FALLBACK-WITH-REPORT-OUT: fmov d0, #1.0
 define [1 x double] @constant() {
   ret [1 x double] [double 1.0]
 }
 
   ; The key problem here is that we may fail to create an MBB referenced by a
   ; PHI. If so, we cannot complete the G_PHI and mustn't try or bad things
   ; happen.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: G_STORE %vreg6, %vreg2; mem:ST4[%addr] GPR:%vreg6,%vreg2 (in function: pending_phis)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: G_STORE %6, %2; mem:ST4[%addr] GPR:%6,%2 (in function: pending_phis)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for pending_phis
 ; FALLBACK-WITH-REPORT-OUT-LABEL: pending_phis:
 define i32 @pending_phis(i1 %tst, i32 %val, i32* %addr) {
   br i1 %tst, label %true, label %false
 
 end:
   %res = phi i32 [%val, %true], [42, %false]
   ret i32 %res
 
 true:
   store atomic i32 42, i32* %addr seq_cst, align 4
   br label %end
 
 false:
   br label %end
 
 }
 
   ; General legalizer inability to handle types whose size wasn't a power of 2.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg1, %vreg0; mem:ST6[%addr](align=8) (in function: odd_type)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %1, %0; mem:ST6[%addr](align=8) (in function: odd_type)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type
 ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type:
 define void @odd_type(i42* %addr) {
   %val42 = load i42, i42* %addr
   store i42 %val42, i42* %addr
   ret void
 }
 
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg1, %vreg0; mem:ST28[%addr](align=32) (in function: odd_vector)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %1, %0; mem:ST28[%addr](align=32) (in function: odd_vector)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_vector
 ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_vector:
 define void @odd_vector(<7 x i32>* %addr) {
   %vec = load <7 x i32>, <7 x i32>* %addr
   store <7 x i32> %vec, <7 x i32>* %addr
   ret void
 }
 
   ; AArch64 was asserting instead of returning an invalid mapping for unknown
   ; sizes.
 ; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: ret: '  ret i128 undef' (in function: sequence_sizes)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for sequence_sizes
 ; FALLBACK-WITH-REPORT-LABEL: sequence_sizes:
 define i128 @sequence_sizes([8 x i8] %in) {
   ret i128 undef
 }
 
 ; Just to make sure we don't accidentally emit a normal load/store.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: %vreg2<def>(s64) = G_LOAD %vreg0; mem:LD8[%addr] GPR:%vreg2,%vreg0 (in function: atomic_ops)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: %2<def>(s64) = G_LOAD %0; mem:LD8[%addr] GPR:%2,%0 (in function: atomic_ops)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for atomic_ops
 ; FALLBACK-WITH-REPORT-LABEL: atomic_ops:
 define i64 @atomic_ops(i64* %addr) {
   store atomic i64 0, i64* %addr unordered, align 8
   %res = load atomic i64, i64* %addr seq_cst, align 8
   ret i64 %res
 }
 
broken:
   landingpad { i8*, i32 } catch i8* bitcast(i8** @_ZTIi to i8*)
   ret void
 
 continue:
   ret void
 }
 
 ; Check that we fallback on invoke translation failures.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(s128) = G_FCONSTANT quad 2
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %0<def>(s128) = G_FCONSTANT quad 2
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_quad_dump
 ; FALLBACK-WITH-REPORT-OUT-LABEL: test_quad_dump:
 define fp128 @test_quad_dump() {
   ret fp128 0xL00000000000000004000000000000000
 }
 
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(p0) = G_EXTRACT_VECTOR_ELT %vreg1, %vreg2; (in function: vector_of_pointers_extractelement)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %0<def>(p0) = G_EXTRACT_VECTOR_ELT %1, %2; (in function: vector_of_pointers_extractelement)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_extractelement
 ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_extractelement:
 @var = global <2 x i16*> zeroinitializer
 define void @vector_of_pointers_extractelement() {
   br label %end
 
 block:
   %dummy = extractelement <2 x i16*> %vec, i32 0
   store i16* %dummy, i16** undef
   ret void
 
 end:
   %vec = load <2 x i16*>, <2 x i16*>* undef
   br label %block
 }
 
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg0, %vreg4; mem:ST16[undef] (in function: vector_of_pointers_insertelement)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %0, %4; mem:ST16[undef] (in function: vector_of_pointers_insertelement)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement
 ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement:
 define void @vector_of_pointers_insertelement() {
   br label %end
 
 block:
   %dummy = insertelement <2 x i16*> %vec, i16* null, i32 0
   store <2 x i16*> %dummy, <2 x i16*>* undef
   ret void
 
 end:
   %vec = load <2 x i16*>, <2 x i16*>* undef
   br label %block
 }
 
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg1, %vreg3; mem:ST12[undef](align=4) (in function: nonpow2_insertvalue_narrowing)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %1, %3; mem:ST12[undef](align=4) (in function: nonpow2_insertvalue_narrowing)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_insertvalue_narrowing
 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_insertvalue_narrowing:
 %struct96 = type { float, float, float }
 define void @nonpow2_insertvalue_narrowing(float %a) {
   %dummy = insertvalue %struct96 undef, float %a, 0
   store %struct96 %dummy, %struct96* undef
   ret void
 }
 
-; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg3, %vreg4; mem:ST12[undef](align=16) (in function: nonpow2_add_narrowing)
+; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %3, %4; mem:ST12[undef](align=16) (in function: nonpow2_add_narrowing)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_add_narrowing
 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_add_narrowing:
 define void @nonpow2_add_narrowing() {
   %a = add i128 undef, undef
   %b = trunc i128 %a to i96
   %dummy = add i96 %b, %b
   store i96 %dummy, i96* undef
   ret void
 }
 
-; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg3, %vreg4; mem:ST12[undef](align=16) (in function: nonpow2_add_narrowing)
+; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %3, %4; mem:ST12[undef](align=16) (in function: nonpow2_add_narrowing)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_or_narrowing
 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_or_narrowing:
 define void @nonpow2_or_narrowing() {
   %a = add i128 undef, undef
   %b = trunc i128 %a to i96
   %dummy = or i96 %b, %b
   store i96 %dummy, i96* undef
   ret void
 }
 
-; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg0, %vreg1; mem:ST12[undef](align=16) (in function: nonpow2_load_narrowing)
+; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %0, %1; mem:ST12[undef](align=16) (in function: nonpow2_load_narrowing)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_load_narrowing
 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_load_narrowing:
 define void @nonpow2_load_narrowing() {
   %dummy = load i96, i96* undef
   store i96 %dummy, i96* undef
   ret void
 }
 
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg3, %vreg0; mem:ST12[%c](align=16) (in function: nonpow2_store_narrowing
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %3, %0; mem:ST12[%c](align=16) (in function: nonpow2_store_narrowing
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_store_narrowing
 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_store_narrowing:
 define void @nonpow2_store_narrowing(i96* %c) {
   %a = add i128 undef, undef
   %b = trunc i128 %a to i96
   store i96 %b, i96* %c
   ret void
 }
 
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg0, %vreg1; mem:ST12[undef](align=16) (in function: nonpow2_constant_narrowing)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %0, %1; mem:ST12[undef](align=16) (in function: nonpow2_constant_narrowing)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_constant_narrowing
 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_constant_narrowing:
 define void @nonpow2_constant_narrowing() {
   store i96 0, i96* undef
   ret void
 }
 
 ; Currently can't handle vector lengths that aren't an exact multiple of
 ; natively supported vector lengths. Test that the fall-back works for those.
-; FALLBACK-WITH-REPORT-ERR-G_IMPLICIT_DEF-LEGALIZABLE: (FIXME: this is what is expected once we can legalize non-pow-of-2 G_IMPLICIT_DEF) remark: <unknown>:0:0: unable to legalize instruction: %vreg1<def>(<7 x s64>) = G_ADD %vreg0, %vreg0; (in function: nonpow2_vector_add_fewerelements
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg2<def>(s64) = G_EXTRACT_VECTOR_ELT %vreg1, %vreg3; (in function: nonpow2_vector_add_fewerelements)
+; FALLBACK-WITH-REPORT-ERR-G_IMPLICIT_DEF-LEGALIZABLE: (FIXME: this is what is expected once we can legalize non-pow-of-2 G_IMPLICIT_DEF) remark: <unknown>:0:0: unable to legalize instruction: %1<def>(<7 x s64>) = G_ADD %0, %0; (in function: nonpow2_vector_add_fewerelements
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2<def>(s64) = G_EXTRACT_VECTOR_ELT %1, %3; (in function: nonpow2_vector_add_fewerelements)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_vector_add_fewerelements
 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_vector_add_fewerelements:
 define void @nonpow2_vector_add_fewerelements() {
   %dummy = add <7 x i64> undef, undef
   %ex = extractelement <7 x i64> %dummy, i64 0
   store i64 %ex, i64* undef
   ret void
 }

test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir

 # RUN: not llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 
 --- |
 
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64--"
   define void @test() { ret void }
 
 ...
 ---
 # CHECK: *** Bad machine code: Generic virtual register must have a bank in a RegBankSelected function ***
-# CHECK: instruction: %vreg0<def>(s64) = COPY
-# CHECK: operand 0: %vreg0<def>
+# CHECK: instruction: %0<def>(s64) = COPY
+# CHECK: operand 0: %0<def>
 name:            test
 regBankSelected: true
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0:
    liveins: %x0
    %0(s64) = COPY %x0
 ...

test/CodeGen/AArch64/GlobalISel/verify-selected.mir

registers:
   - { id: 1, class: gpr64 }
   - { id: 2, class: gpr }
 body: |
   bb.0:
    liveins: %x0
    %0 = COPY %x0
 
    ; CHECK: *** Bad machine code: Unexpected generic instruction in a Selected function ***
-   ; CHECK: instruction: %vreg1<def> = G_ADD
+   ; CHECK: instruction: %1<def> = G_ADD
    %1 = G_ADD %0, %0
 
    ; CHECK: *** Bad machine code: Generic virtual register invalid in a Selected function ***
-   ; CHECK: instruction: %vreg2<def>(s64) = COPY
-   ; CHECK: operand 0: %vreg2<def>
+   ; CHECK: instruction: %2<def>(s64) = COPY
+   ; CHECK: operand 0: %2<def>
    %2(s64) = COPY %x0
 ...

test/CodeGen/AArch64/aarch64-stp-cluster.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -aarch64-enable-stp-suppress=false -o - 2>&1 > /dev/null | FileCheck %s
 
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: stp_i64_scale:BB#0
 ; CHECK:Cluster ld/st SU(4) - SU(3)
 ; CHECK:Cluster ld/st SU(2) - SU(5)
-; CHECK:SU(4):   STRXui %vreg1, %vreg0, 1
-; CHECK:SU(3):   STRXui %vreg1, %vreg0, 2
-; CHECK:SU(2):   STRXui %vreg1, %vreg0, 3
-; CHECK:SU(5):   STRXui %vreg1, %vreg0, 4
+; CHECK:SU(4):   STRXui %1, %0, 1
+; CHECK:SU(3):   STRXui %1, %0, 2
+; CHECK:SU(2):   STRXui %1, %0, 3
+; CHECK:SU(5):   STRXui %1, %0, 4
 define i64 @stp_i64_scale(i64* nocapture %P, i64 %v) {
 entry:
   %arrayidx = getelementptr inbounds i64, i64* %P, i64 3
   store i64 %v, i64* %arrayidx
   %arrayidx1 = getelementptr inbounds i64, i64* %P, i64 2
   store i64 %v, i64* %arrayidx1
   %arrayidx2 = getelementptr inbounds i64, i64* %P, i64 1
   store i64 %v, i64* %arrayidx2
   %arrayidx3 = getelementptr inbounds i64, i64* %P, i64 4
   store i64 %v, i64* %arrayidx3
   ret i64 %v
 }
 
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: stp_i32_scale:BB#0
 ; CHECK:Cluster ld/st SU(4) - SU(3)
 ; CHECK:Cluster ld/st SU(2) - SU(5)
-; CHECK:SU(4):   STRWui %vreg1, %vreg0, 1
-; CHECK:SU(3):   STRWui %vreg1, %vreg0, 2
-; CHECK:SU(2):   STRWui %vreg1, %vreg0, 3
-; CHECK:SU(5):   STRWui %vreg1, %vreg0, 4
+; CHECK:SU(4):   STRWui %1, %0, 1
+; CHECK:SU(3):   STRWui %1, %0, 2
+; CHECK:SU(2):   STRWui %1, %0, 3
+; CHECK:SU(5):   STRWui %1, %0, 4
 define i32 @stp_i32_scale(i32* nocapture %P, i32 %v) {
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %P, i32 3
   store i32 %v, i32* %arrayidx
   %arrayidx1 = getelementptr inbounds i32, i32* %P, i32 2
   store i32 %v, i32* %arrayidx1
   %arrayidx2 = getelementptr inbounds i32, i32* %P, i32 1
   store i32 %v, i32* %arrayidx2
   %arrayidx3 = getelementptr inbounds i32, i32* %P, i32 4
   store i32 %v, i32* %arrayidx3
   ret i32 %v
 }
 
 ; CHECK:********** MI Scheduling **********
 ; CHECK-LABEL:stp_i64_unscale:BB#0 entry
 ; CHECK:Cluster ld/st SU(5) - SU(2)
 ; CHECK:Cluster ld/st SU(4) - SU(3)
-; CHECK:SU(5):   STURXi %vreg1, %vreg0, -32
-; CHECK:SU(2):   STURXi %vreg1, %vreg0, -24
-; CHECK:SU(4):   STURXi %vreg1, %vreg0, -16
-; CHECK:SU(3):   STURXi %vreg1, %vreg0, -8
+; CHECK:SU(5):   STURXi %1, %0, -32
+; CHECK:SU(2):   STURXi %1, %0, -24
+; CHECK:SU(4):   STURXi %1, %0, -16
+; CHECK:SU(3):   STURXi %1, %0, -8
 define void @stp_i64_unscale(i64* nocapture %P, i64 %v) #0 {
 entry:
   %arrayidx = getelementptr inbounds i64, i64* %P, i64 -3
   store i64 %v, i64* %arrayidx
   %arrayidx1 = getelementptr inbounds i64, i64* %P, i64 -1
   store i64 %v, i64* %arrayidx1
   %arrayidx2 = getelementptr inbounds i64, i64* %P, i64 -2
   store i64 %v, i64* %arrayidx2
   %arrayidx3 = getelementptr inbounds i64, i64* %P, i64 -4
   store i64 %v, i64* %arrayidx3
   ret void
 }
 
 ; CHECK:********** MI Scheduling **********
 ; CHECK-LABEL:stp_i32_unscale:BB#0 entry
 ; CHECK:Cluster ld/st SU(5) - SU(2)
 ; CHECK:Cluster ld/st SU(4) - SU(3)
-; CHECK:SU(5):   STURWi %vreg1, %vreg0, -16
-; CHECK:SU(2):   STURWi %vreg1, %vreg0, -12
-; CHECK:SU(4):   STURWi %vreg1, %vreg0, -8
-; CHECK:SU(3):   STURWi %vreg1, %vreg0, -4
+; CHECK:SU(5):   STURWi %1, %0, -16
+; CHECK:SU(2):   STURWi %1, %0, -12
+; CHECK:SU(4):   STURWi %1, %0, -8
+; CHECK:SU(3):   STURWi %1, %0, -4
 define void @stp_i32_unscale(i32* nocapture %P, i32 %v) #0 {
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %P, i32 -3
   store i32 %v, i32* %arrayidx
   %arrayidx1 = getelementptr inbounds i32, i32* %P, i32 -1
   store i32 %v, i32* %arrayidx1
   %arrayidx2 = getelementptr inbounds i32, i32* %P, i32 -2
   store i32 %v, i32* %arrayidx2
   %arrayidx3 = getelementptr inbounds i32, i32* %P, i32 -4
   store i32 %v, i32* %arrayidx3
   ret void
 }
 
 ; CHECK:********** MI Scheduling **********
 ; CHECK-LABEL:stp_double:BB#0
 ; CHECK:Cluster ld/st SU(3) - SU(4)
 ; CHECK:Cluster ld/st SU(2) - SU(5)
-; CHECK:SU(3):   STRDui %vreg1, %vreg0, 1
-; CHECK:SU(4):   STRDui %vreg1, %vreg0, 2
-; CHECK:SU(2):   STRDui %vreg1, %vreg0, 3
-; CHECK:SU(5):   STRDui %vreg1, %vreg0, 4
+; CHECK:SU(3):   STRDui %1, %0, 1
+; CHECK:SU(4):   STRDui %1, %0, 2
+; CHECK:SU(2):   STRDui %1, %0, 3
+; CHECK:SU(5):   STRDui %1, %0, 4
 define void @stp_double(double* nocapture %P, double %v)  {
 entry:
   %arrayidx = getelementptr inbounds double, double* %P, i64 3
   store double %v, double* %arrayidx
   %arrayidx1 = getelementptr inbounds double, double* %P, i64 1
   store double %v, double* %arrayidx1
   %arrayidx2 = getelementptr inbounds double, double* %P, i64 2
   store double %v, double* %arrayidx2
   %arrayidx3 = getelementptr inbounds double, double* %P, i64 4
   store double %v, double* %arrayidx3
   ret void
 }
 
 ; CHECK:********** MI Scheduling **********
 ; CHECK-LABEL:stp_float:BB#0
 ; CHECK:Cluster ld/st SU(3) - SU(4)
 ; CHECK:Cluster ld/st SU(2) - SU(5)
-; CHECK:SU(3):   STRSui %vreg1, %vreg0, 1
-; CHECK:SU(4):   STRSui %vreg1, %vreg0, 2
-; CHECK:SU(2):   STRSui %vreg1, %vreg0, 3
-; CHECK:SU(5):   STRSui %vreg1, %vreg0, 4
+; CHECK:SU(3):   STRSui %1, %0, 1
+; CHECK:SU(4):   STRSui %1, %0, 2
+; CHECK:SU(2):   STRSui %1, %0, 3
+; CHECK:SU(5):   STRSui %1, %0, 4
 define void @stp_float(float* nocapture %P, float %v)  {
 entry:
   %arrayidx = getelementptr inbounds float, float* %P, i64 3
   store float %v, float* %arrayidx
   %arrayidx1 = getelementptr inbounds float, float* %P, i64 1
   store float %v, float* %arrayidx1
   %arrayidx2 = getelementptr inbounds float, float* %P, i64 2
   store float %v, float* %arrayidx2
   %arrayidx3 = getelementptr inbounds float, float* %P, i64 4
   store float %v, float* %arrayidx3
   ret void
 }
 
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: stp_volatile:BB#0
 ; CHECK-NOT: Cluster ld/st
-; CHECK:SU(2):   STRXui %vreg1, %vreg0, 3; mem:Volatile
-; CHECK:SU(3):   STRXui %vreg1, %vreg0, 2; mem:Volatile
-; CHECK:SU(4):   STRXui %vreg1, %vreg0, 1; mem:Volatile
-; CHECK:SU(5):   STRXui %vreg1, %vreg0, 4; mem:Volatile
+; CHECK:SU(2):   STRXui %1, %0, 3; mem:Volatile
+; CHECK:SU(3):   STRXui %1, %0, 2; mem:Volatile
+; CHECK:SU(4):   STRXui %1, %0, 1; mem:Volatile
+; CHECK:SU(5):   STRXui %1, %0, 4; mem:Volatile
 define i64 @stp_volatile(i64* nocapture %P, i64 %v) {
 entry:
   %arrayidx = getelementptr inbounds i64, i64* %P, i64 3
   store volatile i64 %v, i64* %arrayidx
   %arrayidx1 = getelementptr inbounds i64, i64* %P, i64 2
   store volatile i64 %v, i64* %arrayidx1
   %arrayidx2 = getelementptr inbounds i64, i64* %P, i64 1
   store volatile i64 %v, i64* %arrayidx2
   %arrayidx3 = getelementptr inbounds i64, i64* %P, i64 4
   store volatile i64 %v, i64* %arrayidx3
   ret i64 %v
 }
 

test/CodeGen/AArch64/arm64-fast-isel-rem.ll

 ; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
 ; RUN: llc %s -O0 -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
 ; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
 
 ; CHECK-SSA-LABEL: Machine code for function t1
 
-; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr
+; CHECK-SSA: [[QUOTREG:%[0-9]+]]<def> = SDIVWr
 ; CHECK-SSA-NOT: [[QUOTREG]]<def> =
-; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
+; CHECK-SSA: {{%[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
 
 ; CHECK-SSA-LABEL: Machine code for function t2
 
 define i32 @t1(i32 %a, i32 %b) {
 ; CHECK: @t1
 ; CHECK: sdiv [[TMP:w[0-9]+]], w0, w1
 ; CHECK: msub w0, [[TMP]], w1, w0
   %1 = srem i32 %a, %b

test/CodeGen/AArch64/arm64-ldp-cluster.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m1 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck --check-prefix=EXYNOS %s
 
 ; Test ldr clustering.
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldr_int:BB#0
 ; CHECK: Cluster ld/st SU(1) - SU(2)
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
-; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; CHECK: SU(1):   %{{[0-9]+}}<def> = LDRWui
+; CHECK: SU(2):   %{{[0-9]+}}<def> = LDRWui
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldr_int:BB#0
 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
-; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
-; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; EXYNOS: SU(1):   %{{[0-9]+}}<def> = LDRWui
+; EXYNOS: SU(2):   %{{[0-9]+}}<def> = LDRWui
 define i32 @ldr_int(i32* %a) nounwind {
   %p1 = getelementptr inbounds i32, i32* %a, i32 1
   %tmp1 = load i32, i32* %p1, align 2
   %p2 = getelementptr inbounds i32, i32* %a, i32 2
   %tmp2 = load i32, i32* %p2, align 2
   %tmp3 = add i32 %tmp1, %tmp2
   ret i32 %tmp3
 }
 
 ; Test ldpsw clustering
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldp_sext_int:BB#0
 ; CHECK: Cluster ld/st SU(1) - SU(2)
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRSWui
-; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDRSWui
+; CHECK: SU(1):   %{{[0-9]+}}<def> = LDRSWui
+; CHECK: SU(2):   %{{[0-9]+}}<def> = LDRSWui
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldp_sext_int:BB#0
 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
-; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDRSWui
-; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: SU(1):   %{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: SU(2):   %{{[0-9]+}}<def> = LDRSWui
 define i64 @ldp_sext_int(i32* %p) nounwind {
   %tmp = load i32, i32* %p, align 4
   %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
   %tmp1 = load i32, i32* %add.ptr, align 4
   %sexttmp = sext i32 %tmp to i64
   %sexttmp1 = sext i32 %tmp1 to i64
   %add = add nsw i64 %sexttmp1, %sexttmp
   ret i64 %add
 }
 
 ; Test ldur clustering.
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldur_int:BB#0
 ; CHECK: Cluster ld/st SU(2) - SU(1)
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDURWi
-; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDURWi
+; CHECK: SU(1):   %{{[0-9]+}}<def> = LDURWi
+; CHECK: SU(2):   %{{[0-9]+}}<def> = LDURWi
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldur_int:BB#0
 ; EXYNOS: Cluster ld/st SU(2) - SU(1)
-; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDURWi
-; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDURWi
+; EXYNOS: SU(1):   %{{[0-9]+}}<def> = LDURWi
+; EXYNOS: SU(2):   %{{[0-9]+}}<def> = LDURWi
 define i32 @ldur_int(i32* %a) nounwind {
   %p1 = getelementptr inbounds i32, i32* %a, i32 -1
   %tmp1 = load i32, i32* %p1, align 2
   %p2 = getelementptr inbounds i32, i32* %a, i32 -2
   %tmp2 = load i32, i32* %p2, align 2
   %tmp3 = add i32 %tmp1, %tmp2
   ret i32 %tmp3
 }
 
 ; Test sext + zext clustering.
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldp_half_sext_zext_int:BB#0
 ; CHECK: Cluster ld/st SU(3) - SU(4)
-; CHECK: SU(3):   %vreg{{[0-9]+}}<def> = LDRSWui
-; CHECK: SU(4):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
+; CHECK: SU(3):   %{{[0-9]+}}<def> = LDRSWui
+; CHECK: SU(4):   %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldp_half_sext_zext_int:BB#0
 ; EXYNOS: Cluster ld/st SU(3) - SU(4)
-; EXYNOS: SU(3):   %vreg{{[0-9]+}}<def> = LDRSWui
-; EXYNOS: SU(4):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
+; EXYNOS: SU(3):   %{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: SU(4):   %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
 define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
   %tmp0 = load i64, i64* %q, align 4
   %tmp = load i32, i32* %p, align 4
   %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
   %tmp1 = load i32, i32* %add.ptr, align 4
   %sexttmp = sext i32 %tmp to i64
   %sexttmp1 = zext i32 %tmp1 to i64
   %add = add nsw i64 %sexttmp1, %sexttmp
   %add1 = add nsw i64 %add, %tmp0
   ret i64 %add1
 }
 
 ; Test zext + sext clustering.
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldp_half_zext_sext_int:BB#0
 ; CHECK: Cluster ld/st SU(3) - SU(4)
-; CHECK: SU(3):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
-; CHECK: SU(4):   %vreg{{[0-9]+}}<def> = LDRSWui
+; CHECK: SU(3):   %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
+; CHECK: SU(4):   %{{[0-9]+}}<def> = LDRSWui
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldp_half_zext_sext_int:BB#0
 ; EXYNOS: Cluster ld/st SU(3) - SU(4)
-; EXYNOS: SU(3):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
-; EXYNOS: SU(4):   %vreg{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: SU(3):   %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
+; EXYNOS: SU(4):   %{{[0-9]+}}<def> = LDRSWui
 define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
   %tmp0 = load i64, i64* %q, align 4
   %tmp = load i32, i32* %p, align 4
   %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
   %tmp1 = load i32, i32* %add.ptr, align 4
   %sexttmp = zext i32 %tmp to i64
   %sexttmp1 = sext i32 %tmp1 to i64
   %add = add nsw i64 %sexttmp1, %sexttmp
   %add1 = add nsw i64 %add, %tmp0
   ret i64 %add1
 }
 
 ; Verify we don't cluster volatile loads.
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldr_int_volatile:BB#0
 ; CHECK-NOT: Cluster ld/st
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
-; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; CHECK: SU(1):   %{{[0-9]+}}<def> = LDRWui
+; CHECK: SU(2):   %{{[0-9]+}}<def> = LDRWui
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldr_int_volatile:BB#0
 ; EXYNOS-NOT: Cluster ld/st
-; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
-; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; EXYNOS: SU(1):   %{{[0-9]+}}<def> = LDRWui
+; EXYNOS: SU(2):   %{{[0-9]+}}<def> = LDRWui
 define i32 @ldr_int_volatile(i32* %a) nounwind {
   %p1 = getelementptr inbounds i32, i32* %a, i32 1
   %tmp1 = load volatile i32, i32* %p1, align 2
   %p2 = getelementptr inbounds i32, i32* %a, i32 2
   %tmp2 = load volatile i32, i32* %p2, align 2
   %tmp3 = add i32 %tmp1, %tmp2
   ret i32 %tmp3
 }
 
 ; Test ldq clustering (no clustering for Exynos).
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldq_cluster:BB#0
 ; CHECK: Cluster ld/st SU(1) - SU(3)
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRQui
-; CHECK: SU(3):   %vreg{{[0-9]+}}<def> = LDRQui
+; CHECK: SU(1):   %{{[0-9]+}}<def> = LDRQui
+; CHECK: SU(3):   %{{[0-9]+}}<def> = LDRQui
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldq_cluster:BB#0
 ; EXYNOS-NOT: Cluster ld/st
 define <2 x i64> @ldq_cluster(i64* %p) {
   %a1 = bitcast i64* %p to <2 x i64>*
   %tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8
   %add.ptr2 = getelementptr inbounds i64, i64* %p, i64 2
   %a2 = bitcast i64* %add.ptr2 to <2 x i64>*
   %tmp2 = add nsw <2 x i64> %tmp1, %tmp1
   %tmp3 = load <2 x i64>, <2 x i64>* %a2, align 8
   %res  = mul nsw <2 x i64> %tmp2, %tmp3
   ret <2 x i64> %res
 }

test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
 ;
 ; For Cortex-A53, shiftable operands that are not actually shifted
 ; are not needed for an additional two cycles.
 ;
 ; CHECK: ********** MI Scheduling **********
 ; CHECK: shiftable
-; CHECK: SU(2):   %vreg2<def> = SUBXri %vreg1, 20, 0
+; CHECK: SU(2):   %2<def> = SUBXri %1, 20, 0
 ; CHECK:   Successors:
-; CHECK-NEXT:    SU(4): Data Latency=1 Reg=%vreg2
-; CHECK-NEXT:    SU(3): Data Latency=2 Reg=%vreg2
+; CHECK-NEXT:    SU(4): Data Latency=1 Reg=%2
+; CHECK-NEXT:    SU(3): Data Latency=2 Reg=%2
 ; CHECK: ********** INTERVALS **********
 define i64 @shiftable(i64 %A, i64 %B) {
         %tmp0 = sub i64 %B, 20
         %tmp1 = shl i64 %tmp0, 5;
         %tmp2 = add i64 %A, %tmp1;
         %tmp3 = add i64 %A, %tmp0
         %tmp4 = mul i64 %tmp2, %tmp3
 
         ret i64 %tmp4
 }

test/CodeGen/AArch64/arm64-misched-memdep-bug.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
 ;
 ; Test for bug in misched memory dependency calculation.
 ;
 ; CHECK: ********** MI Scheduling **********
 ; CHECK: misched_bug:BB#0 entry
-; CHECK: SU(2):   %vreg2<def> = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vreg0
+; CHECK: SU(2):   %2<def> = LDRWui %0, 1; mem:LD4[%ptr1_plus1] GPR32:%2 GPR64common:%0
 ; CHECK:   Successors:
-; CHECK-NEXT:    SU(5): Data Latency=4 Reg=%vreg2
+; CHECK-NEXT:    SU(5): Data Latency=4 Reg=%2
 ; CHECK-NEXT:    SU(4): Ord  Latency=0
-; CHECK: SU(3):   STRWui %wzr, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
+; CHECK: SU(3):   STRWui %wzr, %0, 0; mem:ST4[%ptr1] GPR64common:%0
 ; CHECK:   Successors:
 ; CHECK: SU(4): Ord  Latency=0
-; CHECK: SU(4):   STRWui %wzr, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
-; CHECK: SU(5):   %w0<def> = COPY %vreg2; GPR32:%vreg2
+; CHECK: SU(4):   STRWui %wzr, %1, 0; mem:ST4[%ptr2] GPR64common:%1
+; CHECK: SU(5):   %w0<def> = COPY %2; GPR32:%2
 ; CHECK: ** ScheduleDAGMI::schedule picking next node
 define i32 @misched_bug(i32* %ptr1, i32* %ptr2) {
 entry:
   %ptr1_plus1 = getelementptr inbounds i32, i32* %ptr1, i64 1
   %val1 = load i32, i32* %ptr1_plus1, align 4
   store i32 0, i32* %ptr1, align 4
   store i32 0, i32* %ptr2, align 4
   ret i32 %val1
 }

test/CodeGen/AArch64/tailcall_misched_graph.ll

 ; time.
 
 ; CHECK: Frame Objects
 ; CHECK:  fi#-4: {{.*}} fixed, at location [SP+8]
 ; CHECK:  fi#-3: {{.*}} fixed, at location [SP]
 ; CHECK:  fi#-2: {{.*}} fixed, at location [SP+8]
 ; CHECK:  fi#-1: {{.*}} fixed, at location [SP]
 
-; CHECK:  [[VRA:%vreg.*]]<def> = LDRXui <fi#-1>
-; CHECK:  [[VRB:%vreg.*]]<def> = LDRXui <fi#-2>
-; CHECK:  STRXui %vreg{{.*}}, <fi#-4>
+; CHECK:  [[VRA:%.*]]<def> = LDRXui <fi#-1>
+; CHECK:  [[VRB:%.*]]<def> = LDRXui <fi#-2>
+; CHECK:  STRXui %{{.*}}, <fi#-4>
 ; CHECK:  STRXui [[VRB]], <fi#-3>
 
 ; Make sure that there is an dependence edge between fi#-2 and fi#-4.
 ; Without this edge the scheduler would be free to move the store accross the load.
 
 ; CHECK: SU({{.*}}):   [[VRB]]<def> = LDRXui <fi#-2>
 ; CHECK-NOT: SU
 ; CHECK:  Successors:
 ; CHECK:   SU([[DEPSTOREB:.*]]): Ord  Latency=0
 ; CHECK:   SU([[DEPSTOREA:.*]]): Ord  Latency=0
 
-; CHECK: SU([[DEPSTOREA]]):   STRXui %vreg{{.*}}, <fi#-4>
-; CHECK: SU([[DEPSTOREB]]):   STRXui %vreg{{.*}}, <fi#-3>
+; CHECK: SU([[DEPSTOREA]]):   STRXui %{{.*}}, <fi#-4>
+; CHECK: SU([[DEPSTOREB]]):   STRXui %{{.*}}, <fi#-3>

test/CodeGen/AMDGPU/lds-output-queue.ll

 ; has been declared in the local memory space:
 ;
 ;  %0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index
 ;  %1 = load i32, i32 addrspace(3)* %0
 ;  %2 = load i32, i32 addrspace(1)* %in
 ;
 ; The instruction selection phase will generate ISA that looks like this:
 ; %OQAP = LDS_READ_RET
-; %vreg0 = MOV %OQAP
-; %vreg1 = VTX_READ_32
-; %vreg2 = ADD_INT %vreg1, %vreg0
+; %0 = MOV %OQAP
+; %1 = VTX_READ_32
+; %2 = ADD_INT %1, %0
 ;
 ; The bottom scheduler will schedule the two ALU instructions first:
 ;
 ; UNSCHEDULED:
 ; %OQAP = LDS_READ_RET
-; %vreg1 = VTX_READ_32
+; %1 = VTX_READ_32
 ;
 ; SCHEDULED:
 ;
 ; vreg0 = MOV %OQAP
-; vreg2 = ADD_INT %vreg1, %vreg2
+; vreg2 = ADD_INT %1, %2
 ;
 ; The lack of proper aliasing results in the local memory read (LDS_READ_RET)
 ; to consider the global memory read (VTX_READ_32) has a chain dependency, so
 ; the global memory read will always be scheduled first.  This will give us a
 ; final program which looks like this:
 ;
 ; Alu clause:
 ; %OQAP = LDS_READ_RET
 ; VTX clause:
-; %vreg1 = VTX_READ_32
+; %1 = VTX_READ_32
 ; Alu clause:
 ; vreg0 = MOV %OQAP
-; vreg2 = ADD_INT %vreg1, %vreg2
+; vreg2 = ADD_INT %1, %2
 ;
 ; This is an illegal program because the OQAP def and use know occur in
 ; different ALU clauses.
 ;
 ; This test checks this scenario and makes sure it doesn't result in an
 ; illegal program.  For now, we have fixed this issue by merging the
 ; LDS_READ_RET and MOV together during instruction selection and then
 ; expanding them after scheduling.  Once the scheduler has better alias

test/CodeGen/AMDGPU/liveness.mir

 # RUN: llc -march=amdgcn -run-pass liveintervals -verify-machineinstrs -o /dev/null -debug-only=regalloc %s 2>&1 | FileCheck %s
 # REQUIRES: asserts
 # We currently maintain a main liveness range which operates like a superset of
 # all subregister liveranges. We may need to create additional SSA values at
 # merge point in this main liverange even though none of the subregister
 # liveranges needed it.
 #
 # Should see three distinct value numbers:
-# CHECK: %vreg0 [{{.*}}:0)[{{.*}}:1)[{{.*}}:2) 0@{{[0-9]+[Berd]}} 1@{{[0-9]+[Berd]}} 2@{{[0-9]+B-phi}}
+# CHECK: %0 [{{.*}}:0)[{{.*}}:1)[{{.*}}:2) 0@{{[0-9]+[Berd]}} 1@{{[0-9]+[Berd]}} 2@{{[0-9]+B-phi}}
 --- |
   define amdgpu_kernel void @test0() { ret void }
 ...
 ---
 name: test0
 registers:
   - { id: 0, class: sreg_64 }
 body: |

test/CodeGen/AMDGPU/spill-empty-live-interval.mir

 # RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s
 # https://bugs.llvm.org/show_bug.cgi?id=33620
 
 ---
-# This would assert due to the empty live interval created for %vreg9
+# This would assert due to the empty live interval created for %9
 # on the last S_NOP with an undef subreg use.
 
 # CHECK-LABEL: name: expecting_non_empty_interval
 
 # CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit %exec
 # CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 8 into %stack.0, align 4)
 # CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit %exec
 # CHECK-NEXT: dead %2:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit %exec

test/CodeGen/AMDGPU/subreg-intervals.mir

 # RUN: llc -march=amdgcn -run-pass liveintervals -debug-only=regalloc -o /dev/null %s 2>&1 | FileCheck %s
 # REQUIRES: asserts
 
 # CHECK: INTERVALS
-# CHECK: vreg0
+# CHECK: %0
 # CHECK-LABEL: Machine code for function test0:
 
 # CHECK: INTERVALS
-# CHECK: vreg0
+# CHECK: %0
 # CHECK-LABEL: Machine code for function test1:
 
 --- |
   define amdgpu_kernel void @test0() { ret void }
   define amdgpu_kernel void @test1() { ret void }
 ...
 ---
 name: test0

test/CodeGen/ARM/2011-11-14-EarlyClobber.ll

 ; RUN: llc < %s -mcpu=cortex-a8 -verify-regalloc
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
 target triple = "thumbv7-apple-ios"
 
 ; This test calls shrinkToUses with an early-clobber redefined live range during
 ; spilling.
 ;
-;   Shrink: %vreg47,1.158257e-02 = [384r,400e:0)[400e,420r:1)  0@384r 1@400e
+;   Shrink: %47,1.158257e-02 = [384r,400e:0)[400e,420r:1)  0@384r 1@400e
 ;
 ; The early-clobber instruction is an str:
 ;
-;   %vreg12<earlyclobber,def> = t2STR_PRE %vreg6, %vreg12, 32, pred:14, pred:_
+;   %12<earlyclobber,def> = t2STR_PRE %6, %12, 32, pred:14, pred:_
 ;
 ; This tests that shrinkToUses handles the EC redef correctly.
 
 %struct.Transform_Struct.0.11.12.17.43.46.56.58.60 = type { [4 x [4 x double]] }
 
 define void @Compute_Axis_Rotation_Transform(%struct.Transform_Struct.0.11.12.17.43.46.56.58.60* nocapture %transform, double* nocapture %V1, double %angle) nounwind {
 entry:
   store double 1.000000e+00, double* null, align 4

test/CodeGen/ARM/Windows/dbzchk.ll

 ; CHECK-CFG-DAG: BB#0
 ; CHECK-CFG-DAG: t2Bcc <BB#2>
 ; CHECK-CFG-DAG: t2B <BB#1>
 
 ; CHECK-CFG-DAG: BB#1
 ; CHECK-CFG-DAG: t2B <BB#3>
 
 ; CHECK-CFG-DAG: BB#2
-; CHECK-CFG-DAG: tCMPi8 %vreg{{[0-9]}}, 0
+; CHECK-CFG-DAG: tCMPi8 %{{[0-9]}}, 0
 ; CHECK-CFG-DAG: t2Bcc <BB#5>
 
 ; CHECK-CFG-DAG: BB#4
 
 ; CHECK-CFG-DAG: BB#3
 ; CHECK-CFG-DAG: tBX_RET
 
 ; CHECK-CFG-DAG: BB#5

test/CodeGen/ARM/crash-greedy.ll

; CHECK: vldr
   %sub149 = fsub double %sub143, %div148
   %conv150 = fptrunc double %sub149 to float
   store float %conv150, float* %ret_df, align 4
   ret void
 }
 
 ; CHECK: insert_elem
 ; This test has a sub-register copy with a kill flag:
-;   %vreg6:ssub_3<def> = COPY %vreg6:ssub_2<kill>; QPR_VFP2:%vreg6
+;   %6:ssub_3<def> = COPY %6:ssub_2<kill>; QPR_VFP2:%6
 ; The rewriter must do something sensible with that, or the scavenger crashes.
 define void @insert_elem() nounwind {
 entry:
   br i1 undef, label %if.end251, label %if.then84
 
 if.then84:                                        ; preds = %entry
   br i1 undef, label %if.end251, label %if.then195
 

test/CodeGen/ARM/misched-copy-arm.ll

for.end:                                          ; preds = %for.body, %entry
   %s.0.lcssa = phi i32 [ 0, %entry ], [ %mul, %for.body ]
   ret i32 %s.0.lcssa
 }
 
 
 ; This case was a crasher in constrainLocalCopy.
 ; The problem was the t2LDR_PRE defining both the global and local lrg.
 ; CHECK-LABEL: *** Final schedule for BB#5 ***
-; CHECK: %[[R4:vreg[0-9]+]]<def>, %[[R1:vreg[0-9]+]]<def,tied2> = t2LDR_PRE %[[R1]]<tied1>
-; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R1]]
-; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R4]]
+; CHECK: %[[R4:[0-9]+]]<def>, %[[R1:[0-9]+]]<def,tied2> = t2LDR_PRE %[[R1]]<tied1>
+; CHECK: %{{[0-9]+}}<def> = COPY %[[R1]]
+; CHECK: %{{[0-9]+}}<def> = COPY %[[R4]]
 ; CHECK-LABEL: MACHINEINSTRS
 %struct.rtx_def = type { [4 x i8], [1 x %union.rtunion_def] }
 %union.rtunion_def = type { i64 }
 
 ; Function Attrs: nounwind ssp
 declare hidden fastcc void @df_ref_record(i32* nocapture, %struct.rtx_def*, %struct.rtx_def**, %struct.rtx_def*, i32, i32) #0
 
 ; Function Attrs: nounwind ssp

test/CodeGen/ARM/misched-int-basic-thumb2.mir

entry:
     %conv1130 = zext i32 %add10 to i64
     %mul12 = mul nuw nsw i64 %conv1130, %conv1130
     %mul13 = mul nsw i64 %mul12, %mul12
     %add14 = add nuw nsw i64 %mul13, %mul12
     ret i64 %add14
   }
 #
 # CHECK:       ********** MI Scheduling **********
-# CHECK:       SU(2):   %vreg2<def> = t2MOVi32imm <ga:@g1>; rGPR:%vreg2
+# CHECK:       SU(2):   %2<def> = t2MOVi32imm <ga:@g1>; rGPR:%2
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 2
 # CHECK_R52:   Latency    : 2
 #
-# CHECK:       SU(3):   %vreg3<def> = t2LDRi12 %vreg2, 0, pred:14, pred:_; mem:LD4[@g1](dereferenceable) rGPR:%vreg3,%vreg2
+# CHECK:       SU(3):   %3<def> = t2LDRi12 %2, 0, pred:14, pred:_; mem:LD4[@g1](dereferenceable) rGPR:%3,%2
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 3
 # CHECK_R52:   Latency    : 4
 #
-# CHECK :      SU(6):   %vreg6<def> = t2ADDrr %vreg3, %vreg3, pred:14, pred:_, opt:_; rGPR:%vreg6,%vreg3,%vreg3
+# CHECK :      SU(6):   %6<def> = t2ADDrr %3, %3, pred:14, pred:_, opt:_; rGPR:%6,%3,%3
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 1
 # CHECK_R52:   Latency    : 3
 
-# CHECK:       SU(7):   %vreg7<def> = t2SDIV %vreg6, %vreg5, pred:14, pred:_; rGPR:%vreg7,%vreg6,%vreg5
+# CHECK:       SU(7):   %7<def> = t2SDIV %6, %5, pred:14, pred:_; rGPR:%7,%6,%5
 # CHECK_A9:    Latency    : 0
 # CHECK_SWIFT: Latency    : 14
 # CHECK_R52:   Latency    : 8
 
-# CHECK:       SU(8):   t2STRi12 %vreg7, %vreg2, 0, pred:14, pred:_; mem:ST4[@g1] rGPR:%vreg7,%vreg2
+# CHECK:       SU(8):   t2STRi12 %7, %2, 0, pred:14, pred:_; mem:ST4[@g1] rGPR:%7,%2
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 0
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(9):   %vreg8<def> = t2SMULBB %vreg1, %vreg1, pred:14, pred:_; rGPR:%vreg8,%vreg1,%vreg1
+# CHECK:       SU(9):   %8<def> = t2SMULBB %1, %1, pred:14, pred:_; rGPR:%8,%1,%1
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(10):   %vreg9<def> = t2SMLABB %vreg0, %vreg0, %vreg8, pred:14, pred:_; rGPR:%vreg9,%vreg0,%vreg0,%vreg8
+# CHECK:       SU(10):   %9<def> = t2SMLABB %0, %0, %8, pred:14, pred:_; rGPR:%9,%0,%0,%8
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(11):   %vreg10<def> = t2UXTH %vreg9, 0, pred:14, pred:_; rGPR:%vreg10,%vreg9
+# CHECK:       SU(11):   %10<def> = t2UXTH %9, 0, pred:14, pred:_; rGPR:%10,%9
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 1
 # CHECK_R52:   Latency    : 3
 #
-# CHECK:       SU(12):   %vreg11<def> = t2MUL %vreg10, %vreg7, pred:14, pred:_; rGPR:%vreg11,%vreg10,%vreg7
+# CHECK:       SU(12):   %11<def> = t2MUL %10, %7, pred:14, pred:_; rGPR:%11,%10,%7
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(13):   %vreg12<def> = t2MLA %vreg11, %vreg11, %vreg11, pred:14, pred:_; rGPR:%vreg12,%vreg11,%vreg11,%vreg11
+# CHECK:       SU(13):   %12<def> = t2MLA %11, %11, %11, pred:14, pred:_; rGPR:%12,%11,%11,%11
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(14):   %vreg13<def>, %vreg14<def> = t2UMULL %vreg12, %vreg12, pred:14, pred:_; rGPR:%vreg13,%vreg14,%vreg12,%vreg12
+# CHECK:       SU(14):   %13<def>, %14<def> = t2UMULL %12, %12, pred:14, pred:_; rGPR:%13,%14,%12,%12
 # CHECK_A9:    Latency    : 3
 # CHECK_SWIFT: Latency    : 5
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(18):   %vreg19<def,tied4>, %vreg20<def,tied5> = t2UMLAL %vreg12, %vreg12, %vreg19<tied0>, %vreg20<tied1>, pred:14, pred:_; rGPR:%vreg19,%vreg20,%vreg12,%vreg12,%vreg20
+# CHECK:       SU(18):   %19<def,tied4>, %20<def,tied5> = t2UMLAL %12, %12, %19<tied0>, %20<tied1>, pred:14, pred:_; rGPR:%19,%20,%12,%12,%20
 # CHECK_A9:    Latency    : 3
 # CHECK_SWIFT: Latency    : 7
 # CHECK_R52:   Latency    : 4
 # CHECK:  ** ScheduleDAGMILive::schedule picking next node
 ...
 ---
 name:            foo
 alignment:       1

test/CodeGen/ARM/misched-int-basic.mir

entry:
     %conv1130 = zext i32 %add10 to i64
     %mul12 = mul nuw nsw i64 %conv1130, %conv1130
     %mul13 = mul nsw i64 %mul12, %mul12
     %add14 = add nuw nsw i64 %mul13, %mul12
     ret i64 %add14
   }
 
 # CHECK:       ********** MI Scheduling **********
-# CHECK:       SU(2):   %vreg2<def> = SMULBB %vreg1, %vreg1, pred:14, pred:_; GPR:%vreg2,%vreg1,%vreg1
+# CHECK:       SU(2):   %2<def> = SMULBB %1, %1, pred:14, pred:_; GPR:%2,%1,%1
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(3):   %vreg3<def> = SMLABB %vreg0, %vreg0, %vreg2, pred:14, pred:_; GPRnopc:%vreg3,%vreg0,%vreg0 GPR:%vreg2
+# CHECK:       SU(3):   %3<def> = SMLABB %0, %0, %2, pred:14, pred:_; GPRnopc:%3,%0,%0 GPR:%2
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(4):   %vreg4<def> = UXTH %vreg3, 0, pred:14, pred:_; GPRnopc:%vreg4,%vreg3
+# CHECK:       SU(4):   %4<def> = UXTH %3, 0, pred:14, pred:_; GPRnopc:%4,%3
 # CHECK_A9:    Latency    : 1
 # CHECK_SWIFT: Latency    : 1
 # CHECK_R52:   Latency    : 3
 #
-# CHECK:       SU(5):   %vreg5<def> = MUL %vreg4, %vreg4, pred:14, pred:_, opt:_; GPRnopc:%vreg5,%vreg4,%vreg4
+# CHECK:       SU(5):   %5<def> = MUL %4, %4, pred:14, pred:_, opt:_; GPRnopc:%5,%4,%4
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(6):   %vreg6<def> = MLA %vreg5, %vreg5, %vreg5, pred:14, pred:_, opt:_; GPRnopc:%vreg6,%vreg5,%vreg5,%vreg5
+# CHECK:       SU(6):   %6<def> = MLA %5, %5, %5, pred:14, pred:_, opt:_; GPRnopc:%6,%5,%5,%5
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 4
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(7):   %vreg7<def>, %vreg8<def> = UMULL %vreg6, %vreg6, pred:14, pred:_, opt:_; GPRnopc:%vreg7,%vreg8,%vreg6,%vreg6
+# CHECK:       SU(7):   %7<def>, %8<def> = UMULL %6, %6, pred:14, pred:_, opt:_; GPRnopc:%7,%8,%6,%6
 # CHECK_A9:    Latency    : 3
 # CHECK_SWIFT: Latency    : 5
 # CHECK_R52:   Latency    : 4
 #
-# CHECK:       SU(11):   %vreg13<def,tied4>, %vreg14<def,tied5> = UMLAL %vreg6, %vreg6, %vreg13<tied0>, %vreg14<tied1>, pred:14, pred:_, opt:_; GPR:%vreg13 GPRnopc:%vreg14,%vreg6,%vreg6
+# CHECK:       SU(11):   %13<def,tied4>, %14<def,tied5> = UMLAL %6, %6, %13<tied0>, %14<tied1>, pred:14, pred:_, opt:_; GPR:%13 GPRnopc:%14,%6,%6
 # CHECK_SWIFT: Latency    : 7
 # CHECK_A9:    Latency    : 3
 # CHECK_R52:   Latency    : 4
 # CHECK:  ** ScheduleDAGMILive::schedule picking next node
 ...
 ---
 name:            foo
 alignment:       2

test/CodeGen/ARM/single-issue-r52.mir

define <8 x i8> @foo(i8* %A) {
     %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 1
     %tmp4 = add <8 x i8> %tmp2, %tmp3
     ret <8 x i8> %tmp4
   }
   declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8*, i32)
 
 # CHECK: ********** MI Scheduling **********
 # CHECK: ScheduleDAGMILive::schedule starting
-# CHECK: SU(1):   %vreg1<def> = VLD4d8Pseudo %vreg0, 8, pred:14, pred:_; mem:LD32[%A](align=8) QQPR:%vreg1 GPR:%vreg0
+# CHECK: SU(1):   %1<def> = VLD4d8Pseudo %0, 8, pred:14, pred:_; mem:LD32[%A](align=8) QQPR:%1 GPR:%0
 # CHECK: Latency            : 8
 # CHECK: Single Issue       : true;
-# CHECK: SU(2):   %vreg4<def> = VADDv8i8 %vreg1:dsub_0, %vreg1:dsub_1, pred:14, pred:_; DPR:%vreg4 QQPR:%vreg1
+# CHECK: SU(2):   %4<def> = VADDv8i8 %1:dsub_0, %1:dsub_1, pred:14, pred:_; DPR:%4 QQPR:%1
 # CHECK: Latency            : 5
 # CHECK: Single Issue       : false;
-# CHECK: SU(3):   %vreg5<def>, %vreg6<def> = VMOVRRD %vreg4, pred:14, pred:_; GPR:%vreg5,%vreg6 DPR:%vreg4
+# CHECK: SU(3):   %5<def>, %6<def> = VMOVRRD %4, pred:14, pred:_; GPR:%5,%6 DPR:%4
 # CHECK: Latency            : 4
 # CHECK: Single Issue       : false;
 
-# TOPDOWN: Scheduling SU(1) %vreg1<def> = VLD4d8Pseudo
+# TOPDOWN: Scheduling SU(1) %1<def> = VLD4d8Pseudo
 # TOPDOWN: Bump cycle to end group
-# TOPDOWN: Scheduling SU(2) %vreg4<def> = VADDv8i8
+# TOPDOWN: Scheduling SU(2) %4<def> = VADDv8i8
 
-# BOTTOMUP: Scheduling SU(2) %vreg4<def> = VADDv8i8
-# BOTTOMUP: Scheduling SU(1) %vreg1<def> = VLD4d8Pseudo
+# BOTTOMUP: Scheduling SU(2) %4<def> = VADDv8i8
+# BOTTOMUP: Scheduling SU(1) %1<def> = VLD4d8Pseudo
 # BOTTOMUP: Bump cycle to begin group
 
 ...
 ---
 name:            foo
 alignment:       2
 exposesReturnsTwice: false
 legalized:       false

test/CodeGen/ARM/subreg-remat.ll

 ; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source -no-integrated-as | FileCheck %s
 target triple = "thumbv7-apple-ios"
 ; <rdar://problem/10032939>
 ;
 ; The vector %v2 is built like this:
 ;
-;   %vreg6:ssub_1<def> = ...
-;   %vreg6:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:_; mem:LD4[ConstantPool] DPR_VFP2:%vreg6
+;   %6:ssub_1<def> = ...
+;   %6:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:_; mem:LD4[ConstantPool] DPR_VFP2:%6
 ;
-; When %vreg6 spills, the VLDRS constant pool load cannot be rematerialized
+; When %6 spills, the VLDRS constant pool load cannot be rematerialized
 ; since it implicitly reads the ssub_1 sub-register.
 ;
 ; CHECK: f1
 ; CHECK: vmov    d0, r0, r0
 ; CHECK: vldr s1, LCPI
 ; The vector must be spilled:
 ; CHECK: vstr d0,
 ; CHECK: asm clobber d0
 ; And reloaded after the asm:
 ; CHECK: vldr [[D16:d[0-9]+]],
 ; CHECK: vstr [[D16]], [r1]
 define void @f1(float %x, <2 x float>* %p) {
   %v1 = insertelement <2 x float> undef, float %x, i32 0
   %v2 = insertelement <2 x float> %v1, float 0x400921FB60000000, i32 1
   %y = call double asm sideeffect "asm clobber $0", "=w,0,~{d1},~{d2},~{d3},~{d4},~{d5},~{d6},~{d7},~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15},~{d16},~{d17},~{d18},~{d19},~{d20},~{d21},~{d22},~{d23},~{d24},~{d25},~{d26},~{d27},~{d28},~{d29},~{d30},~{d31}"(<2 x float> %v2) nounwind
   store <2 x float> %v2, <2 x float>* %p, align 8
   ret void
 }
 
 ; On the other hand, when the partial redef doesn't read the full register
 ; because the bits are undef, we should rematerialize.  The vector is now built
 ; like this:
 ;
-;   %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:_, %vreg2<imp-def>; mem:LD4[ConstantPool]
+;   %2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:_, %2<imp-def>; mem:LD4[ConstantPool]
 ;
 ; The extra <imp-def> operand indicates that the instruction fully defines the
 ; virtual register.  It doesn't read the old value.
 ;
 ; CHECK: f2
 ; CHECK: vldr s0, LCPI
 ; The vector must not be spilled:
 ; CHECK-NOT: vstr

test/CodeGen/Hexagon/circ_ldd_bug.ll

 ; RUN: llc -O2 < %s
 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
 target triple = "hexagon"
 
 ; We would fail on this file with:
 ; Unimplemented
 ; UNREACHABLE executed at llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp:615!
 ; This happened because after unrolling a loop with a ldd_circ instruction we
 ; would have several TFCR and ldd_circ instruction sequences.
-; %vreg0 (CRRegs) = TFCR %vreg0 (IntRegs)
+; %0 (CRRegs) = TFCR %0 (IntRegs)
 ;                 = ldd_circ( , , vreg0)
-; %vreg1 (CRRegs) = TFCR %vreg1 (IntRegs)
+; %1 (CRRegs) = TFCR %1 (IntRegs)
 ;                 = ldd_circ( , , vreg0)
 ; The scheduler would move the CRRegs to the top of the loop. The allocator
 ; would try to spill the CRRegs after running out of them. We don't have code to
 ; spill CRRegs and the above assertion would be triggered.
 declare i8* @llvm.hexagon.circ.ldd(i8*, i8*, i32, i32) nounwind
 
 define i32 @test(i16 zeroext %var0, i16* %var1, i16 signext %var2, i16* nocapture %var3) nounwind {
 entry:

test/CodeGen/Hexagon/post-inc-aa-metadata.ll

 ; RUN: llc -march=hexagon -debug-only=isel < %s 2>&1 | FileCheck %s
 ; REQUIRES: asserts
 
 ; Check that the generated post-increment load has TBAA information.
 ; CHECK-LABEL: Machine code for function fred:
-; CHECK: = V6_vL32b_pi %vreg{{[0-9]+}}<tied1>, 64; mem:LD64[{{.*}}](tbaa=
+; CHECK: = V6_vL32b_pi %{{[0-9]+}}<tied1>, 64; mem:LD64[{{.*}}](tbaa=
 
 target triple = "hexagon"
 
 ; Function Attrs: norecurse nounwind
 define void @fred(<16 x i32>* nocapture %p, <16 x i32>* nocapture readonly %q, i32 %n) local_unnamed_addr #0 {
 entry:
   %tobool2 = icmp eq i32 %n, 0
   br i1 %tobool2, label %while.end, label %while.body

test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll

 
 ; CHECK-LABEL: foo
 ; CHECK-LABEL: SU({{.*}}):   SW_RI{{.*}}, 0,
 ; CHECK:  # preds left       : 2
 ; CHECK:  # succs left       : 0
 ; CHECK-LABEL: SU({{.*}}):   SW_RI{{.*}}, 4,
 ; CHECK:  # preds left       : 2
 ; CHECK:  # succs left       : 0
-; CHECK-LABEL: SU({{.*}}):   %vreg{{.*}}<def> = LDW_RI{{.*}}, 12,
+; CHECK-LABEL: SU({{.*}}):   %{{.*}}<def> = LDW_RI{{.*}}, 12,
 ; CHECK:  # preds left       : 1
 ; CHECK:  # succs left       : 4
 ; CHECK-LABEL: SU({{.*}}):   STH_RI{{.*}}, 10,
 ; CHECK:  # preds left       : 2
 ; CHECK:  # succs left       : 0
 ; CHECK-LABEL: SU({{.*}}):   STH_RI{{.*}}, 12,
 ; CHECK:  # preds left       : 3
 ; CHECK:  # succs left       : 0

test/CodeGen/PowerPC/quadint-return.ll

 ; REQUIRES: asserts
 ; RUN: llc -verify-machineinstrs -O0 -debug -o - < %s 2>&1 | FileCheck %s
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define i128 @foo() nounwind {
 entry:
   %x = alloca i128, align 16
   store i128 27, i128* %x, align 16
   %0 = load i128, i128* %x, align 16
   ret i128 %0
 }
 
 ; CHECK: ********** Function: foo
 ; CHECK: ********** FAST REGISTER ALLOCATION **********
-; CHECK: %x3<def> = COPY %vreg
-; CHECK-NEXT: %x4<def> = COPY %vreg
+; CHECK: %x3<def> = COPY %{{[0-9]+}}
+; CHECK-NEXT: %x4<def> = COPY %{{[0-9]+}}
 ; CHECK-NEXT: BLR

test/CodeGen/WebAssembly/dbgvalue.ll

 ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=wasm32-unknown-unknown-wasm | FileCheck %s
 
 ; CHECK: BB#0
-; CHECK: #DEBUG_VALUE: usage:self <- %vreg4
+; CHECK: #DEBUG_VALUE: usage:self <- %4
 ; CHECK: BB#1
 ; CHECK: DW_TAG_variable
 source_filename = "test/CodeGen/WebAssembly/dbgvalue.ll"
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown-wasm"
 
 @key = external local_unnamed_addr global [15 x i8], align 1
 @.str = external unnamed_addr constant [33 x i8], align 1

test/CodeGen/X86/GlobalISel/x86_64-fallback.ll

 ; RUN: llc -O0 -mtriple=x86_64-linux-gnu -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err
 ; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out
 ; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err
 ; This file checks that the fallback path to selection dag works.
 ; The test is fragile in the sense that it must be updated to expose
 ; something that fails with global-isel.
 ; When we cannot produce a test case anymore, that means we can remove
 ; the fallback path.
 
 ; Check that we fallback on invoke translation failures.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg1, %vreg0; mem:ST10[%ptr](align=16) (in function: test_x86_fp80_dump)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %1, %0; mem:ST10[%ptr](align=16) (in function: test_x86_fp80_dump)
 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_x86_fp80_dump
 ; FALLBACK-WITH-REPORT-OUT-LABEL: test_x86_fp80_dump:
 define void @test_x86_fp80_dump(x86_fp80* %ptr){
   store x86_fp80 0xK4002A000000000000000, x86_fp80* %ptr, align 16
   ret void
 }
 
 ; Check that we fallback on byVal argument

test/CodeGen/X86/cmovcmov.ll

 }
 
 attributes #0 = { nounwind }
 
 @g8 = global i8 0
 
 ; The following test failed because llvm had a bug where a structure like:
 ;
-; %vreg12<def> = CMOV_GR8 %vreg7, %vreg11 ... (lt)
-; %vreg13<def> = CMOV_GR8 %vreg12, %vreg11 ... (gt)
+; %12<def> = CMOV_GR8 %7, %11 ... (lt)
+; %13<def> = CMOV_GR8 %12, %11 ... (gt)
 ;
 ; was lowered to:
 ;
 ; The first two cmovs got expanded to:
 ; BB#0:
 ;   JL_1 BB#9
 ; BB#7:
 ;   JG_1 BB#9
 ; BB#8:
 ; BB#9:
 ;   vreg12 = phi(vreg7, BB#8, vreg11, BB#0, vreg12, BB#7)
 ;   vreg13 = COPY vreg12
-; Which was invalid as %vreg12 is not the same value as %vreg13
+; Which was invalid as %12 is not the same value as %13
 
 ; CHECK-LABEL: no_cascade_opt:
 ; CMOV-DAG: cmpl %edx, %esi
 ; CMOV-DAG: movb $20, %al
 ; CMOV-DAG: movb $20, %dl
 ; CMOV:   jge [[BB2:.LBB[0-9_]+]]
 ; CMOV:   jle [[BB3:.LBB[0-9_]+]]
 ; CMOV: [[BB0:.LBB[0-9_]+]]

test/CodeGen/X86/coalescer-dce.ll

 ; RUN: llc < %s -verify-machineinstrs -disable-fp-elim -disable-machine-dce -verify-coalescing
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-macosx10.7.0"
 
 ; This test case has a sub-register join followed by a remat:
 ;
-; 256L    %vreg2<def> = COPY %vreg7:sub_32bit<kill>; GR32:%vreg2 GR64:%vreg7
-;         Considering merging %vreg2 with %vreg7:sub_32bit
+; 256L    %2<def> = COPY %7:sub_32bit<kill>; GR32:%2 GR64:%7
+;         Considering merging %2 with %7:sub_32bit
 ;         Cross-class to GR64.
-;                 RHS = %vreg2 = [256d,272d:0)  0@256d
-;                 LHS = %vreg7 = [208d,256d:0)[304L,480L:0)  0@208d
-;                 updated: 272L   %vreg0<def> = COPY %vreg7:sub_32bit<kill>; GR32:%vreg0 GR64:%vreg7
-;         Joined. Result = %vreg7 = [208d,272d:0)[304L,480L:0)  0@208d
+;                 RHS = %2 = [256d,272d:0)  0@256d
+;                 LHS = %7 = [208d,256d:0)[304L,480L:0)  0@208d
+;                 updated: 272L   %0<def> = COPY %7:sub_32bit<kill>; GR32:%0 GR64:%7
+;         Joined. Result = %7 = [208d,272d:0)[304L,480L:0)  0@208d
 ;
-; 272L    %vreg10:sub_32bit<def> = COPY %vreg7:sub_32bit<kill>, %vreg10<imp-def>; GR64:%vreg10,%vreg7
-;         Considering merging %vreg7 with %vreg10
-;                 RHS = %vreg7 = [208d,272d:0)[304L,480L:0)  0@208d
-;                 LHS = %vreg10 = [16d,64L:2)[64L,160L:1)[192L,240L:1)[272d,304L:3)[304L,352d:1)[352d,400d:0)[400d,400S:4)  0@352d 1@64L-phidef 2@16d-phikill 3@272d-phikill 4@400d
-; Remat: %vreg10<def> = MOV64r0 %vreg10<imp-def>, %EFLAGS<imp-def,dead>, %vreg10<imp-def>; GR64:%vreg10
-; Shrink: %vreg7 = [208d,272d:0)[304L,480L:0)  0@208d
+; 272L    %10:sub_32bit<def> = COPY %7:sub_32bit<kill>, %10<imp-def>; GR64:%10,%7
+;         Considering merging %7 with %10
+;                 RHS = %7 = [208d,272d:0)[304L,480L:0)  0@208d
+;                 LHS = %10 = [16d,64L:2)[64L,160L:1)[192L,240L:1)[272d,304L:3)[304L,352d:1)[352d,400d:0)[400d,400S:4)  0@352d 1@64L-phidef 2@16d-phikill 3@272d-phikill 4@400d
+; Remat: %10<def> = MOV64r0 %10<imp-def>, %EFLAGS<imp-def,dead>, %10<imp-def>; GR64:%10
+; Shrink: %7 = [208d,272d:0)[304L,480L:0)  0@208d
 ;  live-in at 240L
 ;  live-in at 416L
 ;  live-in at 320L
 ;  live-in at 304L
-; Shrunk: %vreg7 = [208d,256d:0)[304L,480L:0)  0@208d
+; Shrunk: %7 = [208d,256d:0)[304L,480L:0)  0@208d
 ;
 ; The COPY at 256L is rewritten as a partial def, and that would artificially
-; extend the live range of %vreg7 to end at 256d.  When the joined copy is
+; extend the live range of %7 to end at 256d.  When the joined copy is
 ; removed, -verify-coalescing complains about the dangling kill.
 ;
 ; <rdar://problem/9967101>
 
 define void @f1() nounwind uwtable ssp {
 bb:
   br label %bb1
 

test/CodeGen/X86/crash.ll

for.inc:                                          ; preds = %for.cond
   %ins = or i576 %5, %mask
   br label %for.cond
 }
 
 declare void @fn3(...)
 
 ; Check coalescing of IMPLICIT_DEF instructions:
 ;
-; %vreg1 = IMPLICIT_DEF
-; %vreg2 = MOV32r0
+; %1 = IMPLICIT_DEF
+; %2 = MOV32r0
 ;
-; When coalescing %vreg1 and %vreg2, the IMPLICIT_DEF instruction should be
+; When coalescing %1 and %2, the IMPLICIT_DEF instruction should be
 ; erased along with its value number.
 ;
 define void @rdar12474033() nounwind ssp {
 bb:
   br i1 undef, label %bb21, label %bb1
 
 bb1:                                              ; preds = %bb
   switch i32 undef, label %bb10 [

test/CodeGen/X86/handle-move.ll

 ; RUN: llc -mtriple=x86_64-- -mcpu=core2 -fast-isel -enable-misched -misched=shuffle -misched-bottomup -verify-machineinstrs < %s
 ; RUN: llc -mtriple=x86_64-- -mcpu=core2 -fast-isel -enable-misched -misched=shuffle -misched-topdown -verify-machineinstrs < %s
 ; REQUIRES: asserts
 ;
 ; Test the LiveIntervals::handleMove() function.
 ;
 ; Moving the DIV32r instruction exercises the regunit update code because
 ; %edx has a live range into the function and is used by the DIV32r.
 ;
 ; Here sinking a kill + dead def:
-; 144B -> 180B: DIV32r %vreg4, %eax<imp-def>, %edx<imp-def,dead>, %EFLAGS<imp-def,dead>, %eax<imp-use,kill>, %edx<imp-use>
-;       %vreg4: [48r,144r:0)  0@48r
+; 144B -> 180B: DIV32r %4, %eax<imp-def>, %edx<imp-def,dead>, %EFLAGS<imp-def,dead>, %eax<imp-use,kill>, %edx<imp-use>
+;       %4: [48r,144r:0)  0@48r
 ;         -->   [48r,180r:0)  0@48r
 ;       DH:     [0B,16r:0)[128r,144r:2)[144r,144d:1)  0@0B-phi 1@144r 2@128r
 ;         -->   [0B,16r:0)[128r,180r:2)[180r,180d:1)  0@0B-phi 1@180r 2@128r
 ;       DL:     [0B,16r:0)[128r,144r:2)[144r,144d:1)  0@0B-phi 1@144r 2@128r
 ;         -->   [0B,16r:0)[128r,180r:2)[180r,180d:1)  0@0B-phi 1@180r 2@128r
 ;
 define i32 @f1(i32 %a, i32 %b, i32 %c) nounwind uwtable readnone ssp {
 entry:
   %y = add i32 %c, 1
   %x = udiv i32 %b, %a
   %add = add nsw i32 %y, %x
   ret i32 %add
 }
 
 ; Same as above, but moving a kill + live def:
-; 144B -> 180B: DIV32r %vreg4, %eax<imp-def,dead>, %edx<imp-def>, %EFLAGS<imp-def,dead>, %eax<imp-use,kill>, %edx<imp-use>
-;       %vreg4: [48r,144r:0)  0@48r
+; 144B -> 180B: DIV32r %4, %eax<imp-def,dead>, %edx<imp-def>, %EFLAGS<imp-def,dead>, %eax<imp-use,kill>, %edx<imp-use>
+;       %4: [48r,144r:0)  0@48r
 ;         -->   [48r,180r:0)  0@48r
 ;       DH:     [0B,16r:0)[128r,144r:2)[144r,184r:1)  0@0B-phi 1@144r 2@128r
 ;         -->   [0B,16r:0)[128r,180r:2)[180r,184r:1)  0@0B-phi 1@180r 2@128r
 ;       DL:     [0B,16r:0)[128r,144r:2)[144r,184r:1)  0@0B-phi 1@144r 2@128r
 ;         -->   [0B,16r:0)[128r,180r:2)[180r,184r:1)  0@0B-phi 1@180r 2@128r
 ;
 define i32 @f2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind uwtable readnone ssp {
 entry:
   %y = sub i32 %c, %d
   %x = urem i32 %b, %a
   %add = add nsw i32 %x, %y
   ret i32 %add
 }
 
-; Moving a use below the existing kill (%vreg5):
-; Moving a tied virtual register def (%vreg11):
+; Moving a use below the existing kill (%5):
+; Moving a tied virtual register def (%11):
 ;
-; 96B -> 120B: %vreg11<def,tied1> = SUB32rr %vreg11<tied0>, %vreg5
-;       %vreg11:        [80r,96r:1)[96r,144r:0)  0@96r 1@80r
+; 96B -> 120B: %11<def,tied1> = SUB32rr %11<tied0>, %5
+;       %11:        [80r,96r:1)[96r,144r:0)  0@96r 1@80r
 ;            -->        [80r,120r:1)[120r,144r:0)  0@120r 1@80r
-;       %vreg5:         [16r,112r:0)  0@16r
+;       %5:         [16r,112r:0)  0@16r
 ;            -->        [16r,120r:0)  0@16r
 ;
 define i32 @f3(i32 %a, i32 %b) nounwind uwtable readnone ssp {
 entry:
   %y = sub i32 %a, %b
   %x = add i32 %a, %b
   %r = mul i32 %x, %y
   ret i32 %r

test/CodeGen/X86/invalid-liveness.mir

 # RUN: not llc -mtriple=i686-- -run-pass liveintervals -o - %s 2>&1 | FileCheck %s
 # REQUIRES: asserts
 
 --- |
   define void @func() { ret void }
 ...
 ---
 # Liveness calculation should detect that we do not have a definition for vreg0
 # on all paths; In this example a def for vreg0 is missing when jumping from
 # bb.0 to bb.3.
 #
-# CHECK: Use of %vreg0 does not have a corresponding definition on every path
+# CHECK: Use of %0 does not have a corresponding definition on every path
 # CHECK: ERROR: Use not jointly dominated by defs.
 name: func
 registers:
   - { id: 0, class: gr32 }
 body: |
   bb.0:
     JG_1 %bb.2, implicit %eflags
     JMP_1 %bb.3

test/CodeGen/X86/liveness-local-regalloc.ll

infloop:                                          ; preds = %infloop, %bb3
   br label %infloop
 
 infloop1:                                         ; preds = %infloop1, %bb5
   br label %infloop1
 }
 
 
 ; RAFast would forget to add a super-register <imp-def> when rewriting:
-;  %vreg10:sub_32bit<def,read-undef> = COPY %R9D<kill>
+;  %10:sub_32bit<def,read-undef> = COPY %R9D<kill>
 ; This trips up the machine code verifier.
 define void @autogen_SD24657(i8*, i32*, i64*, i32, i64, i8) {
 BB:
   %A4 = alloca <16 x i16>
   %A3 = alloca double
   %A2 = alloca <2 x i8>
   %A1 = alloca i1
   %A = alloca i32

test/CodeGen/X86/misched-copy.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -verify-machineinstrs -mtriple=i686-- -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
 ;
 ; Test scheduling of copy instructions.
 ;
 ; Argument copies should be hoisted to the top of the block.
 ; Return copies should be sunk to the end.
 ; MUL_HiLo PhysReg use copies should be just above the mul.
 ; MUL_HiLo PhysReg def copies should be just below the mul.
 ;
 ; CHECK: *** Final schedule for BB#1 ***
 ; CHECK:      %eax<def> = COPY
-; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %eax<imp-def>, %edx<imp-def>, %eflags<imp-def,dead>, %eax<imp-use>;
+; CHECK-NEXT: MUL32r %{{[0-9]+}}, %eax<imp-def>, %edx<imp-def>, %eflags<imp-def,dead>, %eax<imp-use>;
 ; CHECK-NEXT: COPY %e{{[ad]}}x
 ; CHECK-NEXT: COPY %e{{[ad]}}x
 ; CHECK:      DIVSSrm
 define i64 @mulhoist(i32 %a, i32 %b) #0 {
 entry:
   br label %body
 
 body:

test/CodeGen/X86/norex-subreg.ll

entry:
   %9 = shl i16 %8, 8
   %10 = or i16 undef, %9
   store i16 %10, i16* undef, align 1
   ret void
 }
 
 ; This test case extracts a sub_8bit_hi sub-register:
 ;
-;       %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8:%vreg2 GR64_ABCD:%vreg1
-;       TEST8ri %vreg2, 1, %EFLAGS<imp-def>; GR8:%vreg2
+;       %2<def> = COPY %1:sub_8bit_hi; GR8:%2 GR64_ABCD:%1
+;       TEST8ri %2, 1, %EFLAGS<imp-def>; GR8:%2
 ;
-; %vreg2 must be constrained to GR8_NOREX, or the COPY could become impossible.
+; %2 must be constrained to GR8_NOREX, or the COPY could become impossible.
 ;
 ; PR11088
 
 define fastcc i32 @g(i64 %FB) nounwind uwtable readnone align 2 {
 entry:
   %and32 = and i64 %FB, 256
   %cmp33 = icmp eq i64 %and32, 0
   %Features.6.or35 = select i1 %cmp33, i32 0, i32 undef

test/CodeGen/X86/phys_subreg_coalesce-3.ll

 ; RUN: llc < %s -verify-machineinstrs -mtriple=i386-apple-darwin -mcpu=corei7 | FileCheck %s
 ; rdar://5571034
 
-; This requires physreg joining, %vreg13 is live everywhere:
-; 304L    %cl<def> = COPY %vreg13:sub_8bit; GR32_ABCD:%vreg13
-; 320L    %vreg15<def> = COPY %vreg19; GR32:%vreg15 GR32_NOSP:%vreg19
-; 336L    %vreg15<def> = SAR32rCL %vreg15, %EFLAGS<imp-def,dead>, %cl<imp-use,kill>; GR32:%vreg15
+; This requires physreg joining, %13 is live everywhere:
+; 304L    %cl<def> = COPY %13:sub_8bit; GR32_ABCD:%13
+; 320L    %15<def> = COPY %19; GR32:%15 GR32_NOSP:%19
+; 336L    %15<def> = SAR32rCL %15, %EFLAGS<imp-def,dead>, %cl<imp-use,kill>; GR32:%15
 
 define void @foo(i32* nocapture %quadrant, i32* nocapture %ptr, i32 %bbSize, i32 %bbStart, i32 %shifts) nounwind ssp {
 ; CHECK-LABEL: foo:
 entry:
   %j.03 = add i32 %bbSize, -1                     ; <i32> [#uses=2]
   %0 = icmp sgt i32 %j.03, -1                     ; <i1> [#uses=1]
   br i1 %0, label %bb.nph, label %return
 

test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir

bb.0.entry:
     ADJCALLSTACKUP64 0, 0, implicit-def dead %rsp, implicit-def dead %eflags, implicit %rsp, debug-location !35
     %eax = MOV32r0 implicit-def dead %eflags, debug-location !36
     RET 0, killed %eax, debug-location !36
 
 ...
 
 # Let's verify that the slot index ranges for the unused variables argc/argv,
 # connected to physical regs %EDI and %RSI, does not overlap with the ranges
-# for %vreg2 and %vreg3. The register allocator is actually allocating the
-# virtual registers # to %EDI and %ESI, so the ranges for argc/argv should
-# not cover the whole BB.
+# for %2 and %3. The register allocator is actually allocating the# virtual
+# registers # to %EDI and %ESI, so the ranges for argc/argv should not cover
+# the whole BB.
 #
 # CHECKDBG-LABEL: ********** EMITTING LIVE DEBUG VARIABLES **********
 # CHECKDBG-NEXT: !"argc,5"        [0B;0e):0 Loc0=%edi
 # CHECKDBG-NEXT:         [0B;0e):0 BB#0-160B
 # CHECKDBG-NEXT: !"argv,5"        [0B;0e):0 Loc0=%rsi
 # CHECKDBG-NEXT:         [0B;0e):0 BB#0-160B
-# CHECKDBG-NEXT: !"a0,7"  [16r;64r):0 Loc0=%vreg2
+# CHECKDBG-NEXT: !"a0,7"  [16r;64r):0 Loc0=%2
 # CHECKDBG-NEXT:         [16r;64r):0 BB#0-160B
-# CHECKDBG-NEXT: !"a1,8"  [32r;80r):0 Loc0=%vreg3
+# CHECKDBG-NEXT: !"a1,8"  [32r;80r):0 Loc0=%3
 # CHECKDBG-NEXT:         [32r;80r):0 BB#0-160B