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Differential D40421

[CodeGen] Always use `printReg` to print registers in both MIR and debug output
ClosedPublic

Authored by thegameg on Nov 24 2017, 3:33 AM.

Details

Reviewers
MatzeB
qcolombet
Commits
rGc71cced0aae4: [CodeGen] Always use `printReg` to print registers in both MIR and debug output
rL319445: [CodeGen] Always use `printReg` to print registers in both MIR and debug
Summary

As part of the unification of the debug format and the MIR format, always use printReg to print all kinds of registers.

Diff Detail

Repository
rL LLVM

Event Timeline

thegameg created this revision.Nov 24 2017, 3:33 AM
Herald added subscribers: JDevlieghere, eraman, javed.absar. · View Herald TranscriptNov 24 2017, 3:33 AM
MatzeB accepted this revision.Nov 27 2017, 10:58 AM

LGTM, thanks

This revision is now accepted and ready to land.Nov 27 2017, 10:58 AM
Closed by commit rL319445: [CodeGen] Always use `printReg` to print registers in both MIR and debug (authored by thegameg). · Explain WhyNov 30 2017, 8:13 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

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Diff 124946

llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 Lines for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) {
if (CriticalPathSet.none()) if (CriticalPathSet.none())
CriticalPathSet = CPSet; CriticalPathSet = CPSet;
else else
CriticalPathSet |= CPSet; CriticalPathSet |= CPSet;
} }
DEBUG(dbgs() << "AntiDep Critical-Path Registers:"); DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
DEBUG(for (unsigned r : CriticalPathSet.set_bits()) DEBUG(for (unsigned r : CriticalPathSet.set_bits())
dbgs() << " " << TRI->getName(r)); dbgs() << " " << printReg(r, TRI));
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
} }
AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() { AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
delete State; delete State;
} }
void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) { void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
// If Reg is current live, then mark that it can't be renamed as // If Reg is current live, then mark that it can't be renamed as
// we don't know the extent of its live-range anymore (now that it // we don't know the extent of its live-range anymore (now that it
// has been scheduled). If it is not live but was defined in the // has been scheduled). If it is not live but was defined in the
// previous schedule region, then set its def index to the most // previous schedule region, then set its def index to the most
// conservative location (i.e. the beginning of the previous // conservative location (i.e. the beginning of the previous
// schedule region). // schedule region).
if (State->IsLive(Reg)) { if (State->IsLive(Reg)) {
DEBUG(if (State->GetGroup(Reg) != 0) DEBUG(if (State->GetGroup(Reg) != 0)
dbgs() << " " << TRI->getName(Reg) << "=g" << dbgs() << " " << printReg(Reg, TRI) << "=g" <<
State->GetGroup(Reg) << "->g0(region live-out)"); State->GetGroup(Reg) << "->g0(region live-out)");
State->UnionGroups(Reg, 0); State->UnionGroups(Reg, 0);
} else if ((DefIndices[Reg] < InsertPosIndex) } else if ((DefIndices[Reg] < InsertPosIndex)
&& (DefIndices[Reg] >= Count)) { && (DefIndices[Reg] >= Count)) {
DefIndices[Reg] = Count; DefIndices[Reg] = Count;
} }
} }
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
} }
if (!State->IsLive(Reg)) { if (!State->IsLive(Reg)) {
KillIndices[Reg] = KillIdx; KillIndices[Reg] = KillIdx;
DefIndices[Reg] = ~0u; DefIndices[Reg] = ~0u;
RegRefs.erase(Reg); RegRefs.erase(Reg);
State->LeaveGroup(Reg); State->LeaveGroup(Reg);
DEBUG(if (header) { DEBUG(if (header) {
dbgs() << header << TRI->getName(Reg); header = nullptr; }); dbgs() << header << printReg(Reg, TRI); header = nullptr; });
DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag); DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
// Repeat for subregisters. Note that we only do this if the superregister // Repeat for subregisters. Note that we only do this if the superregister
// was not live because otherwise, regardless whether we have an explicit // was not live because otherwise, regardless whether we have an explicit
// use of the subregister, the subregister's contents are needed for the // use of the subregister, the subregister's contents are needed for the
// uses of the superregister. // uses of the superregister.
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
unsigned SubregReg = *SubRegs; unsigned SubregReg = *SubRegs;
if (!State->IsLive(SubregReg)) { if (!State->IsLive(SubregReg)) {
KillIndices[SubregReg] = KillIdx; KillIndices[SubregReg] = KillIdx;
DefIndices[SubregReg] = ~0u; DefIndices[SubregReg] = ~0u;
RegRefs.erase(SubregReg); RegRefs.erase(SubregReg);
State->LeaveGroup(SubregReg); State->LeaveGroup(SubregReg);
DEBUG(if (header) { DEBUG(if (header) {
dbgs() << header << TRI->getName(Reg); header = nullptr; }); dbgs() << header << printReg(Reg, TRI); header = nullptr; });
DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" << DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" <<
State->GetGroup(SubregReg) << tag); State->GetGroup(SubregReg) << tag);
} }
} }
} }
DEBUG(if (!header && footer) dbgs() << footer); DEBUG(if (!header && footer) dbgs() << footer);
} }
Show All 19 Linesvoid AggressiveAntiDepBreaker::PrescanInstruction(
DEBUG(dbgs() << "\tDef Groups:"); DEBUG(dbgs() << "\tDef Groups:");
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i); MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isDef()) continue; if (!MO.isReg() || !MO.isDef()) continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (Reg == 0) continue; if (Reg == 0) continue;
DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg)); DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg));
// If MI's defs have a special allocation requirement, don't allow // If MI's defs have a special allocation requirement, don't allow
// any def registers to be changed. Also assume all registers // any def registers to be changed. Also assume all registers
// defined in a call must not be changed (ABI). Inline assembly may // defined in a call must not be changed (ABI). Inline assembly may
// reference either system calls or the register directly. Skip it until we // reference either system calls or the register directly. Skip it until we
// can tell user specified registers from compiler-specified. // can tell user specified registers from compiler-specified.
if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) ||
MI.isInlineAsm()) { MI.isInlineAsm()) {
DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)"); DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
State->UnionGroups(Reg, 0); State->UnionGroups(Reg, 0);
} }
// Any aliased that are live at this point are completely or // Any aliased that are live at this point are completely or
// partially defined here, so group those aliases with Reg. // partially defined here, so group those aliases with Reg.
for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) { for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
unsigned AliasReg = *AI; unsigned AliasReg = *AI;
if (State->IsLive(AliasReg)) { if (State->IsLive(AliasReg)) {
State->UnionGroups(Reg, AliasReg); State->UnionGroups(Reg, AliasReg);
DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " << DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via "
TRI->getName(AliasReg) << ")"); << printReg(AliasReg, TRI) << ")");
} }
} }
// Note register reference... // Note register reference...
const TargetRegisterClass *RC = nullptr; const TargetRegisterClass *RC = nullptr;
if (i < MI.getDesc().getNumOperands()) if (i < MI.getDesc().getNumOperands())
RC = TII->getRegClass(MI.getDesc(), i, TRI, MF); RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
AggressiveAntiDepState::RegisterReference RR = { &MO, RC }; AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Linesvoid AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
// Scan the register uses for this instruction and update // Scan the register uses for this instruction and update
// live-ranges, groups and RegRefs. // live-ranges, groups and RegRefs.
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i); MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isUse()) continue; if (!MO.isReg() || !MO.isUse()) continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (Reg == 0) continue; if (Reg == 0) continue;
DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg));
State->GetGroup(Reg));
// It wasn't previously live but now it is, this is a kill. Forget // It wasn't previously live but now it is, this is a kill. Forget
// the previous live-range information and start a new live-range // the previous live-range information and start a new live-range
// for the register. // for the register.
HandleLastUse(Reg, Count, "(last-use)"); HandleLastUse(Reg, Count, "(last-use)");
if (Special) { if (Special) {
DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)"); DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
Show All 18 Lines if (MI.isKill()) {
unsigned FirstReg = 0; unsigned FirstReg = 0;
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i); MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg()) continue; if (!MO.isReg()) continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (Reg == 0) continue; if (Reg == 0) continue;
if (FirstReg != 0) { if (FirstReg != 0) {
DEBUG(dbgs() << "=" << TRI->getName(Reg)); DEBUG(dbgs() << "=" << printReg(Reg, TRI));
State->UnionGroups(FirstReg, Reg); State->UnionGroups(FirstReg, Reg);
} else { } else {
DEBUG(dbgs() << " " << TRI->getName(Reg)); DEBUG(dbgs() << " " << printReg(Reg, TRI));
FirstReg = Reg; FirstReg = Reg;
} }
} }
DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
} }
} }
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Linesbool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
unsigned SuperReg = 0; unsigned SuperReg = 0;
for (unsigned i = 0, e = Regs.size(); i != e; ++i) { for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
unsigned Reg = Regs[i]; unsigned Reg = Regs[i];
if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg)) if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
SuperReg = Reg; SuperReg = Reg;
// If Reg has any references, then collect possible rename regs // If Reg has any references, then collect possible rename regs
if (RegRefs.count(Reg) > 0) { if (RegRefs.count(Reg) > 0) {
DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":"); DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":");
BitVector &BV = RenameRegisterMap[Reg]; BitVector &BV = RenameRegisterMap[Reg];
assert(BV.empty()); assert(BV.empty());
BV = GetRenameRegisters(Reg); BV = GetRenameRegisters(Reg);
DEBUG({ DEBUG({
dbgs() << " ::"; dbgs() << " ::";
for (unsigned r : BV.set_bits()) for (unsigned r : BV.set_bits())
dbgs() << " " << TRI->getName(r); dbgs() << " " << printReg(r, TRI);
dbgs() << "\n"; dbgs() << "\n";
}); });
} }
} }
// All group registers should be a subreg of SuperReg. // All group registers should be a subreg of SuperReg.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) { for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
unsigned Reg = Regs[i]; unsigned Reg = Regs[i];
if (Reg == SuperReg) continue; if (Reg == SuperReg) continue;
bool IsSub = TRI->isSubRegister(SuperReg, Reg); bool IsSub = TRI->isSubRegister(SuperReg, Reg);
// FIXME: remove this once PR18663 has been properly fixed. For now, // FIXME: remove this once PR18663 has been properly fixed. For now,
// return a conservative answer: // return a conservative answer:
// assert(IsSub && "Expecting group subregister"); // assert(IsSub && "Expecting group subregister");
if (!IsSub) if (!IsSub)
return false; return false;
} }
#ifndef NDEBUG #ifndef NDEBUG
// If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod // If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod
if (DebugDiv > 0) { if (DebugDiv > 0) {
static int renamecnt = 0; static int renamecnt = 0;
if (renamecnt++ % DebugDiv != DebugMod) if (renamecnt++ % DebugDiv != DebugMod)
return false; return false;
dbgs() << "*** Performing rename " << TRI->getName(SuperReg) << dbgs() << "*** Performing rename " << printReg(SuperReg, TRI)
" for debug ***\n"; << " for debug ***\n";
} }
#endif #endif
// Check each possible rename register for SuperReg in round-robin // Check each possible rename register for SuperReg in round-robin
// order. If that register is available, and the corresponding // order. If that register is available, and the corresponding
// registers are available for the other group subregisters, then we // registers are available for the other group subregisters, then we
// can use those registers to rename. // can use those registers to rename.
Show All 20 Lines do {
if (R == 0) R = Order.size(); if (R == 0) R = Order.size();
--R; --R;
const unsigned NewSuperReg = Order[R]; const unsigned NewSuperReg = Order[R];
// Don't consider non-allocatable registers // Don't consider non-allocatable registers
if (!MRI.isAllocatable(NewSuperReg)) continue; if (!MRI.isAllocatable(NewSuperReg)) continue;
// Don't replace a register with itself. // Don't replace a register with itself.
if (NewSuperReg == SuperReg) continue; if (NewSuperReg == SuperReg) continue;
DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':'); DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':');
RenameMap.clear(); RenameMap.clear();
// For each referenced group register (which must be a SuperReg or // For each referenced group register (which must be a SuperReg or
// a subregister of SuperReg), find the corresponding subregister // a subregister of SuperReg), find the corresponding subregister
// of NewSuperReg and make sure it is free to be renamed. // of NewSuperReg and make sure it is free to be renamed.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) { for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
unsigned Reg = Regs[i]; unsigned Reg = Regs[i];
unsigned NewReg = 0; unsigned NewReg = 0;
if (Reg == SuperReg) { if (Reg == SuperReg) {
NewReg = NewSuperReg; NewReg = NewSuperReg;
} else { } else {
unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
if (NewSubRegIdx != 0) if (NewSubRegIdx != 0)
NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx); NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
} }
DEBUG(dbgs() << " " << TRI->getName(NewReg)); DEBUG(dbgs() << " " << printReg(NewReg, TRI));
// Check if Reg can be renamed to NewReg. // Check if Reg can be renamed to NewReg.
if (!RenameRegisterMap[Reg].test(NewReg)) { if (!RenameRegisterMap[Reg].test(NewReg)) {
DEBUG(dbgs() << "(no rename)"); DEBUG(dbgs() << "(no rename)");
goto next_super_reg; goto next_super_reg;
} }
// If NewReg is dead and NewReg's most recent def is not before // If NewReg is dead and NewReg's most recent def is not before
// Regs's kill, it's safe to replace Reg with NewReg. We // Regs's kill, it's safe to replace Reg with NewReg. We
// must also check all aliases of NewReg, because we can't define a // must also check all aliases of NewReg, because we can't define a
// register when any sub or super is already live. // register when any sub or super is already live.
if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) { if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
DEBUG(dbgs() << "(live)"); DEBUG(dbgs() << "(live)");
goto next_super_reg; goto next_super_reg;
} else { } else {
bool found = false; bool found = false;
for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) { for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) {
unsigned AliasReg = *AI; unsigned AliasReg = *AI;
if (State->IsLive(AliasReg) || if (State->IsLive(AliasReg) ||
(KillIndices[Reg] > DefIndices[AliasReg])) { (KillIndices[Reg] > DefIndices[AliasReg])) {
DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)"); DEBUG(dbgs() << "(alias " << printReg(AliasReg, TRI) << " live)");
found = true; found = true;
break; break;
} }
} }
if (found) if (found)
goto next_super_reg; goto next_super_reg;
} }
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines if (CriticalPathSet.any()) {
CriticalPathMI = CriticalPathSU->getInstr(); CriticalPathMI = CriticalPathSU->getInstr();
} }
#ifndef NDEBUG #ifndef NDEBUG
DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n"); DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
DEBUG(dbgs() << "Available regs:"); DEBUG(dbgs() << "Available regs:");
for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
if (!State->IsLive(Reg)) if (!State->IsLive(Reg))
DEBUG(dbgs() << " " << TRI->getName(Reg)); DEBUG(dbgs() << " " << printReg(Reg, TRI));
} }
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
#endif #endif
BitVector RegAliases(TRI->getNumRegs()); BitVector RegAliases(TRI->getNumRegs());
// Attempt to break anti-dependence edges. Walk the instructions // Attempt to break anti-dependence edges. Walk the instructions
// from the bottom up, tracking information about liveness as we go // from the bottom up, tracking information about liveness as we go
Show All 39 Lines if (!MI.isKill()) {
for (unsigned i = 0, e = Edges.size(); i != e; ++i) { for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
const SDep *Edge = Edges[i]; const SDep *Edge = Edges[i];
SUnit *NextSU = Edge->getSUnit(); SUnit *NextSU = Edge->getSUnit();
if ((Edge->getKind() != SDep::Anti) && if ((Edge->getKind() != SDep::Anti) &&
(Edge->getKind() != SDep::Output)) continue; (Edge->getKind() != SDep::Output)) continue;
unsigned AntiDepReg = Edge->getReg(); unsigned AntiDepReg = Edge->getReg();
DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg)); DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI));
assert(AntiDepReg != 0 && "Anti-dependence on reg0?"); assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
if (!MRI.isAllocatable(AntiDepReg)) { if (!MRI.isAllocatable(AntiDepReg)) {
// Don't break anti-dependencies on non-allocatable registers. // Don't break anti-dependencies on non-allocatable registers.
DEBUG(dbgs() << " (non-allocatable)\n"); DEBUG(dbgs() << " (non-allocatable)\n");
continue; continue;
} else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) { } else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) {
// Don't break anti-dependencies for critical path registers // Don't break anti-dependencies for critical path registers
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines if (!MI.isKill()) {
} }
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
// Look for a suitable register to use to break the anti-dependence. // Look for a suitable register to use to break the anti-dependence.
std::map<unsigned, unsigned> RenameMap; std::map<unsigned, unsigned> RenameMap;
if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) { if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
DEBUG(dbgs() << "\tBreaking anti-dependence edge on " DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
<< TRI->getName(AntiDepReg) << ":"); << printReg(AntiDepReg, TRI) << ":");
// Handle each group register... // Handle each group register...
for (std::map<unsigned, unsigned>::iterator for (std::map<unsigned, unsigned>::iterator
S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) { S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
unsigned CurrReg = S->first; unsigned CurrReg = S->first;
unsigned NewReg = S->second; unsigned NewReg = S->second;
DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" << DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->"
TRI->getName(NewReg) << "(" << << printReg(NewReg, TRI) << "("
RegRefs.count(CurrReg) << " refs)"); << RegRefs.count(CurrReg) << " refs)");
// Update the references to the old register CurrReg to // Update the references to the old register CurrReg to
// refer to the new register NewReg. // refer to the new register NewReg.
for (const auto &Q : make_range(RegRefs.equal_range(CurrReg))) { for (const auto &Q : make_range(RegRefs.equal_range(CurrReg))) {
Q.second.Operand->setReg(NewReg); Q.second.Operand->setReg(NewReg);
// If the SU for the instruction being updated has debug // If the SU for the instruction being updated has debug
// information related to the anti-dependency register, make // information related to the anti-dependency register, make
// sure to update that as well. // sure to update that as well.
Show All 34 Lines

llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp

Show First 20 Lines • Show All 460 Lines • ▼ Show 20 Lines
#ifndef NDEBUG #ifndef NDEBUG
{ {
DEBUG(dbgs() << "Critical path has total latency " DEBUG(dbgs() << "Critical path has total latency "
<< (Max->getDepth() + Max->Latency) << "\n"); << (Max->getDepth() + Max->Latency) << "\n");
DEBUG(dbgs() << "Available regs:"); DEBUG(dbgs() << "Available regs:");
for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
if (KillIndices[Reg] == ~0u) if (KillIndices[Reg] == ~0u)
DEBUG(dbgs() << " " << TRI->getName(Reg)); DEBUG(dbgs() << " " << printReg(Reg, TRI));
} }
DEBUG(dbgs() << '\n'); DEBUG(dbgs() << '\n');
} }
#endif #endif
// Track progress along the critical path through the SUnit graph as we walk // Track progress along the critical path through the SUnit graph as we walk
// the instructions. // the instructions.
const SUnit *CriticalPathSU = Max; const SUnit *CriticalPathSU = Max;
▲ Show 20 Lines • Show All 163 Lines • ▼ Show 20 Lines if (AntiDepReg != 0) {
std::pair<std::multimap<unsigned, MachineOperand *>::iterator, std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
std::multimap<unsigned, MachineOperand *>::iterator> std::multimap<unsigned, MachineOperand *>::iterator>
Range = RegRefs.equal_range(AntiDepReg); Range = RegRefs.equal_range(AntiDepReg);
if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second, if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
AntiDepReg, AntiDepReg,
LastNewReg[AntiDepReg], LastNewReg[AntiDepReg],
RC, ForbidRegs)) { RC, ForbidRegs)) {
DEBUG(dbgs() << "Breaking anti-dependence edge on " DEBUG(dbgs() << "Breaking anti-dependence edge on "
<< TRI->getName(AntiDepReg) << printReg(AntiDepReg, TRI) << " with "
<< " with " << RegRefs.count(AntiDepReg) << " references" << RegRefs.count(AntiDepReg) << " references"
<< " using " << TRI->getName(NewReg) << "!\n"); << " using " << printReg(NewReg, TRI) << "!\n");
// Update the references to the old register to refer to the new // Update the references to the old register to refer to the new
// register. // register.
for (std::multimap<unsigned, MachineOperand *>::iterator for (std::multimap<unsigned, MachineOperand *>::iterator
Q = Range.first, QE = Range.second; Q != QE; ++Q) { Q = Range.first, QE = Range.second; Q != QE; ++Q) {
Q->second->setReg(NewReg); Q->second->setReg(NewReg);
// If the SU for the instruction being updated has debug information // If the SU for the instruction being updated has debug information
// related to the anti-dependency register, make sure to update that // related to the anti-dependency register, make sure to update that
Show All 35 Lines

llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp

Show First 20 Lines • Show All 388 Lines • ▼ Show 20 Lines for (unsigned i = 0,
i != e; ++i) { i != e; ++i) {
MachineOperand &MO = MI->getOperand(i); MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg()) if (!MO.isReg())
continue; continue;
if (MO.isUse()) if (MO.isUse())
continue; continue;
for (int rx : regIndices(MO.getReg())) { for (int rx : regIndices(MO.getReg())) {
// This instruction explicitly defines rx. // This instruction explicitly defines rx.
DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << CurInstr
<< '\t' << *MI); << '\t' << *MI);
if (breakDependency) { if (breakDependency) {
// Check clearance before partial register updates. // Check clearance before partial register updates.
// Call breakDependence before setting LiveRegs[rx].Def. // Call breakDependence before setting LiveRegs[rx].Def.
unsigned Pref = TII->getPartialRegUpdateClearance(*MI, i, TRI); unsigned Pref = TII->getPartialRegUpdateClearance(*MI, i, TRI);
if (Pref && shouldBreakDependence(MI, i, Pref)) if (Pref && shouldBreakDependence(MI, i, Pref))
TII->breakPartialRegDependency(*MI, i, TRI); TII->breakPartialRegDependency(*MI, i, TRI);
▲ Show 20 Lines • Show All 350 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MIRPrinter.cpp

Show First 20 Lines • Show All 186 Lines • ▼ Show 20 Lines static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
llvm_unreachable("LLVM Module is supposed to be parsed separately"); llvm_unreachable("LLVM Module is supposed to be parsed separately");
return ""; return "";
} }
}; };
} // end namespace yaml } // end namespace yaml
} // end namespace llvm } // end namespace llvm
static void printRegMIR(unsigned Reg, raw_ostream &OS,
const TargetRegisterInfo *TRI) {
// TODO: Print Stack Slots.
if (!Reg)
OS << '_';
else if (TargetRegisterInfo::isVirtualRegister(Reg))
OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
else if (Reg < TRI->getNumRegs())
OS << '%' << StringRef(TRI->getName(Reg)).lower();
else
llvm_unreachable("Can't print this kind of register yet");
}
static void printRegMIR(unsigned Reg, yaml::StringValue &Dest, static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
const TargetRegisterInfo *TRI) { const TargetRegisterInfo *TRI) {
raw_string_ostream OS(Dest.Value); raw_string_ostream OS(Dest.Value);
printRegMIR(Reg, OS, TRI); OS << printReg(Reg, TRI);
} }
void MIRPrinter::print(const MachineFunction &MF) { void MIRPrinter::print(const MachineFunction &MF) {
initRegisterMaskIds(MF); initRegisterMaskIds(MF);
yaml::MachineFunction YamlMF; yaml::MachineFunction YamlMF;
YamlMF.Name = MF.getName(); YamlMF.Name = MF.getName();
YamlMF.Alignment = MF.getAlignment(); YamlMF.Alignment = MF.getAlignment();
Show All 37 Linesstatic void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
OS << StringRef("CustomRegMask("); OS << StringRef("CustomRegMask(");
bool IsRegInRegMaskFound = false; bool IsRegInRegMaskFound = false;
for (int I = 0, E = TRI->getNumRegs(); I < E; I++) { for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
// Check whether the register is asserted in regmask. // Check whether the register is asserted in regmask.
if (RegMask[I / 32] & (1u << (I % 32))) { if (RegMask[I / 32] & (1u << (I % 32))) {
if (IsRegInRegMaskFound) if (IsRegInRegMaskFound)
OS << ','; OS << ',';
printRegMIR(I, OS, TRI); OS << printReg(I, TRI);
IsRegInRegMaskFound = true; IsRegInRegMaskFound = true;
} }
} }
OS << ')'; OS << ')';
} }
static void printRegClassOrBank(unsigned Reg, raw_ostream &OS, static void printRegClassOrBank(unsigned Reg, raw_ostream &OS,
▲ Show 20 Lines • Show All 369 Lines • ▼ Show 20 Linesvoid MIPrinter::print(const MachineBasicBlock &MBB) {
if (MRI.tracksLiveness() && !MBB.livein_empty()) { if (MRI.tracksLiveness() && !MBB.livein_empty()) {
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
OS.indent(2) << "liveins: "; OS.indent(2) << "liveins: ";
bool First = true; bool First = true;
for (const auto &LI : MBB.liveins()) { for (const auto &LI : MBB.liveins()) {
if (!First) if (!First)
OS << ", "; OS << ", ";
First = false; First = false;
printRegMIR(LI.PhysReg, OS, &TRI); OS << printReg(LI.PhysReg, &TRI);
if (!LI.LaneMask.all()) if (!LI.LaneMask.all())
OS << ":0x" << PrintLaneMask(LI.LaneMask); OS << ":0x" << PrintLaneMask(LI.LaneMask);
} }
OS << "\n"; OS << "\n";
HasLineAttributes = true; HasLineAttributes = true;
} }
if (HasLineAttributes) if (HasLineAttributes)
▲ Show 20 Lines • Show All 284 Lines • ▼ Show 20 Lines case MachineOperand::MO_Register: {
if (Op.isKill()) if (Op.isKill())
OS << "killed "; OS << "killed ";
if (Op.isUndef()) if (Op.isUndef())
OS << "undef "; OS << "undef ";
if (Op.isEarlyClobber()) if (Op.isEarlyClobber())
OS << "early-clobber "; OS << "early-clobber ";
if (Op.isDebug()) if (Op.isDebug())
OS << "debug-use "; OS << "debug-use ";
printRegMIR(Reg, OS, TRI); OS << printReg(Reg, TRI);
// Print the sub register. // Print the sub register.
if (Op.getSubReg() != 0) if (Op.getSubReg() != 0)
OS << '.' << TRI->getSubRegIndexName(Op.getSubReg()); OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
if (TargetRegisterInfo::isVirtualRegister(Reg)) { if (TargetRegisterInfo::isVirtualRegister(Reg)) {
const MachineRegisterInfo &MRI = Op.getParent()->getMF()->getRegInfo(); const MachineRegisterInfo &MRI = Op.getParent()->getMF()->getRegInfo();
if (IsDef || MRI.def_empty(Reg)) { if (IsDef || MRI.def_empty(Reg)) {
OS << ':'; OS << ':';
printRegClassOrBank(Reg, OS, MRI, TRI); printRegClassOrBank(Reg, OS, MRI, TRI);
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Linesvoid MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
case MachineOperand::MO_RegisterLiveOut: { case MachineOperand::MO_RegisterLiveOut: {
const uint32_t *RegMask = Op.getRegLiveOut(); const uint32_t *RegMask = Op.getRegLiveOut();
OS << "liveout("; OS << "liveout(";
bool IsCommaNeeded = false; bool IsCommaNeeded = false;
for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) { for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
if (RegMask[Reg / 32] & (1U << (Reg % 32))) { if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
if (IsCommaNeeded) if (IsCommaNeeded)
OS << ", "; OS << ", ";
printRegMIR(Reg, OS, TRI); OS << printReg(Reg, TRI);
IsCommaNeeded = true; IsCommaNeeded = true;
} }
} }
OS << ")"; OS << ")";
break; break;
} }
case MachineOperand::MO_Metadata: case MachineOperand::MO_Metadata:
Op.getMetadata()->printAsOperand(OS, MST); Op.getMetadata()->printAsOperand(OS, MST);
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
const TargetRegisterInfo *TRI) { const TargetRegisterInfo *TRI) {
int Reg = TRI->getLLVMRegNum(DwarfReg, true); int Reg = TRI->getLLVMRegNum(DwarfReg, true);
if (Reg == -1) { if (Reg == -1) {
OS << "<badreg>"; OS << "<badreg>";
return; return;
} }
printRegMIR(Reg, OS, TRI); OS << printReg(Reg, TRI);
} }
void MIPrinter::print(const MCCFIInstruction &CFI, void MIPrinter::print(const MCCFIInstruction &CFI,
const TargetRegisterInfo *TRI) { const TargetRegisterInfo *TRI) {
switch (CFI.getOperation()) { switch (CFI.getOperation()) {
case MCCFIInstruction::OpSameValue: case MCCFIInstruction::OpSameValue:
OS << "same_value "; OS << "same_value ";
if (CFI.getLabel()) if (CFI.getLabel())
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Show First 20 Lines • Show All 1,091 Lines • ▼ Show 20 Lines if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
report("Illegal subregister index for physical register", MO, MONum); report("Illegal subregister index for physical register", MO, MONum);
return; return;
} }
if (MONum < MCID.getNumOperands()) { if (MONum < MCID.getNumOperands()) {
if (const TargetRegisterClass *DRC = if (const TargetRegisterClass *DRC =
TII->getRegClass(MCID, MONum, TRI, *MF)) { TII->getRegClass(MCID, MONum, TRI, *MF)) {
if (!DRC->contains(Reg)) { if (!DRC->contains(Reg)) {
report("Illegal physical register for instruction", MO, MONum); report("Illegal physical register for instruction", MO, MONum);
errs() << TRI->getName(Reg) << " is not a " errs() << printReg(Reg, TRI) << " is not a "
<< TRI->getRegClassName(DRC) << " register.\n"; << TRI->getRegClassName(DRC) << " register.\n";
} }
} }
} }
} else { } else {
// Virtual register. // Virtual register.
const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg); const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
if (!RC) { if (!RC) {
// This is a generic virtual register. // This is a generic virtual register.
▲ Show 20 Lines • Show All 574 Lines • ▼ Show 20 Linesvoid MachineVerifier::visitMachineFunctionAfter() {
for (const auto &MBB : *MF) { for (const auto &MBB : *MF) {
BBInfo &MInfo = MBBInfoMap[&MBB]; BBInfo &MInfo = MBBInfoMap[&MBB];
for (RegSet::iterator for (RegSet::iterator
I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E; I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
++I) ++I)
if (MInfo.regsKilled.count(*I)) { if (MInfo.regsKilled.count(*I)) {
report("Virtual register killed in block, but needed live out.", &MBB); report("Virtual register killed in block, but needed live out.", &MBB);
errs() << "Virtual register " << printReg(*I) errs() << "Virtual register " << printReg(*I)
<< " is used after the block.\n"; << " is used after the block.\n";
} }
} }
if (!MF->empty()) { if (!MF->empty()) {
BBInfo &MInfo = MBBInfoMap[&MF->front()]; BBInfo &MInfo = MBBInfoMap[&MF->front()];
for (RegSet::iterator for (RegSet::iterator
I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E; I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
++I) { ++I) {
Show All 16 Lines for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
for (const auto &MBB : *MF) { for (const auto &MBB : *MF) {
BBInfo &MInfo = MBBInfoMap[&MBB]; BBInfo &MInfo = MBBInfoMap[&MBB];
// Our vregsRequired should be identical to LiveVariables' AliveBlocks // Our vregsRequired should be identical to LiveVariables' AliveBlocks
if (MInfo.vregsRequired.count(Reg)) { if (MInfo.vregsRequired.count(Reg)) {
if (!VI.AliveBlocks.test(MBB.getNumber())) { if (!VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block missing from AliveBlocks", &MBB); report("LiveVariables: Block missing from AliveBlocks", &MBB);
errs() << "Virtual register " << printReg(Reg) errs() << "Virtual register " << printReg(Reg)
<< " must be live through the block.\n"; << " must be live through the block.\n";
} }
} else { } else {
if (VI.AliveBlocks.test(MBB.getNumber())) { if (VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block should not be in AliveBlocks", &MBB); report("LiveVariables: Block should not be in AliveBlocks", &MBB);
errs() << "Virtual register " << printReg(Reg) errs() << "Virtual register " << printReg(Reg)
<< " is not needed live through the block.\n"; << " is not needed live through the block.\n";
} }
} }
} }
} }
} }
void MachineVerifier::verifyLiveIntervals() { void MachineVerifier::verifyLiveIntervals() {
assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts"); assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
▲ Show 20 Lines • Show All 497 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegAllocBasic.cpp

Show First 20 Lines • Show All 213 Lines • ▼ Show 20 Lines for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
Q.collectInterferingVRegs(); Q.collectInterferingVRegs();
for (unsigned i = Q.interferingVRegs().size(); i; --i) { for (unsigned i = Q.interferingVRegs().size(); i; --i) {
LiveInterval *Intf = Q.interferingVRegs()[i - 1]; LiveInterval *Intf = Q.interferingVRegs()[i - 1];
if (!Intf->isSpillable() || Intf->weight > VirtReg.weight) if (!Intf->isSpillable() || Intf->weight > VirtReg.weight)
return false; return false;
Intfs.push_back(Intf); Intfs.push_back(Intf);
} }
} }
DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) << DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI)
" interferences with " << VirtReg << "\n"); << " interferences with " << VirtReg << "\n");
assert(!Intfs.empty() && "expected interference"); assert(!Intfs.empty() && "expected interference");
// Spill each interfering vreg allocated to PhysReg or an alias. // Spill each interfering vreg allocated to PhysReg or an alias.
for (unsigned i = 0, e = Intfs.size(); i != e; ++i) { for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
LiveInterval &Spill = *Intfs[i]; LiveInterval &Spill = *Intfs[i];
// Skip duplicates. // Skip duplicates.
if (!VRM->hasPhys(Spill.reg)) if (!VRM->hasPhys(Spill.reg))
▲ Show 20 Lines • Show All 104 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegAllocFast.cpp

Show First 20 Lines • Show All 807 Lines • ▼ Show 20 Linesvoid RegAllocFast::handleThroughOperands(MachineInstr &MI,
for (unsigned PartialDef : PartialDefs) for (unsigned PartialDef : PartialDefs)
markRegUsedInInstr(PartialDef); markRegUsedInInstr(PartialDef);
} }
#ifndef NDEBUG #ifndef NDEBUG
void RegAllocFast::dumpState() { void RegAllocFast::dumpState() {
for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) { for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
if (PhysRegState[Reg] == regDisabled) continue; if (PhysRegState[Reg] == regDisabled) continue;
dbgs() << " " << TRI->getName(Reg); dbgs() << " " << printReg(Reg, TRI);
switch(PhysRegState[Reg]) { switch(PhysRegState[Reg]) {
case regFree: case regFree:
break; break;
case regReserved: case regReserved:
dbgs() << "*"; dbgs() << "*";
break; break;
default: { default: {
dbgs() << '=' << printReg(PhysRegState[Reg]); dbgs() << '=' << printReg(PhysRegState[Reg]);
▲ Show 20 Lines • Show All 292 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegUsageInfoCollector.cpp

Show First 20 Lines • Show All 135 Lines • ▼ Show 20 Linesbool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
} else { } else {
++NumCSROpt; ++NumCSROpt;
DEBUG(dbgs() << MF.getName() DEBUG(dbgs() << MF.getName()
<< " function optimized for not having CSR.\n"); << " function optimized for not having CSR.\n");
} }
for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg)
if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg)) if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
DEBUG(dbgs() << TRI->getName(PReg) << " "); DEBUG(dbgs() << printReg(PReg, TRI) << " ");
DEBUG(dbgs() << " \n----------------------------------------\n"); DEBUG(dbgs() << " \n----------------------------------------\n");
PRUI->storeUpdateRegUsageInfo(F, std::move(RegMask)); PRUI->storeUpdateRegUsageInfo(F, std::move(RegMask));
return false; return false;
} }

llvm/trunk/lib/CodeGen/RegisterScavenging.cpp

Show First 20 Lines • Show All 282 Lines • ▼ Show 20 Linesbool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const {
if (isReserved(Reg)) if (isReserved(Reg))
return includeReserved; return includeReserved;
return !LiveUnits.available(Reg); return !LiveUnits.available(Reg);
} }
unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
for (unsigned Reg : *RC) { for (unsigned Reg : *RC) {
if (!isRegUsed(Reg)) { if (!isRegUsed(Reg)) {
DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(Reg) << DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)
"\n"); << "\n");
return Reg; return Reg;
} }
} }
return 0; return 0;
} }
BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
BitVector Mask(TRI->getNumRegs()); BitVector Mask(TRI->getNumRegs());
▲ Show 20 Lines • Show All 255 Lines • ▼ Show 20 Lines if (Available.any())
Candidates = Available; Candidates = Available;
// Find the register whose use is furthest away. // Find the register whose use is furthest away.
MachineBasicBlock::iterator UseMI; MachineBasicBlock::iterator UseMI;
unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
// If we found an unused register there is no reason to spill it. // If we found an unused register there is no reason to spill it.
if (!isRegUsed(SReg)) { if (!isRegUsed(SReg)) {
DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n"); DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
return SReg; return SReg;
} }
ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI); ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
Scavenged.Restore = &*std::prev(UseMI); Scavenged.Restore = &*std::prev(UseMI);
DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) << DEBUG(dbgs() << "Scavenged register (with spill): " << printReg(SReg, TRI)
"\n"); << "\n");
return SReg; return SReg;
} }
unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC, unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
MachineBasicBlock::iterator To, MachineBasicBlock::iterator To,
bool RestoreAfter, int SPAdj) { bool RestoreAfter, int SPAdj) {
const MachineBasicBlock &MBB = *To->getParent(); const MachineBasicBlock &MBB = *To->getParent();
Show All 13 Lines if (SpillBefore != MBB.end()) {
MachineBasicBlock::iterator ReloadAfter = MachineBasicBlock::iterator ReloadAfter =
RestoreAfter ? std::next(MBBI) : MBBI; RestoreAfter ? std::next(MBBI) : MBBI;
MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter); MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter);
DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n'); DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n');
ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore); ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);
Scavenged.Restore = &*std::prev(SpillBefore); Scavenged.Restore = &*std::prev(SpillBefore);
LiveUnits.removeReg(Reg); LiveUnits.removeReg(Reg);
DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI) DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)
<< " until " << *SpillBefore); << " until " << *SpillBefore);
} else { } else {
DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) << '\n'); DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) << '\n');
} }
return Reg; return Reg;
} }
/// Allocate a register for the virtual register \p VReg. The last use of /// Allocate a register for the virtual register \p VReg. The last use of
/// \p VReg is around the current position of the register scavenger \p RS. /// \p VReg is around the current position of the register scavenger \p RS.
▲ Show 20 Lines • Show All 197 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/RegisterUsageInfo.cpp

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Linesvoid PhysicalRegisterUsageInfo::print(raw_ostream &OS, const Module *M) const {
for (const FuncPtrRegMaskPair *FPRMPair : FPRMPairVector) { for (const FuncPtrRegMaskPair *FPRMPair : FPRMPairVector) {
OS << FPRMPair->first->getName() << " " OS << FPRMPair->first->getName() << " "
<< "Clobbered Registers: "; << "Clobbered Registers: ";
TRI = TM->getSubtarget<TargetSubtargetInfo>(*(FPRMPair->first)) TRI = TM->getSubtarget<TargetSubtargetInfo>(*(FPRMPair->first))
.getRegisterInfo(); .getRegisterInfo();
for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg)) if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg))
OS << TRI->getName(PReg) << " "; OS << printReg(PReg, TRI) << " ";
} }
OS << "\n"; OS << "\n";
} }
} }

llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Show First 20 Lines • Show All 1,424 Lines • ▼ Show 20 Lines
/// (3) No Interferences: may unschedule to break register interferences. /// (3) No Interferences: may unschedule to break register interferences.
SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() { SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() {
SUnit *CurSU = AvailableQueue->empty() ? nullptr : AvailableQueue->pop(); SUnit *CurSU = AvailableQueue->empty() ? nullptr : AvailableQueue->pop();
auto FindAvailableNode = [&]() { auto FindAvailableNode = [&]() {
while (CurSU) { while (CurSU) {
SmallVector<unsigned, 4> LRegs; SmallVector<unsigned, 4> LRegs;
if (!DelayForLiveRegsBottomUp(CurSU, LRegs)) if (!DelayForLiveRegsBottomUp(CurSU, LRegs))
break; break;
DEBUG(dbgs() << " Interfering reg " << DEBUG(dbgs() << " Interfering reg ";
(LRegs[0] == TRI->getNumRegs() ? "CallResource" if (LRegs[0] == TRI->getNumRegs())
: TRI->getName(LRegs[0])) dbgs() << "CallResource";
<< " SU #" << CurSU->NodeNum << '\n'); else
dbgs() << printReg(LRegs[0], TRI);
dbgs() << " SU #" << CurSU->NodeNum << '\n');
std::pair<LRegsMapT::iterator, bool> LRegsPair = std::pair<LRegsMapT::iterator, bool> LRegsPair =
LRegsMap.insert(std::make_pair(CurSU, LRegs)); LRegsMap.insert(std::make_pair(CurSU, LRegs));
if (LRegsPair.second) { if (LRegsPair.second) {
CurSU->isPending = true; // This SU is not in AvailableQueue right now. CurSU->isPending = true; // This SU is not in AvailableQueue right now.
Interferences.push_back(CurSU); Interferences.push_back(CurSU);
} }
else { else {
assert(CurSU->isPending && "Interferences are pending"); assert(CurSU->isPending && "Interferences are pending");
▲ Show 20 Lines • Show All 1,674 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/StackMaps.cpp

Show First 20 Lines • Show All 187 Lines • ▼ Show 20 Lines for (const auto &Loc : CSLocs) {
OS << WSMP << "\t\tLoc " << Idx << ": "; OS << WSMP << "\t\tLoc " << Idx << ": ";
switch (Loc.Type) { switch (Loc.Type) {
case Location::Unprocessed: case Location::Unprocessed:
OS << "<Unprocessed operand>"; OS << "<Unprocessed operand>";
break; break;
case Location::Register: case Location::Register:
OS << "Register "; OS << "Register ";
if (TRI) if (TRI)
OS << TRI->getName(Loc.Reg); OS << printReg(Loc.Reg, TRI);
else else
OS << Loc.Reg; OS << Loc.Reg;
break; break;
case Location::Direct: case Location::Direct:
OS << "Direct "; OS << "Direct ";
if (TRI) if (TRI)
OS << TRI->getName(Loc.Reg); OS << printReg(Loc.Reg, TRI);
else else
OS << Loc.Reg; OS << Loc.Reg;
if (Loc.Offset) if (Loc.Offset)
OS << " + " << Loc.Offset; OS << " + " << Loc.Offset;
break; break;
case Location::Indirect: case Location::Indirect:
OS << "Indirect "; OS << "Indirect ";
if (TRI) if (TRI)
OS << TRI->getName(Loc.Reg); OS << printReg(Loc.Reg, TRI);
else else
OS << Loc.Reg; OS << Loc.Reg;
OS << "+" << Loc.Offset; OS << "+" << Loc.Offset;
break; break;
case Location::Constant: case Location::Constant:
OS << "Constant " << Loc.Offset; OS << "Constant " << Loc.Offset;
break; break;
case Location::ConstantIndex: case Location::ConstantIndex:
OS << "Constant Index " << Loc.Offset; OS << "Constant Index " << Loc.Offset;
break; break;
} }
OS << "\t[encoding: .byte " << Loc.Type << ", .byte 0" OS << "\t[encoding: .byte " << Loc.Type << ", .byte 0"
<< ", .short " << Loc.Size << ", .short " << Loc.Reg << ", .short 0" << ", .short " << Loc.Size << ", .short " << Loc.Reg << ", .short 0"
<< ", .int " << Loc.Offset << "]\n"; << ", .int " << Loc.Offset << "]\n";
Idx++; Idx++;
} }
OS << WSMP << "\thas " << LiveOuts.size() << " live-out registers\n"; OS << WSMP << "\thas " << LiveOuts.size() << " live-out registers\n";
Idx = 0; Idx = 0;
for (const auto &LO : LiveOuts) { for (const auto &LO : LiveOuts) {
OS << WSMP << "\t\tLO " << Idx << ": "; OS << WSMP << "\t\tLO " << Idx << ": ";
if (TRI) if (TRI)
OS << TRI->getName(LO.Reg); OS << printReg(LO.Reg, TRI);
else else
OS << LO.Reg; OS << LO.Reg;
OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte " OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte "
<< LO.Size << "]\n"; << LO.Size << "]\n";
Idx++; Idx++;
} }
} }
} }
▲ Show 20 Lines • Show All 338 Lines • Show Last 20 Lines

llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 LinesPrintable printReg(unsigned Reg, const TargetRegisterInfo *TRI,
unsigned SubIdx) { unsigned SubIdx) {
return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
if (!Reg) if (!Reg)
OS << "%noreg"; OS << "%noreg";
else if (TargetRegisterInfo::isStackSlot(Reg)) else if (TargetRegisterInfo::isStackSlot(Reg))
OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
else if (TargetRegisterInfo::isVirtualRegister(Reg)) else if (TargetRegisterInfo::isVirtualRegister(Reg))
OS << '%' << TargetRegisterInfo::virtReg2Index(Reg); OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
else if (TRI && Reg < TRI->getNumRegs()) { else if (!TRI)
OS << '%' << "physreg" << Reg;
else if (Reg < TRI->getNumRegs()) {
OS << '%'; OS << '%';
printLowerCase(TRI->getName(Reg), OS); printLowerCase(TRI->getName(Reg), OS);
} else } else
OS << "%physreg" << Reg; llvm_unreachable("Register kind is unsupported.");
if (SubIdx) { if (SubIdx) {
if (TRI) if (TRI)
OS << ':' << TRI->getSubRegIndexName(SubIdx); OS << ':' << TRI->getSubRegIndexName(SubIdx);
else else
OS << ":sub(" << SubIdx << ')'; OS << ":sub(" << SubIdx << ')';
} }
}); });
} }
▲ Show 20 Lines • Show All 327 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

Show First 20 Lines • Show All 532 Lines • ▼ Show 20 Linesbool AArch64A57FPLoadBalancing::colorChain(Chain *G, Color C,
// Try and obtain a free register of the right class. Without a register // Try and obtain a free register of the right class. Without a register
// to play with we cannot continue. // to play with we cannot continue.
int Reg = scavengeRegister(G, C, MBB); int Reg = scavengeRegister(G, C, MBB);
if (Reg == -1) { if (Reg == -1) {
DEBUG(dbgs() << "Scavenging (thus coloring) failed!\n"); DEBUG(dbgs() << "Scavenging (thus coloring) failed!\n");
return false; return false;
} }
DEBUG(dbgs() << " - Scavenged register: " << TRI->getName(Reg) << "\n"); DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n");
std::map<unsigned, unsigned> Substs; std::map<unsigned, unsigned> Substs;
for (MachineInstr &I : *G) { for (MachineInstr &I : *G) {
if (!G->contains(I) && (&I != G->getKill() || G->isKillImmutable())) if (!G->contains(I) && (&I != G->getKill() || G->isKillImmutable()))
continue; continue;
// I is a member of G, or I is a mutable instruction that kills G. // I is a member of G, or I is a mutable instruction that kills G.
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines for (auto &I : MI->uses())
maybeKillChain(I, Idx, ActiveChains); maybeKillChain(I, Idx, ActiveChains);
for (auto &I : MI->defs()) for (auto &I : MI->defs())
maybeKillChain(I, Idx, ActiveChains); maybeKillChain(I, Idx, ActiveChains);
// Create a new chain. Multiplies don't require forwarding so can go on any // Create a new chain. Multiplies don't require forwarding so can go on any
// unit. // unit.
unsigned DestReg = MI->getOperand(0).getReg(); unsigned DestReg = MI->getOperand(0).getReg();
DEBUG(dbgs() << "New chain started for register " DEBUG(dbgs() << "New chain started for register " << printReg(DestReg, TRI)
<< TRI->getName(DestReg) << " at " << *MI); << " at " << *MI);
auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg)); auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg));
ActiveChains[DestReg] = G.get(); ActiveChains[DestReg] = G.get();
AllChains.push_back(std::move(G)); AllChains.push_back(std::move(G));
} else if (isMla(MI)) { } else if (isMla(MI)) {
// It is beneficial to keep MLAs on the same functional unit as their // It is beneficial to keep MLAs on the same functional unit as their
// accumulator operand. // accumulator operand.
unsigned DestReg = MI->getOperand(0).getReg(); unsigned DestReg = MI->getOperand(0).getReg();
unsigned AccumReg = MI->getOperand(3).getReg(); unsigned AccumReg = MI->getOperand(3).getReg();
maybeKillChain(MI->getOperand(1), Idx, ActiveChains); maybeKillChain(MI->getOperand(1), Idx, ActiveChains);
maybeKillChain(MI->getOperand(2), Idx, ActiveChains); maybeKillChain(MI->getOperand(2), Idx, ActiveChains);
if (DestReg != AccumReg) if (DestReg != AccumReg)
maybeKillChain(MI->getOperand(0), Idx, ActiveChains); maybeKillChain(MI->getOperand(0), Idx, ActiveChains);
if (ActiveChains.find(AccumReg) != ActiveChains.end()) { if (ActiveChains.find(AccumReg) != ActiveChains.end()) {
DEBUG(dbgs() << "Chain found for accumulator register " DEBUG(dbgs() << "Chain found for accumulator register "
<< TRI->getName(AccumReg) << " in MI " << *MI); << printReg(AccumReg, TRI) << " in MI " << *MI);
// For simplicity we only chain together sequences of MULs/MLAs where the // For simplicity we only chain together sequences of MULs/MLAs where the
// accumulator register is killed on each instruction. This means we don't // accumulator register is killed on each instruction. This means we don't
// need to track other uses of the registers we want to rewrite. // need to track other uses of the registers we want to rewrite.
// //
// FIXME: We could extend to handle the non-kill cases for more coverage. // FIXME: We could extend to handle the non-kill cases for more coverage.
if (MI->getOperand(3).isKill()) { if (MI->getOperand(3).isKill()) {
// Add to chain. // Add to chain.
DEBUG(dbgs() << "Instruction was successfully added to chain.\n"); DEBUG(dbgs() << "Instruction was successfully added to chain.\n");
ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg));
// Handle cases where the destination is not the same as the accumulator. // Handle cases where the destination is not the same as the accumulator.
if (DestReg != AccumReg) { if (DestReg != AccumReg) {
ActiveChains[DestReg] = ActiveChains[AccumReg]; ActiveChains[DestReg] = ActiveChains[AccumReg];
ActiveChains.erase(AccumReg); ActiveChains.erase(AccumReg);
} }
return; return;
} }
DEBUG(dbgs() << "Cannot add to chain because accumulator operand wasn't " DEBUG(dbgs() << "Cannot add to chain because accumulator operand wasn't "
<< "marked <kill>!\n"); << "marked <kill>!\n");
maybeKillChain(MI->getOperand(3), Idx, ActiveChains); maybeKillChain(MI->getOperand(3), Idx, ActiveChains);
} }
DEBUG(dbgs() << "Creating new chain for dest register " DEBUG(dbgs() << "Creating new chain for dest register "
<< TRI->getName(DestReg) << "\n"); << printReg(DestReg, TRI) << "\n");
auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg)); auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg));
ActiveChains[DestReg] = G.get(); ActiveChains[DestReg] = G.get();
AllChains.push_back(std::move(G)); AllChains.push_back(std::move(G));
} else { } else {
// Non-MUL or MLA instruction. Invalidate any chain in the uses or defs // Non-MUL or MLA instruction. Invalidate any chain in the uses or defs
// lists. // lists.
Show All 11 LinesmaybeKillChain(MachineOperand &MO, unsigned Idx,
// Given an operand and the set of active chains (keyed by register), // Given an operand and the set of active chains (keyed by register),
// determine if a chain should be ended and remove from ActiveChains. // determine if a chain should be ended and remove from ActiveChains.
MachineInstr *MI = MO.getParent(); MachineInstr *MI = MO.getParent();
if (MO.isReg()) { if (MO.isReg()) {
// If this is a KILL of a current chain, record it. // If this is a KILL of a current chain, record it.
if (MO.isKill() && ActiveChains.find(MO.getReg()) != ActiveChains.end()) { if (MO.isKill() && ActiveChains.find(MO.getReg()) != ActiveChains.end()) {
DEBUG(dbgs() << "Kill seen for chain " << TRI->getName(MO.getReg()) DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI)
<< "\n"); << "\n");
ActiveChains[MO.getReg()]->setKill(MI, Idx, /*Immutable=*/MO.isTied()); ActiveChains[MO.getReg()]->setKill(MI, Idx, /*Immutable=*/MO.isTied());
} }
ActiveChains.erase(MO.getReg()); ActiveChains.erase(MO.getReg());
} else if (MO.isRegMask()) { } else if (MO.isRegMask()) {
for (auto I = ActiveChains.begin(), E = ActiveChains.end(); for (auto I = ActiveChains.begin(), E = ActiveChains.end();
I != E;) { I != E;) {
if (MO.clobbersPhysReg(I->first)) { if (MO.clobbersPhysReg(I->first)) {
DEBUG(dbgs() << "Kill (regmask) seen for chain " DEBUG(dbgs() << "Kill (regmask) seen for chain "
<< TRI->getName(I->first) << "\n"); << printReg(I->first, TRI) << "\n");
I->second->setKill(MI, Idx, /*Immutable=*/true); I->second->setKill(MI, Idx, /*Immutable=*/true);
ActiveChains.erase(I++); ActiveChains.erase(I++);
} else } else
++I; ++I;
} }
} }
} }
Show All 12 Lines

llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp

Show First 20 Lines • Show All 1,054 Lines • ▼ Show 20 Lines for (auto RPII = RegPairs.rbegin(), RPIE = RegPairs.rend(); RPII != RPIE;
// stp fp, lr, [sp, #32] // addImm(+4) // stp fp, lr, [sp, #32] // addImm(+4)
// Rationale: This sequence saves uop updates compared to a sequence of // Rationale: This sequence saves uop updates compared to a sequence of
// pre-increment spills like stp xi,xj,[sp,#-16]! // pre-increment spills like stp xi,xj,[sp,#-16]!
// Note: Similar rationale and sequence for restores in epilog. // Note: Similar rationale and sequence for restores in epilog.
if (RPI.IsGPR) if (RPI.IsGPR)
StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui; StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui;
else else
StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui; StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui;
DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1); DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI);
if (RPI.isPaired()) if (RPI.isPaired())
dbgs() << ", " << TRI->getName(Reg2); dbgs() << ", " << printReg(Reg2, TRI);
dbgs() << ") -> fi#(" << RPI.FrameIdx; dbgs() << ") -> fi#(" << RPI.FrameIdx;
if (RPI.isPaired()) if (RPI.isPaired())
dbgs() << ", " << RPI.FrameIdx+1; dbgs() << ", " << RPI.FrameIdx+1;
dbgs() << ")\n"); dbgs() << ")\n");
MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc)); MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc));
if (!MRI.isReserved(Reg1)) if (!MRI.isReserved(Reg1))
MBB.addLiveIn(Reg1); MBB.addLiveIn(Reg1);
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines for (auto RPII = RegPairs.begin(), RPIE = RegPairs.end(); RPII != RPIE;
// ldp x20, x19, [sp, #16] // addImm(+2) // ldp x20, x19, [sp, #16] // addImm(+2)
// ldp x22, x21, [sp, #0] // addImm(+0) // ldp x22, x21, [sp, #0] // addImm(+0)
// Note: see comment in spillCalleeSavedRegisters() // Note: see comment in spillCalleeSavedRegisters()
unsigned LdrOpc; unsigned LdrOpc;
if (RPI.IsGPR) if (RPI.IsGPR)
LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui; LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui;
else else
LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui; LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui;
DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1); DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI);
if (RPI.isPaired()) if (RPI.isPaired())
dbgs() << ", " << TRI->getName(Reg2); dbgs() << ", " << printReg(Reg2, TRI);
dbgs() << ") -> fi#(" << RPI.FrameIdx; dbgs() << ") -> fi#(" << RPI.FrameIdx;
if (RPI.isPaired()) if (RPI.isPaired())
dbgs() << ", " << RPI.FrameIdx+1; dbgs() << ", " << RPI.FrameIdx+1;
dbgs() << ")\n"); dbgs() << ")\n");
MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdrOpc)); MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdrOpc));
if (RPI.isPaired()) { if (RPI.isPaired()) {
MIB.addReg(Reg2, getDefRegState(true)); MIB.addReg(Reg2, getDefRegState(true));
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Linesvoid AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
// to materialize a stack offset. If so, either spill one additional // to materialize a stack offset. If so, either spill one additional
// callee-saved register or reserve a special spill slot to facilitate // callee-saved register or reserve a special spill slot to facilitate
// register scavenging. If we already spilled an extra callee-saved register // register scavenging. If we already spilled an extra callee-saved register
// above to keep the number of spills even, we don't need to do anything else // above to keep the number of spills even, we don't need to do anything else
// here. // here.
if (BigStack) { if (BigStack) {
if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) { if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) {
DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo) DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)
<< " to get a scratch register.\n"); << " to get a scratch register.\n");
SavedRegs.set(UnspilledCSGPR); SavedRegs.set(UnspilledCSGPR);
// MachO's compact unwind format relies on all registers being stored in // MachO's compact unwind format relies on all registers being stored in
// pairs, so if we need to spill one extra for BigStack, then we need to // pairs, so if we need to spill one extra for BigStack, then we need to
// store the pair. // store the pair.
if (produceCompactUnwindFrame(MF)) if (produceCompactUnwindFrame(MF))
SavedRegs.set(UnspilledCSGPRPaired); SavedRegs.set(UnspilledCSGPRPaired);
ExtraCSSpill = UnspilledCSGPRPaired; ExtraCSSpill = UnspilledCSGPRPaired;
NumRegsSpilled = SavedRegs.count(); NumRegsSpilled = SavedRegs.count();
Show All 26 Lines

llvm/trunk/lib/Target/BPF/BPFISelDAGToDAG.cpp

Show First 20 Lines • Show All 540 Lines • ▼ Show 20 Linesvoid BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node,
if (BaseV.getOpcode() != ISD::CopyFromReg) if (BaseV.getOpcode() != ISD::CopyFromReg)
return; return;
const RegisterSDNode *RegN = const RegisterSDNode *RegN =
dyn_cast<RegisterSDNode>(BaseV.getNode()->getOperand(1)); dyn_cast<RegisterSDNode>(BaseV.getNode()->getOperand(1));
if (!RegN || !TargetRegisterInfo::isVirtualRegister(RegN->getReg())) if (!RegN || !TargetRegisterInfo::isVirtualRegister(RegN->getReg()))
return; return;
unsigned AndOpReg = RegN->getReg(); unsigned AndOpReg = RegN->getReg();
DEBUG(dbgs() << "Examine %" << TargetRegisterInfo::virtReg2Index(AndOpReg) DEBUG(dbgs() << "Examine " << printReg(AndOpReg) << '\n');
<< '\n');
// Examine the PHI insns in the MachineBasicBlock to found out the // Examine the PHI insns in the MachineBasicBlock to found out the
// definitions of this virtual register. At this stage (DAG2DAG // definitions of this virtual register. At this stage (DAG2DAG
// transformation), only PHI machine insns are available in the machine basic // transformation), only PHI machine insns are available in the machine basic
// block. // block.
MachineBasicBlock *MBB = FuncInfo->MBB; MachineBasicBlock *MBB = FuncInfo->MBB;
MachineInstr *MII = nullptr; MachineInstr *MII = nullptr;
for (auto &MI : *MBB) { for (auto &MI : *MBB) {
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/debug-insts.ll

; RUN: llc -global-isel -mtriple=aarch64 %s -stop-after=irtranslator -o - | FileCheck %s ; RUN: llc -global-isel -mtriple=aarch64 %s -stop-after=irtranslator -o - | FileCheck %s
; RUN: llc -mtriple=aarch64 -global-isel --global-isel-abort=0 -o /dev/null ; RUN: llc -mtriple=aarch64 -global-isel --global-isel-abort=0 -o /dev/null
; CHECK-LABEL: name: debug_declare ; CHECK-LABEL: name: debug_declare
; CHECK: stack: ; CHECK: stack:
; CHECK: - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}}, ; CHECK: - { id: {{.*}}, name: in.addr, type: default, offset: 0, size: {{.*}}, alignment: {{.*}},
; CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true, ; CHECK-NEXT: callee-saved-register: '', callee-saved-restored: true,
; CHECK-NEXT: di-variable: '!11', di-expression: '!DIExpression()', ; CHECK-NEXT: di-variable: '!11', di-expression: '!DIExpression()',
; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !11, !DIExpression(), debug-location !12 ; CHECK: DBG_VALUE debug-use %0(s32), debug-use %noreg, !11, !DIExpression(), debug-location !12
define void @debug_declare(i32 %in) #0 !dbg !7 { define void @debug_declare(i32 %in) #0 !dbg !7 {
entry: entry:
%in.addr = alloca i32, align 4 %in.addr = alloca i32, align 4
store i32 %in, i32* %in.addr, align 4 store i32 %in, i32* %in.addr, align 4
call void @llvm.dbg.declare(metadata i32* %in.addr, metadata !11, metadata !DIExpression()), !dbg !12 call void @llvm.dbg.declare(metadata i32* %in.addr, metadata !11, metadata !DIExpression()), !dbg !12
call void @llvm.dbg.declare(metadata i32 %in, metadata !11, metadata !DIExpression()), !dbg !12 call void @llvm.dbg.declare(metadata i32 %in, metadata !11, metadata !DIExpression()), !dbg !12
ret void, !dbg !12 ret void, !dbg !12
} }
; CHECK-LABEL: name: debug_declare_vla ; CHECK-LABEL: name: debug_declare_vla
; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use _, !14, !DIExpression(), debug-location !15 ; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use %noreg, !14, !DIExpression(), debug-location !15
define void @debug_declare_vla(i32 %in) #0 !dbg !13 { define void @debug_declare_vla(i32 %in) #0 !dbg !13 {
entry: entry:
%vla.addr = alloca i32, i32 %in %vla.addr = alloca i32, i32 %in
call void @llvm.dbg.declare(metadata i32* %vla.addr, metadata !14, metadata !DIExpression()), !dbg !15 call void @llvm.dbg.declare(metadata i32* %vla.addr, metadata !14, metadata !DIExpression()), !dbg !15
ret void, !dbg !15 ret void, !dbg !15
} }
; CHECK-LABEL: name: debug_value ; CHECK-LABEL: name: debug_value
; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0 ; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
define void @debug_value(i32 %in) #0 !dbg !16 { define void @debug_value(i32 %in) #0 !dbg !16 {
%addr = alloca i32 %addr = alloca i32
; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use _, !17, !DIExpression(), debug-location !18 ; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use %noreg, !17, !DIExpression(), debug-location !18
call void @llvm.dbg.value(metadata i32 %in, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 call void @llvm.dbg.value(metadata i32 %in, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
store i32 %in, i32* %addr store i32 %in, i32* %addr
; CHECK: DBG_VALUE debug-use %1(p0), debug-use _, !17, !DIExpression(DW_OP_deref), debug-location !18 ; CHECK: DBG_VALUE debug-use %1(p0), debug-use %noreg, !17, !DIExpression(DW_OP_deref), debug-location !18
call void @llvm.dbg.value(metadata i32* %addr, i64 0, metadata !17, metadata !DIExpression(DW_OP_deref)), !dbg !18 call void @llvm.dbg.value(metadata i32* %addr, i64 0, metadata !17, metadata !DIExpression(DW_OP_deref)), !dbg !18
; CHECK: DBG_VALUE 123, 0, !17, !DIExpression(), debug-location !18 ; CHECK: DBG_VALUE 123, 0, !17, !DIExpression(), debug-location !18
call void @llvm.dbg.value(metadata i32 123, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 call void @llvm.dbg.value(metadata i32 123, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
; CHECK: DBG_VALUE float 1.000000e+00, 0, !17, !DIExpression(), debug-location !18 ; CHECK: DBG_VALUE float 1.000000e+00, 0, !17, !DIExpression(), debug-location !18
call void @llvm.dbg.value(metadata float 1.000000e+00, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 call void @llvm.dbg.value(metadata float 1.000000e+00, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
; CHECK: DBG_VALUE _, 0, !17, !DIExpression(), debug-location !18 ; CHECK: DBG_VALUE %noreg, 0, !17, !DIExpression(), debug-location !18
call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !17, metadata !DIExpression()), !dbg !18
ret void ret void
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare void @llvm.dbg.declare(metadata, metadata, metadata) declare void @llvm.dbg.declare(metadata, metadata, metadata)
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
Show All 23 Lines

llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir

Show All 30 Lines
name: test_dbg_value name: test_dbg_value
legalized: true legalized: true
# CHECK: registers: # CHECK: registers:
# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } # CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
body: | body: |
bb.0: bb.0:
liveins: %w0 liveins: %w0
%0:_(s32) = COPY %w0 %0:_(s32) = COPY %w0
; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9 ; CHECK: DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9 DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
; CHECK: DBG_VALUE _, 0, !7, !DIExpression(), debug-location !9 ; CHECK: DBG_VALUE %noreg, 0, !7, !DIExpression(), debug-location !9
DBG_VALUE _, 0, !7, !DIExpression(), debug-location !9 DBG_VALUE %noreg, 0, !7, !DIExpression(), debug-location !9
... ...

llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir

Show All 40 Lines
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: %w0 liveins: %w0
; CHECK-LABEL: name: test_dbg_value ; CHECK-LABEL: name: test_dbg_value
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY]] ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY]]
; CHECK: %w0 = COPY [[ADDWrr]] ; CHECK: %w0 = COPY [[ADDWrr]]
; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use _, !7, !DIExpression(), debug-location !9 ; CHECK: DBG_VALUE debug-use [[ADDWrr]], debug-use %noreg, !7, !DIExpression(), debug-location !9
%0:gpr(s32) = COPY %w0 %0:gpr(s32) = COPY %w0
%1:gpr(s32) = G_ADD %0, %0 %1:gpr(s32) = G_ADD %0, %0
%w0 = COPY %1(s32) %w0 = COPY %1(s32)
DBG_VALUE debug-use %1(s32), debug-use _, !7, !DIExpression(), debug-location !9 DBG_VALUE debug-use %1(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
... ...
--- ---
name: test_dbg_value_dead name: test_dbg_value_dead
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: %w0 liveins: %w0
; CHECK-LABEL: name: test_dbg_value_dead ; CHECK-LABEL: name: test_dbg_value_dead
; CHECK-NOT: COPY ; CHECK-NOT: COPY
; CHECK: DBG_VALUE debug-use _, debug-use _, !7, !DIExpression(), debug-location !9 ; CHECK: DBG_VALUE debug-use %noreg, debug-use %noreg, !7, !DIExpression(), debug-location !9
%0:gpr(s32) = COPY %w0 %0:gpr(s32) = COPY %w0
DBG_VALUE debug-use %0(s32), debug-use _, !7, !DIExpression(), debug-location !9 DBG_VALUE debug-use %0(s32), debug-use %noreg, !7, !DIExpression(), debug-location !9
... ...

llvm/trunk/test/CodeGen/AArch64/machine-outliner-remarks.ll

Show First 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
!12 = !DILocation(line: 5, column: 9, scope: !8) !12 = !DILocation(line: 5, column: 9, scope: !8)
!14 = distinct !DISubprogram(name: "cat", scope: !1, file: !1, line: 10, type: !9, isLocal: false, isDefinition: true, scopeLine: 11, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !14 = distinct !DISubprogram(name: "cat", scope: !1, file: !1, line: 10, type: !9, isLocal: false, isDefinition: true, scopeLine: 11, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
!16 = !DILocation(line: 13, column: 9, scope: !14) !16 = !DILocation(line: 13, column: 9, scope: !14)
!18 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 26, type: !9, isLocal: false, isDefinition: true, scopeLine: 26, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !18 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 26, type: !9, isLocal: false, isDefinition: true, scopeLine: 26, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
!24 = !DILocation(line: 27, column: 9, scope: !18) !24 = !DILocation(line: 27, column: 9, scope: !18)
!26 = !DILocation(line: 29, column: 9, scope: !18) !26 = !DILocation(line: 29, column: 9, scope: !18)
!27 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 35, type: !9, isLocal: false, isDefinition: true, scopeLine: 35, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !27 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 35, type: !9, isLocal: false, isDefinition: true, scopeLine: 35, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
!33 = !DILocation(line: 36, column: 1, scope: !27) !33 = !DILocation(line: 36, column: 1, scope: !27)
!35 = !DILocation(line: 38, column: 1, scope: !27) !35 = !DILocation(line: 38, column: 1, scope: !27)
No newline at end of file

llvm/trunk/test/CodeGen/AMDGPU/fadd.ll

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
; SI-NOT: v_add_f32 ; SI-NOT: v_add_f32
define amdgpu_kernel void @fadd_0_nsz_attr_f32(float addrspace(1)* %out, float %a) #1 { define amdgpu_kernel void @fadd_0_nsz_attr_f32(float addrspace(1)* %out, float %a) #1 {
%add = fadd float %a, 0.0 %add = fadd float %a, 0.0
store float %add, float addrspace(1)* %out, align 4 store float %add, float addrspace(1)* %out, align 4
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" } attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" }
No newline at end of file

llvm/trunk/test/CodeGen/AMDGPU/inserted-wait-states.mir

Show First 20 Lines • Show All 542 Lines • ▼ Show 20 Linesstack:
- { id: 0, name: A.addr, offset: 0, size: 8, alignment: 8, local-offset: 0 } - { id: 0, name: A.addr, offset: 0, size: 8, alignment: 8, local-offset: 0 }
- { id: 1, offset: 8, size: 4, alignment: 4 } - { id: 1, offset: 8, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %sgpr4_sgpr5, %sgpr6_sgpr7, %sgpr9, %sgpr0_sgpr1_sgpr2_sgpr3 liveins: %sgpr4_sgpr5, %sgpr6_sgpr7, %sgpr9, %sgpr0_sgpr1_sgpr2_sgpr3
%flat_scr_lo = S_ADD_U32 %sgpr6, %sgpr9, implicit-def %scc %flat_scr_lo = S_ADD_U32 %sgpr6, %sgpr9, implicit-def %scc
%flat_scr_hi = S_ADDC_U32 %sgpr7, 0, implicit-def %scc, implicit %scc %flat_scr_hi = S_ADDC_U32 %sgpr7, 0, implicit-def %scc, implicit %scc
DBG_VALUE _, 2, !5, !11, debug-location !12 DBG_VALUE %noreg, 2, !5, !11, debug-location !12
%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr4_sgpr5, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
dead %sgpr6_sgpr7 = KILL %sgpr4_sgpr5 dead %sgpr6_sgpr7 = KILL %sgpr4_sgpr5
%sgpr8 = S_MOV_B32 %sgpr5 %sgpr8 = S_MOV_B32 %sgpr5
%vgpr0 = V_MOV_B32_e32 killed %sgpr8, implicit %exec %vgpr0 = V_MOV_B32_e32 killed %sgpr8, implicit %exec
BUFFER_STORE_DWORD_OFFSET %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr9, 4, 0, 0, 0, implicit %exec :: (store 4 into %ir.A.addr + 4) BUFFER_STORE_DWORD_OFFSET %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr9, 4, 0, 0, 0, implicit %exec :: (store 4 into %ir.A.addr + 4)
%sgpr8 = S_MOV_B32 %sgpr4, implicit killed %sgpr4_sgpr5 %sgpr8 = S_MOV_B32 %sgpr4, implicit killed %sgpr4_sgpr5
%vgpr0 = V_MOV_B32_e32 killed %sgpr8, implicit %exec %vgpr0 = V_MOV_B32_e32 killed %sgpr8, implicit %exec
BUFFER_STORE_DWORD_OFFSET %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr9, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.A.addr) BUFFER_STORE_DWORD_OFFSET %vgpr0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr9, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.A.addr)
S_ENDPGM S_ENDPGM
... ...

llvm/trunk/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Linesbb:
%tmp3 = select i1 %tmp2, double* null, double* %tmp %tmp3 = select i1 %tmp2, double* null, double* %tmp
store double 1.000000e+00, double* %tmp3, align 8 store double 1.000000e+00, double* %tmp3, align 8
%tmp4 = load double, double* %tmp, align 8 %tmp4 = load double, double* %tmp, align 8
store double %tmp4, double addrspace(1)* %arg store double %tmp4, double addrspace(1)* %arg
ret void ret void
} }
attributes #0 = { norecurse nounwind "amdgpu-waves-per-eu"="1,1" } attributes #0 = { norecurse nounwind "amdgpu-waves-per-eu"="1,1" }
attributes #1 = { norecurse nounwind } attributes #1 = { norecurse nounwind }
No newline at end of file

llvm/trunk/test/CodeGen/AMDGPU/regcoalesce-dbg.mir

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines bb.0:
%0 = COPY killed %sgpr0_sgpr1 %0 = COPY killed %sgpr0_sgpr1
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
%5 = S_LOAD_DWORD_IMM killed %0, 13, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`) %5 = S_LOAD_DWORD_IMM killed %0, 13, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)
%18 = V_ASHRREV_I32_e32 31, %3, implicit %exec %18 = V_ASHRREV_I32_e32 31, %3, implicit %exec
undef %19.sub0 = COPY killed %3 undef %19.sub0 = COPY killed %3
%19.sub1 = COPY killed %18 %19.sub1 = COPY killed %18
%10 = S_MOV_B32 61440 %10 = S_MOV_B32 61440
%11 = S_MOV_B32 0 %11 = S_MOV_B32 0
DBG_VALUE debug-use %11, debug-use _, !1, !8, debug-location !9 DBG_VALUE debug-use %11, debug-use %noreg, !1, !8, debug-location !9
undef %12.sub0 = COPY killed %11 undef %12.sub0 = COPY killed %11
%12.sub1 = COPY killed %10 %12.sub1 = COPY killed %10
undef %13.sub0_sub1 = COPY killed %4 undef %13.sub0_sub1 = COPY killed %4
%13.sub2_sub3 = COPY killed %12 %13.sub2_sub3 = COPY killed %12
%20 = V_LSHL_B64 killed %19, 2, implicit %exec %20 = V_LSHL_B64 killed %19, 2, implicit %exec
%16 = COPY killed %5 %16 = COPY killed %5
BUFFER_STORE_DWORD_ADDR64 killed %16, killed %20, killed %13, 0, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.out) BUFFER_STORE_DWORD_ADDR64 killed %16, killed %20, killed %13, 0, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.out)
S_ENDPGM S_ENDPGM
... ...

llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir

Show First 20 Lines • Show All 114 Lines • ▼ Show 20 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
stack: stack:
- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr', callee-saved-restored: false } - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr', callee-saved-restored: false }
- { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7', callee-saved-restored: true } - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7', callee-saved-restored: true }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0, %r1, %r2, %r3, %lr, %r7 liveins: %r0, %r1, %r2, %r3, %lr, %r7
DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31 t2CMPri %r3, 4, 14, %noreg, implicit-def %cpsr, debug-location !31
t2Bcc %bb.2.if.end, 2, killed %cpsr t2Bcc %bb.2.if.end, 2, killed %cpsr
bb.1: bb.1:
liveins: %lr, %r7 liveins: %lr, %r7
DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
%r0 = t2MOVi -1, 14, _, _ %r0 = t2MOVi -1, 14, %noreg, %noreg
DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
tBX_RET 14, _, implicit %r0, debug-location !34 tBX_RET 14, %noreg, implicit %r0, debug-location !34
bb.2.if.end: bb.2.if.end:
liveins: %r0, %r2, %r3, %r7, %lr liveins: %r0, %r2, %r3, %r7, %lr
%sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr %sp = frame-setup t2STMDB_UPD %sp, 14, %noreg, killed %r7, killed %lr
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset %lr, -4 frame-setup CFI_INSTRUCTION offset %lr, -4
frame-setup CFI_INSTRUCTION offset %r7, -8 frame-setup CFI_INSTRUCTION offset %r7, -8
DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
%r1 = COPY killed %r2, debug-location !32 %r1 = COPY killed %r2, debug-location !32
DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
%r2 = COPY killed %r3, debug-location !32 %r2 = COPY killed %r3, debug-location !32
tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32 tBL 14, %noreg, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
%r0 = t2MOVi 0, 14, _, _ %r0 = t2MOVi 0, 14, %noreg, %noreg
%sp = t2LDMIA_UPD %sp, 14, _, def %r7, def %lr %sp = t2LDMIA_UPD %sp, 14, %noreg, def %r7, def %lr
tBX_RET 14, _, implicit %r0, debug-location !34 tBX_RET 14, %noreg, implicit %r0, debug-location !34
# Verify that the DBG_VALUE is ignored. # Verify that the DBG_VALUE is ignored.
# CHECK: %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0 # CHECK: %sp = t2LDMIA_RET %sp, 14, %noreg, def %r7, def %pc, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll

; RUN: llc -mtriple arm-unknown -mattr=-v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NOV4T ; RUN: llc -mtriple arm-unknown -mattr=-v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,NOV4T
; RUN: llc -mtriple arm-unknown -mattr=+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V4T ; RUN: llc -mtriple arm-unknown -mattr=+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V4T
; RUN: llc -mtriple arm-unknown -mattr=+v5t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V5T ; RUN: llc -mtriple arm-unknown -mattr=+v5t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=CHECK,V5T
define arm_aapcscc void @test_indirect_call(void() *%fptr) { define arm_aapcscc void @test_indirect_call(void() *%fptr) {
; CHECK-LABEL: name: test_indirect_call ; CHECK-LABEL: name: test_indirect_call
; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY %r0 ; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY %r0
; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0 ; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0 ; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY %r0
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp ; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp ; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp ; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
entry: entry:
notail call arm_aapcscc void %fptr() notail call arm_aapcscc void %fptr()
ret void ret void
} }
declare arm_aapcscc void @call_target() declare arm_aapcscc void @call_target()
define arm_aapcscc void @test_direct_call() { define arm_aapcscc void @test_direct_call() {
; CHECK-LABEL: name: test_direct_call ; CHECK-LABEL: name: test_direct_call
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: BL @call_target, csr_aapcs, implicit-def %lr, implicit %sp ; CHECK: BL @call_target, csr_aapcs, implicit-def %lr, implicit %sp
; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
entry: entry:
notail call arm_aapcscc void @call_target() notail call arm_aapcscc void @call_target()
ret void ret void
} }

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Linesregisters:
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
; CHECK-LABEL: name: test_icmp_eq_s32 ; CHECK-LABEL: name: test_icmp_eq_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1 %2(s1) = G_ICMP intpred(eq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_icmp_ne_s32 name: test_icmp_ne_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
; CHECK-LABEL: name: test_icmp_ne_s32 ; CHECK-LABEL: name: test_icmp_ne_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(ne), %0(s32), %1 %2(s1) = G_ICMP intpred(ne), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_icmp_ugt_s32 name: test_icmp_ugt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
; CHECK-LABEL: name: test_icmp_ugt_s32 ; CHECK-LABEL: name: test_icmp_ugt_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(ugt), %0(s32), %1 %2(s1) = G_ICMP intpred(ugt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_icmp_uge_s32 name: test_icmp_uge_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
; CHECK-LABEL: name: test_icmp_uge_s32 ; CHECK-LABEL: name: test_icmp_uge_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 2, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 2, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(uge), %0(s32), %1 %2(s1) = G_ICMP intpred(uge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_icmp_ult_s32 name: test_icmp_ult_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
; CHECK-LABEL: name: test_icmp_ult_s32 ; CHECK-LABEL: name: test_icmp_ult_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 3, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 3, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(ult), %0(s32), %1 %2(s1) = G_ICMP intpred(ult), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_icmp_ule_s32 name: test_icmp_ule_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
; CHECK-LABEL: name: test_icmp_ule_s32 ; CHECK-LABEL: name: test_icmp_ule_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(ule), %0(s32), %1 %2(s1) = G_ICMP intpred(ule), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_icmp_sgt_s32 name: test_icmp_sgt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
; CHECK-LABEL: name: test_icmp_sgt_s32 ; CHECK-LABEL: name: test_icmp_sgt_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(sgt), %0(s32), %1 %2(s1) = G_ICMP intpred(sgt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_icmp_sge_s32 name: test_icmp_sge_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
; CHECK-LABEL: name: test_icmp_sge_s32 ; CHECK-LABEL: name: test_icmp_sge_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(sge), %0(s32), %1 %2(s1) = G_ICMP intpred(sge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_icmp_slt_s32 name: test_icmp_slt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
; CHECK-LABEL: name: test_icmp_slt_s32 ; CHECK-LABEL: name: test_icmp_slt_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(slt), %0(s32), %1 %2(s1) = G_ICMP intpred(slt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_icmp_sle_s32 name: test_icmp_sle_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
; CHECK-LABEL: name: test_icmp_sle_s32 ; CHECK-LABEL: name: test_icmp_sle_s32
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY %r0
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY %r1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, %noreg, implicit-def %cpsr
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(sle), %0(s32), %1 %2(s1) = G_ICMP intpred(sle), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_true_s32 name: test_fcmp_true_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_true_s32 ; CHECK-LABEL: name: test_fcmp_true_s32
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, %noreg, %noreg
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(true), %0(s32), %1 %2(s1) = G_FCMP floatpred(true), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_false_s32 name: test_fcmp_false_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_false_s32 ; CHECK-LABEL: name: test_fcmp_false_s32
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(false), %0(s32), %1 %2(s1) = G_FCMP floatpred(false), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_oeq_s32 name: test_fcmp_oeq_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_oeq_s32 ; CHECK-LABEL: name: test_fcmp_oeq_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(oeq), %0(s32), %1 %2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ogt_s32 name: test_fcmp_ogt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_ogt_s32 ; CHECK-LABEL: name: test_fcmp_ogt_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(ogt), %0(s32), %1 %2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_oge_s32 name: test_fcmp_oge_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_oge_s32 ; CHECK-LABEL: name: test_fcmp_oge_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(oge), %0(s32), %1 %2(s1) = G_FCMP floatpred(oge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_olt_s32 name: test_fcmp_olt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_olt_s32 ; CHECK-LABEL: name: test_fcmp_olt_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(olt), %0(s32), %1 %2(s1) = G_FCMP floatpred(olt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ole_s32 name: test_fcmp_ole_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_ole_s32 ; CHECK-LABEL: name: test_fcmp_ole_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(ole), %0(s32), %1 %2(s1) = G_FCMP floatpred(ole), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ord_s32 name: test_fcmp_ord_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_ord_s32 ; CHECK-LABEL: name: test_fcmp_ord_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(ord), %0(s32), %1 %2(s1) = G_FCMP floatpred(ord), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ugt_s32 name: test_fcmp_ugt_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_ugt_s32 ; CHECK-LABEL: name: test_fcmp_ugt_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(ugt), %0(s32), %1 %2(s1) = G_FCMP floatpred(ugt), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_uge_s32 name: test_fcmp_uge_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_uge_s32 ; CHECK-LABEL: name: test_fcmp_uge_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(uge), %0(s32), %1 %2(s1) = G_FCMP floatpred(uge), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ult_s32 name: test_fcmp_ult_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_ult_s32 ; CHECK-LABEL: name: test_fcmp_ult_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(ult), %0(s32), %1 %2(s1) = G_FCMP floatpred(ult), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ule_s32 name: test_fcmp_ule_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_ule_s32 ; CHECK-LABEL: name: test_fcmp_ule_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(ule), %0(s32), %1 %2(s1) = G_FCMP floatpred(ule), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_une_s32 name: test_fcmp_une_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_une_s32 ; CHECK-LABEL: name: test_fcmp_une_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(une), %0(s32), %1 %2(s1) = G_FCMP floatpred(une), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_uno_s32 name: test_fcmp_uno_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_uno_s32 ; CHECK-LABEL: name: test_fcmp_uno_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(uno), %0(s32), %1 %2(s1) = G_FCMP floatpred(uno), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_one_s32 name: test_fcmp_one_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_one_s32 ; CHECK-LABEL: name: test_fcmp_one_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(one), %0(s32), %1 %2(s1) = G_FCMP floatpred(one), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ueq_s32 name: test_fcmp_ueq_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
; CHECK-LABEL: name: test_fcmp_ueq_s32 ; CHECK-LABEL: name: test_fcmp_ueq_s32
; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY %s0
; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY %s1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(ueq), %0(s32), %1 %2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_true_s64 name: test_fcmp_true_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_true_s64 ; CHECK-LABEL: name: test_fcmp_true_s64
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, %noreg, %noreg
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(true), %0(s64), %1 %2(s1) = G_FCMP floatpred(true), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_false_s64 name: test_fcmp_false_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_false_s64 ; CHECK-LABEL: name: test_fcmp_false_s64
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(false), %0(s64), %1 %2(s1) = G_FCMP floatpred(false), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_oeq_s64 name: test_fcmp_oeq_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_oeq_s64 ; CHECK-LABEL: name: test_fcmp_oeq_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(oeq), %0(s64), %1 %2(s1) = G_FCMP floatpred(oeq), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ogt_s64 name: test_fcmp_ogt_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_ogt_s64 ; CHECK-LABEL: name: test_fcmp_ogt_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(ogt), %0(s64), %1 %2(s1) = G_FCMP floatpred(ogt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_oge_s64 name: test_fcmp_oge_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_oge_s64 ; CHECK-LABEL: name: test_fcmp_oge_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(oge), %0(s64), %1 %2(s1) = G_FCMP floatpred(oge), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_olt_s64 name: test_fcmp_olt_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_olt_s64 ; CHECK-LABEL: name: test_fcmp_olt_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(olt), %0(s64), %1 %2(s1) = G_FCMP floatpred(olt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ole_s64 name: test_fcmp_ole_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_ole_s64 ; CHECK-LABEL: name: test_fcmp_ole_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(ole), %0(s64), %1 %2(s1) = G_FCMP floatpred(ole), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ord_s64 name: test_fcmp_ord_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_ord_s64 ; CHECK-LABEL: name: test_fcmp_ord_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(ord), %0(s64), %1 %2(s1) = G_FCMP floatpred(ord), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ugt_s64 name: test_fcmp_ugt_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_ugt_s64 ; CHECK-LABEL: name: test_fcmp_ugt_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(ugt), %0(s64), %1 %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_uge_s64 name: test_fcmp_uge_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_uge_s64 ; CHECK-LABEL: name: test_fcmp_uge_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(uge), %0(s64), %1 %2(s1) = G_FCMP floatpred(uge), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ult_s64 name: test_fcmp_ult_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_ult_s64 ; CHECK-LABEL: name: test_fcmp_ult_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(ult), %0(s64), %1 %2(s1) = G_FCMP floatpred(ult), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ule_s64 name: test_fcmp_ule_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_ule_s64 ; CHECK-LABEL: name: test_fcmp_ule_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(ule), %0(s64), %1 %2(s1) = G_FCMP floatpred(ule), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_une_s64 name: test_fcmp_une_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_une_s64 ; CHECK-LABEL: name: test_fcmp_une_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(une), %0(s64), %1 %2(s1) = G_FCMP floatpred(une), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_uno_s64 name: test_fcmp_uno_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_uno_s64 ; CHECK-LABEL: name: test_fcmp_uno_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(uno), %0(s64), %1 %2(s1) = G_FCMP floatpred(uno), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_one_s64 name: test_fcmp_one_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_one_s64 ; CHECK-LABEL: name: test_fcmp_one_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, %cpsr
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(one), %0(s64), %1 %2(s1) = G_FCMP floatpred(one), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ueq_s64 name: test_fcmp_ueq_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
- { id: 3, class: gprb } - { id: 3, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
; CHECK-LABEL: name: test_fcmp_ueq_s64 ; CHECK-LABEL: name: test_fcmp_ueq_s64
; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY %d0
; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY %d1
; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, _, _ ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, %noreg, %noreg
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, %cpsr
; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, %noreg, implicit-def %fpscr_nzcv
; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv ; CHECK: FMSTAT 14, %noreg, implicit-def %cpsr, implicit %fpscr_nzcv
; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, %cpsr
; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, _, _ ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, %noreg, %noreg
; CHECK: %r0 = COPY [[ANDri]] ; CHECK: %r0 = COPY [[ANDri]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(ueq), %0(s64), %1 %2(s1) = G_FCMP floatpred(ueq), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines bb.0:
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = COPY %r2 %2(s32) = COPY %r2
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2 ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2
%3(s32) = G_MUL %0, %1 %3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %3, %2 %4(s32) = G_ADD %3, %2
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
%r0 = COPY %4(s32) %r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]] ; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_mla_commutative name: test_mla_commutative
# CHECK-LABEL: name: test_mla_commutative # CHECK-LABEL: name: test_mla_commutative
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 11 Lines bb.0:
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = COPY %r2 %2(s32) = COPY %r2
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2 ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2
%3(s32) = G_MUL %0, %1 %3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %2, %3 %4(s32) = G_ADD %2, %3
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
%r0 = COPY %4(s32) %r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]] ; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_mla_v5 name: test_mla_v5
# CHECK-LABEL: name: test_mla_v5 # CHECK-LABEL: name: test_mla_v5
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 11 Lines bb.0:
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = COPY %r2 %2(s32) = COPY %r2
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2 ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2
%3(s32) = G_MUL %0, %1 %3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %3, %2 %4(s32) = G_ADD %3, %2
; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _ ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg
%r0 = COPY %4(s32) %r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]] ; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_mls name: test_mls
# CHECK-LABEL: name: test_mls # CHECK-LABEL: name: test_mls
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 11 Lines bb.0:
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = COPY %r2 %2(s32) = COPY %r2
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY %r2 ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY %r2
%3(s32) = G_MUL %0, %1 %3(s32) = G_MUL %0, %1
%4(s32) = G_SUB %2, %3 %4(s32) = G_SUB %2, %3
; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, _ ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg
%r0 = COPY %4(s32) %r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]] ; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_no_mls name: test_no_mls
# CHECK-LABEL: name: test_no_mls # CHECK-LABEL: name: test_no_mls
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 11 Lines bb.0:
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = COPY %r2 %2(s32) = COPY %r2
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY %r2 ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY %r2
%3(s32) = G_MUL %0, %1 %3(s32) = G_MUL %0, %1
%4(s32) = G_SUB %2, %3 %4(s32) = G_SUB %2, %3
; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, _, _ ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, %noreg, %noreg
; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, _, _ ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, %noreg, %noreg
%r0 = COPY %4(s32) %r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]] ; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_shifts_to_revsh name: test_shifts_to_revsh
# CHECK-LABEL: name: test_shifts_to_revsh # CHECK-LABEL: name: test_shifts_to_revsh
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 28 Lines bb.0:
%8(s32) = G_AND %6(s32), %7(s32) %8(s32) = G_AND %6(s32), %7(s32)
%9(s32) = G_OR %4(s32), %8(s32) %9(s32) = G_OR %4(s32), %8(s32)
; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]] ; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
%r0 = COPY %9(s32) %r0 = COPY %9(s32)
; CHECK: %r0 = COPY [[VREGR]] ; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_shifts_to_revsh_commutative name: test_shifts_to_revsh_commutative
# CHECK-LABEL: name: test_shifts_to_revsh_commutative # CHECK-LABEL: name: test_shifts_to_revsh_commutative
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 28 Lines bb.0:
%8(s32) = G_AND %6(s32), %7(s32) %8(s32) = G_AND %6(s32), %7(s32)
%9(s32) = G_OR %8(s32), %4(s32) %9(s32) = G_OR %8(s32), %4(s32)
; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]] ; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
%r0 = COPY %9(s32) %r0 = COPY %9(s32)
; CHECK: %r0 = COPY [[VREGR]] ; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_shifts_no_revsh_features name: test_shifts_no_revsh_features
# CHECK-LABEL: name: test_shifts_no_revsh # CHECK-LABEL: name: test_shifts_no_revsh
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 27 Lines bb.0:
%8(s32) = G_AND %6(s32), %7(s32) %8(s32) = G_AND %6(s32), %7(s32)
%9(s32) = G_OR %4(s32), %8(s32) %9(s32) = G_OR %4(s32), %8(s32)
; We don't really care how this is folded as long as it's not into a REVSH. ; We don't really care how this is folded as long as it's not into a REVSH.
; CHECK-NOT: REVSH ; CHECK-NOT: REVSH
%r0 = COPY %9(s32) %r0 = COPY %9(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_shifts_no_revsh_constants name: test_shifts_no_revsh_constants
# CHECK-LABEL: name: test_shifts_no_revsh_constants # CHECK-LABEL: name: test_shifts_no_revsh_constants
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 27 Lines bb.0:
%8(s32) = G_AND %6(s32), %7(s32) %8(s32) = G_AND %6(s32), %7(s32)
%9(s32) = G_OR %4(s32), %8(s32) %9(s32) = G_OR %4(s32), %8(s32)
; We don't really care how this is folded as long as it's not into a REVSH. ; We don't really care how this is folded as long as it's not into a REVSH.
; CHECK-NOT: REVSH ; CHECK-NOT: REVSH
%r0 = COPY %9(s32) %r0 = COPY %9(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_bicrr name: test_bicrr
# CHECK-LABEL: name: test_bicrr # CHECK-LABEL: name: test_bicrr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
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%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2 %3(s32) = G_XOR %1, %2
%4(s32) = G_AND %0, %3 %4(s32) = G_AND %0, %3
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, _, _ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
%r0 = COPY %4(s32) %r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]] ; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_bicrr_commutative name: test_bicrr_commutative
# CHECK-LABEL: name: test_bicrr_commutative # CHECK-LABEL: name: test_bicrr_commutative
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
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%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2 %3(s32) = G_XOR %1, %2
%4(s32) = G_AND %3, %0 %4(s32) = G_AND %3, %0
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, _, _ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
%r0 = COPY %4(s32) %r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]] ; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_bicri name: test_bicri
# CHECK-LABEL: name: test_bicri # CHECK-LABEL: name: test_bicri
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
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; TableGen pattern that defines BICri. We also have a pattern for matching a ; TableGen pattern that defines BICri. We also have a pattern for matching a
; G_AND with a G_CONSTANT operand directly, which is the more common case, ; G_AND with a G_CONSTANT operand directly, which is the more common case,
; but that will be covered by different tests. ; but that will be covered by different tests.
%1(s32) = G_CONSTANT i32 192 %1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2 %3(s32) = G_XOR %1, %2
%4(s32) = G_AND %0, %3 %4(s32) = G_AND %0, %3
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
%r0 = COPY %4(s32) %r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]] ; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_bicri_commutative_xor name: test_bicri_commutative_xor
# CHECK-LABEL: name: test_bicri_commutative_xor # CHECK-LABEL: name: test_bicri_commutative_xor
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
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%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = G_CONSTANT i32 192 %1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %2, %1 %3(s32) = G_XOR %2, %1
%4(s32) = G_AND %0, %3 %4(s32) = G_AND %0, %3
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
%r0 = COPY %4(s32) %r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]] ; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_bicri_commutative_and name: test_bicri_commutative_and
# CHECK-LABEL: name: test_bicri_commutative_and # CHECK-LABEL: name: test_bicri_commutative_and
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
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%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = G_CONSTANT i32 192 %1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %1, %2 %3(s32) = G_XOR %1, %2
%4(s32) = G_AND %3, %0 %4(s32) = G_AND %3, %0
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
%r0 = COPY %4(s32) %r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]] ; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_bicri_commutative_both name: test_bicri_commutative_both
# CHECK-LABEL: name: test_bicri_commutative_both # CHECK-LABEL: name: test_bicri_commutative_both
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
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%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = G_CONSTANT i32 192 %1(s32) = G_CONSTANT i32 192
%2(s32) = G_CONSTANT i32 -1 %2(s32) = G_CONSTANT i32 -1
%3(s32) = G_XOR %2, %1 %3(s32) = G_XOR %2, %1
%4(s32) = G_AND %3, %0 %4(s32) = G_AND %3, %0
; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _ ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg
%r0 = COPY %4(s32) %r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]] ; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines bb.0:
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
%1(s1) = G_TRUNC %0(s32) %1(s1) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]] ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
%2(s32) = G_ZEXT %1(s1) %2(s32) = G_ZEXT %1(s1)
; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, _, _ ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, %noreg, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGEXT]] ; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_trunc_and_sext_s1 name: test_trunc_and_sext_s1
# CHECK-LABEL: name: test_trunc_and_sext_s1 # CHECK-LABEL: name: test_trunc_and_sext_s1
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0 liveins: %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
%1(s1) = G_TRUNC %0(s32) %1(s1) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]] ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
%2(s32) = G_SEXT %1(s1) %2(s32) = G_SEXT %1(s1)
; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, _, _ ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, %noreg, %noreg
; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, _, _ ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, %noreg, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGEXT]] ; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_trunc_and_sext_s8 name: test_trunc_and_sext_s8
# CHECK-LABEL: name: test_trunc_and_sext_s8 # CHECK-LABEL: name: test_trunc_and_sext_s8
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0 liveins: %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
%1(s8) = G_TRUNC %0(s32) %1(s8) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]] ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
%2(s32) = G_SEXT %1(s8) %2(s32) = G_SEXT %1(s8)
; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, _ ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGEXT]] ; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_trunc_and_zext_s16 name: test_trunc_and_zext_s16
# CHECK-LABEL: name: test_trunc_and_zext_s16 # CHECK-LABEL: name: test_trunc_and_zext_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0 liveins: %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
%1(s16) = G_TRUNC %0(s32) %1(s16) = G_TRUNC %0(s32)
; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]] ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
%2(s32) = G_ZEXT %1(s16) %2(s32) = G_ZEXT %1(s16)
; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, _ ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGEXT]] ; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_trunc_and_anyext_s8 name: test_trunc_and_anyext_s8
# CHECK-LABEL: name: test_trunc_and_anyext_s8 # CHECK-LABEL: name: test_trunc_and_anyext_s8
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 12 Lines bb.0:
; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]] ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
%2(s32) = G_ANYEXT %1(s8) %2(s32) = G_ANYEXT %1(s8)
; CHECK: [[VREGEXT:%[0-9]+]]:gpr = COPY [[VREGTRUNC]] ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = COPY [[VREGTRUNC]]
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGEXT]] ; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_trunc_and_anyext_s16 name: test_trunc_and_anyext_s16
# CHECK-LABEL: name: test_trunc_and_anyext_s16 # CHECK-LABEL: name: test_trunc_and_anyext_s16
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 12 Lines bb.0:
; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]] ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
%2(s32) = G_ANYEXT %1(s16) %2(s32) = G_ANYEXT %1(s16)
; CHECK: [[VREGEXT:%[0-9]+]]:gpr = COPY [[VREGTRUNC]] ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = COPY [[VREGTRUNC]]
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGEXT]] ; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_add_s32 name: test_add_s32
# CHECK-LABEL: name: test_add_s32 # CHECK-LABEL: name: test_add_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
%2(s32) = G_ADD %0, %1 %2(s32) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, _, _ ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGSUM]] ; CHECK: %r0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_add_fold_imm_s32 name: test_add_fold_imm_s32
# CHECK-LABEL: name: test_add_fold_imm_s32 # CHECK-LABEL: name: test_add_fold_imm_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0 liveins: %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = G_CONSTANT i32 255 %1(s32) = G_CONSTANT i32 255
%2(s32) = G_ADD %0, %1 %2(s32) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, _, _ ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, %noreg, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGSUM]] ; CHECK: %r0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_add_no_fold_imm_s32 name: test_add_no_fold_imm_s32
# CHECK-LABEL: name: test_add_no_fold_imm_s32 # CHECK-LABEL: name: test_add_no_fold_imm_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0 liveins: %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = G_CONSTANT i32 65535 %1(s32) = G_CONSTANT i32 65535
; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, _ ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, %noreg
%2(s32) = G_ADD %0, %1 %2(s32) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, _, _ ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGSUM]] ; CHECK: %r0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fadd_s32 name: test_fadd_s32
# CHECK-LABEL: name: test_fadd_s32 # CHECK-LABEL: name: test_fadd_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
%0(s32) = COPY %s0 %0(s32) = COPY %s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
%2(s32) = G_FADD %0, %1 %2(s32) = G_FADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, _ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, %noreg
%s0 = COPY %2(s32) %s0 = COPY %2(s32)
; CHECK: %s0 = COPY [[VREGSUM]] ; CHECK: %s0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %s0 BX_RET 14, %noreg, implicit %s0
; CHECK: BX_RET 14, _, implicit %s0 ; CHECK: BX_RET 14, %noreg, implicit %s0
... ...
--- ---
name: test_fadd_s64 name: test_fadd_s64
# CHECK-LABEL: name: test_fadd_s64 # CHECK-LABEL: name: test_fadd_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
%0(s64) = COPY %d0 %0(s64) = COPY %d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
%2(s64) = G_FADD %0, %1 %2(s64) = G_FADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, _ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, %noreg
%d0 = COPY %2(s64) %d0 = COPY %2(s64)
; CHECK: %d0 = COPY [[VREGSUM]] ; CHECK: %d0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %d0 BX_RET 14, %noreg, implicit %d0
; CHECK: BX_RET 14, _, implicit %d0 ; CHECK: BX_RET 14, %noreg, implicit %d0
... ...
--- ---
name: test_fsub_s32 name: test_fsub_s32
# CHECK-LABEL: name: test_fsub_s32 # CHECK-LABEL: name: test_fsub_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
%0(s32) = COPY %s0 %0(s32) = COPY %s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
%2(s32) = G_FSUB %0, %1 %2(s32) = G_FSUB %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, _ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, %noreg
%s0 = COPY %2(s32) %s0 = COPY %2(s32)
; CHECK: %s0 = COPY [[VREGSUM]] ; CHECK: %s0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %s0 BX_RET 14, %noreg, implicit %s0
; CHECK: BX_RET 14, _, implicit %s0 ; CHECK: BX_RET 14, %noreg, implicit %s0
... ...
--- ---
name: test_fsub_s64 name: test_fsub_s64
# CHECK-LABEL: name: test_fsub_s64 # CHECK-LABEL: name: test_fsub_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
%0(s64) = COPY %d0 %0(s64) = COPY %d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
%2(s64) = G_FSUB %0, %1 %2(s64) = G_FSUB %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, _ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, %noreg
%d0 = COPY %2(s64) %d0 = COPY %2(s64)
; CHECK: %d0 = COPY [[VREGSUM]] ; CHECK: %d0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %d0 BX_RET 14, %noreg, implicit %d0
; CHECK: BX_RET 14, _, implicit %d0 ; CHECK: BX_RET 14, %noreg, implicit %d0
... ...
--- ---
name: test_fmul_s32 name: test_fmul_s32
# CHECK-LABEL: name: test_fmul_s32 # CHECK-LABEL: name: test_fmul_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
%0(s32) = COPY %s0 %0(s32) = COPY %s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
%2(s32) = G_FMUL %0, %1 %2(s32) = G_FMUL %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, _ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, %noreg
%s0 = COPY %2(s32) %s0 = COPY %2(s32)
; CHECK: %s0 = COPY [[VREGSUM]] ; CHECK: %s0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %s0 BX_RET 14, %noreg, implicit %s0
; CHECK: BX_RET 14, _, implicit %s0 ; CHECK: BX_RET 14, %noreg, implicit %s0
... ...
--- ---
name: test_fmul_s64 name: test_fmul_s64
# CHECK-LABEL: name: test_fmul_s64 # CHECK-LABEL: name: test_fmul_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
%0(s64) = COPY %d0 %0(s64) = COPY %d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
%2(s64) = G_FMUL %0, %1 %2(s64) = G_FMUL %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, _ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, %noreg
%d0 = COPY %2(s64) %d0 = COPY %2(s64)
; CHECK: %d0 = COPY [[VREGSUM]] ; CHECK: %d0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %d0 BX_RET 14, %noreg, implicit %d0
; CHECK: BX_RET 14, _, implicit %d0 ; CHECK: BX_RET 14, %noreg, implicit %d0
... ...
--- ---
name: test_fdiv_s32 name: test_fdiv_s32
# CHECK-LABEL: name: test_fdiv_s32 # CHECK-LABEL: name: test_fdiv_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
%0(s32) = COPY %s0 %0(s32) = COPY %s0
; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0 ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1 ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
%2(s32) = G_FDIV %0, %1 %2(s32) = G_FDIV %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, _ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, %noreg
%s0 = COPY %2(s32) %s0 = COPY %2(s32)
; CHECK: %s0 = COPY [[VREGSUM]] ; CHECK: %s0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %s0 BX_RET 14, %noreg, implicit %s0
; CHECK: BX_RET 14, _, implicit %s0 ; CHECK: BX_RET 14, %noreg, implicit %s0
... ...
--- ---
name: test_fdiv_s64 name: test_fdiv_s64
# CHECK-LABEL: name: test_fdiv_s64 # CHECK-LABEL: name: test_fdiv_s64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: fprb } - { id: 0, class: fprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
- { id: 2, class: fprb } - { id: 2, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
%0(s64) = COPY %d0 %0(s64) = COPY %d0
; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0 ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1 ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
%2(s64) = G_FDIV %0, %1 %2(s64) = G_FDIV %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, _ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, %noreg
%d0 = COPY %2(s64) %d0 = COPY %2(s64)
; CHECK: %d0 = COPY [[VREGSUM]] ; CHECK: %d0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %d0 BX_RET 14, %noreg, implicit %d0
; CHECK: BX_RET 14, _, implicit %d0 ; CHECK: BX_RET 14, %noreg, implicit %d0
... ...
--- ---
name: test_sub_s32 name: test_sub_s32
# CHECK-LABEL: name: test_sub_s32 # CHECK-LABEL: name: test_sub_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
%2(s32) = G_SUB %0, %1 %2(s32) = G_SUB %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, _, _ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]] ; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_sub_imm_s32 name: test_sub_imm_s32
# CHECK-LABEL: name: test_sub_imm_s32 # CHECK-LABEL: name: test_sub_imm_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = G_CONSTANT i32 17 %1(s32) = G_CONSTANT i32 17
%2(s32) = G_SUB %0, %1 %2(s32) = G_SUB %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, _, _ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, %noreg, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]] ; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_sub_rev_imm_s32 name: test_sub_rev_imm_s32
# CHECK-LABEL: name: test_sub_rev_imm_s32 # CHECK-LABEL: name: test_sub_rev_imm_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = G_CONSTANT i32 17 %1(s32) = G_CONSTANT i32 17
%2(s32) = G_SUB %1, %0 %2(s32) = G_SUB %1, %0
; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, _, _ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, %noreg, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]] ; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_mul_s32 name: test_mul_s32
# CHECK-LABEL: name: test_mul_s32 # CHECK-LABEL: name: test_mul_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
%2(s32) = G_MUL %0, %1 %2(s32) = G_MUL %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, _, _ ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, %noreg, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]] ; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_mulv5_s32 name: test_mulv5_s32
# CHECK-LABEL: name: test_mulv5_s32 # CHECK-LABEL: name: test_mulv5_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1
%2(s32) = G_MUL %0, %1 %2(s32) = G_MUL %0, %1
; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, _, _ ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, %noreg, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]] ; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_sdiv_s32 name: test_sdiv_s32
# CHECK-LABEL: name: test_sdiv_s32 # CHECK-LABEL: name: test_sdiv_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
%2(s32) = G_SDIV %0, %1 %2(s32) = G_SDIV %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, _ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]] ; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_udiv_s32 name: test_udiv_s32
# CHECK-LABEL: name: test_udiv_s32 # CHECK-LABEL: name: test_udiv_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
%2(s32) = G_UDIV %0, %1 %2(s32) = G_UDIV %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, _ ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]] ; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_lshr_s32 name: test_lshr_s32
# CHECK-LABEL: name: test_lshr_s32 # CHECK-LABEL: name: test_lshr_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
%2(s32) = G_LSHR %0, %1 %2(s32) = G_LSHR %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, _, _ ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, %noreg, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]] ; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_ashr_s32 name: test_ashr_s32
# CHECK-LABEL: name: test_ashr_s32 # CHECK-LABEL: name: test_ashr_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
%2(s32) = G_ASHR %0, %1 %2(s32) = G_ASHR %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, _, _ ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, %noreg, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]] ; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_shl_s32 name: test_shl_s32
# CHECK-LABEL: name: test_shl_s32 # CHECK-LABEL: name: test_shl_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
%2(s32) = G_SHL %0, %1 %2(s32) = G_SHL %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, _, _ ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, %noreg, %noreg
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]] ; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_load_from_stack name: test_load_from_stack
# CHECK-LABEL: name: test_load_from_stack # CHECK-LABEL: name: test_load_from_stack
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 9 LinesfixedStack:
- { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
# CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1 # CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1
# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8 # CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1, %r2, %r3 liveins: %r0, %r1, %r2, %r3
%0(p0) = G_FRAME_INDEX %fixed-stack.2 %0(p0) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, _, _ ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, %noreg, %noreg
%1(s32) = G_LOAD %0(p0) :: (load 4) %1(s32) = G_LOAD %0(p0) :: (load 4)
; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, _ ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, %noreg
%r0 = COPY %1 %r0 = COPY %1
; CHECK: %r0 = COPY [[LD32VREG]] ; CHECK: %r0 = COPY [[LD32VREG]]
%2(p0) = G_FRAME_INDEX %fixed-stack.0 %2(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, _, _ ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, %noreg, %noreg
%3(s1) = G_LOAD %2(p0) :: (load 1) %3(s1) = G_LOAD %2(p0) :: (load 1)
; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, _ ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, %noreg
%4(s32) = G_ANYEXT %3(s1) %4(s32) = G_ANYEXT %3(s1)
; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]] ; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]]
%r0 = COPY %4 %r0 = COPY %4
; CHECK: %r0 = COPY [[RES]] ; CHECK: %r0 = COPY [[RES]]
BX_RET 14, _ BX_RET 14, %noreg
; CHECK: BX_RET 14, _ ; CHECK: BX_RET 14, %noreg
... ...
--- ---
name: test_load_f32 name: test_load_f32
# CHECK-LABEL: name: test_load_f32 # CHECK-LABEL: name: test_load_f32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: %r0 liveins: %r0
%0(p0) = COPY %r0 %0(p0) = COPY %r0
; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0 ; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0
%1(s32) = G_LOAD %0(p0) :: (load 4) %1(s32) = G_LOAD %0(p0) :: (load 4)
; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, _ ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, %noreg
%s0 = COPY %1 %s0 = COPY %1
; CHECK: %s0 = COPY %[[V]] ; CHECK: %s0 = COPY %[[V]]
BX_RET 14, _, implicit %s0 BX_RET 14, %noreg, implicit %s0
; CHECK: BX_RET 14, _, implicit %s0 ; CHECK: BX_RET 14, %noreg, implicit %s0
... ...
--- ---
name: test_load_f64 name: test_load_f64
# CHECK-LABEL: name: test_load_f64 # CHECK-LABEL: name: test_load_f64
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: fprb } - { id: 1, class: fprb }
body: | body: |
bb.0: bb.0:
liveins: %r0 liveins: %r0
%0(p0) = COPY %r0 %0(p0) = COPY %r0
; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0 ; CHECK: %[[P:[0-9]+]]:gpr = COPY %r0
%1(s64) = G_LOAD %0(p0) :: (load 8) %1(s64) = G_LOAD %0(p0) :: (load 8)
; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, _ ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, %noreg
%d0 = COPY %1 %d0 = COPY %1
; CHECK: %d0 = COPY %[[V]] ; CHECK: %d0 = COPY %[[V]]
BX_RET 14, _, implicit %d0 BX_RET 14, %noreg, implicit %d0
; CHECK: BX_RET 14, _, implicit %d0 ; CHECK: BX_RET 14, %noreg, implicit %d0
... ...
--- ---
name: test_stores name: test_stores
# CHECK-LABEL: name: test_stores # CHECK-LABEL: name: test_stores
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 17 Lines bb.0:
%0(p0) = COPY %r0 %0(p0) = COPY %r0
%3(s32) = COPY %r1 %3(s32) = COPY %r1
%4(s32) = COPY %s0 %4(s32) = COPY %s0
%5(s64) = COPY %d2 %5(s64) = COPY %d2
%1(s8) = G_TRUNC %3(s32) %1(s8) = G_TRUNC %3(s32)
%2(s16) = G_TRUNC %3(s32) %2(s16) = G_TRUNC %3(s32)
G_STORE %1(s8), %0(p0) :: (store 1) G_STORE %1(s8), %0(p0) :: (store 1)
; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, _ ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, %noreg
G_STORE %2(s16), %0(p0) :: (store 2) G_STORE %2(s16), %0(p0) :: (store 2)
; CHECK: STRH %[[I16]], %[[P]], _, 0, 14, _ ; CHECK: STRH %[[I16]], %[[P]], %noreg, 0, 14, %noreg
G_STORE %3(s32), %0(p0) :: (store 4) G_STORE %3(s32), %0(p0) :: (store 4)
; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, _ ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, %noreg
G_STORE %4(s32), %0(p0) :: (store 4) G_STORE %4(s32), %0(p0) :: (store 4)
; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, _ ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, %noreg
G_STORE %5(s64), %0(p0) :: (store 8) G_STORE %5(s64), %0(p0) :: (store 8)
; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, _ ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, %noreg
BX_RET 14, _ BX_RET 14, %noreg
... ...
--- ---
name: test_gep name: test_gep
# CHECK-LABEL: name: test_gep # CHECK-LABEL: name: test_gep
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
- { id: 2, class: gprb } - { id: 2, class: gprb }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(p0) = COPY %r0 %0(p0) = COPY %r0
; CHECK: %[[PTR:[0-9]+]]:gpr = COPY %r0 ; CHECK: %[[PTR:[0-9]+]]:gpr = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: %[[OFF:[0-9]+]]:gpr = COPY %r1 ; CHECK: %[[OFF:[0-9]+]]:gpr = COPY %r1
%2(p0) = G_GEP %0, %1(s32) %2(p0) = G_GEP %0, %1(s32)
; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, _, _ ; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, %noreg, %noreg
%r0 = COPY %2(p0) %r0 = COPY %2(p0)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_constant_imm name: test_constant_imm
# CHECK-LABEL: name: test_constant_imm # CHECK-LABEL: name: test_constant_imm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
body: | body: |
bb.0: bb.0:
%0(s32) = G_CONSTANT 42 %0(s32) = G_CONSTANT 42
; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, _, _ ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, %noreg, %noreg
%r0 = COPY %0(s32) %r0 = COPY %0(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_constant_cimm name: test_constant_cimm
# CHECK-LABEL: name: test_constant_cimm # CHECK-LABEL: name: test_constant_cimm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
body: | body: |
bb.0: bb.0:
; Adding a type on G_CONSTANT changes its operand from an Imm into a CImm. ; Adding a type on G_CONSTANT changes its operand from an Imm into a CImm.
; We still want to see the same thing in the output though. ; We still want to see the same thing in the output though.
%0(s32) = G_CONSTANT i32 42 %0(s32) = G_CONSTANT i32 42
; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, _, _ ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, %noreg, %noreg
%r0 = COPY %0(s32) %r0 = COPY %0(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_select_s32 name: test_select_s32
# CHECK-LABEL: name: test_select_s32 # CHECK-LABEL: name: test_select_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 11 Lines bb.0:
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
%2(s1) = G_TRUNC %1(s32) %2(s1) = G_TRUNC %1(s32)
; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY [[VREGY]] ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY [[VREGY]]
%3(s32) = G_SELECT %2(s1), %0, %1 %3(s32) = G_SELECT %2(s1), %0, %1
; CHECK: CMPri [[VREGC]], 0, 14, _, implicit-def %cpsr ; CHECK: CMPri [[VREGC]], 0, 14, %noreg, implicit-def %cpsr
; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[RES]] ; CHECK: %r0 = COPY [[RES]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_select_ptr name: test_select_ptr
# CHECK-LABEL: name: test_select_ptr # CHECK-LABEL: name: test_select_ptr
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 15 Lines bb.0:
%2(s32) = COPY %r2 %2(s32) = COPY %r2
; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY %r2 ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY %r2
%3(s1) = G_TRUNC %2(s32) %3(s1) = G_TRUNC %2(s32)
; CHECK: [[VREGD:%[0-9]+]]:gpr = COPY [[VREGC]] ; CHECK: [[VREGD:%[0-9]+]]:gpr = COPY [[VREGC]]
%4(p0) = G_SELECT %3(s1), %0, %1 %4(p0) = G_SELECT %3(s1), %0, %1
; CHECK: CMPri [[VREGD]], 0, 14, _, implicit-def %cpsr ; CHECK: CMPri [[VREGD]], 0, 14, %noreg, implicit-def %cpsr
; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
%r0 = COPY %4(p0) %r0 = COPY %4(p0)
; CHECK: %r0 = COPY [[RES]] ; CHECK: %r0 = COPY [[RES]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_br name: test_br
# CHECK-LABEL: name: test_br # CHECK-LABEL: name: test_br
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
; CHECK: bb.0 ; CHECK: bb.0
successors: %bb.1(0x40000000), %bb.2(0x40000000) successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: %r0 liveins: %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
; CHECK: [[COND32:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[COND32:%[0-9]+]]:gpr = COPY %r0
%1(s1) = G_TRUNC %0(s32) %1(s1) = G_TRUNC %0(s32)
; CHECK: [[COND:%[0-9]+]]:gpr = COPY [[COND32]] ; CHECK: [[COND:%[0-9]+]]:gpr = COPY [[COND32]]
G_BRCOND %1(s1), %bb.1 G_BRCOND %1(s1), %bb.1
; CHECK: TSTri [[COND]], 1, 14, _, implicit-def %cpsr ; CHECK: TSTri [[COND]], 1, 14, %noreg, implicit-def %cpsr
; CHECK: Bcc %bb.1, 1, %cpsr ; CHECK: Bcc %bb.1, 1, %cpsr
G_BR %bb.2 G_BR %bb.2
; CHECK: B %bb.2 ; CHECK: B %bb.2
bb.1: bb.1:
; CHECK: bb.1 ; CHECK: bb.1
successors: %bb.2(0x80000000) successors: %bb.2(0x80000000)
G_BR %bb.2 G_BR %bb.2
; CHECK: B %bb.2 ; CHECK: B %bb.2
bb.2: bb.2:
; CHECK: bb.2 ; CHECK: bb.2
BX_RET 14, _ BX_RET 14, %noreg
; CHECK: BX_RET 14, _ ; CHECK: BX_RET 14, %noreg
... ...
--- ---
name: test_soft_fp_double name: test_soft_fp_double
# CHECK-LABEL: name: test_soft_fp_double # CHECK-LABEL: name: test_soft_fp_double
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
Show All 20 Lines bb.0:
; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]] ; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]]
%r0 = COPY %3 %r0 = COPY %3
; CHECK: %r0 = COPY [[OUT1]] ; CHECK: %r0 = COPY [[OUT1]]
%r1 = COPY %4 %r1 = COPY %4
; CHECK: %r1 = COPY [[OUT2]] ; CHECK: %r1 = COPY [[OUT2]]
BX_RET 14, _, implicit %r0, implicit %r1 BX_RET 14, %noreg, implicit %r0, implicit %r1
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
... ...

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll

; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE ; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE
; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=BIG ; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=BIG
define void @test_void_return() { define void @test_void_return() {
; CHECK-LABEL: name: test_void_return ; CHECK-LABEL: name: test_void_return
; CHECK: BX_RET 14, _ ; CHECK: BX_RET 14, %noreg
entry: entry:
ret void ret void
} }
define signext i1 @test_add_i1(i1 %x, i1 %y) { define signext i1 @test_add_i1(i1 %x, i1 %y) {
; CHECK-LABEL: name: test_add_i1 ; CHECK-LABEL: name: test_add_i1
; CHECK: liveins: %r0, %r1 ; CHECK: liveins: %r0, %r1
; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR0]] ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR0]]
; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR1]] ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s1) = G_TRUNC [[VREGR1]]
; CHECK: [[SUM:%[0-9]+]]:_(s1) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[SUM:%[0-9]+]]:_(s1) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_SEXT [[SUM]] ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_SEXT [[SUM]]
; CHECK: %r0 = COPY [[EXT]](s32) ; CHECK: %r0 = COPY [[EXT]](s32)
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%sum = add i1 %x, %y %sum = add i1 %x, %y
ret i1 %sum ret i1 %sum
} }
define i8 @test_add_i8(i8 %x, i8 %y) { define i8 @test_add_i8(i8 %x, i8 %y) {
; CHECK-LABEL: name: test_add_i8 ; CHECK-LABEL: name: test_add_i8
; CHECK: liveins: %r0, %r1 ; CHECK: liveins: %r0, %r1
; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]] ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]] ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]
; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
; CHECK: %r0 = COPY [[SUM_EXT]](s32) ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%sum = add i8 %x, %y %sum = add i8 %x, %y
ret i8 %sum ret i8 %sum
} }
define i8 @test_sub_i8(i8 %x, i8 %y) { define i8 @test_sub_i8(i8 %x, i8 %y) {
; CHECK-LABEL: name: test_sub_i8 ; CHECK-LABEL: name: test_sub_i8
; CHECK: liveins: %r0, %r1 ; CHECK: liveins: %r0, %r1
; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]] ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]] ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR1]]
; CHECK: [[RES:%[0-9]+]]:_(s8) = G_SUB [[VREGX]], [[VREGY]] ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_SUB [[VREGX]], [[VREGY]]
; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]] ; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
; CHECK: %r0 = COPY [[RES_EXT]](s32) ; CHECK: %r0 = COPY [[RES_EXT]](s32)
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%res = sub i8 %x, %y %res = sub i8 %x, %y
ret i8 %res ret i8 %res
} }
define signext i8 @test_return_sext_i8(i8 %x) { define signext i8 @test_return_sext_i8(i8 %x) {
; CHECK-LABEL: name: test_return_sext_i8 ; CHECK-LABEL: name: test_return_sext_i8
; CHECK: liveins: %r0 ; CHECK: liveins: %r0
; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]] ; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]] ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]]
; CHECK: %r0 = COPY [[VREGEXT]](s32) ; CHECK: %r0 = COPY [[VREGEXT]](s32)
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
ret i8 %x ret i8 %x
} }
define i16 @test_add_i16(i16 %x, i16 %y) { define i16 @test_add_i16(i16 %x, i16 %y) {
; CHECK-LABEL: name: test_add_i16 ; CHECK-LABEL: name: test_add_i16
; CHECK: liveins: %r0, %r1 ; CHECK: liveins: %r0, %r1
; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]] ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]] ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
; CHECK: %r0 = COPY [[SUM_EXT]](s32) ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%sum = add i16 %x, %y %sum = add i16 %x, %y
ret i16 %sum ret i16 %sum
} }
define i16 @test_sub_i16(i16 %x, i16 %y) { define i16 @test_sub_i16(i16 %x, i16 %y) {
; CHECK-LABEL: name: test_sub_i16 ; CHECK-LABEL: name: test_sub_i16
; CHECK: liveins: %r0, %r1 ; CHECK: liveins: %r0, %r1
; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]] ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]] ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
; CHECK: [[RES:%[0-9]+]]:_(s16) = G_SUB [[VREGX]], [[VREGY]] ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_SUB [[VREGX]], [[VREGY]]
; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]] ; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]]
; CHECK: %r0 = COPY [[RES_EXT]](s32) ; CHECK: %r0 = COPY [[RES_EXT]](s32)
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%res = sub i16 %x, %y %res = sub i16 %x, %y
ret i16 %res ret i16 %res
} }
define zeroext i16 @test_return_zext_i16(i16 %x) { define zeroext i16 @test_return_zext_i16(i16 %x) {
; CHECK-LABEL: name: test_return_zext_i16 ; CHECK-LABEL: name: test_return_zext_i16
; CHECK: liveins: %r0 ; CHECK: liveins: %r0
; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[VREGR0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]] ; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]] ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]]
; CHECK: %r0 = COPY [[VREGEXT]](s32) ; CHECK: %r0 = COPY [[VREGEXT]](s32)
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
ret i16 %x ret i16 %x
} }
define i32 @test_add_i32(i32 %x, i32 %y) { define i32 @test_add_i32(i32 %x, i32 %y) {
; CHECK-LABEL: name: test_add_i32 ; CHECK-LABEL: name: test_add_i32
; CHECK: liveins: %r0, %r1 ; CHECK: liveins: %r0, %r1
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1
; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGX]], [[VREGY]]
; CHECK: %r0 = COPY [[SUM]](s32) ; CHECK: %r0 = COPY [[SUM]](s32)
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%sum = add i32 %x, %y %sum = add i32 %x, %y
ret i32 %sum ret i32 %sum
} }
define i32 @test_sub_i32(i32 %x, i32 %y) { define i32 @test_sub_i32(i32 %x, i32 %y) {
; CHECK-LABEL: name: test_sub_i32 ; CHECK-LABEL: name: test_sub_i32
; CHECK: liveins: %r0, %r1 ; CHECK: liveins: %r0, %r1
; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[VREGX:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY %r1
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SUB [[VREGX]], [[VREGY]] ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SUB [[VREGX]], [[VREGY]]
; CHECK: %r0 = COPY [[RES]](s32) ; CHECK: %r0 = COPY [[RES]](s32)
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%res = sub i32 %x, %y %res = sub i32 %x, %y
ret i32 %res ret i32 %res
} }
define i32 @test_stack_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) { define i32 @test_stack_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {
; CHECK-LABEL: name: test_stack_args ; CHECK-LABEL: name: test_stack_args
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4
; CHECK: liveins: %r0, %r1, %r2, %r3 ; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK: [[VREGP2:%[0-9]+]]:_(s32) = COPY %r2 ; CHECK: [[VREGP2:%[0-9]+]]:_(s32) = COPY %r2
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]] ; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]]{{.*}}load 4 ; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]]{{.*}}load 4
; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGP2]], [[VREGP5]] ; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGP2]], [[VREGP5]]
; CHECK: %r0 = COPY [[SUM]] ; CHECK: %r0 = COPY [[SUM]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%sum = add i32 %p2, %p5 %sum = add i32 %p2, %p5
ret i32 %sum ret i32 %sum
} }
define i16 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, define i16 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
i8 signext %p4, i16 signext %p5) { i8 signext %p4, i16 signext %p5) {
; CHECK-LABEL: name: test_stack_args_signext ; CHECK-LABEL: name: test_stack_args_signext
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
; CHECK: liveins: %r0, %r1, %r2, %r3 ; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[VREGR1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK: [[VREGP1:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]] ; CHECK: [[VREGP1:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR1]]
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]] ; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4 ; CHECK: [[VREGP5EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5EXT]] ; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5EXT]]
; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGP1]], [[VREGP5]] ; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGP1]], [[VREGP5]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
; CHECK: %r0 = COPY [[SUM_EXT]](s32) ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%sum = add i16 %p1, %p5 %sum = add i16 %p1, %p5
ret i16 %sum ret i16 %sum
} }
define i8 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, define i8 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
i8 zeroext %p4, i16 zeroext %p5) { i8 zeroext %p4, i16 zeroext %p5) {
; CHECK-LABEL: name: test_stack_args_zeroext ; CHECK-LABEL: name: test_stack_args_zeroext
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
; CHECK: liveins: %r0, %r1, %r2, %r3 ; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY %r2 ; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY %r2
; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]] ; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]
; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]] ; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
; CHECK: [[VREGP4EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP4]](p0){{.*}}load 4 ; CHECK: [[VREGP4EXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP4]](p0){{.*}}load 4
; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_TRUNC [[VREGP4EXT]] ; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_TRUNC [[VREGP4EXT]]
; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]] ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
; CHECK: %r0 = COPY [[SUM_EXT]](s32) ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%sum = add i8 %p2, %p4 %sum = add i8 %p2, %p4
ret i8 %sum ret i8 %sum
} }
define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
i8 %p4, i16 %p5) { i8 %p4, i16 %p5) {
; CHECK-LABEL: name: test_stack_args_noext ; CHECK-LABEL: name: test_stack_args_noext
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
; CHECK: liveins: %r0, %r1, %r2, %r3 ; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY %r2 ; CHECK: [[VREGR2:%[0-9]+]]:_(s32) = COPY %r2
; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]] ; CHECK: [[VREGP2:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR2]]
; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]] ; CHECK: [[FIP4:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P4]]
; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_LOAD [[FIP4]](p0){{.*}}load 1 ; CHECK: [[VREGP4:%[0-9]+]]:_(s8) = G_LOAD [[FIP4]](p0){{.*}}load 1
; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]] ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]]
; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]]
; CHECK: %r0 = COPY [[SUM_EXT]](s32) ; CHECK: %r0 = COPY [[SUM_EXT]](s32)
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%sum = add i8 %p2, %p4 %sum = add i8 %p2, %p4
ret i8 %sum ret i8 %sum
} }
define zeroext i16 @test_stack_args_extend_the_extended(i32 %p0, i16 %p1, i8 %p2, i1 %p3, define zeroext i16 @test_stack_args_extend_the_extended(i32 %p0, i16 %p1, i8 %p2, i1 %p3,
i8 signext %p4, i16 signext %p5) { i8 signext %p4, i16 signext %p5) {
; CHECK-LABEL: name: test_stack_args_extend_the_extended ; CHECK-LABEL: name: test_stack_args_extend_the_extended
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 1
; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 2
; CHECK: liveins: %r0, %r1, %r2, %r3 ; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]] ; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5SEXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4 ; CHECK: [[VREGP5SEXT:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5SEXT]] ; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5SEXT]]
; CHECK: [[VREGP5ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREGP5]] ; CHECK: [[VREGP5ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREGP5]]
; CHECK: %r0 = COPY [[VREGP5ZEXT]] ; CHECK: %r0 = COPY [[VREGP5ZEXT]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
ret i16 %p5 ret i16 %p5
} }
define i16 @test_ptr_arg(i16* %p) { define i16 @test_ptr_arg(i16* %p) {
; CHECK-LABEL: name: test_ptr_arg ; CHECK-LABEL: name: test_ptr_arg
; CHECK: liveins: %r0 ; CHECK: liveins: %r0
; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY %r0 ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY %r0
; CHECK: [[VREGV:%[0-9]+]]:_(s16) = G_LOAD [[VREGP]](p0){{.*}}load 2 ; CHECK: [[VREGV:%[0-9]+]]:_(s16) = G_LOAD [[VREGP]](p0){{.*}}load 2
entry: entry:
%v = load i16, i16* %p %v = load i16, i16* %p
ret i16 %v ret i16 %v
} }
define i32* @test_ptr_ret(i32** %p) { define i32* @test_ptr_ret(i32** %p) {
; Test pointer returns and pointer-to-pointer arguments ; Test pointer returns and pointer-to-pointer arguments
; CHECK-LABEL: name: test_ptr_ret ; CHECK-LABEL: name: test_ptr_ret
; CHECK: liveins: %r0 ; CHECK: liveins: %r0
; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY %r0 ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY %r0
; CHECK: [[VREGV:%[0-9]+]]:_(p0) = G_LOAD [[VREGP]](p0){{.*}}load 4 ; CHECK: [[VREGV:%[0-9]+]]:_(p0) = G_LOAD [[VREGP]](p0){{.*}}load 4
; CHECK: %r0 = COPY [[VREGV]] ; CHECK: %r0 = COPY [[VREGV]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%v = load i32*, i32** %p %v = load i32*, i32** %p
ret i32* %v ret i32* %v
} }
define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32* %p) { define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32* %p) {
; CHECK-LABEL: name: test_ptr_arg_on_stack ; CHECK-LABEL: name: test_ptr_arg_on_stack
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK: id: [[P:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4 ; CHECK: id: [[P:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
; CHECK: liveins: %r0, %r1, %r2, %r3 ; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK: [[FIP:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P]] ; CHECK: [[FIP:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P]]
; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load 4 ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load 4
; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load 4 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load 4
; CHECK: %r0 = COPY [[VREGV]] ; CHECK: %r0 = COPY [[VREGV]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%v = load i32, i32* %p %v = load i32, i32* %p
ret i32 %v ret i32 %v
} }
define arm_aapcscc float @test_float_aapcscc(float %p0, float %p1, float %p2, define arm_aapcscc float @test_float_aapcscc(float %p0, float %p1, float %p2,
float %p3, float %p4, float %p5) { float %p3, float %p4, float %p5) {
; CHECK-LABEL: name: test_float_aapcscc ; CHECK-LABEL: name: test_float_aapcscc
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4 ; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4 ; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
; CHECK: liveins: %r0, %r1, %r2, %r3 ; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]] ; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4 ; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4
; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGP5]] ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGP5]]
; CHECK: %r0 = COPY [[VREGV]] ; CHECK: %r0 = COPY [[VREGV]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%v = fadd float %p1, %p5 %v = fadd float %p1, %p5
ret float %v ret float %v
} }
define arm_aapcs_vfpcc float @test_float_vfpcc(float %p0, float %p1, float %p2, define arm_aapcs_vfpcc float @test_float_vfpcc(float %p0, float %p1, float %p2,
float %p3, float %p4, float %p5, float %p3, float %p4, float %p5,
float %ridiculous, float %ridiculous,
Show All 12 Lines
; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4 ; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4 ; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
; CHECK: liveins: %s0, %s1, %s2, %s3, %s4, %s5, %s6, %s7, %s8, %s9, %s10, %s11, %s12, %s13, %s14, %s15 ; CHECK: liveins: %s0, %s1, %s2, %s3, %s4, %s5, %s6, %s7, %s8, %s9, %s10, %s11, %s12, %s13, %s14, %s15
; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY %s1 ; CHECK: [[VREGP1:%[0-9]+]]:_(s32) = COPY %s1
; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]] ; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
; CHECK: [[VREGQ1:%[0-9]+]]:_(s32) = G_LOAD [[FIQ1]](p0){{.*}}load 4 ; CHECK: [[VREGQ1:%[0-9]+]]:_(s32) = G_LOAD [[FIQ1]](p0){{.*}}load 4
; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGQ1]]
; CHECK: %s0 = COPY [[VREGV]] ; CHECK: %s0 = COPY [[VREGV]]
; CHECK: BX_RET 14, _, implicit %s0 ; CHECK: BX_RET 14, %noreg, implicit %s0
entry: entry:
%v = fadd float %p1, %q1 %v = fadd float %p1, %q1
ret float %v ret float %v
} }
define arm_aapcs_vfpcc double @test_double_vfpcc(double %p0, double %p1, double %p2, define arm_aapcs_vfpcc double @test_double_vfpcc(double %p0, double %p1, double %p2,
double %p3, double %p4, double %p5, double %p3, double %p4, double %p5,
double %reasonable, double %reasonable,
double %parameters, double %parameters,
double %q0, double %q1) { double %q0, double %q1) {
; CHECK-LABEL: name: test_double_vfpcc ; CHECK-LABEL: name: test_double_vfpcc
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8 ; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8 ; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
; CHECK: liveins: %d0, %d1, %d2, %d3, %d4, %d5, %d6, %d7 ; CHECK: liveins: %d0, %d1, %d2, %d3, %d4, %d5, %d6, %d7
; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY %d1 ; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY %d1
; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]] ; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8 ; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
; CHECK: %d0 = COPY [[VREGV]] ; CHECK: %d0 = COPY [[VREGV]]
; CHECK: BX_RET 14, _, implicit %d0 ; CHECK: BX_RET 14, %noreg, implicit %d0
entry: entry:
%v = fadd double %p1, %q1 %v = fadd double %p1, %q1
ret double %v ret double %v
} }
define arm_aapcscc double @test_double_aapcscc(double %p0, double %p1, double %p2, define arm_aapcscc double @test_double_aapcscc(double %p0, double %p1, double %p2,
double %p3, double %p4, double %p5) { double %p3, double %p4, double %p5) {
; CHECK-LABEL: name: test_double_aapcscc ; CHECK-LABEL: name: test_double_aapcscc
Show All 9 Lines
; BIG: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1HI]](s32), [[VREGP1LO]](s32) ; BIG: [[VREGP1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP1HI]](s32), [[VREGP1LO]](s32)
; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]] ; CHECK: [[FIP5:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5:%[0-9]+]]:_(s64) = G_LOAD [[FIP5]](p0){{.*}}load 8 ; CHECK: [[VREGP5:%[0-9]+]]:_(s64) = G_LOAD [[FIP5]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGP5]] ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGP5]]
; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; CHECK-DAG: %r0 = COPY [[VREGVLO]] ; CHECK-DAG: %r0 = COPY [[VREGVLO]]
; CHECK-DAG: %r1 = COPY [[VREGVHI]] ; CHECK-DAG: %r1 = COPY [[VREGVHI]]
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
entry: entry:
%v = fadd double %p1, %p5 %v = fadd double %p1, %p5
ret double %v ret double %v
} }
define arm_aapcs_vfpcc double @test_double_gap_vfpcc(double %p0, float %filler, define arm_aapcs_vfpcc double @test_double_gap_vfpcc(double %p0, float %filler,
double %p1, double %p2, double %p1, double %p2,
double %p3, double %p4, double %p3, double %p4,
double %reasonable, double %reasonable,
double %parameters, double %parameters,
double %q0, double %q1) { double %q0, double %q1) {
; CHECK-LABEL: name: test_double_gap_vfpcc ; CHECK-LABEL: name: test_double_gap_vfpcc
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8 ; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8 ; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 8{{.*}}size: 8
; CHECK: liveins: %d0, %d2, %d3, %d4, %d5, %d6, %d7, %s2 ; CHECK: liveins: %d0, %d2, %d3, %d4, %d5, %d6, %d7, %s2
; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY %d2 ; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = COPY %d2
; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]] ; CHECK: [[FIQ1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8 ; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]]
; CHECK: %d0 = COPY [[VREGV]] ; CHECK: %d0 = COPY [[VREGV]]
; CHECK: BX_RET 14, _, implicit %d0 ; CHECK: BX_RET 14, %noreg, implicit %d0
entry: entry:
%v = fadd double %p1, %q1 %v = fadd double %p1, %q1
ret double %v ret double %v
} }
define arm_aapcscc double @test_double_gap_aapcscc(float %filler, double %p0, define arm_aapcscc double @test_double_gap_aapcscc(float %filler, double %p0,
double %p1) { double %p1) {
; CHECK-LABEL: name: test_double_gap_aapcscc ; CHECK-LABEL: name: test_double_gap_aapcscc
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8 ; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
; CHECK: liveins: %r0, %r2, %r3 ; CHECK: liveins: %r0, %r2, %r3
; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY %r2 ; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY %r2
; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY %r3 ; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY %r3
; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32) ; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32) ; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]] ; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load 8 ; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]] ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]
; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; CHECK-DAG: %r0 = COPY [[VREGVLO]] ; CHECK-DAG: %r0 = COPY [[VREGVLO]]
; CHECK-DAG: %r1 = COPY [[VREGVHI]] ; CHECK-DAG: %r1 = COPY [[VREGVHI]]
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
entry: entry:
%v = fadd double %p0, %p1 %v = fadd double %p0, %p1
ret double %v ret double %v
} }
define arm_aapcscc double @test_double_gap2_aapcscc(double %p0, float %filler, define arm_aapcscc double @test_double_gap2_aapcscc(double %p0, float %filler,
double %p1) { double %p1) {
; CHECK-LABEL: name: test_double_gap2_aapcscc ; CHECK-LABEL: name: test_double_gap2_aapcscc
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8 ; CHECK-DAG: id: [[P1:[0-9]+]]{{.*}}offset: 0{{.*}}size: 8
; CHECK: liveins: %r0, %r1, %r2 ; CHECK: liveins: %r0, %r1, %r2
; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[VREGP0LO:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[VREGP0HI:%[0-9]+]]:_(s32) = COPY %r1
; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32) ; LITTLE: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0LO]](s32), [[VREGP0HI]](s32)
; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32) ; BIG: [[VREGP0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREGP0HI]](s32), [[VREGP0LO]](s32)
; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]] ; CHECK: [[FIP1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P1]]
; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load 8 ; CHECK: [[VREGP1:%[0-9]+]]:_(s64) = G_LOAD [[FIP1]](p0){{.*}}load 8
; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]] ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP0]], [[VREGP1]]
; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; LITTLE: [[VREGVLO:%[0-9]+]]:_(s32), [[VREGVHI:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64)
; CHECK-DAG: %r0 = COPY [[VREGVLO]] ; CHECK-DAG: %r0 = COPY [[VREGVLO]]
; CHECK-DAG: %r1 = COPY [[VREGVHI]] ; CHECK-DAG: %r1 = COPY [[VREGVHI]]
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
entry: entry:
%v = fadd double %p0, %p1 %v = fadd double %p0, %p1
ret double %v ret double %v
} }
define i32 @test_shufflevector_s32_v2s32(i32 %arg) { define i32 @test_shufflevector_s32_v2s32(i32 %arg) {
; CHECK-LABEL: name: test_shufflevector_s32_v2s32 ; CHECK-LABEL: name: test_shufflevector_s32_v2s32
; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY %r0
▲ Show 20 Lines • Show All 109 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines bb.0:
; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0
; SOFT-DEFAULT: BL $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: BL $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV ; SOFT-NOT: G_SDIV
%2(s32) = G_SDIV %0, %1 %2(s32) = G_SDIV %0, %1
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_udiv_i32 name: test_udiv_i32
# CHECK-LABEL: name: test_udiv_i32 # CHECK-LABEL: name: test_udiv_i32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 19 Lines bb.0:
; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r0
; SOFT-DEFAULT: BL $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: BL $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
%2(s32) = G_UDIV %0, %1 %2(s32) = G_UDIV %0, %1
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_sdiv_i16 name: test_sdiv_i16
# CHECK-LABEL: name: test_sdiv_i16 # CHECK-LABEL: name: test_sdiv_i16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 37 Lines bb.0:
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV ; SOFT-NOT: G_SDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SDIV ; SOFT-NOT: G_SDIV
%4(s16) = G_SDIV %1, %3 %4(s16) = G_SDIV %1, %3
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s16) %5(s32) = G_SEXT %4(s16)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_udiv_i16 name: test_udiv_i16
# CHECK-LABEL: name: test_udiv_i16 # CHECK-LABEL: name: test_udiv_i16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 35 Lines bb.0:
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND ; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
%4(s16) = G_UDIV %1, %3 %4(s16) = G_UDIV %1, %3
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s16) %5(s32) = G_ZEXT %4(s16)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_sdiv_i8 name: test_sdiv_i8
# CHECK-LABEL: name: test_sdiv_i8 # CHECK-LABEL: name: test_sdiv_i8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 37 Lines bb.0:
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV ; SOFT-NOT: G_SDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SDIV ; SOFT-NOT: G_SDIV
%4(s8) = G_SDIV %1, %3 %4(s8) = G_SDIV %1, %3
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s8) %5(s32) = G_SEXT %4(s8)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_udiv_i8 name: test_udiv_i8
# CHECK-LABEL: name: test_udiv_i8 # CHECK-LABEL: name: test_udiv_i8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 35 Lines bb.0:
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND ; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UDIV ; SOFT-NOT: G_UDIV
%4(s8) = G_UDIV %1, %3 %4(s8) = G_UDIV %1, %3
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s8) %5(s32) = G_ZEXT %4(s8)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_srem_i32 name: test_srem_i32
# CHECK-LABEL: name: test_srem_i32 # CHECK-LABEL: name: test_srem_i32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 21 Lines bb.0:
; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1 ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1
; SOFT-DEFAULT: BL $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: BL $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM ; SOFT-NOT: G_SREM
%2(s32) = G_SREM %0, %1 %2(s32) = G_SREM %0, %1
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_urem_i32 name: test_urem_i32
# CHECK-LABEL: name: test_urem_i32 # CHECK-LABEL: name: test_urem_i32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 21 Lines bb.0:
; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1 ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY %r1
; SOFT-DEFAULT: BL $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: BL $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM ; SOFT-NOT: G_UREM
%2(s32) = G_UREM %0, %1 %2(s32) = G_UREM %0, %1
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_srem_i16 name: test_srem_i16
# CHECK-LABEL: name: test_srem_i16 # CHECK-LABEL: name: test_srem_i16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 39 Lines bb.0:
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM ; SOFT-NOT: G_SREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SREM ; SOFT-NOT: G_SREM
%4(s16) = G_SREM %1, %3 %4(s16) = G_SREM %1, %3
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s16) %5(s32) = G_SEXT %4(s16)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_urem_i16 name: test_urem_i16
# CHECK-LABEL: name: test_urem_i16 # CHECK-LABEL: name: test_urem_i16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 37 Lines bb.0:
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM ; SOFT-NOT: G_UREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND ; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UREM ; SOFT-NOT: G_UREM
%4(s16) = G_UREM %1, %3 %4(s16) = G_UREM %1, %3
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s16) %5(s32) = G_ZEXT %4(s16)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_srem_i8 name: test_srem_i8
# CHECK-LABEL: name: test_srem_i8 # CHECK-LABEL: name: test_srem_i8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 39 Lines bb.0:
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM ; SOFT-NOT: G_SREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SREM ; SOFT-NOT: G_SREM
%4(s8) = G_SREM %1, %3 %4(s8) = G_SREM %1, %3
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%5(s32) = G_SEXT %4(s8) %5(s32) = G_SEXT %4(s8)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_urem_i8 name: test_urem_i8
# CHECK-LABEL: name: test_urem_i8 # CHECK-LABEL: name: test_urem_i8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 37 Lines bb.0:
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM ; SOFT-NOT: G_UREM
; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND ; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UREM ; SOFT-NOT: G_UREM
%4(s8) = G_UREM %1, %3 %4(s8) = G_UREM %1, %3
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%5(s32) = G_ZEXT %4(s8) %5(s32) = G_ZEXT %4(s8)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines bb.0:
; HARD: BL $fmodf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0 ; HARD: BL $fmodf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0 ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0
; CHECK: ADJCALLSTACKUP ; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FREM ; CHECK-NOT: G_FREM
%2(s32) = G_FREM %0, %1 %2(s32) = G_FREM %0, %1
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_frem_double name: test_frem_double
# CHECK-LABEL: name: test_frem_double # CHECK-LABEL: name: test_frem_double
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines bb.0:
; SOFT: BL $fmod, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; SOFT: BL $fmod, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
; HARD: BL $fmod, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0 ; HARD: BL $fmod, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0
; CHECK: ADJCALLSTACKUP ; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FREM ; CHECK-NOT: G_FREM
%6(s64) = G_FREM %4, %5 %6(s64) = G_FREM %4, %5
%7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64) %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
%r1 = COPY %8(s32) %r1 = COPY %8(s32)
BX_RET 14, _, implicit %r0, implicit %r1 BX_RET 14, %noreg, implicit %r0, implicit %r1
... ...
--- ---
name: test_fpow_float name: test_fpow_float
# CHECK-LABEL: name: test_fpow_float # CHECK-LABEL: name: test_fpow_float
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 20 Lines bb.0:
; HARD: BL $powf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0 ; HARD: BL $powf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0 ; HARD: [[R:%[0-9]+]]:_(s32) = COPY %s0
; CHECK: ADJCALLSTACKUP ; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FPOW ; CHECK-NOT: G_FPOW
%2(s32) = G_FPOW %0, %1 %2(s32) = G_FPOW %0, %1
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fpow_double name: test_fpow_double
# CHECK-LABEL: name: test_fpow_double # CHECK-LABEL: name: test_fpow_double
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines bb.0:
; SOFT: BL $pow, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; SOFT: BL $pow, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
; HARD: BL $pow, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0 ; HARD: BL $pow, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0
; CHECK: ADJCALLSTACKUP ; CHECK: ADJCALLSTACKUP
; CHECK-NOT: G_FPOW ; CHECK-NOT: G_FPOW
%6(s64) = G_FPOW %4, %5 %6(s64) = G_FPOW %4, %5
%7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64) %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
%r1 = COPY %8(s32) %r1 = COPY %8(s32)
BX_RET 14, _, implicit %r0, implicit %r1 BX_RET 14, %noreg, implicit %r0, implicit %r1
... ...
--- ---
name: test_fadd_float name: test_fadd_float
# CHECK-LABEL: name: test_fadd_float # CHECK-LABEL: name: test_fadd_float
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 18 Lines bb.0:
; SOFT-AEABI: BL $__aeabi_fadd, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: BL $__aeabi_fadd, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT-DEFAULT: BL $__addsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: BL $__addsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FADD ; SOFT-NOT: G_FADD
%2(s32) = G_FADD %0, %1 %2(s32) = G_FADD %0, %1
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fadd_double name: test_fadd_double
# CHECK-LABEL: name: test_fadd_double # CHECK-LABEL: name: test_fadd_double
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 35 Lines bb.0:
; SOFT-DEFAULT: BL $__adddf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; SOFT-DEFAULT: BL $__adddf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FADD ; SOFT-NOT: G_FADD
%6(s64) = G_FADD %4, %5 %6(s64) = G_FADD %4, %5
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64) ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
%r1 = COPY %8(s32) %r1 = COPY %8(s32)
BX_RET 14, _, implicit %r0, implicit %r1 BX_RET 14, %noreg, implicit %r0, implicit %r1
... ...
--- ---
name: test_fsub_float name: test_fsub_float
# CHECK-LABEL: name: test_fsub_float # CHECK-LABEL: name: test_fsub_float
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT-AEABI: BL $__aeabi_fsub, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: BL $__aeabi_fsub, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT-DEFAULT: BL $__subsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: BL $__subsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FSUB ; SOFT-NOT: G_FSUB
%2(s32) = G_FSUB %0, %1 %2(s32) = G_FSUB %0, %1
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fsub_double name: test_fsub_double
# CHECK-LABEL: name: test_fsub_double # CHECK-LABEL: name: test_fsub_double
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT-DEFAULT: BL $__subdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; SOFT-DEFAULT: BL $__subdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FSUB ; SOFT-NOT: G_FSUB
%6(s64) = G_FSUB %4, %5 %6(s64) = G_FSUB %4, %5
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64) ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
%r1 = COPY %8(s32) %r1 = COPY %8(s32)
BX_RET 14, _, implicit %r0, implicit %r1 BX_RET 14, %noreg, implicit %r0, implicit %r1
... ...
--- ---
name: test_fmul_float name: test_fmul_float
# CHECK-LABEL: name: test_fmul_float # CHECK-LABEL: name: test_fmul_float
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT-AEABI: BL $__aeabi_fmul, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: BL $__aeabi_fmul, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT-DEFAULT: BL $__mulsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: BL $__mulsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMUL ; SOFT-NOT: G_FMUL
%2(s32) = G_FMUL %0, %1 %2(s32) = G_FMUL %0, %1
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fmul_double name: test_fmul_double
# CHECK-LABEL: name: test_fmul_double # CHECK-LABEL: name: test_fmul_double
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT-DEFAULT: BL $__muldf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; SOFT-DEFAULT: BL $__muldf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FMUL ; SOFT-NOT: G_FMUL
%6(s64) = G_FMUL %4, %5 %6(s64) = G_FMUL %4, %5
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64) ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
%r1 = COPY %8(s32) %r1 = COPY %8(s32)
BX_RET 14, _, implicit %r0, implicit %r1 BX_RET 14, %noreg, implicit %r0, implicit %r1
... ...
--- ---
name: test_fdiv_float name: test_fdiv_float
# CHECK-LABEL: name: test_fdiv_float # CHECK-LABEL: name: test_fdiv_float
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT-AEABI: BL $__aeabi_fdiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-AEABI: BL $__aeabi_fdiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT-DEFAULT: BL $__divsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 ; SOFT-DEFAULT: BL $__divsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FDIV ; SOFT-NOT: G_FDIV
%2(s32) = G_FDIV %0, %1 %2(s32) = G_FDIV %0, %1
; CHECK: %r0 = COPY [[R]] ; CHECK: %r0 = COPY [[R]]
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fdiv_double name: test_fdiv_double
# CHECK-LABEL: name: test_fdiv_double # CHECK-LABEL: name: test_fdiv_double
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT-DEFAULT: BL $__divdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; SOFT-DEFAULT: BL $__divdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_FDIV ; SOFT-NOT: G_FDIV
%6(s64) = G_FDIV %4, %5 %6(s64) = G_FDIV %4, %5
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64) ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64) %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
%r1 = COPY %8(s32) %r1 = COPY %8(s32)
BX_RET 14, _, implicit %r0, implicit %r1 BX_RET 14, %noreg, implicit %r0, implicit %r1
... ...
--- ---
name: test_fcmp_true_s32 name: test_fcmp_true_s32
# CHECK-LABEL: name: test_fcmp_true_s32 # CHECK-LABEL: name: test_fcmp_true_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
- { id: 3, class: _ } - { id: 3, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_FCMP floatpred(true), %0(s32), %1 %2(s1) = G_FCMP floatpred(true), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]] ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
; For soft float we just need to return a '-1' constant, but the truncation ; For soft float we just need to return a '-1' constant, but the truncation
; to 1 bit is converted by the combiner to the following masking sequence. ; to 1 bit is converted by the combiner to the following masking sequence.
; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
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bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_FCMP floatpred(false), %0(s32), %1 %2(s1) = G_FCMP floatpred(false), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0 ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1 ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]] ; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]]
; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
; For soft float we just need to return a '0' constant, but the truncation ; For soft float we just need to return a '0' constant, but the truncation
; to 1 bit is converted by the combiner to the following masking sequence. ; to 1 bit is converted by the combiner to the following masking sequence.
; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines bb.0:
; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ogt_s32 name: test_fcmp_ogt_s32
# CHECK-LABEL: name: test_fcmp_ogt_s32 # CHECK-LABEL: name: test_fcmp_ogt_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_oge_s32 name: test_fcmp_oge_s32
# CHECK-LABEL: name: test_fcmp_oge_s32 # CHECK-LABEL: name: test_fcmp_oge_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_olt_s32 name: test_fcmp_olt_s32
# CHECK-LABEL: name: test_fcmp_olt_s32 # CHECK-LABEL: name: test_fcmp_olt_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ole_s32 name: test_fcmp_ole_s32
# CHECK-LABEL: name: test_fcmp_ole_s32 # CHECK-LABEL: name: test_fcmp_ole_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ord_s32 name: test_fcmp_ord_s32
# CHECK-LABEL: name: test_fcmp_ord_s32 # CHECK-LABEL: name: test_fcmp_ord_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ugt_s32 name: test_fcmp_ugt_s32
# CHECK-LABEL: name: test_fcmp_ugt_s32 # CHECK-LABEL: name: test_fcmp_ugt_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_uge_s32 name: test_fcmp_uge_s32
# CHECK-LABEL: name: test_fcmp_uge_s32 # CHECK-LABEL: name: test_fcmp_uge_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 24 Lines bb.0:
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ult_s32 name: test_fcmp_ult_s32
# CHECK-LABEL: name: test_fcmp_ult_s32 # CHECK-LABEL: name: test_fcmp_ult_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 24 Lines bb.0:
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ule_s32 name: test_fcmp_ule_s32
# CHECK-LABEL: name: test_fcmp_ule_s32 # CHECK-LABEL: name: test_fcmp_ule_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 24 Lines bb.0:
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_une_s32 name: test_fcmp_une_s32
# CHECK-LABEL: name: test_fcmp_une_s32 # CHECK-LABEL: name: test_fcmp_une_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_uno_s32 name: test_fcmp_uno_s32
# CHECK-LABEL: name: test_fcmp_uno_s32 # CHECK-LABEL: name: test_fcmp_uno_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 29 Lines bb.0:
; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_one_s32 name: test_fcmp_one_s32
# CHECK-LABEL: name: test_fcmp_one_s32 # CHECK-LABEL: name: test_fcmp_one_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines bb.0:
; truncation into the following masking sequence. ; truncation into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]] ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ueq_s32 name: test_fcmp_ueq_s32
# CHECK-LABEL: name: test_fcmp_ueq_s32 # CHECK-LABEL: name: test_fcmp_ueq_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines bb.0:
; truncation into the following masking sequence. ; truncation into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]] ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_true_s64 name: test_fcmp_true_s64
# CHECK-LABEL: name: test_fcmp_true_s64 # CHECK-LABEL: name: test_fcmp_true_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 32 Lines bb.0:
; into the following masking sequence. ; into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]] ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_false_s64 name: test_fcmp_false_s64
# CHECK-LABEL: name: test_fcmp_false_s64 # CHECK-LABEL: name: test_fcmp_false_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 33 Lines bb.0:
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]] ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_oeq_s64 name: test_fcmp_oeq_s64
# CHECK-LABEL: name: test_fcmp_oeq_s64 # CHECK-LABEL: name: test_fcmp_oeq_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines bb.0:
; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ogt_s64 name: test_fcmp_ogt_s64
# CHECK-LABEL: name: test_fcmp_ogt_s64 # CHECK-LABEL: name: test_fcmp_ogt_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines bb.0:
; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_oge_s64 name: test_fcmp_oge_s64
# CHECK-LABEL: name: test_fcmp_oge_s64 # CHECK-LABEL: name: test_fcmp_oge_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines bb.0:
; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_olt_s64 name: test_fcmp_olt_s64
# CHECK-LABEL: name: test_fcmp_olt_s64 # CHECK-LABEL: name: test_fcmp_olt_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines bb.0:
; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ole_s64 name: test_fcmp_ole_s64
# CHECK-LABEL: name: test_fcmp_ole_s64 # CHECK-LABEL: name: test_fcmp_ole_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines bb.0:
; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ord_s64 name: test_fcmp_ord_s64
# CHECK-LABEL: name: test_fcmp_ord_s64 # CHECK-LABEL: name: test_fcmp_ord_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 37 Lines bb.0:
; SOFT: ADJCALLSTACKUP ; SOFT: ADJCALLSTACKUP
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ugt_s64 name: test_fcmp_ugt_s64
# CHECK-LABEL: name: test_fcmp_ugt_s64 # CHECK-LABEL: name: test_fcmp_ugt_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 38 Lines bb.0:
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_uge_s64 name: test_fcmp_uge_s64
# CHECK-LABEL: name: test_fcmp_uge_s64 # CHECK-LABEL: name: test_fcmp_uge_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 38 Lines bb.0:
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ult_s64 name: test_fcmp_ult_s64
# CHECK-LABEL: name: test_fcmp_ult_s64 # CHECK-LABEL: name: test_fcmp_ult_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ule_s64 name: test_fcmp_ule_s64
# CHECK-LABEL: name: test_fcmp_ule_s64 # CHECK-LABEL: name: test_fcmp_ule_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 38 Lines bb.0:
; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_une_s64 name: test_fcmp_une_s64
# CHECK-LABEL: name: test_fcmp_une_s64 # CHECK-LABEL: name: test_fcmp_une_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
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; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]] ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_uno_s64 name: test_fcmp_uno_s64
# CHECK-LABEL: name: test_fcmp_uno_s64 # CHECK-LABEL: name: test_fcmp_uno_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines bb.0:
; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]] ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1) ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_one_s64 name: test_fcmp_one_s64
# CHECK-LABEL: name: test_fcmp_one_s64 # CHECK-LABEL: name: test_fcmp_one_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines bb.0:
; truncation into the following masking sequence. ; truncation into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]] ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ueq_s64 name: test_fcmp_ueq_s64
# CHECK-LABEL: name: test_fcmp_ueq_s64 # CHECK-LABEL: name: test_fcmp_ueq_s64
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines bb.0:
; truncation into the following masking sequence. ; truncation into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]] ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]] ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP ; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1) %7(s32) = G_ZEXT %6(s1)
%r0 = COPY %7(s32) %r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]] ; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines bb.0:
liveins: %r0 liveins: %r0
%0(p0) = COPY %r0 %0(p0) = COPY %r0
%1(s8) = G_LOAD %0(p0) :: (load 1) %1(s8) = G_LOAD %0(p0) :: (load 1)
%2(s32) = G_SEXT %1 %2(s32) = G_SEXT %1
; G_SEXT with s8 is legal, so we should find it unchanged in the output ; G_SEXT with s8 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SEXT {{%[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_SEXT {{%[0-9]+}}
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_zext_s16 name: test_zext_s16
# CHECK-LABEL: name: test_zext_s16 # CHECK-LABEL: name: test_zext_s16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0 liveins: %r0
%0(p0) = COPY %r0 %0(p0) = COPY %r0
%1(s16) = G_LOAD %0 :: (load 2) %1(s16) = G_LOAD %0 :: (load 2)
%2(s32) = G_ZEXT %1 %2(s32) = G_ZEXT %1
; G_ZEXT with s16 is legal, so we should find it unchanged in the output ; G_ZEXT with s16 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_ZEXT {{%[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_ZEXT {{%[0-9]+}}
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_add_s8 name: test_add_s8
# CHECK-LABEL: name: test_add_s8 # CHECK-LABEL: name: test_add_s8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 15 Lines bb.0:
%3(s8) = G_LOAD %2 :: (load 1) %3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_ADD %1, %3 %4(s8) = G_ADD %1, %3
; G_ADD with s8 should widen ; G_ADD with s8 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8) %5(s32) = G_SEXT %4(s8)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_add_s16 name: test_add_s16
# CHECK-LABEL: name: test_add_s16 # CHECK-LABEL: name: test_add_s16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 15 Lines bb.0:
%3(s16) = G_LOAD %2 :: (load 2) %3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_ADD %1, %3 %4(s16) = G_ADD %1, %3
; G_ADD with s16 should widen ; G_ADD with s16 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16) %5(s32) = G_SEXT %4(s16)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_add_s32 name: test_add_s32
# CHECK-LABEL: name: test_add_s32 # CHECK-LABEL: name: test_add_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_ADD %0, %1 %2(s32) = G_ADD %0, %1
; G_ADD with s32 is legal, so we should find it unchanged in the output ; G_ADD with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_sub_s8 name: test_sub_s8
# CHECK-LABEL: name: test_sub_s8 # CHECK-LABEL: name: test_sub_s8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
Show All 16 Lines bb.0:
%3(s8) = G_LOAD %2 :: (load 1) %3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_SUB %1, %3 %4(s8) = G_SUB %1, %3
; G_SUB with s8 should widen ; G_SUB with s8 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8) %5(s32) = G_SEXT %4(s8)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_sub_s16 name: test_sub_s16
# CHECK-LABEL: name: test_sub_s16 # CHECK-LABEL: name: test_sub_s16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 15 Lines bb.0:
%3(s16) = G_LOAD %2 :: (load 2) %3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_SUB %1, %3 %4(s16) = G_SUB %1, %3
; G_SUB with s16 should widen ; G_SUB with s16 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16) %5(s32) = G_SEXT %4(s16)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_sub_s32 name: test_sub_s32
# CHECK-LABEL: name: test_sub_s32 # CHECK-LABEL: name: test_sub_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_SUB %0, %1 %2(s32) = G_SUB %0, %1
; G_SUB with s32 is legal, so we should find it unchanged in the output ; G_SUB with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_mul_s8 name: test_mul_s8
# CHECK-LABEL: name: test_mul_s8 # CHECK-LABEL: name: test_mul_s8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
Show All 16 Lines bb.0:
%3(s8) = G_LOAD %2 :: (load 1) %3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_MUL %1, %3 %4(s8) = G_MUL %1, %3
; G_MUL with s8 should widen ; G_MUL with s8 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8) %5(s32) = G_SEXT %4(s8)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_mul_s16 name: test_mul_s16
# CHECK-LABEL: name: test_mul_s16 # CHECK-LABEL: name: test_mul_s16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 15 Lines bb.0:
%3(s16) = G_LOAD %2 :: (load 2) %3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_MUL %1, %3 %4(s16) = G_MUL %1, %3
; G_MUL with s16 should widen ; G_MUL with s16 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16) %5(s32) = G_SEXT %4(s16)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_mul_s32 name: test_mul_s32
# CHECK-LABEL: name: test_mul_s32 # CHECK-LABEL: name: test_mul_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_MUL %0, %1 %2(s32) = G_MUL %0, %1
; G_MUL with s32 is legal, so we should find it unchanged in the output ; G_MUL with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_and_s8 name: test_and_s8
# CHECK-LABEL: name: test_and_s8 # CHECK-LABEL: name: test_and_s8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
Show All 16 Lines bb.0:
%3(s8) = G_LOAD %2 :: (load 1) %3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_AND %1, %3 %4(s8) = G_AND %1, %3
; G_AND with s8 should widen ; G_AND with s8 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_AND {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8) %5(s32) = G_SEXT %4(s8)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_and_s16 name: test_and_s16
# CHECK-LABEL: name: test_and_s16 # CHECK-LABEL: name: test_and_s16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 15 Lines bb.0:
%3(s16) = G_LOAD %2 :: (load 2) %3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_AND %1, %3 %4(s16) = G_AND %1, %3
; G_AND with s16 should widen ; G_AND with s16 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_AND {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16) %5(s32) = G_SEXT %4(s16)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_and_s32 name: test_and_s32
# CHECK-LABEL: name: test_and_s32 # CHECK-LABEL: name: test_and_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_AND %0, %1 %2(s32) = G_AND %0, %1
; G_AND with s32 is legal, so we should find it unchanged in the output ; G_AND with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_AND {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_or_s8 name: test_or_s8
# CHECK-LABEL: name: test_or_s8 # CHECK-LABEL: name: test_or_s8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
Show All 16 Lines bb.0:
%3(s8) = G_LOAD %2 :: (load 1) %3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_OR %1, %3 %4(s8) = G_OR %1, %3
; G_OR with s8 should widen ; G_OR with s8 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_OR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8) %5(s32) = G_SEXT %4(s8)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_or_s16 name: test_or_s16
# CHECK-LABEL: name: test_or_s16 # CHECK-LABEL: name: test_or_s16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 15 Lines bb.0:
%3(s16) = G_LOAD %2 :: (load 2) %3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_OR %1, %3 %4(s16) = G_OR %1, %3
; G_OR with s16 should widen ; G_OR with s16 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_OR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16) %5(s32) = G_SEXT %4(s16)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_or_s32 name: test_or_s32
# CHECK-LABEL: name: test_or_s32 # CHECK-LABEL: name: test_or_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_OR %0, %1 %2(s32) = G_OR %0, %1
; G_OR with s32 is legal, so we should find it unchanged in the output ; G_OR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_OR {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_xor_s8 name: test_xor_s8
# CHECK-LABEL: name: test_xor_s8 # CHECK-LABEL: name: test_xor_s8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
Show All 16 Lines bb.0:
%3(s8) = G_LOAD %2 :: (load 1) %3(s8) = G_LOAD %2 :: (load 1)
%4(s8) = G_XOR %1, %3 %4(s8) = G_XOR %1, %3
; G_XOR with s8 should widen ; G_XOR with s8 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s8) = G_XOR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s8) %5(s32) = G_SEXT %4(s8)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_xor_s16 name: test_xor_s16
# CHECK-LABEL: name: test_xor_s16 # CHECK-LABEL: name: test_xor_s16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 15 Lines bb.0:
%3(s16) = G_LOAD %2 :: (load 2) %3(s16) = G_LOAD %2 :: (load 2)
%4(s16) = G_XOR %1, %3 %4(s16) = G_XOR %1, %3
; G_XOR with s16 should widen ; G_XOR with s16 should widen
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s16) = G_XOR {{%[0-9]+, %[0-9]+}}
%5(s32) = G_SEXT %4(s16) %5(s32) = G_SEXT %4(s16)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_xor_s32 name: test_xor_s32
# CHECK-LABEL: name: test_xor_s32 # CHECK-LABEL: name: test_xor_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_XOR %0, %1 %2(s32) = G_XOR %0, %1
; G_XOR with s32 is legal, so we should find it unchanged in the output ; G_XOR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_XOR {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_lshr_s32 name: test_lshr_s32
# CHECK-LABEL: name: test_lshr_s32 # CHECK-LABEL: name: test_lshr_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_LSHR %0, %1 %2(s32) = G_LSHR %0, %1
; G_LSHR with s32 is legal, so we should find it unchanged in the output ; G_LSHR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_LSHR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_LSHR {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_ashr_s32 name: test_ashr_s32
# CHECK-LABEL: name: test_ashr_s32 # CHECK-LABEL: name: test_ashr_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_ASHR %0, %1 %2(s32) = G_ASHR %0, %1
; G_ASHR with s32 is legal, so we should find it unchanged in the output ; G_ASHR with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_ASHR {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_ASHR {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_shl_s32 name: test_shl_s32
# CHECK-LABEL: name: test_shl_s32 # CHECK-LABEL: name: test_shl_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_SHL %0, %1 %2(s32) = G_SHL %0, %1
; G_SHL with s32 is legal, so we should find it unchanged in the output ; G_SHL with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_SHL {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_load_from_stack name: test_load_from_stack
# CHECK-LABEL: name: test_load_from_stack # CHECK-LABEL: name: test_load_from_stack
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
Show All 14 Lines bb.0:
liveins: %r0, %r1, %r2, %r3 liveins: %r0, %r1, %r2, %r3
; This is legal, so we should find it unchanged in the output ; This is legal, so we should find it unchanged in the output
; CHECK: [[FIVREG:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]] ; CHECK: [[FIVREG:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
; CHECK: {{%[0-9]+}}:_(s32) = G_LOAD [[FIVREG]](p0) :: (load 4) ; CHECK: {{%[0-9]+}}:_(s32) = G_LOAD [[FIVREG]](p0) :: (load 4)
%0(p0) = G_FRAME_INDEX %fixed-stack.2 %0(p0) = G_FRAME_INDEX %fixed-stack.2
%1(s32) = G_LOAD %0(p0) :: (load 4) %1(s32) = G_LOAD %0(p0) :: (load 4)
%r0 = COPY %1(s32) %r0 = COPY %1(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_legal_loads_stores name: test_legal_loads_stores
# CHECK-LABEL: name: test_legal_loads_stores # CHECK-LABEL: name: test_legal_loads_stores
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 31 Lines bb.0:
%3(s16) = G_LOAD %0(p0) :: (load 2) %3(s16) = G_LOAD %0(p0) :: (load 2)
G_STORE %3(s16), %0(p0) :: (store 2) G_STORE %3(s16), %0(p0) :: (store 2)
%4(s8) = G_LOAD %0(p0) :: (load 1) %4(s8) = G_LOAD %0(p0) :: (load 1)
G_STORE %4(s8), %0(p0) :: (store 1) G_STORE %4(s8), %0(p0) :: (store 1)
%5(s1) = G_LOAD %0(p0) :: (load 1) %5(s1) = G_LOAD %0(p0) :: (load 1)
G_STORE %5(s1), %0(p0) :: (store 1) G_STORE %5(s1), %0(p0) :: (store 1)
%6(p0) = G_LOAD %0(p0) :: (load 4) %6(p0) = G_LOAD %0(p0) :: (load 4)
G_STORE %6(p0), %0(p0) :: (store 4) G_STORE %6(p0), %0(p0) :: (store 4)
BX_RET 14, _ BX_RET 14, %noreg
... ...
--- ---
name: test_gep name: test_gep
# CHECK-LABEL: name: test_gep # CHECK-LABEL: name: test_gep
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(p0) = COPY %r0 %0(p0) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
; CHECK: {{%[0-9]+}}:_(p0) = G_GEP {{%[0-9]+}}, {{%[0-9]+}}(s32) ; CHECK: {{%[0-9]+}}:_(p0) = G_GEP {{%[0-9]+}}, {{%[0-9]+}}(s32)
%2(p0) = G_GEP %0, %1(s32) %2(p0) = G_GEP %0, %1(s32)
%r0 = COPY %2(p0) %r0 = COPY %2(p0)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_constants name: test_constants
# CHECK-LABEL: name: test_constants # CHECK-LABEL: name: test_constants
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 30 Lines bb.0:
%3(s1) = G_CONSTANT i1 1 %3(s1) = G_CONSTANT i1 1
G_STORE %3(s1), %4(p0) :: (store 1) G_STORE %3(s1), %4(p0) :: (store 1)
; CHECK-NOT: G_CONSTANT i1 ; CHECK-NOT: G_CONSTANT i1
; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[EXT]](s32) ; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[EXT]](s32)
; CHECK-NOT: G_CONSTANT i1 ; CHECK-NOT: G_CONSTANT i1
%r0 = COPY %0(s32) %r0 = COPY %0(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_icmp_s8 name: test_icmp_s8
# CHECK-LABEL: name: test_icmp_s8 # CHECK-LABEL: name: test_icmp_s8
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 14 Lines bb.0:
%2(p0) = COPY %r1 %2(p0) = COPY %r1
%3(s8) = G_LOAD %2 :: (load 1) %3(s8) = G_LOAD %2 :: (load 1)
%4(s1) = G_ICMP intpred(ne), %1(s8), %3 %4(s1) = G_ICMP intpred(ne), %1(s8), %3
; G_ICMP with s8 should widen ; G_ICMP with s8 should widen
; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s32), {{%[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s32), {{%[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}}
%5(s32) = G_ZEXT %4(s1) %5(s32) = G_ZEXT %4(s1)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_icmp_s16 name: test_icmp_s16
# CHECK-LABEL: name: test_icmp_s16 # CHECK-LABEL: name: test_icmp_s16
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 14 Lines bb.0:
%2(p0) = COPY %r1 %2(p0) = COPY %r1
%3(s16) = G_LOAD %2 :: (load 2) %3(s16) = G_LOAD %2 :: (load 2)
%4(s1) = G_ICMP intpred(slt), %1(s16), %3 %4(s1) = G_ICMP intpred(slt), %1(s16), %3
; G_ICMP with s16 should widen ; G_ICMP with s16 should widen
; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s32), {{%[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s32), {{%[0-9]+}}
; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}} ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}}
%5(s32) = G_ZEXT %4(s1) %5(s32) = G_ZEXT %4(s1)
%r0 = COPY %5(s32) %r0 = COPY %5(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_icmp_s32 name: test_icmp_s32
# CHECK-LABEL: name: test_icmp_s32 # CHECK-LABEL: name: test_icmp_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines bb.0:
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1 %2(s1) = G_ICMP intpred(eq), %0(s32), %1
; G_ICMP with s32 is legal, so we should find it unchanged in the output ; G_ICMP with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), {{%[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), {{%[0-9]+}}
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_select_s32 name: test_select_s32
# CHECK-LABEL: name: test_select_s32 # CHECK-LABEL: name: test_select_s32
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines bb.0:
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_CONSTANT i1 1 %2(s1) = G_CONSTANT i1 1
%3(s32) = G_SELECT %2(s1), %0, %1 %3(s32) = G_SELECT %2(s1), %0, %1
; G_SELECT with s32 is legal, so we should find it unchanged in the output ; G_SELECT with s32 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}} ; CHECK: {{%[0-9]+}}:_(s32) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_select_ptr name: test_select_ptr
# CHECK-LABEL: name: test_select_ptr # CHECK-LABEL: name: test_select_ptr
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines bb.0:
%0(p0) = COPY %r0 %0(p0) = COPY %r0
%1(p0) = COPY %r1 %1(p0) = COPY %r1
%2(s1) = G_CONSTANT i1 0 %2(s1) = G_CONSTANT i1 0
%3(p0) = G_SELECT %2(s1), %0, %1 %3(p0) = G_SELECT %2(s1), %0, %1
; G_SELECT with p0 is legal, so we should find it unchanged in the output ; G_SELECT with p0 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(p0) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}} ; CHECK: {{%[0-9]+}}:_(p0) = G_SELECT {{%[0-9]+}}(s1), {{%[0-9]+}}, {{%[0-9]+}}
%r0 = COPY %3(p0) %r0 = COPY %3(p0)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_brcond name: test_brcond
# CHECK-LABEL: name: test_brcond # CHECK-LABEL: name: test_brcond
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 12 Lines bb.0:
%2(s1) = G_ICMP intpred(sgt), %0(s32), %1 %2(s1) = G_ICMP intpred(sgt), %0(s32), %1
G_BRCOND %2(s1), %bb.1 G_BRCOND %2(s1), %bb.1
; G_BRCOND with s1 is legal, so we should find it unchanged in the output ; G_BRCOND with s1 is legal, so we should find it unchanged in the output
; CHECK: G_BRCOND {{%[0-9]+}}(s1), %bb.1 ; CHECK: G_BRCOND {{%[0-9]+}}(s1), %bb.1
G_BR %bb.2 G_BR %bb.2
bb.1: bb.1:
%r0 = COPY %1(s32) %r0 = COPY %1(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
bb.2: bb.2:
%r0 = COPY %0(s32) %r0 = COPY %0(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_global_variable name: test_global_variable
# CHECK-LABEL: name: test_global_variable # CHECK-LABEL: name: test_global_variable
legalized: false legalized: false
# CHECK: legalized: true # CHECK: legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0 liveins: %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(p0) = G_GLOBAL_VALUE @a_global %1(p0) = G_GLOBAL_VALUE @a_global
; G_GLOBAL_VALUE is legal, so we should find it unchanged in the output ; G_GLOBAL_VALUE is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(p0) = G_GLOBAL_VALUE @a_global ; CHECK: {{%[0-9]+}}:_(p0) = G_GLOBAL_VALUE @a_global
%r0 = COPY %1(p0) %r0 = COPY %1(p0)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll

; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE ; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LITTLE
; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=BIG ; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=BIG
declare arm_aapcscc i32* @simple_reg_params_target(i32, i32*) declare arm_aapcscc i32* @simple_reg_params_target(i32, i32*)
define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) { define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) {
; CHECK-LABEL: name: test_call_simple_reg_params ; CHECK-LABEL: name: test_call_simple_reg_params
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK-DAG: %r0 = COPY [[BVREG]] ; CHECK-DAG: %r0 = COPY [[BVREG]]
; CHECK-DAG: %r1 = COPY [[AVREG]] ; CHECK-DAG: %r1 = COPY [[AVREG]]
; CHECK: BL @simple_reg_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0 ; CHECK: BL @simple_reg_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0
; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0 ; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0
; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: %r0 = COPY [[RVREG]] ; CHECK: %r0 = COPY [[RVREG]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%r = notail call arm_aapcscc i32 *@simple_reg_params_target(i32 %b, i32 *%a) %r = notail call arm_aapcscc i32 *@simple_reg_params_target(i32 %b, i32 *%a)
ret i32 *%r ret i32 *%r
} }
declare arm_aapcscc i32* @simple_stack_params_target(i32, i32*, i32, i32*, i32, i32*) declare arm_aapcscc i32* @simple_stack_params_target(i32, i32*, i32, i32*, i32, i32*)
define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) { define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) {
; CHECK-LABEL: name: test_call_simple_stack_params ; CHECK-LABEL: name: test_call_simple_stack_params
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY %r0
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r1
; CHECK: ADJCALLSTACKDOWN 8, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK-DAG: %r0 = COPY [[BVREG]] ; CHECK-DAG: %r0 = COPY [[BVREG]]
; CHECK-DAG: %r1 = COPY [[AVREG]] ; CHECK-DAG: %r1 = COPY [[AVREG]]
; CHECK-DAG: %r2 = COPY [[BVREG]] ; CHECK-DAG: %r2 = COPY [[BVREG]]
; CHECK-DAG: %r3 = COPY [[AVREG]] ; CHECK-DAG: %r3 = COPY [[AVREG]]
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp ; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32) ; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4 ; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp ; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32) ; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4 ; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4
; CHECK: BL @simple_stack_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; CHECK: BL @simple_stack_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0 ; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY %r0
; CHECK: ADJCALLSTACKUP 8, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: %r0 = COPY [[RVREG]] ; CHECK: %r0 = COPY [[RVREG]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%r = notail call arm_aapcscc i32 *@simple_stack_params_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a) %r = notail call arm_aapcscc i32 *@simple_stack_params_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a)
ret i32 *%r ret i32 *%r
} }
declare arm_aapcscc signext i16 @ext_target(i8 signext, i8 zeroext, i16 signext, i16 zeroext, i8 signext, i8 zeroext, i16 signext, i16 zeroext, i1 zeroext) declare arm_aapcscc signext i16 @ext_target(i8 signext, i8 zeroext, i16 signext, i16 zeroext, i8 signext, i8 zeroext, i16 signext, i16 zeroext, i1 zeroext)
define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) { define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) {
; CHECK-LABEL: name: test_call_ext_params ; CHECK-LABEL: name: test_call_ext_params
; CHECK-DAG: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s8) = G_TRUNC [[R0VREG]] ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s8) = G_TRUNC [[R0VREG]]
; CHECK-DAG: [[R1VREG:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[R1VREG:%[0-9]+]]:_(s32) = COPY %r1
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R1VREG]] ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R1VREG]]
; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY %r2 ; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY %r2
; CHECK-DAG: [[CVREG:%[0-9]+]]:_(s1) = G_TRUNC [[R2VREG]] ; CHECK-DAG: [[CVREG:%[0-9]+]]:_(s1) = G_TRUNC [[R2VREG]]
; CHECK: ADJCALLSTACKDOWN 20, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 20, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[SEXTA:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]](s8) ; CHECK: [[SEXTA:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]](s8)
; CHECK: %r0 = COPY [[SEXTA]] ; CHECK: %r0 = COPY [[SEXTA]]
; CHECK: [[ZEXTA:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]](s8) ; CHECK: [[ZEXTA:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]](s8)
; CHECK: %r1 = COPY [[ZEXTA]] ; CHECK: %r1 = COPY [[ZEXTA]]
; CHECK: [[SEXTB:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]](s16) ; CHECK: [[SEXTB:%[0-9]+]]:_(s32) = G_SEXT [[BVREG]](s16)
; CHECK: %r2 = COPY [[SEXTB]] ; CHECK: %r2 = COPY [[SEXTB]]
; CHECK: [[ZEXTB:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]](s16) ; CHECK: [[ZEXTB:%[0-9]+]]:_(s32) = G_ZEXT [[BVREG]](s16)
; CHECK: %r3 = COPY [[ZEXTB]] ; CHECK: %r3 = COPY [[ZEXTB]]
Show All 20 Lines
; CHECK: [[SP5:%[0-9]+]]:_(p0) = COPY %sp ; CHECK: [[SP5:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[OFF5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[OFF5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[FI5:%[0-9]+]]:_(p0) = G_GEP [[SP5]], [[OFF5]](s32) ; CHECK: [[FI5:%[0-9]+]]:_(p0) = G_GEP [[SP5]], [[OFF5]](s32)
; CHECK: [[ZEXTC:%[0-9]+]]:_(s32) = G_ZEXT [[CVREG]] ; CHECK: [[ZEXTC:%[0-9]+]]:_(s32) = G_ZEXT [[CVREG]]
; CHECK: G_STORE [[ZEXTC]](s32), [[FI5]](p0){{.*}}store 4 ; CHECK: G_STORE [[ZEXTC]](s32), [[FI5]](p0){{.*}}store 4
; CHECK: BL @ext_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0 ; CHECK: BL @ext_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY %r0
; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG]] ; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG]]
; CHECK: ADJCALLSTACKUP 20, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 20, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[RExtVREG:%[0-9]+]]:_(s32) = G_SEXT [[RVREG]] ; CHECK: [[RExtVREG:%[0-9]+]]:_(s32) = G_SEXT [[RVREG]]
; CHECK: %r0 = COPY [[RExtVREG]] ; CHECK: %r0 = COPY [[RExtVREG]]
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
entry: entry:
%r = notail call arm_aapcscc signext i16 @ext_target(i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i1 zeroext %c) %r = notail call arm_aapcscc signext i16 @ext_target(i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i1 zeroext %c)
ret i16 %r ret i16 %r
} }
declare arm_aapcs_vfpcc double @vfpcc_fp_target(float, double) declare arm_aapcs_vfpcc double @vfpcc_fp_target(float, double)
define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) { define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) {
; CHECK-LABEL: name: test_call_vfpcc_fp_params ; CHECK-LABEL: name: test_call_vfpcc_fp_params
; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY %d0 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY %d0
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %s2 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %s2
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK-DAG: %s0 = COPY [[BVREG]] ; CHECK-DAG: %s0 = COPY [[BVREG]]
; CHECK-DAG: %d1 = COPY [[AVREG]] ; CHECK-DAG: %d1 = COPY [[AVREG]]
; CHECK: BL @vfpcc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %d1, implicit-def %d0 ; CHECK: BL @vfpcc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %d1, implicit-def %d0
; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY %d0 ; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY %d0
; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: %d0 = COPY [[RVREG]] ; CHECK: %d0 = COPY [[RVREG]]
; CHECK: BX_RET 14, _, implicit %d0 ; CHECK: BX_RET 14, %noreg, implicit %d0
entry: entry:
%r = notail call arm_aapcs_vfpcc double @vfpcc_fp_target(float %b, double %a) %r = notail call arm_aapcs_vfpcc double @vfpcc_fp_target(float %b, double %a)
ret double %r ret double %r
} }
declare arm_aapcscc double @aapcscc_fp_target(float, double, float, double) declare arm_aapcscc double @aapcscc_fp_target(float, double, float, double)
define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) { define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) {
; CHECK-LABEL: name: test_call_aapcs_fp_params ; CHECK-LABEL: name: test_call_aapcs_fp_params
; CHECK-DAG: [[A1:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[A1:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[A2:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[A2:%[0-9]+]]:_(s32) = COPY %r1
; LITTLE-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32) ; LITTLE-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32)
; BIG-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32) ; BIG-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32)
; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r2 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY %r2
; CHECK: ADJCALLSTACKDOWN 16, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 16, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK-DAG: %r0 = COPY [[BVREG]] ; CHECK-DAG: %r0 = COPY [[BVREG]]
; CHECK-DAG: [[A1:%[0-9]+]]:_(s32), [[A2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AVREG]](s64) ; CHECK-DAG: [[A1:%[0-9]+]]:_(s32), [[A2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AVREG]](s64)
; LITTLE-DAG: %r2 = COPY [[A1]] ; LITTLE-DAG: %r2 = COPY [[A1]]
; LITTLE-DAG: %r3 = COPY [[A2]] ; LITTLE-DAG: %r3 = COPY [[A2]]
; BIG-DAG: %r2 = COPY [[A2]] ; BIG-DAG: %r2 = COPY [[A2]]
; BIG-DAG: %r3 = COPY [[A1]] ; BIG-DAG: %r3 = COPY [[A1]]
; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp ; CHECK: [[SP1:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[OFF1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32) ; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_GEP [[SP1]], [[OFF1]](s32)
; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4 ; CHECK: G_STORE [[BVREG]](s32), [[FI1]](p0){{.*}}store 4
; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp ; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32) ; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_GEP [[SP2]], [[OFF2]](s32)
; CHECK: G_STORE [[AVREG]](s64), [[FI2]](p0){{.*}}store 8 ; CHECK: G_STORE [[AVREG]](s64), [[FI2]](p0){{.*}}store 8
; CHECK: BL @aapcscc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; CHECK: BL @aapcscc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r1
; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32) ; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32)
; BIG: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32) ; BIG: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32)
; CHECK: ADJCALLSTACKUP 16, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 16, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](s64) ; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](s64)
; LITTLE-DAG: %r0 = COPY [[R1]] ; LITTLE-DAG: %r0 = COPY [[R1]]
; LITTLE-DAG: %r1 = COPY [[R2]] ; LITTLE-DAG: %r1 = COPY [[R2]]
; BIG-DAG: %r0 = COPY [[R2]] ; BIG-DAG: %r0 = COPY [[R2]]
; BIG-DAG: %r1 = COPY [[R1]] ; BIG-DAG: %r1 = COPY [[R1]]
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
entry: entry:
%r = notail call arm_aapcscc double @aapcscc_fp_target(float %b, double %a, float %b, double %a) %r = notail call arm_aapcscc double @aapcscc_fp_target(float %b, double %a, float %b, double %a)
ret double %r ret double %r
} }
declare arm_aapcscc float @different_call_conv_target(float) declare arm_aapcscc float @different_call_conv_target(float)
define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) { define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) {
; CHECK-LABEL: name: test_call_different_call_conv ; CHECK-LABEL: name: test_call_different_call_conv
; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %s0 ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY %s0
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: %r0 = COPY [[X]] ; CHECK: %r0 = COPY [[X]]
; CHECK: BL @different_call_conv_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit-def %r0 ; CHECK: BL @different_call_conv_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit-def %r0
; CHECK: [[R:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R:%[0-9]+]]:_(s32) = COPY %r0
; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: %s0 = COPY [[R]] ; CHECK: %s0 = COPY [[R]]
; CHECK: BX_RET 14, _, implicit %s0 ; CHECK: BX_RET 14, %noreg, implicit %s0
entry: entry:
%r = notail call arm_aapcscc float @different_call_conv_target(float %x) %r = notail call arm_aapcscc float @different_call_conv_target(float %x)
ret float %r ret float %r
} }
declare arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32]) declare arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32])
define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) { define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {
; CHECK-LABEL: name: test_tiny_int_arrays ; CHECK-LABEL: name: test_tiny_int_arrays
; CHECK: liveins: %r0, %r1 ; CHECK: liveins: %r0, %r1
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK: [[ARG_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) ; CHECK: [[ARG_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s64) ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s64)
; CHECK: %r0 = COPY [[R0]] ; CHECK: %r0 = COPY [[R0]]
; CHECK: %r1 = COPY [[R1]] ; CHECK: %r1 = COPY [[R1]]
; CHECK: BL @tiny_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 ; CHECK: BL @tiny_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2
; CHECK: [[RES_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32) ; CHECK: [[RES_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32)
; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s96) ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s96)
; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say ; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say
; that composite types larger than 4 bytes should be passed through memory), ; that composite types larger than 4 bytes should be passed through memory),
; but it's what DAGISel does. We should fix it in the common code for both. ; but it's what DAGISel does. We should fix it in the common code for both.
; CHECK: %r0 = COPY [[R0]] ; CHECK: %r0 = COPY [[R0]]
; CHECK: %r1 = COPY [[R1]] ; CHECK: %r1 = COPY [[R1]]
; CHECK: %r2 = COPY [[R2]] ; CHECK: %r2 = COPY [[R2]]
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1, implicit %r2 ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1, implicit %r2
entry: entry:
%r = notail call arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32] %arr) %r = notail call arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32] %arr)
ret [3 x i32] %r ret [3 x i32] %r
} }
declare arm_aapcscc void @multiple_int_arrays_target([2 x i32], [2 x i32]) declare arm_aapcscc void @multiple_int_arrays_target([2 x i32], [2 x i32])
define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %arr1) { define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %arr1) {
; CHECK-LABEL: name: test_multiple_int_arrays ; CHECK-LABEL: name: test_multiple_int_arrays
; CHECK: liveins: %r0, %r1 ; CHECK: liveins: %r0, %r1
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %r2
; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %r3 ; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %r3
; CHECK: [[ARG_ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) ; CHECK: [[ARG_ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
; CHECK: [[ARG_ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R3]](s32) ; CHECK: [[ARG_ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R3]](s32)
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR0]](s64) ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR0]](s64)
; CHECK: [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR1]](s64) ; CHECK: [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR1]](s64)
; CHECK: %r0 = COPY [[R0]] ; CHECK: %r0 = COPY [[R0]]
; CHECK: %r1 = COPY [[R1]] ; CHECK: %r1 = COPY [[R1]]
; CHECK: %r2 = COPY [[R2]] ; CHECK: %r2 = COPY [[R2]]
; CHECK: %r3 = COPY [[R3]] ; CHECK: %r3 = COPY [[R3]]
; CHECK: BL @multiple_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3 ; CHECK: BL @multiple_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: BX_RET 14, _ ; CHECK: BX_RET 14, %noreg
entry: entry:
notail call arm_aapcscc void @multiple_int_arrays_target([2 x i32] %arr0, [2 x i32] %arr1) notail call arm_aapcscc void @multiple_int_arrays_target([2 x i32] %arr0, [2 x i32] %arr1)
ret void ret void
} }
declare arm_aapcscc void @large_int_arrays_target([20 x i32]) declare arm_aapcscc void @large_int_arrays_target([20 x i32])
define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) { define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) {
; CHECK-LABEL: name: test_large_int_arrays ; CHECK-LABEL: name: test_large_int_arrays
; CHECK: fixedStack: ; CHECK: fixedStack:
; The parameters live in separate stack locations, one for each element that ; The parameters live in separate stack locations, one for each element that
; doesn't fit in the registers. ; doesn't fit in the registers.
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4, ; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 60, size: 4 ; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 60, size: 4
; CHECK: liveins: %r0, %r1, %r2, %r3 ; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r2 ; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r2
; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY %r3 ; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY %r3
; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]] ; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]] ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[ARG_ARR:%[0-9]+]]:_(s640) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32) ; CHECK: [[ARG_ARR:%[0-9]+]]:_(s640) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
; CHECK: ADJCALLSTACKDOWN 64, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 64, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s640) ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s640)
; CHECK: %r0 = COPY [[R0]] ; CHECK: %r0 = COPY [[R0]]
; CHECK: %r1 = COPY [[R1]] ; CHECK: %r1 = COPY [[R1]]
; CHECK: %r2 = COPY [[R2]] ; CHECK: %r2 = COPY [[R2]]
; CHECK: %r3 = COPY [[R3]] ; CHECK: %r3 = COPY [[R3]]
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32) ; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4 ; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
; Match the second-to-last offset, so we can get the correct SP for the last element ; Match the second-to-last offset, so we can get the correct SP for the last element
; CHECK: G_CONSTANT i32 56 ; CHECK: G_CONSTANT i32 56
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 60 ; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 60
; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32) ; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4 ; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
; CHECK: BL @large_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3 ; CHECK: BL @large_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
; CHECK: ADJCALLSTACKUP 64, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 64, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: BX_RET 14, _ ; CHECK: BX_RET 14, %noreg
entry: entry:
notail call arm_aapcscc void @large_int_arrays_target([20 x i32] %arr) notail call arm_aapcscc void @large_int_arrays_target([20 x i32] %arr)
ret void ret void
} }
declare arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double]) declare arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double])
define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) { define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) {
; CHECK-LABEL: name: test_fp_arrays_aapcs ; CHECK-LABEL: name: test_fp_arrays_aapcs
; CHECK: fixedStack: ; CHECK: fixedStack:
; CHECK: id: [[ARR2_ID:[0-9]+]], type: default, offset: 0, size: 8, ; CHECK: id: [[ARR2_ID:[0-9]+]], type: default, offset: 0, size: 8,
; CHECK: liveins: %r0, %r1, %r2, %r3 ; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK: [[ARR0_0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[ARR0_0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK: [[ARR0_1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[ARR0_1:%[0-9]+]]:_(s32) = COPY %r1
; LITTLE: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32) ; LITTLE: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_0]](s32), [[ARR0_1]](s32)
; BIG: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32) ; BIG: [[ARR0:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR0_1]](s32), [[ARR0_0]](s32)
; CHECK: [[ARR1_0:%[0-9]+]]:_(s32) = COPY %r2 ; CHECK: [[ARR1_0:%[0-9]+]]:_(s32) = COPY %r2
; CHECK: [[ARR1_1:%[0-9]+]]:_(s32) = COPY %r3 ; CHECK: [[ARR1_1:%[0-9]+]]:_(s32) = COPY %r3
; LITTLE: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32) ; LITTLE: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_0]](s32), [[ARR1_1]](s32)
; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32) ; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32)
; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]] ; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]]
; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]] ; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]]
; CHECK: [[ARR_MERGED:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[ARR0]](s64), [[ARR1]](s64), [[ARR2]](s64) ; CHECK: [[ARR_MERGED:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[ARR0]](s64), [[ARR1]](s64), [[ARR2]](s64)
; CHECK: ADJCALLSTACKDOWN 8, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[ARR0:%[0-9]+]]:_(s64), [[ARR1:%[0-9]+]]:_(s64), [[ARR2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ARR_MERGED]](s192) ; CHECK: [[ARR0:%[0-9]+]]:_(s64), [[ARR1:%[0-9]+]]:_(s64), [[ARR2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[ARR_MERGED]](s192)
; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64) ; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64)
; LITTLE: %r0 = COPY [[ARR0_0]](s32) ; LITTLE: %r0 = COPY [[ARR0_0]](s32)
; LITTLE: %r1 = COPY [[ARR0_1]](s32) ; LITTLE: %r1 = COPY [[ARR0_1]](s32)
; BIG: %r0 = COPY [[ARR0_1]](s32) ; BIG: %r0 = COPY [[ARR0_1]](s32)
; BIG: %r1 = COPY [[ARR0_0]](s32) ; BIG: %r1 = COPY [[ARR0_0]](s32)
; CHECK: [[ARR1_0:%[0-9]+]]:_(s32), [[ARR1_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR1]](s64) ; CHECK: [[ARR1_0:%[0-9]+]]:_(s32), [[ARR1_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR1]](s64)
; LITTLE: %r2 = COPY [[ARR1_0]](s32) ; LITTLE: %r2 = COPY [[ARR1_0]](s32)
; LITTLE: %r3 = COPY [[ARR1_1]](s32) ; LITTLE: %r3 = COPY [[ARR1_1]](s32)
; BIG: %r2 = COPY [[ARR1_1]](s32) ; BIG: %r2 = COPY [[ARR1_1]](s32)
; BIG: %r3 = COPY [[ARR1_0]](s32) ; BIG: %r3 = COPY [[ARR1_0]](s32)
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[ARR2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[ARR2_OFFSET:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ARR2_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[ARR2_OFFSET]](s32) ; CHECK: [[ARR2_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[ARR2_OFFSET]](s32)
; CHECK: G_STORE [[ARR2]](s64), [[ARR2_ADDR]](p0){{.*}}store 8 ; CHECK: G_STORE [[ARR2]](s64), [[ARR2_ADDR]](p0){{.*}}store 8
; CHECK: BL @fp_arrays_aapcs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; CHECK: BL @fp_arrays_aapcs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK: [[R_MERGED:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) ; CHECK: [[R_MERGED:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
; CHECK: ADJCALLSTACKUP 8, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 8, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s64) ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s64)
; CHECK: %r0 = COPY [[R0]] ; CHECK: %r0 = COPY [[R0]]
; CHECK: %r1 = COPY [[R1]] ; CHECK: %r1 = COPY [[R1]]
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
entry: entry:
%r = notail call arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double] %arr) %r = notail call arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double] %arr)
ret [2 x float] %r ret [2 x float] %r
} }
declare arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double], [3 x float], [4 x double]) declare arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double], [3 x float], [4 x double])
define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 x float] %y, [4 x double] %z) { define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 x float] %y, [4 x double] %z) {
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; CHECK: [[Z1:%[0-9]+]]:_(s64) = G_LOAD [[Z1_FI]]{{.*}}load 8 ; CHECK: [[Z1:%[0-9]+]]:_(s64) = G_LOAD [[Z1_FI]]{{.*}}load 8
; CHECK: [[Z2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z2_ID]] ; CHECK: [[Z2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z2_ID]]
; CHECK: [[Z2:%[0-9]+]]:_(s64) = G_LOAD [[Z2_FI]]{{.*}}load 8 ; CHECK: [[Z2:%[0-9]+]]:_(s64) = G_LOAD [[Z2_FI]]{{.*}}load 8
; CHECK: [[Z3_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]] ; CHECK: [[Z3_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]]
; CHECK: [[Z3:%[0-9]+]]:_(s64) = G_LOAD [[Z3_FI]]{{.*}}load 8 ; CHECK: [[Z3:%[0-9]+]]:_(s64) = G_LOAD [[Z3_FI]]{{.*}}load 8
; CHECK: [[X_ARR:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[X0]](s64), [[X1]](s64), [[X2]](s64) ; CHECK: [[X_ARR:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[X0]](s64), [[X1]](s64), [[X2]](s64)
; CHECK: [[Y_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32), [[Y2]](s32) ; CHECK: [[Y_ARR:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32), [[Y2]](s32)
; CHECK: [[Z_ARR:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[Z0]](s64), [[Z1]](s64), [[Z2]](s64), [[Z3]](s64) ; CHECK: [[Z_ARR:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[Z0]](s64), [[Z1]](s64), [[Z2]](s64), [[Z3]](s64)
; CHECK: ADJCALLSTACKDOWN 32, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 32, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[X0:%[0-9]+]]:_(s64), [[X1:%[0-9]+]]:_(s64), [[X2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[X_ARR]](s192) ; CHECK: [[X0:%[0-9]+]]:_(s64), [[X1:%[0-9]+]]:_(s64), [[X2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[X_ARR]](s192)
; CHECK: [[Y0:%[0-9]+]]:_(s32), [[Y1:%[0-9]+]]:_(s32), [[Y2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[Y_ARR]](s96) ; CHECK: [[Y0:%[0-9]+]]:_(s32), [[Y1:%[0-9]+]]:_(s32), [[Y2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[Y_ARR]](s96)
; CHECK: [[Z0:%[0-9]+]]:_(s64), [[Z1:%[0-9]+]]:_(s64), [[Z2:%[0-9]+]]:_(s64), [[Z3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[Z_ARR]](s256) ; CHECK: [[Z0:%[0-9]+]]:_(s64), [[Z1:%[0-9]+]]:_(s64), [[Z2:%[0-9]+]]:_(s64), [[Z3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[Z_ARR]](s256)
; CHECK: %d0 = COPY [[X0]](s64) ; CHECK: %d0 = COPY [[X0]](s64)
; CHECK: %d1 = COPY [[X1]](s64) ; CHECK: %d1 = COPY [[X1]](s64)
; CHECK: %d2 = COPY [[X2]](s64) ; CHECK: %d2 = COPY [[X2]](s64)
; CHECK: %s6 = COPY [[Y0]](s32) ; CHECK: %s6 = COPY [[Y0]](s32)
; CHECK: %s7 = COPY [[Y1]](s32) ; CHECK: %s7 = COPY [[Y1]](s32)
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; CHECK: [[Z3_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z3_OFFSET]](s32) ; CHECK: [[Z3_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[Z3_OFFSET]](s32)
; CHECK: G_STORE [[Z3]](s64), [[Z3_ADDR]](p0){{.*}}store 8 ; CHECK: G_STORE [[Z3]](s64), [[Z3_ADDR]](p0){{.*}}store 8
; CHECK: BL @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit %d2, implicit %s6, implicit %s7, implicit %s8, implicit-def %s0, implicit-def %s1, implicit-def %s2, implicit-def %s3 ; CHECK: BL @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit %d2, implicit %s6, implicit %s7, implicit %s8, implicit-def %s0, implicit-def %s1, implicit-def %s2, implicit-def %s3
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %s0 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %s0
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %s1 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %s1
; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %s2 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY %s2
; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %s3 ; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY %s3
; CHECK: [[R_MERGED:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32) ; CHECK: [[R_MERGED:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32)
; CHECK: ADJCALLSTACKUP 32, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 32, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s128) ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R_MERGED]](s128)
; CHECK: %s0 = COPY [[R0]] ; CHECK: %s0 = COPY [[R0]]
; CHECK: %s1 = COPY [[R1]] ; CHECK: %s1 = COPY [[R1]]
; CHECK: %s2 = COPY [[R2]] ; CHECK: %s2 = COPY [[R2]]
; CHECK: %s3 = COPY [[R3]] ; CHECK: %s3 = COPY [[R3]]
; CHECK: BX_RET 14, _, implicit %s0, implicit %s1, implicit %s2, implicit %s3 ; CHECK: BX_RET 14, %noreg, implicit %s0, implicit %s1, implicit %s2, implicit %s3
entry: entry:
%r = notail call arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double] %x, [3 x float] %y, [4 x double] %z) %r = notail call arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double] %x, [3 x float] %y, [4 x double] %z)
ret [4 x float] %r ret [4 x float] %r
} }
declare arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr) declare arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) { define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) {
; CHECK-LABEL: name: test_tough_arrays ; CHECK-LABEL: name: test_tough_arrays
; CHECK: fixedStack: ; CHECK: fixedStack:
; The parameters live in separate stack locations, one for each element that ; The parameters live in separate stack locations, one for each element that
; doesn't fit in the registers. ; doesn't fit in the registers.
; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4, ; CHECK-DAG: id: [[FIRST_STACK_ID:[0-9]+]], type: default, offset: 0, size: 4,
; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 76, size: 4 ; CHECK-DAG: id: [[LAST_STACK_ID:[-0]+]], type: default, offset: 76, size: 4
; CHECK: liveins: %r0, %r1, %r2, %r3 ; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[R0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r2 ; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY %r2
; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY %r3 ; CHECK-DAG: [[R3:%[0-9]+]]:_(s32) = COPY %r3
; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]] ; CHECK: [[FIRST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]] ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]]
; CHECK: [[ARG_ARR:%[0-9]+]]:_(s768) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32) ; CHECK: [[ARG_ARR:%[0-9]+]]:_(s768) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32)
; CHECK: ADJCALLSTACKDOWN 80, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 80, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s768) ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32), [[R3:%[0-9]+]]:_(s32), [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARG_ARR]](s768)
; CHECK: %r0 = COPY [[R0]] ; CHECK: %r0 = COPY [[R0]]
; CHECK: %r1 = COPY [[R1]] ; CHECK: %r1 = COPY [[R1]]
; CHECK: %r2 = COPY [[R2]] ; CHECK: %r2 = COPY [[R2]]
; CHECK: %r3 = COPY [[R3]] ; CHECK: %r3 = COPY [[R3]]
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[OFF_FIRST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32) ; CHECK: [[FIRST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_FIRST_ELEMENT]](s32)
; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4 ; CHECK: G_STORE [[FIRST_STACK_ELEMENT]](s32), [[FIRST_STACK_ARG_ADDR]]{{.*}}store 4
; Match the second-to-last offset, so we can get the correct SP for the last element ; Match the second-to-last offset, so we can get the correct SP for the last element
; CHECK: G_CONSTANT i32 72 ; CHECK: G_CONSTANT i32 72
; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp ; CHECK: [[SP:%[0-9]+]]:_(p0) = COPY %sp
; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 76 ; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]]:_(s32) = G_CONSTANT i32 76
; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32) ; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4 ; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
; CHECK: BL @tough_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; CHECK: BL @tough_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK: [[RES_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) ; CHECK: [[RES_ARR:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
; CHECK: ADJCALLSTACKUP 80, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 80, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s64) ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RES_ARR]](s64)
; CHECK: %r0 = COPY [[R0]] ; CHECK: %r0 = COPY [[R0]]
; CHECK: %r1 = COPY [[R1]] ; CHECK: %r1 = COPY [[R1]]
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
entry: entry:
%r = notail call arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr) %r = notail call arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
ret [2 x i32*] %r ret [2 x i32*] %r
} }
declare arm_aapcscc {i32, i32} @structs_target({i32, i32}) declare arm_aapcscc {i32, i32} @structs_target({i32, i32})
define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) { define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) {
; CHECK-LABEL: test_structs ; CHECK-LABEL: test_structs
; CHECK: liveins: %r0, %r1 ; CHECK: liveins: %r0, %r1
; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) ; CHECK: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[X0:%[0-9]+]]:_(s32), [[X1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[X]](s64) ; CHECK: [[X0:%[0-9]+]]:_(s32), [[X1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[X]](s64)
; CHECK-DAG: %r0 = COPY [[X0]](s32) ; CHECK-DAG: %r0 = COPY [[X0]](s32)
; CHECK-DAG: %r1 = COPY [[X1]](s32) ; CHECK-DAG: %r1 = COPY [[X1]](s32)
; CHECK: BL @structs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 ; CHECK: BL @structs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY %r0
; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY %r1
; CHECK: [[R:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) ; CHECK: [[R:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32)
; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp ; CHECK: ADJCALLSTACKUP 0, 0, 14, %noreg, implicit-def %sp, implicit %sp
; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64) ; CHECK: [[R0:%[0-9]+]]:_(s32), [[R1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[R]](s64)
; CHECK: %r0 = COPY [[R0]](s32) ; CHECK: %r0 = COPY [[R0]](s32)
; CHECK: %r1 = COPY [[R1]](s32) ; CHECK: %r1 = COPY [[R1]](s32)
; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 ; CHECK: BX_RET 14, %noreg, implicit %r0, implicit %r1
%r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x) %r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x)
ret {i32, i32} %r ret {i32, i32} %r
} }

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_ADD %0, %1 %2(s32) = G_ADD %0, %1
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_sub_s32 name: test_sub_s32
# CHECK-LABEL: name: test_sub_s32 # CHECK-LABEL: name: test_sub_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_SUB %0, %1 %2(s32) = G_SUB %0, %1
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_mul_s32 name: test_mul_s32
# CHECK-LABEL: name: test_mul_s32 # CHECK-LABEL: name: test_mul_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_MUL %0, %1 %2(s32) = G_MUL %0, %1
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_sdiv_s32 name: test_sdiv_s32
# CHECK-LABEL: name: test_sdiv_s32 # CHECK-LABEL: name: test_sdiv_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_SDIV %0, %1 %2(s32) = G_SDIV %0, %1
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_udiv_s32 name: test_udiv_s32
# CHECK-LABEL: name: test_udiv_s32 # CHECK-LABEL: name: test_udiv_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_UDIV %0, %1 %2(s32) = G_UDIV %0, %1
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_and_s32 name: test_and_s32
# CHECK-LABEL: name: test_and_s32 # CHECK-LABEL: name: test_and_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_AND %0, %1 %2(s32) = G_AND %0, %1
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_or_s32 name: test_or_s32
# CHECK-LABEL: name: test_or_s32 # CHECK-LABEL: name: test_or_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_OR %0, %1 %2(s32) = G_OR %0, %1
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_xor_s32 name: test_xor_s32
# CHECK-LABEL: name: test_xor_s32 # CHECK-LABEL: name: test_xor_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_XOR %0, %1 %2(s32) = G_XOR %0, %1
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_lshr_s32 name: test_lshr_s32
# CHECK-LABEL: name: test_lshr_s32 # CHECK-LABEL: name: test_lshr_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_LSHR %0, %1 %2(s32) = G_LSHR %0, %1
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_ashr_s32 name: test_ashr_s32
# CHECK-LABEL: name: test_ashr_s32 # CHECK-LABEL: name: test_ashr_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_ASHR %0, %1 %2(s32) = G_ASHR %0, %1
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_shl_s32 name: test_shl_s32
# CHECK-LABEL: name: test_shl_s32 # CHECK-LABEL: name: test_shl_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = G_SHL %0, %1 %2(s32) = G_SHL %0, %1
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_loads name: test_loads
# CHECK-LABEL: name: test_loads # CHECK-LABEL: name: test_loads
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 19 Lines bb.0:
liveins: %r0 liveins: %r0
%0(p0) = COPY %r0 %0(p0) = COPY %r0
%6(s64) = G_LOAD %0 :: (load 8) %6(s64) = G_LOAD %0 :: (load 8)
%1(s32) = G_LOAD %0 :: (load 4) %1(s32) = G_LOAD %0 :: (load 4)
%2(s16) = G_LOAD %0 :: (load 2) %2(s16) = G_LOAD %0 :: (load 2)
%3(s8) = G_LOAD %0 :: (load 1) %3(s8) = G_LOAD %0 :: (load 1)
%4(s1) = G_LOAD %0 :: (load 1) %4(s1) = G_LOAD %0 :: (load 1)
%5(p0) = G_LOAD %0 :: (load 4) %5(p0) = G_LOAD %0 :: (load 4)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_stores name: test_stores
# CHECK-LABEL: name: test_stores # CHECK-LABEL: name: test_stores
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 25 Lines bb.0:
%3(s8) = G_TRUNC %1(s32) %3(s8) = G_TRUNC %1(s32)
G_STORE %3(s8), %0 :: (store 1) G_STORE %3(s8), %0 :: (store 1)
%4(s1) = G_TRUNC %1(s32) %4(s1) = G_TRUNC %1(s32)
G_STORE %4(s1), %0 :: (store 1) G_STORE %4(s1), %0 :: (store 1)
%5(p0) = COPY %r5 %5(p0) = COPY %r5
G_STORE %5(p0), %0 :: (store 4) G_STORE %5(p0), %0 :: (store 4)
%6(s64) = COPY %d6 %6(s64) = COPY %d6
G_STORE %6(s64), %0 :: (store 8) G_STORE %6(s64), %0 :: (store 8)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_stack name: test_stack
# CHECK-LABEL: name: test_stack # CHECK-LABEL: name: test_stack
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 16 Lines bb.0:
%0(p0) = G_FRAME_INDEX %fixed-stack.0 %0(p0) = G_FRAME_INDEX %fixed-stack.0
%1(s32) = G_LOAD %0(p0) :: (load 4 from %fixed-stack.0, align 0) %1(s32) = G_LOAD %0(p0) :: (load 4 from %fixed-stack.0, align 0)
%2(p0) = COPY %sp %2(p0) = COPY %sp
%3(s32) = G_CONSTANT i32 8 %3(s32) = G_CONSTANT i32 8
%4(p0) = G_GEP %2, %3(s32) %4(p0) = G_GEP %2, %3(s32)
G_STORE %1(s32), %4(p0) :: (store 4) G_STORE %1(s32), %4(p0) :: (store 4)
BX_RET 14, _ BX_RET 14, %noreg
... ...
--- ---
name: test_gep name: test_gep
# CHECK-LABEL: name: test_gep # CHECK-LABEL: name: test_gep
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(p0) = COPY %r0 %0(p0) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(p0) = G_GEP %0, %1(s32) %2(p0) = G_GEP %0, %1(s32)
%r0 = COPY %2(p0) %r0 = COPY %2(p0)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_constants name: test_constants
# CHECK-LABEL: name: test_constants # CHECK-LABEL: name: test_constants
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
# CHECK: registers: # CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' } # CHECK: - { id: 0, class: gprb, preferred-register: '' }
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
body: | body: |
bb.0: bb.0:
%0(s32) = G_CONSTANT 42 %0(s32) = G_CONSTANT 42
%r0 = COPY %0(s32) %r0 = COPY %0(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_globals name: test_globals
# CHECK-LABEL: name: test_globals # CHECK-LABEL: name: test_globals
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
# CHECK: registers: # CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' } # CHECK: - { id: 0, class: gprb, preferred-register: '' }
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @a_global %0(p0) = G_GLOBAL_VALUE @a_global
%r0 = COPY %0(p0) %r0 = COPY %0(p0)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_anyext_s8_32 name: test_anyext_s8_32
# CHECK-LABEL: name: test_anyext_s8_32 # CHECK-LABEL: name: test_anyext_s8_32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
# CHECK: registers: # CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' } # CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' } # CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' } # CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0 liveins: %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s8) = G_TRUNC %0(s32) %1(s8) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s8) %2(s32) = G_ANYEXT %1(s8)
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_anyext_s16_32 name: test_anyext_s16_32
# CHECK-LABEL: name: test_anyext_s16_32 # CHECK-LABEL: name: test_anyext_s16_32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
# CHECK: registers: # CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' } # CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' } # CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' } # CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0 liveins: %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s16) = G_TRUNC %0(s32) %1(s16) = G_TRUNC %0(s32)
%2(s32) = G_ANYEXT %1(s16) %2(s32) = G_ANYEXT %1(s16)
%r0 = COPY %2(s32) %r0 = COPY %2(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_trunc_s32_16 name: test_trunc_s32_16
# CHECK-LABEL: name: test_trunc_s32_16 # CHECK-LABEL: name: test_trunc_s32_16
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
# CHECK: registers: # CHECK: registers:
# CHECK: - { id: 0, class: gprb, preferred-register: '' } # CHECK: - { id: 0, class: gprb, preferred-register: '' }
# CHECK: - { id: 1, class: gprb, preferred-register: '' } # CHECK: - { id: 1, class: gprb, preferred-register: '' }
# CHECK: - { id: 2, class: gprb, preferred-register: '' } # CHECK: - { id: 2, class: gprb, preferred-register: '' }
registers: registers:
- { id: 0, class: _ } - { id: 0, class: _ }
- { id: 1, class: _ } - { id: 1, class: _ }
- { id: 2, class: _ } - { id: 2, class: _ }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%2(p0) = COPY %r1 %2(p0) = COPY %r1
%1(s16) = G_TRUNC %0(s32) %1(s16) = G_TRUNC %0(s32)
G_STORE %1(s16), %2 :: (store 2) G_STORE %1(s16), %2 :: (store 2)
BX_RET 14, _ BX_RET 14, %noreg
... ...
--- ---
name: test_icmp_eq_s32 name: test_icmp_eq_s32
# CHECK-LABEL: name: test_icmp_eq_s32 # CHECK-LABEL: name: test_icmp_eq_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
# CHECK: registers: # CHECK: registers:
Show All 11 Linesbody: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s1) = G_ICMP intpred(eq), %0(s32), %1 %2(s1) = G_ICMP intpred(eq), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_one_s32 name: test_fcmp_one_s32
# CHECK-LABEL: name: test_fcmp_one_s32 # CHECK-LABEL: name: test_fcmp_one_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 12 Linesbody: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s1) = G_FCMP floatpred(one), %0(s32), %1 %2(s1) = G_FCMP floatpred(one), %0(s32), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_fcmp_ugt_s64 name: test_fcmp_ugt_s64
# CHECK-LABEL: name: test_fcmp_ugt_s64 # CHECK-LABEL: name: test_fcmp_ugt_s64
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 12 Linesbody: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s1) = G_FCMP floatpred(ugt), %0(s64), %1 %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
%3(s32) = G_ZEXT %2(s1) %3(s32) = G_ZEXT %2(s1)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_select_s32 name: test_select_s32
# CHECK-LABEL: name: test_select_s32 # CHECK-LABEL: name: test_select_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 15 Lines bb.0:
liveins: %r0, %r1, %r2 liveins: %r0, %r1, %r2
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s32) = COPY %r2 %2(s32) = COPY %r2
%3(s1) = G_TRUNC %2(s32) %3(s1) = G_TRUNC %2(s32)
%4(s32) = G_SELECT %3(s1), %0, %1 %4(s32) = G_SELECT %3(s1), %0, %1
%r0 = COPY %4(s32) %r0 = COPY %4(s32)
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_br name: test_br
# CHECK-LABEL: name: test_br # CHECK-LABEL: name: test_br
legalized: true legalized: true
regBankSelected: false regBankSelected: false
# CHECK: regBankSelected: true # CHECK: regBankSelected: true
Show All 11 Lines bb.0:
liveins: %r0 liveins: %r0
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s1) = G_TRUNC %0(s32) %1(s1) = G_TRUNC %0(s32)
G_BRCOND %1(s1), %bb.1 G_BRCOND %1(s1), %bb.1
G_BR %bb.2 G_BR %bb.2
bb.1: bb.1:
BX_RET 14, _ BX_RET 14, %noreg
bb.2: bb.2:
BX_RET 14, _ BX_RET 14, %noreg
... ...
--- ---
name: test_fadd_s32 name: test_fadd_s32
# CHECK-LABEL: name: test_fadd_s32 # CHECK-LABEL: name: test_fadd_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s32) = G_FADD %0, %1 %2(s32) = G_FADD %0, %1
%s0 = COPY %2(s32) %s0 = COPY %2(s32)
BX_RET 14, _, implicit %s0 BX_RET 14, %noreg, implicit %s0
... ...
--- ---
name: test_fadd_s64 name: test_fadd_s64
# CHECK-LABEL: name: test_fadd_s64 # CHECK-LABEL: name: test_fadd_s64
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s64) = G_FADD %0, %1 %2(s64) = G_FADD %0, %1
%d0 = COPY %2(s64) %d0 = COPY %2(s64)
BX_RET 14, _, implicit %d0 BX_RET 14, %noreg, implicit %d0
... ...
--- ---
name: test_fsub_s32 name: test_fsub_s32
# CHECK-LABEL: name: test_fsub_s32 # CHECK-LABEL: name: test_fsub_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s32) = G_FSUB %0, %1 %2(s32) = G_FSUB %0, %1
%s0 = COPY %2(s32) %s0 = COPY %2(s32)
BX_RET 14, _, implicit %s0 BX_RET 14, %noreg, implicit %s0
... ...
--- ---
name: test_fsub_s64 name: test_fsub_s64
# CHECK-LABEL: name: test_fsub_s64 # CHECK-LABEL: name: test_fsub_s64
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s64) = G_FSUB %0, %1 %2(s64) = G_FSUB %0, %1
%d0 = COPY %2(s64) %d0 = COPY %2(s64)
BX_RET 14, _, implicit %d0 BX_RET 14, %noreg, implicit %d0
... ...
--- ---
name: test_fmul_s32 name: test_fmul_s32
# CHECK-LABEL: name: test_fmul_s32 # CHECK-LABEL: name: test_fmul_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s32) = G_FMUL %0, %1 %2(s32) = G_FMUL %0, %1
%s0 = COPY %2(s32) %s0 = COPY %2(s32)
BX_RET 14, _, implicit %s0 BX_RET 14, %noreg, implicit %s0
... ...
--- ---
name: test_fmul_s64 name: test_fmul_s64
# CHECK-LABEL: name: test_fmul_s64 # CHECK-LABEL: name: test_fmul_s64
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s64) = G_FMUL %0, %1 %2(s64) = G_FMUL %0, %1
%d0 = COPY %2(s64) %d0 = COPY %2(s64)
BX_RET 14, _, implicit %d0 BX_RET 14, %noreg, implicit %d0
... ...
--- ---
name: test_fdiv_s32 name: test_fdiv_s32
# CHECK-LABEL: name: test_fdiv_s32 # CHECK-LABEL: name: test_fdiv_s32
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %s0, %s1 liveins: %s0, %s1
%0(s32) = COPY %s0 %0(s32) = COPY %s0
%1(s32) = COPY %s1 %1(s32) = COPY %s1
%2(s32) = G_FDIV %0, %1 %2(s32) = G_FDIV %0, %1
%s0 = COPY %2(s32) %s0 = COPY %2(s32)
BX_RET 14, _, implicit %s0 BX_RET 14, %noreg, implicit %s0
... ...
--- ---
name: test_fdiv_s64 name: test_fdiv_s64
# CHECK-LABEL: name: test_fdiv_s64 # CHECK-LABEL: name: test_fdiv_s64
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 9 Lines
body: | body: |
bb.0: bb.0:
liveins: %d0, %d1 liveins: %d0, %d1
%0(s64) = COPY %d0 %0(s64) = COPY %d0
%1(s64) = COPY %d1 %1(s64) = COPY %d1
%2(s64) = G_FDIV %0, %1 %2(s64) = G_FDIV %0, %1
%d0 = COPY %2(s64) %d0 = COPY %2(s64)
BX_RET 14, _, implicit %d0 BX_RET 14, %noreg, implicit %d0
... ...
--- ---
name: test_soft_fp_s64 name: test_soft_fp_s64
# CHECK-LABEL: name: test_soft_fp_s64 # CHECK-LABEL: name: test_soft_fp_s64
legalized: true legalized: true
regBankSelected: false regBankSelected: false
selected: false selected: false
Show All 15 Lines bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
%0(s32) = COPY %r0 %0(s32) = COPY %r0
%1(s32) = COPY %r1 %1(s32) = COPY %r1
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32) %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
%3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64) %3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
%r0 = COPY %3(s32) %r0 = COPY %3(s32)
%r1 = COPY %4(s32) %r1 = COPY %4(s32)
BX_RET 14, _, implicit %r0, implicit %r1 BX_RET 14, %noreg, implicit %r0, implicit %r1
... ...

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir

Show All 27 Lines
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global %0(p0) = G_GLOBAL_VALUE @internal_global
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel {{.*}}@internal_global ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel {{.*}}@internal_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_global
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_global ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_global) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_global)
%r0 = COPY %1(s32) %r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[V]] ; CHECK: %r0 = COPY [[V]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_external_global name: test_external_global
# CHECK-LABEL: name: test_external_global # CHECK-LABEL: name: test_external_global
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global %0(p0) = G_GLOBAL_VALUE @external_global
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel_ldr {{.*}} @external_global :: (load 4 from got) ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel_ldr {{.*}} @external_global :: (load 4 from got)
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr {{.*}}@external_global :: (load 4 from got) ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr {{.*}}@external_global :: (load 4 from got)
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(<unknown>) @external_global :: (load 4 from got) ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(<unknown>) @external_global :: (load 4 from got)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_global) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_global)
%r0 = COPY %1(s32) %r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[V]] ; CHECK: %r0 = COPY [[V]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_internal_constant name: test_internal_constant
# CHECK-LABEL: name: test_internal_constant # CHECK-LABEL: name: test_internal_constant
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_constant %0(p0) = G_GLOBAL_VALUE @internal_constant
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel {{.*}}@internal_constant ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel {{.*}}@internal_constant
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_constant ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_constant
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_constant ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel {{.*}}@internal_constant
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_constant) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_constant)
%r0 = COPY %1(s32) %r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[V]] ; CHECK: %r0 = COPY [[V]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_external_constant name: test_external_constant
# CHECK-LABEL: name: test_external_constant # CHECK-LABEL: name: test_external_constant
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_constant %0(p0) = G_GLOBAL_VALUE @external_constant
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel_ldr {{.*}} @external_constant :: (load 4 from got) ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel_ldr {{.*}} @external_constant :: (load 4 from got)
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr {{.*}}@external_constant :: (load 4 from got) ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr {{.*}}@external_constant :: (load 4 from got)
; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(<unknown>) @external_constant :: (load 4 from got) ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(<unknown>) @external_constant :: (load 4 from got)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_constant) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_constant)
%r0 = COPY %1(s32) %r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[V]] ; CHECK: %r0 = COPY [[V]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir

Show All 31 Lines
# RW-DEFAULT-NOMOVT: value: 'i32* @internal_global' # RW-DEFAULT-NOMOVT: value: 'i32* @internal_global'
# RWPI-NOMOVT: constants: # RWPI-NOMOVT: constants:
# RWPI-NOMOVT: id: 0 # RWPI-NOMOVT: id: 0
# RWPI-NOMOVT: value: 'internal_global(SBREL)' # RWPI-NOMOVT: value: 'internal_global(SBREL)'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global %0(p0) = G_GLOBAL_VALUE @internal_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @internal_global ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @internal_global
; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, _, _ ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, %noreg, %noreg
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_global) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_global)
%r0 = COPY %1(s32) %r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[V]] ; CHECK: %r0 = COPY [[V]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_external_global name: test_external_global
# CHECK-LABEL: name: test_external_global # CHECK-LABEL: name: test_external_global
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RW-DEFAULT-NOMOVT: constants: # RW-DEFAULT-NOMOVT: constants:
# RW-DEFAULT-NOMOVT: id: 0 # RW-DEFAULT-NOMOVT: id: 0
# RW-DEFAULT-NOMOVT: value: 'i32* @external_global' # RW-DEFAULT-NOMOVT: value: 'i32* @external_global'
# RWPI-NOMOVT: constants: # RWPI-NOMOVT: constants:
# RWPI-NOMOVT: id: 0 # RWPI-NOMOVT: id: 0
# RWPI-NOMOVT: value: 'external_global(SBREL)' # RWPI-NOMOVT: value: 'external_global(SBREL)'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global %0(p0) = G_GLOBAL_VALUE @external_global
; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @external_global ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm {{.*}} @external_global
; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, _, _ ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr %r9, [[OFF]], 14, %noreg, %noreg
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_global) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_global)
%r0 = COPY %1(s32) %r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[V]] ; CHECK: %r0 = COPY [[V]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_internal_constant name: test_internal_constant
# CHECK-LABEL: name: test_internal_constant # CHECK-LABEL: name: test_internal_constant
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RO-DEFAULT-NOMOVT: constants: # RO-DEFAULT-NOMOVT: constants:
# RO-DEFAULT-NOMOVT: id: 0 # RO-DEFAULT-NOMOVT: id: 0
# RO-DEFAULT-NOMOVT: value: 'i32* @internal_constant' # RO-DEFAULT-NOMOVT: value: 'i32* @internal_constant'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_constant %0(p0) = G_GLOBAL_VALUE @internal_constant
; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @internal_constant ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @internal_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant
; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @internal_constant) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @internal_constant)
%r0 = COPY %1(s32) %r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[V]] ; CHECK: %r0 = COPY [[V]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_external_constant name: test_external_constant
# CHECK-LABEL: name: test_external_constant # CHECK-LABEL: name: test_external_constant
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# RO-DEFAULT-NOMOVT: constants: # RO-DEFAULT-NOMOVT: constants:
# RO-DEFAULT-NOMOVT: id: 0 # RO-DEFAULT-NOMOVT: id: 0
# RO-DEFAULT-NOMOVT: value: 'i32* @external_constant' # RO-DEFAULT-NOMOVT: value: 'i32* @external_constant'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_constant %0(p0) = G_GLOBAL_VALUE @external_constant
; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @external_constant ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @external_constant
; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @external_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @external_constant
; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant
; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ :: (load 4 from @external_constant) ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg :: (load 4 from @external_constant)
%r0 = COPY %1(s32) %r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[V]] ; CHECK: %r0 = COPY [[V]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir

Show All 20 Linesregisters:
- { id: 1, class: gprb } - { id: 1, class: gprb }
# ELF-NOMOVT: constants: # ELF-NOMOVT: constants:
# ELF-NOMOVT: id: 0 # ELF-NOMOVT: id: 0
# ELF-NOMOVT: value: 'i32* @internal_global' # ELF-NOMOVT: value: 'i32* @internal_global'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @internal_global %0(p0) = G_GLOBAL_VALUE @internal_global
; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @internal_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @internal_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg
%r0 = COPY %1(s32) %r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[V]] ; CHECK: %r0 = COPY [[V]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test_external_global name: test_external_global
# CHECK-LABEL: name: test_external_global # CHECK-LABEL: name: test_external_global
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
# CHECK: selected: true # CHECK: selected: true
registers: registers:
- { id: 0, class: gprb } - { id: 0, class: gprb }
- { id: 1, class: gprb } - { id: 1, class: gprb }
# ELF-NOMOVT: constants: # ELF-NOMOVT: constants:
# ELF-NOMOVT: id: 0 # ELF-NOMOVT: id: 0
# ELF-NOMOVT: value: 'i32* @external_global' # ELF-NOMOVT: value: 'i32* @external_global'
body: | body: |
bb.0: bb.0:
%0(p0) = G_GLOBAL_VALUE @external_global %0(p0) = G_GLOBAL_VALUE @external_global
; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool) ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, %noreg :: (load 4 from constant-pool)
; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global
; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @external_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @external_global
%1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global)
; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, _ ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, %noreg
%r0 = COPY %1(s32) %r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[V]] ; CHECK: %r0 = COPY [[V]]
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/a15-SD-dep.ll

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Linessw.bb1: ; preds = %entry, %sw.bb
%sum.0 = phi <4 x float> [ %0, %entry ], [ %1, %sw.bb ] %sum.0 = phi <4 x float> [ %0, %entry ], [ %1, %sw.bb ]
%2 = extractelement <4 x float> %sum.0, i32 0 %2 = extractelement <4 x float> %sum.0, i32 0
%conv = fptoui float %2 to i8 %conv = fptoui float %2 to i8
store i8 %conv, i8* %out, align 1 store i8 %conv, i8* %out, align 1
br label %sw.epilog br label %sw.epilog
sw.epilog: ; preds = %entry, %sw.bb1 sw.epilog: ; preds = %entry, %sw.bb1
ret void ret void
} }
No newline at end of file

llvm/trunk/test/CodeGen/ARM/cmp1-peephole-thumb.mir

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 LinesframeInfo:
maxAlignment: 0 maxAlignment: 0
adjustsStack: false adjustsStack: false
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
# CHECK: tMOVi8 1, 14, _ # CHECK: tMOVi8 1, 14, %noreg
# CHECK: tMOVi8 0, 14, _ # CHECK: tMOVi8 0, 14, %noreg
# CHECK: tMUL %1, %0, 14, _ # CHECK: tMUL %1, %0, 14, %noreg
# CHECK-NOT: tCMPi8 # CHECK-NOT: tCMPi8
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0, %r1 liveins: %r0, %r1
%1 = COPY %r1 %1 = COPY %r1
%0 = COPY %r0 %0 = COPY %r0
%2, %cpsr = tMUL %1, %0, 14, _ %2, %cpsr = tMUL %1, %0, 14, %noreg
%3, %cpsr = tMOVi8 1, 14, _ %3, %cpsr = tMOVi8 1, 14, %noreg
%4, %cpsr = tMOVi8 0, 14, _ %4, %cpsr = tMOVi8 0, 14, %noreg
tCMPi8 killed %2, 0, 14, _, implicit-def %cpsr tCMPi8 killed %2, 0, 14, %noreg, implicit-def %cpsr
tBcc %bb.2.entry, 0, %cpsr tBcc %bb.2.entry, 0, %cpsr
bb.1.entry: bb.1.entry:
bb.2.entry: bb.2.entry:
%5 = PHI %4, %bb.1.entry, %3, %bb.0.entry %5 = PHI %4, %bb.1.entry, %3, %bb.0.entry
%r0 = COPY %5 %r0 = COPY %5
tBX_RET 14, _, implicit %r0 tBX_RET 14, %noreg, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/cmp2-peephole-thumb.mir

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
# CHECK-NEXT: tSTRspi # CHECK-NEXT: tSTRspi
# CHECK-NEXT: tCMPi8 # CHECK-NEXT: tCMPi8
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0, %r1 liveins: %r0, %r1
%1 = COPY %r1 %1 = COPY %r1
%0 = COPY %r0 %0 = COPY %r0
%2, %cpsr = tMUL %0, %1, 14, _ %2, %cpsr = tMUL %0, %1, 14, %noreg
tSTRspi %2, %stack.1.mul, 0, 14, _ :: (store 4 into %ir.mul) tSTRspi %2, %stack.1.mul, 0, 14, %noreg :: (store 4 into %ir.mul)
tCMPi8 %2, 0, 14, _, implicit-def %cpsr tCMPi8 %2, 0, 14, %noreg, implicit-def %cpsr
tBcc %bb.2.if.end, 12, %cpsr tBcc %bb.2.if.end, 12, %cpsr
tB %bb.1.if.then, 14, _ tB %bb.1.if.then, 14, %noreg
bb.1.if.then: bb.1.if.then:
%4, %cpsr = tMOVi8 42, 14, _ %4, %cpsr = tMOVi8 42, 14, %noreg
tSTRspi killed %4, %stack.0.retval, 0, 14, _ :: (store 4 into %ir.retval) tSTRspi killed %4, %stack.0.retval, 0, 14, %noreg :: (store 4 into %ir.retval)
tB %bb.3.return, 14, _ tB %bb.3.return, 14, %noreg
bb.2.if.end: bb.2.if.end:
%3, %cpsr = tMOVi8 1, 14, _ %3, %cpsr = tMOVi8 1, 14, %noreg
tSTRspi killed %3, %stack.0.retval, 0, 14, _ :: (store 4 into %ir.retval) tSTRspi killed %3, %stack.0.retval, 0, 14, %noreg :: (store 4 into %ir.retval)
bb.3.return: bb.3.return:
%5 = tLDRspi %stack.0.retval, 0, 14, _ :: (dereferenceable load 4 from %ir.retval) %5 = tLDRspi %stack.0.retval, 0, 14, %noreg :: (dereferenceable load 4 from %ir.retval)
%r0 = COPY %5 %r0 = COPY %5
tBX_RET 14, _, implicit %r0 tBX_RET 14, %noreg, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/constant-islands-cfg.mir

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
# CHECK: successors: %[[DEST2:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}} # CHECK: successors: %[[DEST2:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}}
# CHECK: tB %[[DEST2]] # CHECK: tB %[[DEST2]]
# CHECK: [[DEST1]]: # CHECK: [[DEST1]]:
# CHECK: [[DEST2]]: # CHECK: [[DEST2]]:
body: | body: |
bb.0: bb.0:
liveins: %r0 liveins: %r0
tCMPi8 killed %r0, 0, 14, _, implicit-def %cpsr tCMPi8 killed %r0, 0, 14, %noreg, implicit-def %cpsr
tBcc %bb.2, 1, killed %cpsr tBcc %bb.2, 1, killed %cpsr
tB %bb.3, 14, _ tB %bb.3, 14, %noreg
bb.1: bb.1:
dead %r0 = SPACE 256, undef %r0 dead %r0 = SPACE 256, undef %r0
bb.2: bb.2:
tPOP_RET 14, _, def %pc tPOP_RET 14, %noreg, def %pc
bb.3: bb.3:
tPOP_RET 14, _, def %pc tPOP_RET 14, %noreg, def %pc
... ...

llvm/trunk/test/CodeGen/ARM/dbg-range-extension.mir

Show All 17 Lines
# } # }
# CHECK: [[VAR_A:![0-9]+]] = !DILocalVariable(name: "a", # CHECK: [[VAR_A:![0-9]+]] = !DILocalVariable(name: "a",
# CHECK: [[VAR_B:![0-9]+]] = !DILocalVariable(name: "b", # CHECK: [[VAR_B:![0-9]+]] = !DILocalVariable(name: "b",
# CHECK: [[VAR_C:![0-9]+]] = !DILocalVariable(name: "c", # CHECK: [[VAR_C:![0-9]+]] = !DILocalVariable(name: "c",
# CHECK: [[VAR_I:![0-9]+]] = !DILocalVariable(name: "i", # CHECK: [[VAR_I:![0-9]+]] = !DILocalVariable(name: "i",
# CHECK: bb.0.entry # CHECK: bb.0.entry
# CHECK: DBG_VALUE debug-use %r0, debug-use _, [[VAR_A]] # CHECK: DBG_VALUE debug-use %r0, debug-use %noreg, [[VAR_A]]
# CHECK: DBG_VALUE debug-use [[REG_A:%r[0-9]+]], debug-use _, [[VAR_A]] # CHECK: DBG_VALUE debug-use [[REG_A:%r[0-9]+]], debug-use %noreg, [[VAR_A]]
# CHECK: DBG_VALUE debug-use [[REG_B:%r[0-9]+]], debug-use _, [[VAR_B]] # CHECK: DBG_VALUE debug-use [[REG_B:%r[0-9]+]], debug-use %noreg, [[VAR_B]]
# CHECK: bb.1.if.then # CHECK: bb.1.if.then
# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] # CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] # CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
# CHECK: DBG_VALUE debug-use [[REG_C:%r[0-9]+]], debug-use _, [[VAR_C]] # CHECK: DBG_VALUE debug-use [[REG_C:%r[0-9]+]], debug-use %noreg, [[VAR_C]]
# CHECK: DBG_VALUE 1, 0, [[VAR_I]] # CHECK: DBG_VALUE 1, 0, [[VAR_I]]
# CHECK: bb.2.for.body # CHECK: bb.2.for.body
# CHECK: DBG_VALUE debug-use [[REG_I:%r[0-9]+]], debug-use _, [[VAR_I]] # CHECK: DBG_VALUE debug-use [[REG_I:%r[0-9]+]], debug-use %noreg, [[VAR_I]]
# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]] # CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]]
# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] # CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] # CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use _, [[VAR_I]] # CHECK: DBG_VALUE debug-use [[REG_I]], debug-use %noreg, [[VAR_I]]
# CHECK: bb.3.for.cond # CHECK: bb.3.for.cond
# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]] # CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]]
# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] # CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] # CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
# CHECK: DBG_VALUE debug-use [[REG_I]], debug-use _, [[VAR_I]] # CHECK: DBG_VALUE debug-use [[REG_I]], debug-use %noreg, [[VAR_I]]
# CHECK: bb.4.for.cond.cleanup # CHECK: bb.4.for.cond.cleanup
# CHECK: DBG_VALUE debug-use [[REG_C]], debug-use _, [[VAR_C]] # CHECK: DBG_VALUE debug-use [[REG_C]], debug-use %noreg, [[VAR_C]]
# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] # CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] # CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
# CHECK: bb.5.if.end # CHECK: bb.5.if.end
# CHECK: DBG_VALUE debug-use [[REG_B]], debug-use _, [[VAR_B]] # CHECK: DBG_VALUE debug-use [[REG_B]], debug-use %noreg, [[VAR_B]]
# CHECK: DBG_VALUE debug-use [[REG_A]], debug-use _, [[VAR_A]] # CHECK: DBG_VALUE debug-use [[REG_A]], debug-use %noreg, [[VAR_A]]
--- | --- |
; ModuleID = '/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll' ; ModuleID = '/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll'
source_filename = "/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll" source_filename = "/data/kwalker/work/OpenSource-llvm/llvm/test/CodeGen/ARM/dbg-range-extension.ll"
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "arm---eabi" target triple = "arm---eabi"
; Function Attrs: minsize nounwind optsize ; Function Attrs: minsize nounwind optsize
define void @func(i32 %a) local_unnamed_addr #0 !dbg !8 { define void @func(i32 %a) local_unnamed_addr #0 !dbg !8 {
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Linesstack:
- { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '%r7' } - { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4, callee-saved-register: '%r7' }
- { id: 3, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '%r6' } - { id: 3, type: spill-slot, offset: -16, size: 4, alignment: 4, callee-saved-register: '%r6' }
- { id: 4, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '%r5' } - { id: 4, type: spill-slot, offset: -20, size: 4, alignment: 4, callee-saved-register: '%r5' }
- { id: 5, type: spill-slot, offset: -24, size: 4, alignment: 4, callee-saved-register: '%r4' } - { id: 5, type: spill-slot, offset: -24, size: 4, alignment: 4, callee-saved-register: '%r4' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0, %r4, %r5, %r6, %r7, %r11, %lr liveins: %r0, %r4, %r5, %r6, %r7, %r11, %lr
%sp = frame-setup STMDB_UPD %sp, 14, _, killed %r4, killed %r5, killed %r6, killed %r7, killed %r11, killed %lr %sp = frame-setup STMDB_UPD %sp, 14, %noreg, killed %r4, killed %r5, killed %r6, killed %r7, killed %r11, killed %lr
frame-setup CFI_INSTRUCTION def_cfa_offset 24 frame-setup CFI_INSTRUCTION def_cfa_offset 24
frame-setup CFI_INSTRUCTION offset %lr, -4 frame-setup CFI_INSTRUCTION offset %lr, -4
frame-setup CFI_INSTRUCTION offset %r11, -8 frame-setup CFI_INSTRUCTION offset %r11, -8
frame-setup CFI_INSTRUCTION offset %r7, -12 frame-setup CFI_INSTRUCTION offset %r7, -12
frame-setup CFI_INSTRUCTION offset %r6, -16 frame-setup CFI_INSTRUCTION offset %r6, -16
frame-setup CFI_INSTRUCTION offset %r5, -20 frame-setup CFI_INSTRUCTION offset %r5, -20
frame-setup CFI_INSTRUCTION offset %r4, -24 frame-setup CFI_INSTRUCTION offset %r4, -24
DBG_VALUE debug-use %r0, debug-use _, !13, !20, debug-location !21 DBG_VALUE debug-use %r0, debug-use %noreg, !13, !20, debug-location !21
%r4 = MOVr killed %r0, 14, _, _ %r4 = MOVr killed %r0, 14, %noreg, %noreg
DBG_VALUE debug-use %r4, debug-use _, !13, !20, debug-location !21 DBG_VALUE debug-use %r4, debug-use %noreg, !13, !20, debug-location !21
%r0 = MOVi 10, 14, _, _, debug-location !22 %r0 = MOVi 10, 14, %noreg, _, debug-location !22
%r1 = MOVi 11, 14, _, _, debug-location !22 %r1 = MOVi 11, 14, %noreg, _, debug-location !22
BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !22 BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !22
%r5 = MOVr killed %r0, 14, _, _, debug-location !22 %r5 = MOVr killed %r0, 14, %noreg, _, debug-location !22
DBG_VALUE debug-use %r5, debug-use _, !14, !20, debug-location !23 DBG_VALUE debug-use %r5, debug-use %noreg, !14, !20, debug-location !23
CMPri %r4, 0, 14, _, implicit-def %cpsr, debug-location !25 CMPri %r4, 0, 14, %noreg, implicit-def %cpsr, debug-location !25
Bcc %bb.5.if.end, 0, killed %cpsr Bcc %bb.5.if.end, 0, killed %cpsr
bb.1.if.then: bb.1.if.then:
liveins: %r4, %r5 liveins: %r4, %r5
%r0 = MOVi 12, 14, _, _, debug-location !26 %r0 = MOVi 12, 14, %noreg, _, debug-location !26
%r1 = MOVi 13, 14, _, _, debug-location !26 %r1 = MOVi 13, 14, %noreg, _, debug-location !26
BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !26 BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def %r0, debug-location !26
%r6 = MOVr killed %r0, 14, _, _, debug-location !26 %r6 = MOVr killed %r0, 14, %noreg, _, debug-location !26
DBG_VALUE debug-use %r6, debug-use _, !15, !20, debug-location !27 DBG_VALUE debug-use %r6, debug-use %noreg, !15, !20, debug-location !27
%r7 = MOVi 1, 14, _, _ %r7 = MOVi 1, 14, %noreg, %noreg
DBG_VALUE 1, 0, !18, !20, debug-location !28 DBG_VALUE 1, 0, !18, !20, debug-location !28
B %bb.3.for.cond B %bb.3.for.cond
bb.2.for.body: bb.2.for.body:
liveins: %r4, %r5, %r6, %r7 liveins: %r4, %r5, %r6, %r7
%r1 = ADDrr %r5, %r7, 14, _, _, debug-location !36 %r1 = ADDrr %r5, %r7, 14, %noreg, _, debug-location !36
%r0 = MOVr %r7, 14, _, _, debug-location !36 %r0 = MOVr %r7, 14, %noreg, _, debug-location !36
BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !36 BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !36
%r7 = ADDri killed %r7, 1, 14, _, _, debug-location !38 %r7 = ADDri killed %r7, 1, 14, %noreg, _, debug-location !38
DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28 DBG_VALUE debug-use %r7, debug-use %noreg, !18, !20, debug-location !28
bb.3.for.cond: bb.3.for.cond:
liveins: %r4, %r5, %r6, %r7 liveins: %r4, %r5, %r6, %r7
DBG_VALUE debug-use %r7, debug-use _, !18, !20, debug-location !28 DBG_VALUE debug-use %r7, debug-use %noreg, !18, !20, debug-location !28
CMPrr %r7, %r4, 14, _, implicit-def %cpsr, debug-location !33 CMPrr %r7, %r4, 14, %noreg, implicit-def %cpsr, debug-location !33
Bcc %bb.2.for.body, 11, killed %cpsr, debug-location !33 Bcc %bb.2.for.body, 11, killed %cpsr, debug-location !33
bb.4.for.cond.cleanup: bb.4.for.cond.cleanup:
liveins: %r4, %r5, %r6 liveins: %r4, %r5, %r6
%r0 = MOVr %r5, 14, _, _, debug-location !34 %r0 = MOVr %r5, 14, %noreg, _, debug-location !34
%r1 = MOVr killed %r6, 14, _, _, debug-location !34 %r1 = MOVr killed %r6, 14, %noreg, _, debug-location !34
BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !34 BL @func2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit killed %r0, implicit killed %r1, implicit-def %sp, implicit-def dead %r0, debug-location !34
bb.5.if.end: bb.5.if.end:
liveins: %r4, %r5 liveins: %r4, %r5
%r0 = MOVr killed %r5, 14, _, _, debug-location !43 %r0 = MOVr killed %r5, 14, %noreg, _, debug-location !43
%r1 = MOVr killed %r4, 14, _, _, debug-location !43 %r1 = MOVr killed %r4, 14, %noreg, _, debug-location !43
%sp = LDMIA_UPD %sp, 14, _, def %r4, def %r5, def %r6, def %r7, def %r11, def %lr, debug-location !43 %sp = LDMIA_UPD %sp, 14, %noreg, def %r4, def %r5, def %r6, def %r7, def %r11, def %lr, debug-location !43
TAILJMPd @func2, implicit %sp, implicit %sp, implicit killed %r0, implicit killed %r1, debug-location !43 TAILJMPd @func2, implicit %sp, implicit %sp, implicit killed %r0, implicit killed %r1, debug-location !43
... ...

llvm/trunk/test/CodeGen/ARM/expand-pseudos.mir

Show All 19 Lines
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%r0', virtual-reg: '' } - { reg: '%r0', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0 liveins: %r0
%r1 = MOVi 2, 14, _, _ %r1 = MOVi 2, 14, %noreg, %noreg
CMPri killed %r0, 0, 14, _, implicit-def %cpsr CMPri killed %r0, 0, 14, %noreg, implicit-def %cpsr
%r1 = MOVCCi16 killed %r1, 500, 0, killed %cpsr %r1 = MOVCCi16 killed %r1, 500, 0, killed %cpsr
%r0 = MOVr killed %r1, 14, _, _ %r0 = MOVr killed %r1, 14, %noreg, %noreg
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test2 name: test2
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%r0', virtual-reg: '' } - { reg: '%r0', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0 liveins: %r0
%r1 = MOVi 2, 14, _, _ %r1 = MOVi 2, 14, %noreg, %noreg
CMPri killed %r0, 0, 14, _, implicit-def %cpsr CMPri killed %r0, 0, 14, %noreg, implicit-def %cpsr
%r1 = MOVCCi32imm killed %r1, 500500500, 0, killed %cpsr %r1 = MOVCCi32imm killed %r1, 500500500, 0, killed %cpsr
%r0 = MOVr killed %r1, 14, _, _ %r0 = MOVr killed %r1, 14, %noreg, %noreg
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
--- ---
name: test3 name: test3
alignment: 2 alignment: 2
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%r0', virtual-reg: '' } - { reg: '%r0', virtual-reg: '' }
- { reg: '%r1', virtual-reg: '' } - { reg: '%r1', virtual-reg: '' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0, %r1 liveins: %r0, %r1
CMPri %r1, 500, 14, _, implicit-def %cpsr CMPri %r1, 500, 14, %noreg, implicit-def %cpsr
%r0 = MOVCCr killed %r0, killed %r1, 12, killed %cpsr %r0 = MOVCCr killed %r0, killed %r1, 12, killed %cpsr
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...
# CHECK-LABEL: name: test1 # CHECK-LABEL: name: test1
# CHECK: %r1 = MOVi16 500, 0, killed %cpsr, implicit killed %r1 # CHECK: %r1 = MOVi16 500, 0, killed %cpsr, implicit killed %r1
# CHECK-LABEL: name: test2 # CHECK-LABEL: name: test2
# CHECK: %r1 = MOVi16 2068, 0, %cpsr, implicit killed %r1 # CHECK: %r1 = MOVi16 2068, 0, %cpsr, implicit killed %r1
# CHECK: %r1 = MOVTi16 %r1, 7637, 0, %cpsr # CHECK: %r1 = MOVTi16 %r1, 7637, 0, %cpsr
# CHECK-LABEL: name: test3 # CHECK-LABEL: name: test3
# CHECK: %r0 = MOVr killed %r1, 12, killed %cpsr, _, implicit killed %r0 # CHECK: %r0 = MOVr killed %r1, 12, killed %cpsr, %noreg, implicit killed %r0

llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir

# RUN: llc -o - %s -mtriple=thumbv7-- -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s # RUN: llc -o - %s -mtriple=thumbv7-- -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s
--- ---
# This should trigger an emergency spill in the register scavenger because the # This should trigger an emergency spill in the register scavenger because the
# frame offset into the large argument is too large. # frame offset into the large argument is too large.
# CHECK-LABEL: name: func0 # CHECK-LABEL: name: func0
# CHECK: t2STRi12 killed [[SPILLED:%r[0-9]+]], %sp, 0, 14, _ :: (store 4 into %stack.0) # CHECK: t2STRi12 killed [[SPILLED:%r[0-9]+]], %sp, 0, 14, %noreg :: (store 4 into %stack.0)
# CHECK: [[SPILLED]] = t2ADDri killed %sp, 4096, 14, _, _ # CHECK: [[SPILLED]] = t2ADDri killed %sp, 4096, 14, %noreg, %noreg
# CHECK: %sp = t2LDRi12 killed [[SPILLED]], 40, 14, _ :: (load 4) # CHECK: %sp = t2LDRi12 killed [[SPILLED]], 40, 14, %noreg :: (load 4)
# CHECK: [[SPILLED]] = t2LDRi12 %sp, 0, 14, _ :: (load 4 from %stack.0) # CHECK: [[SPILLED]] = t2LDRi12 %sp, 0, 14, %noreg :: (load 4 from %stack.0)
name: func0 name: func0
tracksRegLiveness: true tracksRegLiveness: true
fixedStack: fixedStack:
- { id: 0, offset: 4084, size: 4, alignment: 4, isImmutable: true, - { id: 0, offset: 4084, size: 4, alignment: 4, isImmutable: true,
isAliased: false } isAliased: false }
- { id: 1, offset: -12, size: 4096, alignment: 4, isImmutable: false, - { id: 1, offset: -12, size: 4096, alignment: 4, isImmutable: false,
isAliased: false } isAliased: false }
body: | body: |
bb.0: bb.0:
%r0 = IMPLICIT_DEF %r0 = IMPLICIT_DEF
%r1 = IMPLICIT_DEF %r1 = IMPLICIT_DEF
%r2 = IMPLICIT_DEF %r2 = IMPLICIT_DEF
%r3 = IMPLICIT_DEF %r3 = IMPLICIT_DEF
%r4 = IMPLICIT_DEF %r4 = IMPLICIT_DEF
%r5 = IMPLICIT_DEF %r5 = IMPLICIT_DEF
%r6 = IMPLICIT_DEF %r6 = IMPLICIT_DEF
%r7 = IMPLICIT_DEF %r7 = IMPLICIT_DEF
%r8 = IMPLICIT_DEF %r8 = IMPLICIT_DEF
%r9 = IMPLICIT_DEF %r9 = IMPLICIT_DEF
%r10 = IMPLICIT_DEF %r10 = IMPLICIT_DEF
%r11 = IMPLICIT_DEF %r11 = IMPLICIT_DEF
%r12 = IMPLICIT_DEF %r12 = IMPLICIT_DEF
%lr = IMPLICIT_DEF %lr = IMPLICIT_DEF
%sp = t2LDRi12 %fixed-stack.0, 0, 14, _ :: (load 4) %sp = t2LDRi12 %fixed-stack.0, 0, 14, %noreg :: (load 4)
KILL %r0 KILL %r0
KILL %r1 KILL %r1
KILL %r2 KILL %r2
KILL %r3 KILL %r3
KILL %r4 KILL %r4
KILL %r5 KILL %r5
KILL %r6 KILL %r6
KILL %r7 KILL %r7
KILL %r8 KILL %r8
KILL %r9 KILL %r9
KILL %r10 KILL %r10
KILL %r11 KILL %r11
KILL %r12 KILL %r12
KILL %lr KILL %lr
... ...
--- ---
# This should not trigger an emergency spill yet. # This should not trigger an emergency spill yet.
# CHECK-LABEL: name: func1 # CHECK-LABEL: name: func1
# CHECK-NOT: t2STRi12 # CHECK-NOT: t2STRi12
# CHECK-NOT: t2ADDri # CHECK-NOT: t2ADDri
# CHECK: %r11 = t2LDRi12 %sp, 4092, 14, _ :: (load 4) # CHECK: %r11 = t2LDRi12 %sp, 4092, 14, %noreg :: (load 4)
# CHECK-NOT: t2LDRi12 # CHECK-NOT: t2LDRi12
name: func1 name: func1
tracksRegLiveness: true tracksRegLiveness: true
fixedStack: fixedStack:
- { id: 0, offset: 4044, size: 4, alignment: 4, isImmutable: true, - { id: 0, offset: 4044, size: 4, alignment: 4, isImmutable: true,
isAliased: false } isAliased: false }
- { id: 1, offset: -12, size: 4056, alignment: 4, isImmutable: false, - { id: 1, offset: -12, size: 4056, alignment: 4, isImmutable: false,
isAliased: false } isAliased: false }
body: | body: |
bb.0: bb.0:
%r0 = IMPLICIT_DEF %r0 = IMPLICIT_DEF
%r1 = IMPLICIT_DEF %r1 = IMPLICIT_DEF
%r2 = IMPLICIT_DEF %r2 = IMPLICIT_DEF
%r3 = IMPLICIT_DEF %r3 = IMPLICIT_DEF
%r4 = IMPLICIT_DEF %r4 = IMPLICIT_DEF
%r5 = IMPLICIT_DEF %r5 = IMPLICIT_DEF
%r6 = IMPLICIT_DEF %r6 = IMPLICIT_DEF
%r8 = IMPLICIT_DEF %r8 = IMPLICIT_DEF
%r9 = IMPLICIT_DEF %r9 = IMPLICIT_DEF
%r10 = IMPLICIT_DEF %r10 = IMPLICIT_DEF
%r11 = IMPLICIT_DEF %r11 = IMPLICIT_DEF
%r12 = IMPLICIT_DEF %r12 = IMPLICIT_DEF
%lr = IMPLICIT_DEF %lr = IMPLICIT_DEF
%r11 = t2LDRi12 %fixed-stack.0, 0, 14, _ :: (load 4) %r11 = t2LDRi12 %fixed-stack.0, 0, 14, %noreg :: (load 4)
KILL %r0 KILL %r0
KILL %r1 KILL %r1
KILL %r2 KILL %r2
KILL %r3 KILL %r3
KILL %r4 KILL %r4
KILL %r5 KILL %r5
KILL %r6 KILL %r6
KILL %r8 KILL %r8
KILL %r9 KILL %r9
KILL %r10 KILL %r10
KILL %r11 KILL %r11
KILL %r12 KILL %r12
KILL %lr KILL %lr
... ...

llvm/trunk/test/CodeGen/ARM/imm-peephole-arm.mir

Show All 36 Lines
liveins: liveins:
- { reg: '%r0', virtual-reg: '%0' } - { reg: '%r0', virtual-reg: '%0' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %r0 liveins: %r0
%0 = COPY %r0 %0 = COPY %r0
%1 = MOVi32imm -25733 %1 = MOVi32imm -25733
%2 = SUBrr %0, killed %1, 14, _, _ %2 = SUBrr %0, killed %1, 14, %noreg, %noreg
%3 = MOVi32imm 25733 %3 = MOVi32imm 25733
%4 = SUBrr %0, killed %3, 14, _, _ %4 = SUBrr %0, killed %3, 14, %noreg, %noreg
%5 = MOVi32imm -25733 %5 = MOVi32imm -25733
%6 = ADDrr %0, killed %5, 14, _, _ %6 = ADDrr %0, killed %5, 14, %noreg, %noreg
%7 = MOVi32imm 25733 %7 = MOVi32imm 25733
%8 = ADDrr killed %0, killed %7, 14, _, _ %8 = ADDrr killed %0, killed %7, 14, %noreg, %noreg
%r0 = COPY killed %8 %r0 = COPY killed %8
BX_RET 14, _, implicit %r0 BX_RET 14, %noreg, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/imm-peephole-thumb.mir

Show All 35 Linesregisters:
- { id: 8, class: rgpr } - { id: 8, class: rgpr }
liveins: liveins:
- { reg: '%r0', virtual-reg: '%0' } - { reg: '%r0', virtual-reg: '%0' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %r0 liveins: %r0
%0 = COPY %r0 %0 = COPY %r0
%1 = t2MOVi32imm -25733 %1 = t2MOVi32imm -25733
%2 = t2SUBrr %0, killed %1, 14, _, _ %2 = t2SUBrr %0, killed %1, 14, %noreg, %noreg
%3 = t2MOVi32imm 25733 %3 = t2MOVi32imm 25733
%4 = t2SUBrr %0, killed %3, 14, _, _ %4 = t2SUBrr %0, killed %3, 14, %noreg, %noreg
%5 = t2MOVi32imm -25733 %5 = t2MOVi32imm -25733
%6= t2ADDrr %0, killed %5, 14, _, _ %6= t2ADDrr %0, killed %5, 14, %noreg, %noreg
%7 = t2MOVi32imm 25733 %7 = t2MOVi32imm 25733
%8 = t2ADDrr killed %0, killed %7, 14, _, _ %8 = t2ADDrr killed %0, killed %7, 14, %noreg, %noreg
%r0 = COPY killed %8 %r0 = COPY killed %8
tBX_RET 14, _, implicit %r0 tBX_RET 14, %noreg, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/indirect-hidden.ll

Show All 13 Lines
; CHECK: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers ; CHECK: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers
; CHECK: .indirect_symbol _var ; CHECK: .indirect_symbol _var
; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 0
; CHECK-NOT: __DATA,__data ; CHECK-NOT: __DATA,__data
; CHECK: .indirect_symbol _var_hidden ; CHECK: .indirect_symbol _var_hidden
; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 0
No newline at end of file

llvm/trunk/test/CodeGen/ARM/litpool-licm.ll

Show All 37 Linesnext:
%inc = add i32 %i, 1 %inc = add i32 %i, 1
%stop = icmp eq i32 %inc, %n %stop = icmp eq i32 %inc, %n
br i1 %stop, label %done, label %loop br i1 %stop, label %done, label %loop
done: done:
ret void ret void
} }
declare void @foo(i32*) declare void @foo(i32*)
No newline at end of file

llvm/trunk/test/CodeGen/ARM/load_store_opt_kill.mir

# RUN: llc -mtriple=armv7-none-eabi -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s # RUN: llc -mtriple=armv7-none-eabi -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s
--- ---
# CHECK-LABEL: name: f # CHECK-LABEL: name: f
name: f name: f
# Make sure the load into %r0 doesn't clobber the base register before the second load uses it. # Make sure the load into %r0 doesn't clobber the base register before the second load uses it.
# CHECK: %r3 = LDRi12 %r0, 12, 14, _ # CHECK: %r3 = LDRi12 %r0, 12, 14, %noreg
# CHECK-NEXT: %r0 = LDRi12 %r0, 8, 14, _ # CHECK-NEXT: %r0 = LDRi12 %r0, 8, 14, %noreg
body: | body: |
bb.0: bb.0:
liveins: %r0, %r3 liveins: %r0, %r3
%r0, %r3 = LDRD %r0, %noreg, 8, 14, %noreg %r0, %r3 = LDRD %r0, %noreg, 8, 14, %noreg
... ...

llvm/trunk/test/CodeGen/ARM/local-call.ll

Show All 11 Lines
} }
define i64 @test_local_call(i64 %a, i64 %b) { define i64 @test_local_call(i64 %a, i64 %b) {
; CHECK-LABEL: test_local_call: ; CHECK-LABEL: test_local_call:
; CHECK: bl ___udivdi3 ; CHECK: bl ___udivdi3
%res = udiv i64 %a, %b %res = udiv i64 %a, %b
ret i64 %res ret i64 %res
} }
No newline at end of file

llvm/trunk/test/CodeGen/ARM/machine-copyprop.mir

# RUN: llc -o - %s -mtriple=armv7s-- -run-pass=machine-cp | FileCheck %s # RUN: llc -o - %s -mtriple=armv7s-- -run-pass=machine-cp | FileCheck %s
--- ---
# Test that machine copy prop recognizes the implicit-def operands on a COPY # Test that machine copy prop recognizes the implicit-def operands on a COPY
# as clobbering the register. # as clobbering the register.
# CHECK-LABEL: name: func # CHECK-LABEL: name: func
# CHECK: %d2 = VMOVv2i32 2, 14, _ # CHECK: %d2 = VMOVv2i32 2, 14, %noreg
# CHECK: %s5 = COPY %s0, implicit %q1, implicit-def %q1 # CHECK: %s5 = COPY %s0, implicit %q1, implicit-def %q1
# CHECK: VST1q32 %r0, 0, %q1, 14, _ # CHECK: VST1q32 %r0, 0, %q1, 14, %noreg
# The following two COPYs must not be removed # The following two COPYs must not be removed
# CHECK: %s4 = COPY %s20, implicit-def %q1 # CHECK: %s4 = COPY %s20, implicit-def %q1
# CHECK: %s5 = COPY %s0, implicit killed %d0, implicit %q1, implicit-def %q1 # CHECK: %s5 = COPY %s0, implicit killed %d0, implicit %q1, implicit-def %q1
# CHECK: VST1q32 %r2, 0, %q1, 14, _ # CHECK: VST1q32 %r2, 0, %q1, 14, %noreg
name: func name: func
body: | body: |
bb.0: bb.0:
%d2 = VMOVv2i32 2, 14, _ %d2 = VMOVv2i32 2, 14, %noreg
%s5 = COPY %s0, implicit %q1, implicit-def %q1 %s5 = COPY %s0, implicit %q1, implicit-def %q1
VST1q32 %r0, 0, %q1, 14, _ VST1q32 %r0, 0, %q1, 14, %noreg
%s4 = COPY %s20, implicit-def %q1 %s4 = COPY %s20, implicit-def %q1
%s5 = COPY %s0, implicit killed %d0, implicit %q1, implicit-def %q1 %s5 = COPY %s0, implicit killed %d0, implicit %q1, implicit-def %q1
VST1q32 %r2, 0, %q1, 14, _ VST1q32 %r2, 0, %q1, 14, %noreg
... ...

llvm/trunk/test/CodeGen/ARM/misched-int-basic-thumb2.mir

Show First 20 Lines • Show All 146 Lines • ▼ Show 20 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0, %r1 liveins: %r0, %r1
%1 = COPY %r1 %1 = COPY %r1
%0 = COPY %r0 %0 = COPY %r0
%2 = t2MOVi32imm @g1 %2 = t2MOVi32imm @g1
%3 = t2LDRi12 %2, 0, 14, _ :: (dereferenceable load 4 from @g1) %3 = t2LDRi12 %2, 0, 14, %noreg :: (dereferenceable load 4 from @g1)
%4 = t2MOVi32imm @g2 %4 = t2MOVi32imm @g2
%5 = t2LDRi12 %4, 0, 14, _ :: (dereferenceable load 4 from @g2) %5 = t2LDRi12 %4, 0, 14, %noreg :: (dereferenceable load 4 from @g2)
%6 = t2ADDrr %3, %3, 14, _, _ %6 = t2ADDrr %3, %3, 14, %noreg, %noreg
%7 = t2SDIV %6, %5, 14, _ %7 = t2SDIV %6, %5, 14, %noreg
t2STRi12 %7, %2, 0, 14, _ :: (store 4 into @g1) t2STRi12 %7, %2, 0, 14, %noreg :: (store 4 into @g1)
%8 = t2SMULBB %1, %1, 14, _ %8 = t2SMULBB %1, %1, 14, %noreg
%9 = t2SMLABB %0, %0, %8, 14, _ %9 = t2SMLABB %0, %0, %8, 14, %noreg
%10 = t2UXTH %9, 0, 14, _ %10 = t2UXTH %9, 0, 14, %noreg
%11 = t2MUL %10, %7, 14, _ %11 = t2MUL %10, %7, 14, %noreg
%12 = t2MLA %11, %11, %11, 14, _ %12 = t2MLA %11, %11, %11, 14, %noreg
%13, %14 = t2UMULL %12, %12, 14, _ %13, %14 = t2UMULL %12, %12, 14, %noreg
%19, %16 = t2UMULL %13, %13, 14, _ %19, %16 = t2UMULL %13, %13, 14, %noreg
%17 = t2MLA %13, %14, %16, 14, _ %17 = t2MLA %13, %14, %16, 14, %noreg
%20 = t2MLA %13, %14, %17, 14, _ %20 = t2MLA %13, %14, %17, 14, %noreg
%19, %20 = t2UMLAL %12, %12, %19, %20, 14, _ %19, %20 = t2UMLAL %12, %12, %19, %20, 14, %noreg
%r0 = COPY %19 %r0 = COPY %19
%r1 = COPY %20 %r1 = COPY %20
tBX_RET 14, _, implicit %r0, implicit %r1 tBX_RET 14, %noreg, implicit %r0, implicit %r1
... ...

llvm/trunk/test/CodeGen/ARM/misched-int-basic.mir

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0, %r1 liveins: %r0, %r1
%1 = COPY %r1 %1 = COPY %r1
%0 = COPY %r0 %0 = COPY %r0
%2 = SMULBB %1, %1, 14, _ %2 = SMULBB %1, %1, 14, %noreg
%3 = SMLABB %0, %0, %2, 14, _ %3 = SMLABB %0, %0, %2, 14, %noreg
%4 = UXTH %3, 0, 14, _ %4 = UXTH %3, 0, 14, %noreg
%5 = MUL %4, %4, 14, _, _ %5 = MUL %4, %4, 14, %noreg, %noreg
%6 = MLA %5, %5, %5, 14, _, _ %6 = MLA %5, %5, %5, 14, %noreg, %noreg
%7, %8 = UMULL %6, %6, 14, _, _ %7, %8 = UMULL %6, %6, 14, %noreg, %noreg
%13, %10 = UMULL %7, %7, 14, _, _ %13, %10 = UMULL %7, %7, 14, %noreg, %noreg
%11 = MLA %7, %8, %10, 14, _, _ %11 = MLA %7, %8, %10, 14, %noreg, %noreg
%14 = MLA %7, %8, %11, 14, _, _ %14 = MLA %7, %8, %11, 14, %noreg, %noreg
%13, %14 = UMLAL %6, %6, %13, %14, 14, _, _ %13, %14 = UMLAL %6, %6, %13, %14, 14, %noreg, %noreg
%r0 = COPY %13 %r0 = COPY %13
%r1 = COPY %14 %r1 = COPY %14
BX_RET 14, _, implicit %r0, implicit %r1 BX_RET 14, %noreg, implicit %r0, implicit %r1
... ...

llvm/trunk/test/CodeGen/ARM/pei-swiftself.mir

Show All 33 Lines bb.0:
%r11 = IMPLICIT_DEF %r11 = IMPLICIT_DEF
%r12 = IMPLICIT_DEF %r12 = IMPLICIT_DEF
%lr = IMPLICIT_DEF %lr = IMPLICIT_DEF
; Computing the large stack offset requires an extra register. We should ; Computing the large stack offset requires an extra register. We should
; not just use %r10 for that. ; not just use %r10 for that.
; CHECK-NOT: STRi12 %1,{{.*}}%r10 ; CHECK-NOT: STRi12 %1,{{.*}}%r10
STRi12 %r1, %stack.0, 0, 14, _ :: (store 4) STRi12 %r1, %stack.0, 0, 14, %noreg :: (store 4)
; use the swiftself parameter value. ; use the swiftself parameter value.
KILL %r10 KILL %r10
KILL %r0 KILL %r0
KILL %r1 KILL %r1
KILL %r2 KILL %r2
KILL %r3 KILL %r3
Show All 10 Lines

llvm/trunk/test/CodeGen/ARM/pr25317.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv7--linux-gnueabihf" target triple = "armv7--linux-gnueabihf"
; CHECK-LABEL: f: ; CHECK-LABEL: f:
; CHECK: str lr, [r0] ; CHECK: str lr, [r0]
define void @f(i32* %p) { define void @f(i32* %p) {
call void asm sideeffect "str lr, $0", "=*o"(i32* %p) call void asm sideeffect "str lr, $0", "=*o"(i32* %p)
ret void ret void
} }
No newline at end of file

llvm/trunk/test/CodeGen/ARM/preferred-align.ll

Show All 12 Lines
@var8 = global i8 zeroinitializer @var8 = global i8 zeroinitializer
; CHECK: .globl var8 ; CHECK: .globl var8
; CHECK-NOT: .p2align ; CHECK-NOT: .p2align
@var16 = global i16 zeroinitializer @var16 = global i16 zeroinitializer
; CHECK: .globl var16 ; CHECK: .globl var16
; CHECK-NEXT: .p2align 1 ; CHECK-NEXT: .p2align 1
No newline at end of file

llvm/trunk/test/CodeGen/ARM/prera-ldst-aliasing.mir

Show All 20 Linesliveins:
- { reg: '%r0', virtual-reg: '%0' } - { reg: '%r0', virtual-reg: '%0' }
- { reg: '%r1', virtual-reg: '%1' } - { reg: '%r1', virtual-reg: '%1' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0, %r1 liveins: %r0, %r1
%1 : gpr = COPY %r1 %1 : gpr = COPY %r1
%0 : gpr = COPY %r0 %0 : gpr = COPY %r0
%2 : gpr = t2LDRi12 %1, 0, 14, _ :: (load 4 from %ir.y) %2 : gpr = t2LDRi12 %1, 0, 14, %noreg :: (load 4 from %ir.y)
t2STRi12 killed %2, %0, 0, 14, _ :: (store 4 into %ir.x) t2STRi12 killed %2, %0, 0, 14, %noreg :: (store 4 into %ir.x)
%3 : gpr = t2LDRi12 %1, 4, 14, _ :: (load 4 from %ir.arrayidx2) %3 : gpr = t2LDRi12 %1, 4, 14, %noreg :: (load 4 from %ir.arrayidx2)
t2STRi12 killed %3, %0, 4, 14, _ :: (store 4 into %ir.arrayidx3) t2STRi12 killed %3, %0, 4, 14, %noreg :: (store 4 into %ir.arrayidx3)
; CHECK: t2LDRi12 ; CHECK: t2LDRi12
; CHECK-NEXT: t2LDRi12 ; CHECK-NEXT: t2LDRi12
; CHECK-NEXT: t2STRi12 ; CHECK-NEXT: t2STRi12
; CHECK-NEXT: t2STRi12 ; CHECK-NEXT: t2STRi12
tBX_RET 14, _ tBX_RET 14, %noreg
... ...

llvm/trunk/test/CodeGen/ARM/prera-ldst-insertpt.mir

Show All 22 Linesliveins:
- { reg: '%r2', virtual-reg: '%2' } - { reg: '%r2', virtual-reg: '%2' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0, %r1, %r2 liveins: %r0, %r1, %r2
%2 : rgpr = COPY %r2 %2 : rgpr = COPY %r2
%1 : rgpr = COPY %r1 %1 : rgpr = COPY %r1
%0 : gpr = COPY %r0 %0 : gpr = COPY %r0
%3 : rgpr = t2MUL %2, %2, 14, _ %3 : rgpr = t2MUL %2, %2, 14, %noreg
%4 : rgpr = t2MUL %1, %1, 14, _ %4 : rgpr = t2MUL %1, %1, 14, %noreg
%5 : rgpr = t2MOVi32imm -858993459 %5 : rgpr = t2MOVi32imm -858993459
%6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, _ %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, %noreg
%8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, _ %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, %noreg
t2STRi12 %1, %0, 0, 14, _ :: (store 4) t2STRi12 %1, %0, 0, 14, %noreg :: (store 4)
%10 : rgpr = t2LSLri %2, 1, 14, _, _ %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg
t2STRi12 killed %10, %0, 4, 14, _ :: (store 4) t2STRi12 killed %10, %0, 4, 14, %noreg :: (store 4)
; Make sure we move the paired stores next to each other, and ; Make sure we move the paired stores next to each other, and
; insert them in an appropriate location. ; insert them in an appropriate location.
; CHECK: t2STRi12 %1, ; CHECK: t2STRi12 %1,
; CHECK-NEXT: t2STRi12 killed %10, ; CHECK-NEXT: t2STRi12 killed %10,
; CHECK-NEXT: t2MOVi ; CHECK-NEXT: t2MOVi
; CHECK-NEXT: t2ADDrs ; CHECK-NEXT: t2ADDrs
%11 : rgpr = t2MOVi 55, 14, _, _ %11 : rgpr = t2MOVi 55, 14, %noreg, %noreg
%12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, _, _ %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, %noreg, %noreg
t2STRi12 killed %12, %0, 16, 14, _ :: (store 4) t2STRi12 killed %12, %0, 16, 14, %noreg :: (store 4)
%13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, _, _ %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, %noreg, %noreg
t2STRi12 killed %13, %0, 20, 14, _ :: (store 4) t2STRi12 killed %13, %0, 20, 14, %noreg :: (store 4)
; Make sure we move the paired stores next to each other. ; Make sure we move the paired stores next to each other.
; CHECK: t2STRi12 killed %12, ; CHECK: t2STRi12 killed %12,
; CHECK-NEXT: t2STRi12 killed %13, ; CHECK-NEXT: t2STRi12 killed %13,
tBX_RET 14, _ tBX_RET 14, %noreg
--- ---
# CHECK-LABEL: name: b # CHECK-LABEL: name: b
name: b name: b
alignment: 1 alignment: 1
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%r0', virtual-reg: '%0' } - { reg: '%r0', virtual-reg: '%0' }
- { reg: '%r1', virtual-reg: '%1' } - { reg: '%r1', virtual-reg: '%1' }
- { reg: '%r2', virtual-reg: '%2' } - { reg: '%r2', virtual-reg: '%2' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0, %r1, %r2 liveins: %r0, %r1, %r2
%2 : rgpr = COPY %r2 %2 : rgpr = COPY %r2
%1 : rgpr = COPY %r1 %1 : rgpr = COPY %r1
%0 : gpr = COPY %r0 %0 : gpr = COPY %r0
t2STRi12 %1, %0, 0, 14, _ :: (store 4) t2STRi12 %1, %0, 0, 14, %noreg :: (store 4)
%10 : rgpr = t2LSLri %2, 1, 14, _, _ %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg
t2STRi12 killed %10, %0, 4, 14, _ :: (store 4) t2STRi12 killed %10, %0, 4, 14, %noreg :: (store 4)
%3 : rgpr = t2MUL %2, %2, 14, _ %3 : rgpr = t2MUL %2, %2, 14, %noreg
t2STRi12 %3, %0, 8, 14, _ :: (store 4) t2STRi12 %3, %0, 8, 14, %noreg :: (store 4)
; Make sure we move the paired stores next to each other, and ; Make sure we move the paired stores next to each other, and
; insert them in an appropriate location. ; insert them in an appropriate location.
; CHECK: t2STRi12 {{.*}}, 0 ; CHECK: t2STRi12 {{.*}}, 0
; CHECK-NEXT: t2STRi12 {{.*}}, 4 ; CHECK-NEXT: t2STRi12 {{.*}}, 4
; CHECK-NEXT: t2STRi12 {{.*}}, 8 ; CHECK-NEXT: t2STRi12 {{.*}}, 8
; CHECK-NEXT: t2MUL ; CHECK-NEXT: t2MUL
; CHECK-NEXT: t2MOVi32imm ; CHECK-NEXT: t2MOVi32imm
%4 : rgpr = t2MUL %1, %1, 14, _ %4 : rgpr = t2MUL %1, %1, 14, %noreg
%5 : rgpr = t2MOVi32imm -858993459 %5 : rgpr = t2MOVi32imm -858993459
%6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, _ %6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, %noreg
%8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, _ %8 : rgpr, %9 : rgpr = t2UMULL killed %4, %5, 14, %noreg
%10 : rgpr = t2LSLri %2, 1, 14, _, _ %10 : rgpr = t2LSLri %2, 1, 14, %noreg, %noreg
%11 : rgpr = t2MOVi 55, 14, _, _ %11 : rgpr = t2MOVi 55, 14, %noreg, %noreg
%12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, _, _ %12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, %noreg, %noreg
t2STRi12 killed %12, %0, 16, 14, _ :: (store 4) t2STRi12 killed %12, %0, 16, 14, %noreg :: (store 4)
%13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, _, _ %13 : gprnopc = t2ADDrs %11, killed %9, 19, 14, %noreg, %noreg
t2STRi12 killed %13, %0, 20, 14, _ :: (store 4) t2STRi12 killed %13, %0, 20, 14, %noreg :: (store 4)
; Make sure we move the paired stores next to each other. ; Make sure we move the paired stores next to each other.
; CHECK: t2STRi12 {{.*}}, 16 ; CHECK: t2STRi12 {{.*}}, 16
; CHECK-NEXT: t2STRi12 {{.*}}, 20 ; CHECK-NEXT: t2STRi12 {{.*}}, 20
tBX_RET 14, _ tBX_RET 14, %noreg
... ...

llvm/trunk/test/CodeGen/ARM/scavenging.mir

Show All 19 Lines bb.0:
%r2 = IMPLICIT_DEF %r2 = IMPLICIT_DEF
%r3 = IMPLICIT_DEF %r3 = IMPLICIT_DEF
%r4 = IMPLICIT_DEF %r4 = IMPLICIT_DEF
%r5 = IMPLICIT_DEF %r5 = IMPLICIT_DEF
%r6 = IMPLICIT_DEF %r6 = IMPLICIT_DEF
%r7 = IMPLICIT_DEF %r7 = IMPLICIT_DEF
%0 : tgpr = IMPLICIT_DEF %0 : tgpr = IMPLICIT_DEF
%0 = tADDhirr %0, %sp, 14, _ %0 = tADDhirr %0, %sp, 14, %noreg
tSTRi %r0, %0, 0, 14, _ tSTRi %r0, %0, 0, 14, %noreg
%1 : tgpr = IMPLICIT_DEF %1 : tgpr = IMPLICIT_DEF
%1 = tADDhirr %1, %sp, 14, _ %1 = tADDhirr %1, %sp, 14, %noreg
tSTRi %r1, %1, 0, 14, _ tSTRi %r1, %1, 0, 14, %noreg
%2 : tgpr = IMPLICIT_DEF %2 : tgpr = IMPLICIT_DEF
%2 = tADDhirr %2, %sp, 14, _ %2 = tADDhirr %2, %sp, 14, %noreg
tSTRi %r2, %2, 0, 14, _ tSTRi %r2, %2, 0, 14, %noreg
%3 : tgpr = IMPLICIT_DEF %3 : tgpr = IMPLICIT_DEF
%3 = tADDhirr %3, %sp, 14, _ %3 = tADDhirr %3, %sp, 14, %noreg
tSTRi %r3, %3, 0, 14, _ tSTRi %r3, %3, 0, 14, %noreg
%4 : tgpr = IMPLICIT_DEF %4 : tgpr = IMPLICIT_DEF
%4 = tADDhirr %4, %sp, 14, _ %4 = tADDhirr %4, %sp, 14, %noreg
tSTRi %r4, %4, 0, 14, _ tSTRi %r4, %4, 0, 14, %noreg
%5 : tgpr = IMPLICIT_DEF %5 : tgpr = IMPLICIT_DEF
%5 = tADDhirr %5, %sp, 14, _ %5 = tADDhirr %5, %sp, 14, %noreg
tSTRi %r5, %5, 0, 14, _ tSTRi %r5, %5, 0, 14, %noreg
%6 : tgpr = IMPLICIT_DEF %6 : tgpr = IMPLICIT_DEF
%6 = tADDhirr %6, %sp, 14, _ %6 = tADDhirr %6, %sp, 14, %noreg
tSTRi %r6, %6, 0, 14, _ tSTRi %r6, %6, 0, 14, %noreg
%7 : tgpr = IMPLICIT_DEF %7 : tgpr = IMPLICIT_DEF
%7 = tADDhirr %7, %sp, 14, _ %7 = tADDhirr %7, %sp, 14, %noreg
tSTRi %r7, %7, 0, 14, _ tSTRi %r7, %7, 0, 14, %noreg
KILL %r0 KILL %r0
KILL %r1 KILL %r1
KILL %r2 KILL %r2
KILL %r3 KILL %r3
KILL %r4 KILL %r4
KILL %r5 KILL %r5
KILL %r6 KILL %r6
KILL %r7 KILL %r7

llvm/trunk/test/CodeGen/ARM/sched-it-debug-nodes.mir

Show First 20 Lines • Show All 125 Lines • ▼ Show 20 LinesframeInfo:
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
stack: stack:
- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr', callee-saved-restored: false } - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr', callee-saved-restored: false }
- { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' } - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0, %r1, %r2, %r3, %lr, %r7 liveins: %r0, %r1, %r2, %r3, %lr, %r7
DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31 t2CMPri %r3, 4, 14, %noreg, implicit-def %cpsr, debug-location !31
DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
%r0 = t2MOVi -1, 3, %cpsr, _, implicit undef %r0 %r0 = t2MOVi -1, 3, %cpsr, %noreg, implicit undef %r0
DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
tBX_RET 3, %cpsr, implicit %r0, debug-location !34 tBX_RET 3, %cpsr, implicit %r0, debug-location !34
%sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr %sp = frame-setup t2STMDB_UPD %sp, 14, %noreg, killed %r7, killed %lr
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset %lr, -4 frame-setup CFI_INSTRUCTION offset %lr, -4
frame-setup CFI_INSTRUCTION offset %r7, -8 frame-setup CFI_INSTRUCTION offset %r7, -8
DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 DBG_VALUE debug-use %r0, debug-use %noreg, !18, !27, debug-location !28
DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 DBG_VALUE debug-use %r1, debug-use %noreg, !19, !27, debug-location !28
DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 DBG_VALUE debug-use %r2, debug-use %noreg, !20, !27, debug-location !28
DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 DBG_VALUE debug-use %r3, debug-use %noreg, !21, !27, debug-location !28
%r1 = tMOVr killed %r2, 14, _, debug-location !32 %r1 = tMOVr killed %r2, 14, %noreg, debug-location !32
%r2 = tMOVr killed %r3, 14, _, debug-location !32 %r2 = tMOVr killed %r3, 14, %noreg, debug-location !32
tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32 tBL 14, %noreg, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32
%r0 = t2MOVi 0, 14, _, _ %r0 = t2MOVi 0, 14, %noreg, %noreg
%sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0 %sp = t2LDMIA_RET %sp, 14, %noreg, def %r7, def %pc, implicit %r0
... ...

llvm/trunk/test/CodeGen/ARM/single-issue-r52.mir

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 LinesframeInfo:
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %r0 liveins: %r0
%0 = COPY %r0 %0 = COPY %r0
%1 = VLD4d8Pseudo %0, 8, 14, _ :: (load 32 from %ir.A, align 8) %1 = VLD4d8Pseudo %0, 8, 14, %noreg :: (load 32 from %ir.A, align 8)
%4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, _ %4 = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, %noreg
%5, %6 = VMOVRRD %4, 14, _ %5, %6 = VMOVRRD %4, 14, %noreg
%r0 = COPY %5 %r0 = COPY %5
%r1 = COPY %6 %r1 = COPY %6
BX_RET 14, _, implicit %r0, implicit killed %r1 BX_RET 14, %noreg, implicit %r0, implicit killed %r1
... ...

llvm/trunk/test/CodeGen/ARM/tail-dup-bundle.mir

Show All 13 Lines
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: %r0, %lr, %r7 liveins: %r0, %lr, %r7
bb.1: bb.1:
liveins: %r0 liveins: %r0
t2CMPri %r0, 32, 14, _, implicit-def %cpsr t2CMPri %r0, 32, 14, %noreg, implicit-def %cpsr
BUNDLE implicit-def dead %itstate, implicit-def %cpsr, implicit killed %r0, implicit killed %cpsr { BUNDLE implicit-def dead %itstate, implicit-def %cpsr, implicit killed %r0, implicit killed %cpsr {
t2IT 1, 24, implicit-def %itstate t2IT 1, 24, implicit-def %itstate
t2CMPri killed %r0, 9, 1, killed %cpsr, implicit-def %cpsr, implicit internal killed %itstate t2CMPri killed %r0, 9, 1, killed %cpsr, implicit-def %cpsr, implicit internal killed %itstate
} }
t2Bcc %bb.3, 1, killed %cpsr t2Bcc %bb.3, 1, killed %cpsr
bb.2: bb.2:
%r0 = IMPLICIT_DEF %r0 = IMPLICIT_DEF
t2B %bb.1, 14, _ t2B %bb.1, 14, %noreg
bb.3: bb.3:
%r0 = IMPLICIT_DEF %r0 = IMPLICIT_DEF
t2B %bb.1, 14, _ t2B %bb.1, 14, %noreg
... ...

llvm/trunk/test/CodeGen/ARM/thumb-litpool.ll

; RUN: llc -mtriple=thumbv6m-apple-macho %s -relocation-model=static -o - | FileCheck %s ; RUN: llc -mtriple=thumbv6m-apple-macho %s -relocation-model=static -o - | FileCheck %s
; RUN: llc -mtriple=thumbv6m-apple-macho %s -relocation-model=pic -o - | FileCheck %s ; RUN: llc -mtriple=thumbv6m-apple-macho %s -relocation-model=pic -o - | FileCheck %s
@var = global i8 zeroinitializer @var = global i8 zeroinitializer
declare void @callee(i8*) declare void @callee(i8*)
define void @foo() minsize { define void @foo() minsize {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: ldr {{r[0-7]}}, LCPI0_0 ; CHECK: ldr {{r[0-7]}}, LCPI0_0
call void @callee(i8* @var) call void @callee(i8* @var)
call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7}"() call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7}"()
call void @callee(i8* @var) call void @callee(i8* @var)
ret void ret void
} }
No newline at end of file

llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir

Show First 20 Lines • Show All 225 Lines • ▼ Show 20 Lines - id: 0
'%bb.2.d1', '%bb.2.d1', '%bb.12.d11', '%bb.13.d12', '%bb.2.d1', '%bb.2.d1', '%bb.12.d11', '%bb.13.d12',
'%bb.14.d13', '%bb.15.d14', '%bb.2.d1', '%bb.16.d15', '%bb.14.d13', '%bb.15.d14', '%bb.2.d1', '%bb.16.d15',
'%bb.17.d16', '%bb.18.d17' ] '%bb.17.d16', '%bb.18.d17' ]
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c) successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)
liveins: %r0, %r1 liveins: %r0, %r1
%r2 = tLDRpci %const.0, 14, _ %r2 = tLDRpci %const.0, 14, %noreg
tSTRi killed %r2, killed %r1, 0, 14, _ :: (store 4 into %ir.addr) tSTRi killed %r2, killed %r1, 0, 14, %noreg :: (store 4 into %ir.addr)
dead %r1 = SPACE 980, undef %r0 dead %r1 = SPACE 980, undef %r0
%r0 = tUXTB killed %r0, 14, _ %r0 = tUXTB killed %r0, 14, %noreg
%r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, _ %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, %noreg
tCMPi8 %r1, 25, 14, _, implicit-def %cpsr tCMPi8 %r1, 25, 14, %noreg, implicit-def %cpsr
tBcc %bb.2.d1, 8, killed %cpsr tBcc %bb.2.d1, 8, killed %cpsr
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2) successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)
liveins: %r1 liveins: %r1
%r0, dead %cpsr = tLSLri killed %r1, 2, 14, _ %r0, dead %cpsr = tLSLri killed %r1, 2, 14, %noreg
%r1 = tLEApcrelJT %jump-table.0, 14, _ %r1 = tLEApcrelJT %jump-table.0, 14, %noreg
%r0 = tLDRr killed %r1, killed %r0, 14, _ :: (load 4 from jump-table) %r0 = tLDRr killed %r1, killed %r0, 14, %noreg :: (load 4 from jump-table)
tBR_JTr killed %r0, %jump-table.0 tBR_JTr killed %r0, %jump-table.0
bb.3.d2: bb.3.d2:
bb.9.d8: bb.9.d8:
bb.4.d3: bb.4.d3:
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines - id: 0
'%bb.2.d1', '%bb.2.d1', '%bb.12.d11', '%bb.13.d12', '%bb.2.d1', '%bb.2.d1', '%bb.12.d11', '%bb.13.d12',
'%bb.14.d13', '%bb.15.d14', '%bb.2.d1', '%bb.16.d15', '%bb.14.d13', '%bb.15.d14', '%bb.2.d1', '%bb.16.d15',
'%bb.17.d16', '%bb.18.d17' ] '%bb.17.d16', '%bb.18.d17' ]
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c) successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)
liveins: %r0, %r1 liveins: %r0, %r1
%r2 = tLDRpci %const.0, 14, _ %r2 = tLDRpci %const.0, 14, %noreg
tSTRi killed %r2, killed %r1, 0, 14, _ :: (store 4 into %ir.addr) tSTRi killed %r2, killed %r1, 0, 14, %noreg :: (store 4 into %ir.addr)
%r0 = tUXTB killed %r0, 14, _ %r0 = tUXTB killed %r0, 14, %noreg
%r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, _ %r1, dead %cpsr = tSUBi3 killed %r0, 1, 14, %noreg
tCMPi8 %r1, 25, 14, _, implicit-def %cpsr tCMPi8 %r1, 25, 14, %noreg, implicit-def %cpsr
tBcc %bb.2.d1, 8, killed %cpsr tBcc %bb.2.d1, 8, killed %cpsr
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2) successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)
liveins: %r1 liveins: %r1
%r0, dead %cpsr = tLSLri killed %r1, 2, 14, _ %r0, dead %cpsr = tLSLri killed %r1, 2, 14, %noreg
%r1 = tLEApcrelJT %jump-table.0, 14, _ %r1 = tLEApcrelJT %jump-table.0, 14, %noreg
%r0 = tLDRr killed %r1, killed %r0, 14, _ :: (load 4 from jump-table) %r0 = tLDRr killed %r1, killed %r0, 14, %noreg :: (load 4 from jump-table)
tBR_JTr killed %r0, %jump-table.0 tBR_JTr killed %r0, %jump-table.0
bb.3.d2: bb.3.d2:
bb.9.d8: bb.9.d8:
bb.4.d3: bb.4.d3:
Show All 29 Lines

llvm/trunk/test/CodeGen/ARM/vcvt_combine.ll

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
} }
; CHECK-LABEL: test_illegal_fp_to_int: ; CHECK-LABEL: test_illegal_fp_to_int:
; CHECK: vcvt.s32.f32 {{q[0-9]+}}, {{q[0-9]+}}, #2 ; CHECK: vcvt.s32.f32 {{q[0-9]+}}, {{q[0-9]+}}, #2
define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) { define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) {
%scale = fmul <3 x float> %in, <float 4.0, float 4.0, float 4.0> %scale = fmul <3 x float> %in, <float 4.0, float 4.0, float 4.0>
%val = fptosi <3 x float> %scale to <3 x i32> %val = fptosi <3 x float> %scale to <3 x i32>
ret <3 x i32> %val ret <3 x i32> %val
} }
No newline at end of file

llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Lines
} }
; CHECK-LABEL: test_illegal_int_to_fp: ; CHECK-LABEL: test_illegal_int_to_fp:
; CHECK: vcvt.f32.s32 ; CHECK: vcvt.f32.s32
define <3 x float> @test_illegal_int_to_fp(<3 x i32> %in) { define <3 x float> @test_illegal_int_to_fp(<3 x i32> %in) {
%conv = sitofp <3 x i32> %in to <3 x float> %conv = sitofp <3 x i32> %in to <3 x float>
%res = fdiv <3 x float> %conv, <float 4.0, float 4.0, float 4.0> %res = fdiv <3 x float> %conv, <float 4.0, float 4.0, float 4.0>
ret <3 x float> %res ret <3 x float> %res
} }
No newline at end of file

llvm/trunk/test/CodeGen/ARM/virtregrewriter-subregliveness.mir

Show All 27 Lines bb.0:
; placeholder. If that's not a kill that means we probably ; placeholder. If that's not a kill that means we probably
; not coalescing %0 and %r0_r1 and thus we are not testing ; not coalescing %0 and %r0_r1 and thus we are not testing
; the problematic code anymore. ; the problematic code anymore.
; ;
; CHECK: %r0 = KILL %r0, implicit killed %r0_r1, implicit-def %r0_r1 ; CHECK: %r0 = KILL %r0, implicit killed %r0_r1, implicit-def %r0_r1
; CHECK-NEXT: %r1 = KILL %r1, implicit killed %r0_r1 ; CHECK-NEXT: %r1 = KILL %r1, implicit killed %r0_r1
undef %0.gsub_0 = COPY %r0 undef %0.gsub_0 = COPY %r0
%0.gsub_1 = COPY %r1 %0.gsub_1 = COPY %r1
tBX_RET 14, _, implicit %0 tBX_RET 14, %noreg, implicit %0
... ...
--- ---
# Check that we properly recognize that r1 is *not* live through # Check that we properly recognize that r1 is *not* live through
# the first subreg copy. # the first subreg copy.
# CHECK-LABEL: name: subregNotLiveThrough # CHECK-LABEL: name: subregNotLiveThrough
name: subregNotLiveThrough name: subregNotLiveThrough
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprpair } - { id: 0, class: gprpair }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
; r1 is not live through so check we are not implicitly using ; r1 is not live through so check we are not implicitly using
; the big register. ; the big register.
; CHECK: %r0 = KILL %r0, implicit-def %r0_r1 ; CHECK: %r0 = KILL %r0, implicit-def %r0_r1
; CHECK-NEXT: tBX_RET ; CHECK-NEXT: tBX_RET
undef %0.gsub_0 = COPY %r0 undef %0.gsub_0 = COPY %r0
tBX_RET 14, _, implicit %0 tBX_RET 14, %noreg, implicit %0
... ...
--- ---
# Check that we properly recognize that r1 is *not* live through # Check that we properly recognize that r1 is *not* live through
# the first subreg copy. It is defined by this copy, but is not # the first subreg copy. It is defined by this copy, but is not
# through. # through.
# CHECK-LABEL: name: subregNotLiveThrough2 # CHECK-LABEL: name: subregNotLiveThrough2
name: subregNotLiveThrough2 name: subregNotLiveThrough2
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gprpair } - { id: 0, class: gprpair }
body: | body: |
bb.0: bb.0:
liveins: %r0, %r1 liveins: %r0, %r1
; r1 is not live through so check we are not implicitly using ; r1 is not live through so check we are not implicitly using
; the big register. ; the big register.
; CHECK: %r0 = KILL %r0, implicit-def %r1, implicit-def %r0_r1 ; CHECK: %r0 = KILL %r0, implicit-def %r1, implicit-def %r0_r1
; CHECK-NEXT: tBX_RET ; CHECK-NEXT: tBX_RET
undef %0.gsub_0 = COPY %r0, implicit-def %r1 undef %0.gsub_0 = COPY %r0, implicit-def %r1
tBX_RET 14, _, implicit %0 tBX_RET 14, %noreg, implicit %0
... ...

llvm/trunk/test/CodeGen/ARM/vldm-liveness.mir

Show All 20 Lines
name: foo name: foo
alignment: 1 alignment: 1
liveins: liveins:
- { reg: '%r0' } - { reg: '%r0' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %r0 liveins: %r0
%s1 = VLDRS %r0, 1, 14, _, implicit-def %q0 :: (load 4) %s1 = VLDRS %r0, 1, 14, %noreg, implicit-def %q0 :: (load 4)
%s3 = VLDRS %r0, 2, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4) %s3 = VLDRS %r0, 2, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
; CHECK: %s3 = VLDRS %r0, 2, 14, _, implicit killed undef %q0, implicit-def %q0 :: (load 4) ; CHECK: %s3 = VLDRS %r0, 2, 14, %noreg, implicit killed undef %q0, implicit-def %q0 :: (load 4)
%s0 = VLDRS %r0, 0, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4) %s0 = VLDRS %r0, 0, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
; CHECK: VLDMSIA %r0, 14, _, def %s0, def %s1, implicit-def _ ; CHECK: VLDMSIA %r0, 14, %noreg, def %s0, def %s1, implicit-def %noreg
%s2 = VLDRS killed %r0, 4, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4) %s2 = VLDRS killed %r0, 4, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
; CHECK: %s2 = VLDRS killed %r0, 4, 14, _, implicit killed %q0, implicit-def %q0 :: (load 4) ; CHECK: %s2 = VLDRS killed %r0, 4, 14, %noreg, implicit killed %q0, implicit-def %q0 :: (load 4)
tBX_RET 14, _, implicit %q0 tBX_RET 14, %noreg, implicit %q0
... ...

llvm/trunk/test/CodeGen/Hexagon/duplex.ll

; RUN: llc -march=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s ; RUN: llc -march=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
; CHECK: c0 3f 00 48 48003fc0 ; CHECK: c0 3f 00 48 48003fc0
define i32 @foo() { define i32 @foo() {
ret i32 0 ret i32 0
} }
No newline at end of file

llvm/trunk/test/CodeGen/Hexagon/early-if-debug.mir

# RUN: llc -march=hexagon -eif-limit=4 -run-pass hexagon-early-if -o - %s | FileCheck %s # RUN: llc -march=hexagon -eif-limit=4 -run-pass hexagon-early-if -o - %s | FileCheck %s
# Check that even with the limit of 4 instructions, the block bb.1 is # Check that even with the limit of 4 instructions, the block bb.1 is
# if-converted. # if-converted.
# CHECK-LABEL: bb.0: # CHECK-LABEL: bb.0:
# CHECK: %0:intregs = COPY %r0 # CHECK: %0:intregs = COPY %r0
# CHECK: %1:predregs = C2_cmpeqi %0, 0 # CHECK: %1:predregs = C2_cmpeqi %0, 0
# CHECK: %2:intregs = A2_tfrsi 123 # CHECK: %2:intregs = A2_tfrsi 123
# CHECK: DBG_VALUE debug-use %0, debug-use _ # CHECK: DBG_VALUE debug-use %0, debug-use %noreg
# CHECK: DBG_VALUE debug-use %0, debug-use _ # CHECK: DBG_VALUE debug-use %0, debug-use %noreg
# CHECK: DBG_VALUE debug-use %0, debug-use _ # CHECK: DBG_VALUE debug-use %0, debug-use %noreg
# CHECK: DBG_VALUE debug-use %0, debug-use _ # CHECK: DBG_VALUE debug-use %0, debug-use %noreg
# CHECK: DBG_VALUE debug-use %0, debug-use _ # CHECK: DBG_VALUE debug-use %0, debug-use %noreg
# CHECK: %3:intregs = A2_tfrsi 321 # CHECK: %3:intregs = A2_tfrsi 321
# CHECK: %5:intregs = C2_mux %1, %2, %3 # CHECK: %5:intregs = C2_mux %1, %2, %3
--- | --- |
define void @foo() { define void @foo() {
ret void ret void
} }
!1 = !DIExpression() !1 = !DIExpression()
Show All 13 Lines bb.0:
%0 = COPY %r0 %0 = COPY %r0
%1 = C2_cmpeqi %0, 0 %1 = C2_cmpeqi %0, 0
%2 = A2_tfrsi 123 %2 = A2_tfrsi 123
J2_jumpt %1, %bb.2, implicit-def dead %pc J2_jumpt %1, %bb.2, implicit-def dead %pc
J2_jump %bb.1, implicit-def dead %pc J2_jump %bb.1, implicit-def dead %pc
bb.1: bb.1:
DBG_VALUE debug-use %0, debug-use _, !1, !1 DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
DBG_VALUE debug-use %0, debug-use _, !1, !1 DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
DBG_VALUE debug-use %0, debug-use _, !1, !1 DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
DBG_VALUE debug-use %0, debug-use _, !1, !1 DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
DBG_VALUE debug-use %0, debug-use _, !1, !1 DBG_VALUE debug-use %0, debug-use %noreg, !1, !1
%3 = A2_tfrsi 321 %3 = A2_tfrsi 321
bb.2: bb.2:
%4 = PHI %2, %bb.0, %3, %bb.1 %4 = PHI %2, %bb.0, %3, %bb.1
... ...

llvm/trunk/test/CodeGen/MIR/ARM/bundled-instructions.mir

Show All 22 Lines
name: test1 name: test1
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%r0' } - { reg: '%r0' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0 liveins: %r0
; CHECK-LABEL: name: test1 ; CHECK-LABEL: name: test1
; CHECK: %r1 = t2MOVi 0, 14, _, _ ; CHECK: %r1 = t2MOVi 0, 14, %noreg, %noreg
; CHECK-NEXT: t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, %noreg, implicit-def %cpsr
; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
; CHECK-NEXT: t2IT 12, 8, implicit-def %itstate ; CHECK-NEXT: t2IT 12, 8, implicit-def %itstate
; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, %noreg, implicit internal killed %itstate
; CHECK-NEXT: } ; CHECK-NEXT: }
; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, _ ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, %noreg
; CHECK-NEXT: tBX_RET 14, _, implicit killed %r0 ; CHECK-NEXT: tBX_RET 14, %noreg, implicit killed %r0
%r1 = t2MOVi 0, 14, _, _ %r1 = t2MOVi 0, 14, _, _
t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
t2IT 12, 8, implicit-def %itstate t2IT 12, 8, implicit-def %itstate
%r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate
} }
%r0 = tMOVr killed %r1, 14, _ %r0 = tMOVr killed %r1, 14, _
tBX_RET 14, _, implicit killed %r0 tBX_RET 14, _, implicit killed %r0
... ...
--- ---
name: test2 name: test2
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%r0' } - { reg: '%r0' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %r0 liveins: %r0
; Verify that the next machine instruction can be on the same line as ; Verify that the next machine instruction can be on the same line as
; '{' or '}'. ; '{' or '}'.
; CHECK-LABEL: name: test2 ; CHECK-LABEL: name: test2
; CHECK: %r1 = t2MOVi 0, 14, _, _ ; CHECK: %r1 = t2MOVi 0, 14, %noreg, %noreg
; CHECK-NEXT: t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, %noreg, implicit-def %cpsr
; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
; CHECK-NEXT: t2IT 12, 8, implicit-def %itstate ; CHECK-NEXT: t2IT 12, 8, implicit-def %itstate
; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, %noreg, implicit internal killed %itstate
; CHECK-NEXT: } ; CHECK-NEXT: }
; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, _ ; CHECK-NEXT: %r0 = tMOVr killed %r1, 14, %noreg
; CHECK-NEXT: tBX_RET 14, _, implicit killed %r0 ; CHECK-NEXT: tBX_RET 14, %noreg, implicit killed %r0
%r1 = t2MOVi 0, 14, _, _ %r1 = t2MOVi 0, 14, _, _
t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { t2IT 12, 8, implicit-def %itstate BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr { t2IT 12, 8, implicit-def %itstate
%r1 = t2MOVi 1, 12, killed %cpsr, _, internal implicit killed %itstate %r1 = t2MOVi 1, 12, killed %cpsr, _, internal implicit killed %itstate
} %r0 = tMOVr killed %r1, 14, _ } %r0 = tMOVr killed %r1, 14, _
tBX_RET 14, _, implicit killed %r0 tBX_RET 14, _, implicit killed %r0
... ...

llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir

Show All 20 Lines
# Diamond testcase with unanalyzable instruction in the BB following the # Diamond testcase with unanalyzable instruction in the BB following the
# diamond. # diamond.
# CHECK: body: | # CHECK: body: |
# CHECK: bb.0: # CHECK: bb.0:
# CHECK: %sp = tADDspi %sp, 2, 1, %cpsr # CHECK: %sp = tADDspi %sp, 2, 1, %cpsr
# CHECK: %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp # CHECK: %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp
# CHECK: %sp = tADDspi %sp, 3, 14, _ # CHECK: %sp = tADDspi %sp, 3, 14, %noreg
# CHECK: BX_RET 14, _ # CHECK: BX_RET 14, %noreg

llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir

Show All 34 Lines
# CHECK: bb.0: # CHECK: bb.0:
# CHECK: successors: %bb.2(0x20000000), %bb.1(0x60000000) # CHECK: successors: %bb.2(0x20000000), %bb.1(0x60000000)
# CHECK: %sp = tADDspi %sp, 2, 1, %cpsr # CHECK: %sp = tADDspi %sp, 2, 1, %cpsr
# CHECK: %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp # CHECK: %sp = tADDspi %sp, 1, 0, %cpsr, implicit %sp
# CHECK: Bcc %bb.2, 1, %cpsr # CHECK: Bcc %bb.2, 1, %cpsr
# CHECK: bb.1: # CHECK: bb.1:
# CHECK: %sp = tADDspi %sp, 4, 14, _ # CHECK: %sp = tADDspi %sp, 4, 14, %noreg
# CHECK: BX_RET 14, _ # CHECK: BX_RET 14, %noreg
# CHECK: bb.2: # CHECK: bb.2:
# CHECK: %sp = tADDspi %sp, 3, 14, _ # CHECK: %sp = tADDspi %sp, 3, 14, %noreg
# CHECK: BX_RET 14, _ # CHECK: BX_RET 14, %noreg

llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir

Show All 15 Lines
... ...
# Simple testcase with unanalyzable instructions in both TBB and FBB. # Simple testcase with unanalyzable instructions in both TBB and FBB.
# CHECK: body: | # CHECK: body: |
# CHECK: bb.0: # CHECK: bb.0:
# CHECK: %sp = tADDspi %sp, 2, 0, %cpsr # CHECK: %sp = tADDspi %sp, 2, 0, %cpsr
# CHECK: BX_RET 0, %cpsr # CHECK: BX_RET 0, %cpsr
# CHECK: BX_RET 14, _ # CHECK: BX_RET 14, %noreg

llvm/trunk/test/CodeGen/MIR/ARM/ifcvt_triangleWoCvtToNextEdge.mir

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
# CHECK: bb.1: # CHECK: bb.1:
# CHECK-NOT: successors: %bb # CHECK-NOT: successors: %bb
# CHECK: tBL 14, %cpsr, @__stack_chk_fail # CHECK: tBL 14, %cpsr, @__stack_chk_fail
# CHECK: bb.2: # CHECK: bb.2:
# CHECK-NOT: successors: %bb # CHECK-NOT: successors: %bb
# CHECK: tBL 1, %cpsr, @__stack_chk_fail # CHECK: tBL 1, %cpsr, @__stack_chk_fail
# CHECK: %sp = tADDspi %sp, 2, 14, _ # CHECK: %sp = tADDspi %sp, 2, 14, %noreg
# CHECK: %sp = tADDspi %sp, 2, 14, _ # CHECK: %sp = tADDspi %sp, 2, 14, %noreg
# CHECK: tTAILJMPdND @bar, 14, %cpsr # CHECK: tTAILJMPdND @bar, 14, %cpsr

llvm/trunk/test/CodeGen/MIR/X86/block-address-operands.mir

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines--- |
} }
... ...
--- ---
name: test name: test
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1.block successors: %bb.1.block
; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _ ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test, %ir-block.block), %noreg
%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _ %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
MOV64mr %rip, 1, _, @addr, _, killed %rax MOV64mr %rip, 1, _, @addr, _, killed %rax
JMP64m %rip, 1, _, @addr, _ JMP64m %rip, 1, _, @addr, _
bb.1.block (address-taken): bb.1.block (address-taken):
RETQ RETQ
... ...
--- ---
name: test2 name: test2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1 successors: %bb.1
; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _ ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test2, %ir-block."quoted block"), %noreg
%rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _ %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
MOV64mr %rip, 1, _, @addr, _, killed %rax MOV64mr %rip, 1, _, @addr, _, killed %rax
JMP64m %rip, 1, _, @addr, _ JMP64m %rip, 1, _, @addr, _
bb.1 (address-taken): bb.1 (address-taken):
RETQ RETQ
... ...
--- ---
name: slot_in_other_function name: slot_in_other_function
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi liveins: %rdi
; CHECK-LABEL: name: slot_in_other_function ; CHECK-LABEL: name: slot_in_other_function
; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test3, %ir-block.0), %noreg
%rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
MOV64mr killed %rdi, 1, _, 0, _, killed %rax MOV64mr killed %rdi, 1, _, 0, _, killed %rax
RETQ RETQ
... ...
--- ---
name: test3 name: test3
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1 successors: %bb.1
; CHECK-LABEL: name: test3 ; CHECK-LABEL: name: test3
; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test3, %ir-block.0), %noreg
%rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _ %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
MOV64mr %rip, 1, _, @addr, _, killed %rax MOV64mr %rip, 1, _, @addr, _, killed %rax
JMP64m %rip, 1, _, @addr, _ JMP64m %rip, 1, _, @addr, _
bb.1 (address-taken): bb.1 (address-taken):
RETQ RETQ
... ...
--- ---
name: test4 name: test4
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1.block successors: %bb.1.block
; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _ ; CHECK: %rax = LEA64r %rip, 1, %noreg, blockaddress(@test, %ir-block.block) + 2, %noreg
%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _ %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
MOV64mr %rip, 1, _, @addr, _, killed %rax MOV64mr %rip, 1, _, @addr, _, killed %rax
JMP64m %rip, 1, _, @addr, _ JMP64m %rip, 1, _, @addr, _
bb.1.block (address-taken): bb.1.block (address-taken):
RETQ RETQ
... ...

llvm/trunk/test/CodeGen/MIR/X86/constant-pool.mir

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Linesconstants:
- id: 0 - id: 0
value: 'double 3.250000e+00' value: 'double 3.250000e+00'
alignment: 8 alignment: 8
- id: 1 - id: 1
value: 'float 6.250000e+00' value: 'float 6.250000e+00'
alignment: 4 alignment: 4
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg
; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.1, %noreg
%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
%xmm1 = CVTSS2SDrr killed %xmm1 %xmm1 = CVTSS2SDrr killed %xmm1
%xmm0 = MULSDrr killed %xmm0, killed %xmm1 %xmm0 = MULSDrr killed %xmm0, killed %xmm1
RETQ %xmm0 RETQ %xmm0
... ...
--- ---
# Verify that alignment can be inferred: # Verify that alignment can be inferred:
Show All 38 Linesconstants:
- id: 0 - id: 0
value: 'double 3.250000e+00' value: 'double 3.250000e+00'
alignment: 128 alignment: 128
- id: 1 - id: 1
value: 'float 6.250000e+00' value: 'float 6.250000e+00'
alignment: 1 alignment: 1
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg
; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.1, %noreg
%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _ %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
%xmm1 = CVTSS2SDrr killed %xmm1 %xmm1 = CVTSS2SDrr killed %xmm1
%xmm0 = MULSDrr killed %xmm0, killed %xmm1 %xmm0 = MULSDrr killed %xmm0, killed %xmm1
RETQ %xmm0 RETQ %xmm0
... ...
--- ---
# CHECK: name: test4 # CHECK: name: test4
name: test4 name: test4
constants: constants:
- id: 0 - id: 0
value: 'double 3.250000e+00' value: 'double 3.250000e+00'
- id: 1 - id: 1
value: 'float 6.250000e+00' value: 'float 6.250000e+00'
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _ ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.1 - 12, %noreg
; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _ ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, %noreg, %const.0 + 8, %noreg
%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _ %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _ %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
%xmm1 = CVTSS2SDrr killed %xmm1 %xmm1 = CVTSS2SDrr killed %xmm1
%xmm0 = MULSDrr killed %xmm0, killed %xmm1 %xmm0 = MULSDrr killed %xmm0, killed %xmm1
RETQ %xmm0 RETQ %xmm0
... ...

llvm/trunk/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir

Show All 25 LinesfixedStack:
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true } - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true }
stack: stack:
- { id: 0, name: b, offset: -8, size: 4, alignment: 4 } - { id: 0, name: b, offset: -8, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp
CFI_INSTRUCTION def_cfa_offset 8 CFI_INSTRUCTION def_cfa_offset 8
; CHECK: name: test ; CHECK: name: test
; CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16) ; CHECK: %eax = MOV32rm %esp, 1, %noreg, 8, %noreg :: (load 4 from %fixed-stack.0, align 16)
%eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16) %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b) MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b)
%edx = POP32r implicit-def %esp, implicit %esp %edx = POP32r implicit-def %esp, implicit %esp
RETL %eax RETL %eax
... ...

llvm/trunk/test/CodeGen/MIR/X86/global-value-operands.mir

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines--- |
} }
... ...
--- ---
# CHECK: name: inc # CHECK: name: inc
name: inc name: inc
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: %rax = MOV64rm %rip, 1, _, @G, _ ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @G, %noreg
%rax = MOV64rm %rip, 1, _, @G, _ %rax = MOV64rm %rip, 1, _, @G, _
%eax = MOV32rm %rax, 1, _, 0, _ %eax = MOV32rm %rax, 1, _, 0, _
%eax = INC32r %eax, implicit-def %eflags %eax = INC32r %eax, implicit-def %eflags
RETQ %eax RETQ %eax
... ...
--- ---
# CHECK: name: inc2 # CHECK: name: inc2
name: inc2 name: inc2
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: %rax = MOV64rm %rip, 1, _, @0, _ ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @0, %noreg
%rax = MOV64rm %rip, 1, _, @0, _ %rax = MOV64rm %rip, 1, _, @0, _
%eax = MOV32rm %rax, 1, _, 0, _ %eax = MOV32rm %rax, 1, _, 0, _
%eax = INC32r %eax, implicit-def %eflags %eax = INC32r %eax, implicit-def %eflags
RETQ %eax RETQ %eax
... ...
--- ---
name: test name: test
body: | body: |
Show All 40 Lines bb.0.entry:
MOV32mr killed %rcx, 1, _, 0, _, %eax MOV32mr killed %rcx, 1, _, 0, _, %eax
RETQ %eax RETQ %eax
... ...
--- ---
# CHECK: name: tf # CHECK: name: tf
name: tf name: tf
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _ ; CHECK: %rax = MOV64rm %rip, 1, %noreg, target-flags(x86-gotpcrel) @G, %noreg
%rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _ %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _
%eax = MOV32rm %rax, 1, _, 0, _ %eax = MOV32rm %rax, 1, _, 0, _
%eax = INC32r %eax, implicit-def %eflags %eax = INC32r %eax, implicit-def %eflags
RETQ %eax RETQ %eax
... ...

llvm/trunk/test/CodeGen/MIR/X86/instructions-debug-location.mir

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Linesregisters:
- { id: 0, class: gr32 } - { id: 0, class: gr32 }
frameInfo: frameInfo:
maxAlignment: 4 maxAlignment: 4
stack: stack:
- { id: 0, name: x.addr, size: 4, alignment: 4 } - { id: 0, name: x.addr, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %edi liveins: %edi
; CHECK: DBG_VALUE debug-use _, 0, !11, !DIExpression(), debug-location !12 ; CHECK: DBG_VALUE debug-use %noreg, 0, !11, !DIExpression(), debug-location !12
; CHECK: %eax = COPY %0, debug-location !13 ; CHECK: %eax = COPY %0, debug-location !13
; CHECK: RETQ %eax, debug-location !13 ; CHECK: RETQ %eax, debug-location !13
%0 = COPY %edi %0 = COPY %edi
DBG_VALUE debug-use _, 0, !12, !DIExpression(), debug-location !13 DBG_VALUE debug-use _, 0, !12, !DIExpression(), debug-location !13
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
%eax = COPY %0, debug-location !14 %eax = COPY %0, debug-location !14
RETQ %eax, debug-location !14 RETQ %eax, debug-location !14
... ...
--- ---
name: test_typed_immediates name: test_typed_immediates
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gr32 } - { id: 0, class: gr32 }
frameInfo: frameInfo:
maxAlignment: 4 maxAlignment: 4
stack: stack:
- { id: 0, name: x.addr, size: 4, alignment: 4 } - { id: 0, name: x.addr, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %edi liveins: %edi
%0 = COPY %edi %0 = COPY %edi
; CHECK: DBG_VALUE _, i32 0, !DIExpression(), !12 ; CHECK: DBG_VALUE %noreg, i32 0, !DIExpression(), !12
; CHECK-NEXT: DBG_VALUE _, i64 -22, !DIExpression(), !12 ; CHECK-NEXT: DBG_VALUE %noreg, i64 -22, !DIExpression(), !12
; CHECK-NEXT: DBG_VALUE _, i128 123492148938512984928424384934328985928, !DIExpression(), !12 ; CHECK-NEXT: DBG_VALUE %noreg, i128 123492148938512984928424384934328985928, !DIExpression(), !12
DBG_VALUE _, i32 0, !DIExpression(), !13 DBG_VALUE _, i32 0, !DIExpression(), !13
DBG_VALUE _, i64 -22, !DIExpression(), !13 DBG_VALUE _, i64 -22, !DIExpression(), !13
DBG_VALUE _, i128 123492148938512984928424384934328985928, !DIExpression(), !13 DBG_VALUE _, i128 123492148938512984928424384934328985928, !DIExpression(), !13
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
%eax = COPY %0 %eax = COPY %0
RETQ %eax RETQ %eax
... ...

llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines bb.0.entry:
successors: %bb.2.def, %bb.1.entry successors: %bb.2.def, %bb.1.entry
%eax = MOV32rr %edi, implicit-def %rax %eax = MOV32rr %edi, implicit-def %rax
CMP32ri8 %edi, 3, implicit-def %eflags CMP32ri8 %edi, 3, implicit-def %eflags
JA_1 %bb.2.def, implicit %eflags JA_1 %bb.2.def, implicit %eflags
bb.1.entry: bb.1.entry:
successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4 successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _ ; CHECK: %rcx = LEA64r %rip, 1, %noreg, %jump-table.0, %noreg
%rcx = LEA64r %rip, 1, _, %jump-table.0, _ %rcx = LEA64r %rip, 1, _, %jump-table.0, _
%rax = MOVSX64rm32 %rcx, 4, %rax, 0, _ %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
%rax = ADD64rr %rax, %rcx, implicit-def %eflags %rax = ADD64rr %rax, %rcx, implicit-def %eflags
JMP64r %rax JMP64r %rax
bb.2.def: bb.2.def:
%eax = MOV32r0 implicit-def %eflags %eax = MOV32r0 implicit-def %eflags
RETQ %eax RETQ %eax
Show All 27 Lines bb.0.entry:
%eax = MOV32rr %edi, implicit-def %rax %eax = MOV32rr %edi, implicit-def %rax
CMP32ri8 %edi, 3, implicit-def %eflags CMP32ri8 %edi, 3, implicit-def %eflags
JA_1 %bb.2.def, implicit %eflags JA_1 %bb.2.def, implicit %eflags
bb.1.entry: bb.1.entry:
successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4 successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
; Verify that the printer will use an id of 0 for this jump table: ; Verify that the printer will use an id of 0 for this jump table:
; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _ ; CHECK: %rcx = LEA64r %rip, 1, %noreg, %jump-table.0, %noreg
%rcx = LEA64r %rip, 1, _, %jump-table.1, _ %rcx = LEA64r %rip, 1, _, %jump-table.1, _
%rax = MOVSX64rm32 %rcx, 4, %rax, 0, _ %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
%rax = ADD64rr %rax, %rcx, implicit-def %eflags %rax = ADD64rr %rax, %rcx, implicit-def %eflags
JMP64r %rax JMP64r %rax
bb.2.def: bb.2.def:
%eax = MOV32r0 implicit-def %eflags %eax = MOV32r0 implicit-def %eflags
RETQ %eax RETQ %eax
Show All 17 Lines

llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir

Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Lines
--- ---
name: test name: test
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi liveins: %rdi
; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a) ; CHECK: %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.a)
; CHECK-NEXT: MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a) ; CHECK-NEXT: MOV32mi killed %rdi, 1, %noreg, 0, %noreg, 42 :: (store 4 into %ir.a)
%eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a) %eax = MOV32rm %rdi, 1, _, 0, _ :: (load 4 from %ir.a)
MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a) MOV32mi killed %rdi, 1, _, 0, _, 42 :: (store 4 into %ir.a)
RETQ %eax RETQ %eax
... ...
--- ---
name: test2 name: test2
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
body: | body: |
bb.0.entry2: bb.0.entry2:
liveins: %rdi liveins: %rdi
; CHECK: INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value") ; CHECK: INC32m killed %rdi, 1, %noreg, 0, %noreg, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")
INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value") INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir."a value"), (load 4 from %ir."a value")
RETQ RETQ
... ...
--- ---
name: test3 name: test3
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
frameInfo: frameInfo:
maxAlignment: 4 maxAlignment: 4
stack: stack:
- { id: 0, offset: -12, size: 4, alignment: 4 } - { id: 0, offset: -12, size: 4, alignment: 4 }
body: | body: |
bb.0.entry3: bb.0.entry3:
liveins: %rdi liveins: %rdi
; Verify that the unnamed local values can be serialized. ; Verify that the unnamed local values can be serialized.
; CHECK-LABEL: name: test3 ; CHECK-LABEL: name: test3
; CHECK: %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.0) ; CHECK: %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.0)
; CHECK: MOV32mr %rsp, 1, _, -4, _, killed %eax :: (store 4 into %ir.1) ; CHECK: MOV32mr %rsp, 1, %noreg, -4, %noreg, killed %eax :: (store 4 into %ir.1)
%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.0) %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.0)
%eax = INC32r killed %eax, implicit-def dead %eflags %eax = INC32r killed %eax, implicit-def dead %eflags
MOV32mr %rsp, 1, _, -4, _, killed %eax :: (store 4 into %ir.1) MOV32mr %rsp, 1, _, -4, _, killed %eax :: (store 4 into %ir.1)
RETQ RETQ
... ...
--- ---
name: volatile_inc name: volatile_inc
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi liveins: %rdi
; CHECK: name: volatile_inc ; CHECK: name: volatile_inc
; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x) ; CHECK: %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg :: (volatile load 4 from %ir.x)
; CHECK: MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x) ; CHECK: MOV32mr killed %rdi, 1, %noreg, 0, %noreg, %eax :: (volatile store 4 into %ir.x)
%eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x) %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile load 4 from %ir.x)
%eax = INC32r killed %eax, implicit-def dead %eflags %eax = INC32r killed %eax, implicit-def dead %eflags
MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x) MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)
RETQ %eax RETQ %eax
... ...
--- ---
name: non_temporal_store name: non_temporal_store
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%esi' } - { reg: '%esi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %esi, %rdi liveins: %esi, %rdi
; CHECK: name: non_temporal_store ; CHECK: name: non_temporal_store
; CHECK: MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a) ; CHECK: MOVNTImr killed %rdi, 1, %noreg, 0, %noreg, killed %esi :: (non-temporal store 4 into %ir.a)
MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a) MOVNTImr killed %rdi, 1, _, 0, _, killed %esi :: (non-temporal store 4 into %ir.a)
RETQ RETQ
... ...
--- ---
name: invariant_load name: invariant_load
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi liveins: %rdi
; CHECK: name: invariant_load ; CHECK: name: invariant_load
; CHECK: %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x) ; CHECK: %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg :: (invariant load 4 from %ir.x)
%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x) %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (invariant load 4 from %ir.x)
RETQ %eax RETQ %eax
... ...
--- ---
name: memory_offset name: memory_offset
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi liveins: %rdi
; CHECK: name: memory_offset ; CHECK: name: memory_offset
; CHECK: %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec) ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, %noreg, 0, %noreg :: (load 16 from %ir.vec)
; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16) ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, %noreg, 16, %noreg :: (load 16 from %ir.vec + 16)
; CHECK: MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec) ; CHECK: MOVAPSmr %rdi, 1, %noreg, 0, %noreg, killed %xmm0 :: (store 16 into %ir.vec)
; CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16) ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, %noreg, 16, %noreg, killed %xmm1 :: (store 16 into %ir.vec + 16)
%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec) %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec)
%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16) %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16)
%xmm2 = FsFLD0SS %xmm2 = FsFLD0SS
%xmm1 = MOVSSrr killed %xmm1, killed %xmm2 %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec) MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec)
MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16) MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16)
RETQ RETQ
... ...
--- ---
name: memory_alignment name: memory_alignment
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi liveins: %rdi
; CHECK: name: memory_alignment ; CHECK: name: memory_alignment
; CHECK: %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32) ; CHECK: %xmm0 = MOVAPSrm %rdi, 1, %noreg, 0, %noreg :: (load 16 from %ir.vec, align 32)
; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) ; CHECK-NEXT: %xmm1 = MOVAPSrm %rdi, 1, %noreg, 16, %noreg :: (load 16 from %ir.vec + 16, align 32)
; CHECK: MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32) ; CHECK: MOVAPSmr %rdi, 1, %noreg, 0, %noreg, killed %xmm0 :: (store 16 into %ir.vec, align 32)
; CHECK-NEXT: MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) ; CHECK-NEXT: MOVAPSmr killed %rdi, 1, %noreg, 16, %noreg, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32) %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align 32)
%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32) %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
%xmm2 = FsFLD0SS %xmm2 = FsFLD0SS
%xmm1 = MOVSSrr killed %xmm1, killed %xmm2 %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32) MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32) MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
RETQ RETQ
... ...
--- ---
name: constant_pool_psv name: constant_pool_psv
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%xmm0' } - { reg: '%xmm0' }
constants: constants:
- id: 0 - id: 0
value: 'double 3.250000e+00' value: 'double 3.250000e+00'
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %xmm0 liveins: %xmm0
; CHECK: name: constant_pool_psv ; CHECK: name: constant_pool_psv
; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool) ; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg :: (load 8 from constant-pool)
; CHECK-NEXT: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8) ; CHECK-NEXT: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, %noreg, %const.0, %noreg :: (load 8 from constant-pool + 8)
%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool) %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool)
%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8) %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _ :: (load 8 from constant-pool + 8)
RETQ %xmm0 RETQ %xmm0
... ...
--- ---
name: stack_psv name: stack_psv
tracksRegLiveness: true tracksRegLiveness: true
frameInfo: frameInfo:
stackSize: 24 stackSize: 24
maxAlignment: 16 maxAlignment: 16
adjustsStack: true adjustsStack: true
hasCalls: true hasCalls: true
maxCallFrameSize: 16 maxCallFrameSize: 16
fixedStack: fixedStack:
- { id: 0, offset: 0, size: 10, alignment: 16, isImmutable: true, isAliased: false } - { id: 0, offset: 0, size: 10, alignment: 16, isImmutable: true, isAliased: false }
body: | body: |
bb.0.entry: bb.0.entry:
%rsp = frame-setup SUB64ri8 %rsp, 24, implicit-def dead %eflags %rsp = frame-setup SUB64ri8 %rsp, 24, implicit-def dead %eflags
CFI_INSTRUCTION def_cfa_offset 32 CFI_INSTRUCTION def_cfa_offset 32
LD_F80m %rsp, 1, _, 32, _, implicit-def dead %fpsw LD_F80m %rsp, 1, %noreg, 32, %noreg, implicit-def dead %fpsw
; CHECK: name: stack_psv ; CHECK: name: stack_psv
; CHECK: ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16) ; CHECK: ST_FP80m %rsp, 1, %noreg, 0, %noreg, implicit-def dead %fpsw :: (store 10 into stack, align 16)
ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16) ST_FP80m %rsp, 1, _, 0, _, implicit-def dead %fpsw :: (store 10 into stack, align 16)
CALL64pcrel32 $cosl, csr_64, implicit %rsp, implicit-def %rsp, implicit-def %fp0 CALL64pcrel32 $cosl, csr_64, implicit %rsp, implicit-def %rsp, implicit-def %fp0
%rsp = ADD64ri8 %rsp, 24, implicit-def dead %eflags %rsp = ADD64ri8 %rsp, 24, implicit-def dead %eflags
RETQ RETQ
... ...
--- ---
name: got_psv name: got_psv
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: name: got_psv ; CHECK: name: got_psv
; CHECK: %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got) ; CHECK: %rax = MOV64rm %rip, 1, %noreg, @G, %noreg :: (load 8 from got)
%rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got) %rax = MOV64rm %rip, 1, _, @G, _ :: (load 8 from got)
%eax = MOV32rm killed %rax, 1, _, 0, _ %eax = MOV32rm killed %rax, 1, _, 0, _
%eax = INC32r killed %eax, implicit-def dead %eflags %eax = INC32r killed %eax, implicit-def dead %eflags
RETQ %eax RETQ %eax
... ...
--- ---
name: global_value name: global_value
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
%rax = MOV64rm %rip, 1, _, @G, _ %rax = MOV64rm %rip, 1, _, @G, _
; CHECK-LABEL: name: global_value ; CHECK-LABEL: name: global_value
; CHECK: %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @G) ; CHECK: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg, implicit-def %rax :: (load 4 from @G)
; CHECK: %ecx = MOV32rm killed %rcx, 1, _, 0, _, implicit-def %rcx :: (load 4 from @0) ; CHECK: %ecx = MOV32rm killed %rcx, 1, %noreg, 0, %noreg, implicit-def %rcx :: (load 4 from @0)
%eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @G) %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @G)
%rcx = MOV64rm %rip, 1, _, @0, _ %rcx = MOV64rm %rip, 1, _, @0, _
%ecx = MOV32rm killed %rcx, 1, _, 0, _, implicit-def %rcx :: (load 4 from @0) %ecx = MOV32rm killed %rcx, 1, _, 0, _, implicit-def %rcx :: (load 4 from @0)
%eax = LEA64_32r killed %rax, 1, killed %rcx, 1, _ %eax = LEA64_32r killed %rax, 1, killed %rcx, 1, _
RETQ %eax RETQ %eax
... ...
--- ---
name: jumptable_psv name: jumptable_psv
Show All 15 Lines bb.0.entry:
JA_1 %bb.2.def, implicit killed %eflags JA_1 %bb.2.def, implicit killed %eflags
bb.1.entry: bb.1.entry:
successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4 successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
liveins: %rax liveins: %rax
%rcx = LEA64r %rip, 1, _, %jump-table.0, _ %rcx = LEA64r %rip, 1, _, %jump-table.0, _
; CHECK: name: jumptable_psv ; CHECK: name: jumptable_psv
; CHECK: %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8) ; CHECK: %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, %noreg :: (load 4 from jump-table, align 8)
%rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8) %rax = MOVSX64rm32 %rcx, 4, killed %rax, 0, _ :: (load 4 from jump-table, align 8)
%rax = ADD64rr killed %rax, killed %rcx, implicit-def dead %eflags %rax = ADD64rr killed %rax, killed %rcx, implicit-def dead %eflags
JMP64r killed %rax JMP64r killed %rax
bb.2.def: bb.2.def:
%eax = MOV32r0 implicit-def dead %eflags %eax = MOV32r0 implicit-def dead %eflags
RETQ %eax RETQ %eax
Show All 15 Lines
... ...
--- ---
name: tbaa_metadata name: tbaa_metadata
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
%rax = MOV64rm %rip, 1, _, @a, _ :: (load 8 from got) %rax = MOV64rm %rip, 1, _, @a, _ :: (load 8 from got)
; CHECK-LABEL: name: tbaa_metadata ; CHECK-LABEL: name: tbaa_metadata
; CHECK: %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @a, !tbaa !2) ; CHECK: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg, implicit-def %rax :: (load 4 from @a, !tbaa !2)
; CHECK-NEXT: %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.total_len2, !tbaa !6) ; CHECK-NEXT: %eax = MOV32rm killed %rax, 1, %noreg, 0, %noreg :: (load 4 from %ir.total_len2, !tbaa !6)
%eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @a, !tbaa !2) %eax = MOV32rm killed %rax, 1, _, 0, _, implicit-def %rax :: (load 4 from @a, !tbaa !2)
%eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.total_len2, !tbaa !6) %eax = MOV32rm killed %rax, 1, _, 0, _ :: (load 4 from %ir.total_len2, !tbaa !6)
RETQ %eax RETQ %eax
... ...
--- ---
name: aa_scope name: aa_scope
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%rsi' } - { reg: '%rsi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
; CHECK-LABEL: name: aa_scope ; CHECK-LABEL: name: aa_scope
; CHECK: %xmm0 = MOVSSrm %rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9) ; CHECK: %xmm0 = MOVSSrm %rsi, 1, %noreg, 0, %noreg :: (load 4 from %ir.c, !alias.scope !9)
%xmm0 = MOVSSrm %rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9) %xmm0 = MOVSSrm %rsi, 1, _, 0, _ :: (load 4 from %ir.c, !alias.scope !9)
; CHECK-NEXT: MOVSSmr %rdi, 1, _, 20, _, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9) ; CHECK-NEXT: MOVSSmr %rdi, 1, %noreg, 20, %noreg, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9)
MOVSSmr %rdi, 1, _, 20, _, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9) MOVSSmr %rdi, 1, _, 20, _, killed %xmm0 :: (store 4 into %ir.arrayidx.i, !noalias !9)
%xmm0 = MOVSSrm killed %rsi, 1, _, 0, _ :: (load 4 from %ir.c) %xmm0 = MOVSSrm killed %rsi, 1, _, 0, _ :: (load 4 from %ir.c)
MOVSSmr killed %rdi, 1, _, 28, _, killed %xmm0 :: (store 4 into %ir.arrayidx) MOVSSmr killed %rdi, 1, _, 28, _, killed %xmm0 :: (store 4 into %ir.arrayidx)
RETQ RETQ
... ...
--- ---
name: range_metadata name: range_metadata
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi liveins: %rdi
; CHECK-LABEL: name: range_metadata ; CHECK-LABEL: name: range_metadata
; CHECK: %al = MOV8rm killed %rdi, 1, _, 0, _ :: (load 1 from %ir.x, !range !11) ; CHECK: %al = MOV8rm killed %rdi, 1, %noreg, 0, %noreg :: (load 1 from %ir.x, !range !11)
%al = MOV8rm killed %rdi, 1, _, 0, _ :: (load 1 from %ir.x, !range !11) %al = MOV8rm killed %rdi, 1, _, 0, _ :: (load 1 from %ir.x, !range !11)
RETQ %al RETQ %al
... ...
--- ---
name: gep_value name: gep_value
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi liveins: %rdi
%rax = MOV64rm %rip, 1, _, @values, _ :: (load 8 from got) %rax = MOV64rm %rip, 1, _, @values, _ :: (load 8 from got)
; CHECK-LABEL: gep_value ; CHECK-LABEL: gep_value
; CHECK: MOV32mr killed %rax, 1, _, 0, _, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16) ; CHECK: MOV32mr killed %rax, 1, %noreg, 0, %noreg, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16)
MOV32mr killed %rax, 1, _, 0, _, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16) MOV32mr killed %rax, 1, _, 0, _, %edi, implicit killed %rdi :: (store 4 into `i32* getelementptr inbounds ([50 x %st], [50 x %st]* @values, i64 0, i64 0, i32 0)`, align 16)
RETQ RETQ
... ...
--- ---
name: undef_value name: undef_value
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: undef_value ; CHECK-LABEL: name: undef_value
; CHECK: %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8 from `i8** undef`) ; CHECK: %rax = MOV64rm undef %rax, 1, %noreg, 0, %noreg :: (load 8 from `i8** undef`)
%rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8 from `i8** undef`) %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8 from `i8** undef`)
RETQ %rax RETQ %rax
... ...
--- ---
# Test memory operand without associated value. # Test memory operand without associated value.
# CHECK-LABEL: name: dummy0 # CHECK-LABEL: name: dummy0
# CHECK: %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8) # CHECK: %rax = MOV64rm undef %rax, 1, %noreg, 0, %noreg :: (load 8)
name: dummy0 name: dummy0
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
%rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8) %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8)
RETQ %rax RETQ %rax
... ...
--- ---
# Test parsing of stack references in machine memory operands. # Test parsing of stack references in machine memory operands.
# CHECK-LABEL: name: dummy1 # CHECK-LABEL: name: dummy1
# CHECK: %rax = MOV64rm %rsp, 1, _, 0, _ :: (load 8 from %stack.0) # CHECK: %rax = MOV64rm %rsp, 1, %noreg, 0, %noreg :: (load 8 from %stack.0)
name: dummy1 name: dummy1
tracksRegLiveness: true tracksRegLiveness: true
stack: stack:
- { id: 0, size: 4, alignment: 4 } - { id: 0, size: 4, alignment: 4 }
body: | body: |
bb.0: bb.0:
%rax = MOV64rm %rsp, 1, _, 0, _ :: (load 8 from %stack.0) %rax = MOV64rm %rsp, 1, _, 0, _ :: (load 8 from %stack.0)
RETQ %rax RETQ %rax
... ...

llvm/trunk/test/CodeGen/MIR/X86/metadata-operands.mir

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
frameInfo: frameInfo:
maxAlignment: 4 maxAlignment: 4
stack: stack:
- { id: 0, name: x.addr, size: 4, alignment: 4 } - { id: 0, name: x.addr, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %edi liveins: %edi
; CHECK: %0:gr32 = COPY %edi ; CHECK: %0:gr32 = COPY %edi
; CHECK-NEXT: DBG_VALUE _, 0, !11, !DIExpression() ; CHECK-NEXT: DBG_VALUE %noreg, 0, !11, !DIExpression()
%0 = COPY %edi %0 = COPY %edi
DBG_VALUE _, 0, !12, !DIExpression() DBG_VALUE _, 0, !12, !DIExpression()
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
%eax = COPY %0 %eax = COPY %0
RETQ %eax RETQ %eax
... ...

llvm/trunk/test/CodeGen/MIR/X86/null-register-operands.mir

Show All 9 Lines--- |
} }
... ...
--- ---
# CHECK: name: deref # CHECK: name: deref
name: deref name: deref
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK: %eax = MOV32rm %rdi, 1, _, 0, _ ; CHECK: %eax = MOV32rm %rdi, 1, %noreg, 0, %noreg
; CHECK-NEXT: RETQ %eax ; CHECK-NEXT: RETQ %eax
%eax = MOV32rm %rdi, 1, _, 0, %noreg %eax = MOV32rm %rdi, 1, _, 0, %noreg
RETQ %eax RETQ %eax
... ...

llvm/trunk/test/CodeGen/MIR/X86/roundtrip.mir

# RUN: llc -o - %s -mtriple=x86_64-- -run-pass=none | llc -o - -x mir - -mtriple=x86_64-- -run-pass=none | FileCheck %s # RUN: llc -o - %s -mtriple=x86_64-- -run-pass=none | llc -o - -x mir - -mtriple=x86_64-- -run-pass=none | FileCheck %s
--- ---
# CHECK-LABEL: name: func0 # CHECK-LABEL: name: func0
# CHECK: registers: # CHECK: registers:
# CHECK: - { id: 0, class: gr32, preferred-register: '' } # CHECK: - { id: 0, class: gr32, preferred-register: '' }
# CHECK: - { id: 1, class: gr32, preferred-register: '' } # CHECK: - { id: 1, class: gr32, preferred-register: '' }
# CHECK: body: | # CHECK: body: |
# CHECK: bb.0: # CHECK: bb.0:
# CHECK: %0:gr32 = MOV32r0 implicit-def %eflags # CHECK: %0:gr32 = MOV32r0 implicit-def %eflags
# CHECK: dead %1:gr32 = COPY %0 # CHECK: dead %1:gr32 = COPY %0
# CHECK: MOV32mr undef %rcx, 1, _, 0, _, killed %0 :: (volatile store 4) # CHECK: MOV32mr undef %rcx, 1, %noreg, 0, %noreg, killed %0 :: (volatile store 4)
# CHECK: RETQ undef %eax # CHECK: RETQ undef %eax
name: func0 name: func0
body: | body: |
bb.0: bb.0:
%0 : gr32 = MOV32r0 implicit-def %eflags %0 : gr32 = MOV32r0 implicit-def %eflags
dead %1 : gr32 = COPY %0 dead %1 : gr32 = COPY %0
MOV32mr undef %rcx, 1, _, 0, _, killed %0 :: (volatile store 4) MOV32mr undef %rcx, 1, _, 0, _, killed %0 :: (volatile store 4)
RETQ undef %eax RETQ undef %eax
... ...

llvm/trunk/test/CodeGen/MIR/X86/stack-object-operands.mir

Show All 26 Lines
fixedStack: fixedStack:
- { id: 0, offset: 0, size: 4, isImmutable: true, isAliased: false } - { id: 0, offset: 0, size: 4, isImmutable: true, isAliased: false }
stack: stack:
- { id: 0, name: b, size: 4, alignment: 4 } - { id: 0, name: b, size: 4, alignment: 4 }
- { id: 1, size: 4, alignment: 4 } - { id: 1, size: 4, alignment: 4 }
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test ; CHECK-LABEL: name: test
; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, %noreg, 0, %noreg
; CHECK: MOV32mr %stack.0.b, 1, _, 0, _, [[MOV32rm]] ; CHECK: MOV32mr %stack.0.b, 1, %noreg, 0, %noreg, [[MOV32rm]]
; CHECK: MOV32mi %stack.1, 1, _, 0, _, 2 ; CHECK: MOV32mi %stack.1, 1, %noreg, 0, %noreg, 2
; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, _, 0, _ ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.0.b, 1, %noreg, 0, %noreg
; CHECK: %eax = COPY [[MOV32rm1]] ; CHECK: %eax = COPY [[MOV32rm1]]
; CHECK: RETL %eax ; CHECK: RETL %eax
%0 = MOV32rm %fixed-stack.0, 1, _, 0, _ %0 = MOV32rm %fixed-stack.0, 1, _, 0, _
MOV32mr %stack.0.b, 1, _, 0, _, %0 MOV32mr %stack.0.b, 1, _, 0, _, %0
MOV32mi %stack.1, 1, _, 0, _, 2 MOV32mi %stack.1, 1, _, 0, _, 2
%1 = MOV32rm %stack.0, 1, _, 0, _ %1 = MOV32rm %stack.0, 1, _, 0, _
%eax = COPY %1 %eax = COPY %1
RETL %eax RETL %eax
... ...

llvm/trunk/test/CodeGen/Mips/const-mult.ll

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; CHECK64-DAG: dsrl $[[R14:[0-9]+]], $[[R13]], 32 ; CHECK64-DAG: dsrl $[[R14:[0-9]+]], $[[R13]], 32
; CHECK64-DAG: dsubu $[[R15:[0-9]+]], $[[R11]], $[[R14]] ; CHECK64-DAG: dsubu $[[R15:[0-9]+]], $[[R11]], $[[R14]]
; CHECK64: dnegu ${{[0-9]+}}, $[[R5]] ; CHECK64: dnegu ${{[0-9]+}}, $[[R5]]
define i128 @mul170141183460469231731687303715884105723_128(i128 signext %a) { define i128 @mul170141183460469231731687303715884105723_128(i128 signext %a) {
entry: entry:
%mul = mul nsw i128 %a, 170141183460469231731687303715884105723 %mul = mul nsw i128 %a, 170141183460469231731687303715884105723
ret i128 %mul ret i128 %mul
} }
No newline at end of file

llvm/trunk/test/CodeGen/Mips/mips64signextendsesf.ll

Show First 20 Lines • Show All 205 Lines • ▼ Show 20 Lines
; CHECK-NOT: dsrl ; CHECK-NOT: dsrl
; CHECK-NOT: lwu ; CHECK-NOT: lwu
} }
declare float @fminf(float, float) #1 declare float @fminf(float, float) #1
attributes #0 = { nounwind "use-soft-float"="true" } attributes #0 = { nounwind "use-soft-float"="true" }
attributes #1 = { nounwind readnone "use-soft-float"="true" } attributes #1 = { nounwind readnone "use-soft-float"="true" }
No newline at end of file

llvm/trunk/test/CodeGen/PowerPC/cxx_tlscc64.ll

Show All 34 Lines
define cxx_fast_tlscc nonnull i32* @_ZTW4sum1() nounwind { define cxx_fast_tlscc nonnull i32* @_ZTW4sum1() nounwind {
ret i32* @sum1 ret i32* @sum1
} }
define cxx_fast_tlscc i32* @_ZTW4sum2() #0 { define cxx_fast_tlscc i32* @_ZTW4sum2() #0 {
ret i32* @sum1 ret i32* @sum1
} }
attributes #0 = { nounwind "no-frame-pointer-elim"="true" } attributes #0 = { nounwind "no-frame-pointer-elim"="true" }
No newline at end of file

llvm/trunk/test/CodeGen/PowerPC/debuginfo-split-int.ll

Show All 21 Lines
; ;
; This file is a slight tweak of that output, with irrelevant ; This file is a slight tweak of that output, with irrelevant
; lifetime intrinsics, metadata, and debug info being removed. ; lifetime intrinsics, metadata, and debug info being removed.
; CHECK: [[DL:![0-9]+]] = !DILocalVariable(name: "result" ; CHECK: [[DL:![0-9]+]] = !DILocalVariable(name: "result"
; ;
; High 32 bits in R3, low 32 bits in R4 ; High 32 bits in R3, low 32 bits in R4
; CHECK: %0:gprc = COPY %r3 ; CHECK: %0:gprc = COPY %r3
; CHECK: DBG_VALUE debug-use %0, debug-use _, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 0, 32) ; CHECK: DBG_VALUE debug-use %0, debug-use %noreg, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 0, 32)
; CHECK: %1:gprc = COPY %r4 ; CHECK: %1:gprc = COPY %r4
; CHECK: DBG_VALUE debug-use %1, debug-use _, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 32, 32) ; CHECK: DBG_VALUE debug-use %1, debug-use %noreg, [[DL]], !DIExpression(DW_OP_LLVM_fragment, 32, 32)
define void @bar() local_unnamed_addr #0 !dbg !6 { define void @bar() local_unnamed_addr #0 !dbg !6 {
%1 = alloca i64, align 8 %1 = alloca i64, align 8
%2 = tail call i64 @foo() %2 = tail call i64 @foo()
tail call void @llvm.dbg.value(metadata i64 %2, metadata !10, metadata !DIExpression()), !dbg !13 tail call void @llvm.dbg.value(metadata i64 %2, metadata !10, metadata !DIExpression()), !dbg !13
store volatile i64 %2, i64* %1, align 8 store volatile i64 %2, i64* %1, align 8
ret void ret void
} }
Show All 26 Lines

llvm/trunk/test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll

Show All 12 Lines
; Do not skip register r4 because of register alignment in soft float mode. Instead skipping ; Do not skip register r4 because of register alignment in soft float mode. Instead skipping
; put in r4 part of first argument for printf function (long double). ; put in r4 part of first argument for printf function (long double).
; CHECK: lwzu 4, x@l({{[0-9]+}}) ; CHECK: lwzu 4, x@l({{[0-9]+}})
declare i32 @printf(i8* nocapture readonly, ...) #0 declare i32 @printf(i8* nocapture readonly, ...) #0
attributes #0 = { "use-soft-float"="true" } attributes #0 = { "use-soft-float"="true" }
No newline at end of file

llvm/trunk/test/CodeGen/SPARC/LeonItinerariesUT.ll

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Linesentry:
%1 = load float, float* %b, align 8 %1 = load float, float* %b, align 8
%2 = load float, float* %c, align 8 %2 = load float, float* %c, align 8
%3 = load float, float* %d, align 8 %3 = load float, float* %d, align 8
%4 = fadd float %0, %1 %4 = fadd float %0, %1
%5 = fsub float %4, %2 %5 = fsub float %4, %2
%6 = fmul float %5, %3 %6 = fmul float %5, %3
%7 = fdiv float %6, %4 %7 = fdiv float %6, %4
ret float %7 ret float %7
} }
No newline at end of file

llvm/trunk/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Linesconstants:
- id: 0 - id: 0
value: double 0xD55960F86F577076 value: double 0xD55960F86F577076
alignment: 8 alignment: 8
body: | body: |
bb.0: bb.0:
%11 = VGBM 0 %11 = VGBM 0
%43 = LHIMux 0 %43 = LHIMux 0
%44 = LARL %const.0 %44 = LARL %const.0
%45 = VL64 %44, 0, _ :: (load 8 from constant-pool) %45 = VL64 %44, 0, %noreg :: (load 8 from constant-pool)
bb.1: bb.1:
ADJCALLSTACKDOWN 0, 0 ADJCALLSTACKDOWN 0, 0
%12 = LZDR %12 = LZDR
%f0d = COPY %12 %f0d = COPY %12
CallBRASL $fmod, killed %f0d, undef %f2d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc, implicit-def %f0d CallBRASL $fmod, killed %f0d, undef %f2d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc, implicit-def %f0d
ADJCALLSTACKUP 0, 0 ADJCALLSTACKUP 0, 0
KILL killed %f0d KILL killed %f0d
bb.2: bb.2:
%17 = VLGVH %11, _, 0 %17 = VLGVH %11, %noreg, 0
%19 = LHR %17.subreg_l32 %19 = LHR %17.subreg_l32
undef %20.subreg_l64 = LGHI 0 undef %20.subreg_l64 = LGHI 0
%20 = DSGFR %20, %19 %20 = DSGFR %20, %19
%22 = VLGVH %11, _, 3 %22 = VLGVH %11, %noreg, 3
%24 = LHR %22.subreg_l32 %24 = LHR %22.subreg_l32
undef %25.subreg_l64 = LGHI 0 undef %25.subreg_l64 = LGHI 0
%25 = DSGFR %25, %24 %25 = DSGFR %25, %24
%31 = VLGVH %11, _, 1 %31 = VLGVH %11, %noreg, 1
%33 = LHR %31.subreg_l32 %33 = LHR %31.subreg_l32
undef %34.subreg_l64 = LGHI 0 undef %34.subreg_l64 = LGHI 0
%34 = DSGFR %34, %33 %34 = DSGFR %34, %33
%37 = VLGVH %11, _, 2 %37 = VLGVH %11, %noreg, 2
%39 = LHR %37.subreg_l32 %39 = LHR %37.subreg_l32
undef %40.subreg_l64 = LGHI 0 undef %40.subreg_l64 = LGHI 0
%40 = DSGFR %40, %39 %40 = DSGFR %40, %39
CHIMux %43, 0, implicit-def %cc CHIMux %43, 0, implicit-def %cc
BRC 14, 6, %bb.2, implicit killed %cc BRC 14, 6, %bb.2, implicit killed %cc
J %bb.3 J %bb.3
bb.3: bb.3:
WFCDB undef %46, %45, implicit-def %cc WFCDB undef %46, %45, implicit-def %cc
%48 = IPM implicit killed %cc %48 = IPM implicit killed %cc
%48 = AFIMux %48, 268435456, implicit-def dead %cc %48 = AFIMux %48, 268435456, implicit-def dead %cc
%6 = RISBMux undef %6, %48, 31, 159, 35 %6 = RISBMux undef %6, %48, 31, 159, 35
WFCDB undef %50, %45, implicit-def %cc WFCDB undef %50, %45, implicit-def %cc
BRC 15, 6, %bb.1, implicit killed %cc BRC 15, 6, %bb.1, implicit killed %cc
J %bb.4 J %bb.4
bb.4: bb.4:
%36 = VLVGP %25.subreg_l64, %25.subreg_l64 %36 = VLVGP %25.subreg_l64, %25.subreg_l64
%36 = VLVGH %36, %20.subreg_l32, _, 0 %36 = VLVGH %36, %20.subreg_l32, %noreg, 0
%36 = VLVGH %36, %34.subreg_l32, _, 1 %36 = VLVGH %36, %34.subreg_l32, %noreg, 1
dead %36 = VLVGH %36, %40.subreg_l32, _, 2 dead %36 = VLVGH %36, %40.subreg_l32, %noreg, 2
%4 = LG undef %42, 0, _ :: (load 8 from `i64* undef`) %4 = LG undef %42, 0, %noreg :: (load 8 from `i64* undef`)
undef %57.subreg_h64 = LLILL 0 undef %57.subreg_h64 = LLILL 0
undef %66.subreg_h64 = LLILL 0 undef %66.subreg_h64 = LLILL 0
undef %79.subreg_h64 = LLILL 0 undef %79.subreg_h64 = LLILL 0
undef %89.subreg_h64 = LLILL 0 undef %89.subreg_h64 = LLILL 0
%92 = LHIMux 0 %92 = LHIMux 0
bb.5: bb.5:
bb.6: bb.6:
%51 = VLGVH undef %7, _, 0 %51 = VLGVH undef %7, %noreg, 0
%53 = LLHRMux %51.subreg_l32 %53 = LLHRMux %51.subreg_l32
%54 = VLGVH undef %1, _, 0 %54 = VLGVH undef %1, %noreg, 0
%57.subreg_l32 = LLHRMux %54.subreg_l32 %57.subreg_l32 = LLHRMux %54.subreg_l32
%58 = COPY %57 %58 = COPY %57
%58 = DLR %58, %53 %58 = DLR %58, %53
%60 = VLGVH undef %7, _, 3 %60 = VLGVH undef %7, %noreg, 3
%62 = LLHRMux %60.subreg_l32 %62 = LLHRMux %60.subreg_l32
%63 = VLGVH undef %1, _, 3 %63 = VLGVH undef %1, %noreg, 3
%66.subreg_l32 = LLHRMux %63.subreg_l32 %66.subreg_l32 = LLHRMux %63.subreg_l32
%67 = COPY %66 %67 = COPY %66
%67 = DLR %67, %62 %67 = DLR %67, %62
%73 = VLGVH undef %7, _, 1 %73 = VLGVH undef %7, %noreg, 1
%75 = LLHRMux %73.subreg_l32 %75 = LLHRMux %73.subreg_l32
%76 = VLGVH undef %1, _, 1 %76 = VLGVH undef %1, %noreg, 1
%79.subreg_l32 = LLHRMux %76.subreg_l32 %79.subreg_l32 = LLHRMux %76.subreg_l32
%80 = COPY %79 %80 = COPY %79
%80 = DLR %80, %75 %80 = DLR %80, %75
%83 = VLGVH undef %7, _, 2 %83 = VLGVH undef %7, %noreg, 2
%85 = LLHRMux %83.subreg_l32 %85 = LLHRMux %83.subreg_l32
%86 = VLGVH undef %1, _, 2 %86 = VLGVH undef %1, %noreg, 2
%89.subreg_l32 = LLHRMux %86.subreg_l32 %89.subreg_l32 = LLHRMux %86.subreg_l32
%90 = COPY %89 %90 = COPY %89
%90 = DLR %90, %85 %90 = DLR %90, %85
CHIMux %92, 0, implicit-def %cc CHIMux %92, 0, implicit-def %cc
BRC 14, 6, %bb.7, implicit killed %cc BRC 14, 6, %bb.7, implicit killed %cc
J %bb.6 J %bb.6
bb.7: bb.7:
CGHI undef %93, 0, implicit-def %cc CGHI undef %93, 0, implicit-def %cc
%96 = IPM implicit killed %cc %96 = IPM implicit killed %cc
CGHI undef %97, 0, implicit-def %cc CGHI undef %97, 0, implicit-def %cc
BRC 14, 6, %bb.6, implicit killed %cc BRC 14, 6, %bb.6, implicit killed %cc
bb.8: bb.8:
CHIMux %6, 0, implicit-def %cc CHIMux %6, 0, implicit-def %cc
%10 = LLILL 41639 %10 = LLILL 41639
dead %10 = LOCGR %10, %4, 14, 6, implicit killed %cc dead %10 = LOCGR %10, %4, 14, 6, implicit killed %cc
CHIMux %92, 0, implicit-def %cc CHIMux %92, 0, implicit-def %cc
BRC 14, 6, %bb.5, implicit killed %cc BRC 14, 6, %bb.5, implicit killed %cc
J %bb.9 J %bb.9
bb.9: bb.9:
%82 = VLVGP %67.subreg_h64, %67.subreg_h64 %82 = VLVGP %67.subreg_h64, %67.subreg_h64
%82 = VLVGH %82, %58.subreg_hl32, _, 0 %82 = VLVGH %82, %58.subreg_hl32, %noreg, 0
%82 = VLVGH %82, %80.subreg_hl32, _, 1 %82 = VLVGH %82, %80.subreg_hl32, %noreg, 1
dead %82 = VLVGH %82, %90.subreg_hl32, _, 2 dead %82 = VLVGH %82, %90.subreg_hl32, %noreg, 2
%96 = AFIMux %96, 1879048192, implicit-def dead %cc %96 = AFIMux %96, 1879048192, implicit-def dead %cc
%96 = SRL %96, _, 31 %96 = SRL %96, %noreg, 31
dead %11 = VLVGF %11, %96, _, 1 dead %11 = VLVGF %11, %96, %noreg, 1
%100 = LHIMux 0 %100 = LHIMux 0
bb.10: bb.10:
CHIMux %100, 0, implicit-def %cc CHIMux %100, 0, implicit-def %cc
BRC 14, 6, %bb.10, implicit killed %cc BRC 14, 6, %bb.10, implicit killed %cc
J %bb.11 J %bb.11
bb.11: bb.11:
Return Return
... ...

llvm/trunk/test/CodeGen/SystemZ/clear-liverange-spillreg.mir

Show First 20 Lines • Show All 217 Lines • ▼ Show 20 Lines bb.10:
successors: %bb.35(0x00000001), %bb.37(0x7fffffff) successors: %bb.35(0x00000001), %bb.37(0x7fffffff)
CHIMux undef %32, 2, implicit-def %cc CHIMux undef %32, 2, implicit-def %cc
BRC 14, 8, %bb.35, implicit killed %cc BRC 14, 8, %bb.35, implicit killed %cc
J %bb.37 J %bb.37
bb.11: bb.11:
%4 = COPY %60 %4 = COPY %60
%6 = SLLG %120, _, 1 %6 = SLLG %120, %noreg, 1
%7 = LA %6, 64, %41 %7 = LA %6, 64, %41
%6 = AGR %6, %42, implicit-def dead %cc %6 = AGR %6, %42, implicit-def dead %cc
%45 = SRLK %120.subreg_l32, _, 31 %45 = SRLK %120.subreg_l32, %noreg, 31
%45 = AR %45, %120.subreg_l32, implicit-def dead %cc %45 = AR %45, %120.subreg_l32, implicit-def dead %cc
%45 = NIFMux %45, 536870910, implicit-def dead %cc %45 = NIFMux %45, 536870910, implicit-def dead %cc
%47 = SRK %120.subreg_l32, %45, implicit-def dead %cc %47 = SRK %120.subreg_l32, %45, implicit-def dead %cc
%47 = SLL %47, _, 3 %47 = SLL %47, %noreg, 3
%81 = LGFR %47 %81 = LGFR %47
bb.12: bb.12:
successors: %bb.56, %bb.13 successors: %bb.56, %bb.13
CHIMux %38, 0, implicit-def %cc CHIMux %38, 0, implicit-def %cc
BRC 14, 8, %bb.13, implicit killed %cc BRC 14, 8, %bb.13, implicit killed %cc
Show All 37 Lines bb.16:
J %bb.17 J %bb.17
bb.17: bb.17:
successors: %bb.18, %bb.19 successors: %bb.18, %bb.19
MVHI %0, 332, 2 :: (store 4) MVHI %0, 332, 2 :: (store 4)
%60 = COPY %126 %60 = COPY %126
%60 = AR %60, %4, implicit-def dead %cc %60 = AR %60, %4, implicit-def dead %cc
%18 = LHMux %6, 0, _ :: (load 2) %18 = LHMux %6, 0, %noreg :: (load 2)
CHIMux %38, 0, implicit-def %cc CHIMux %38, 0, implicit-def %cc
BRC 14, 6, %bb.19, implicit killed %cc BRC 14, 6, %bb.19, implicit killed %cc
J %bb.18 J %bb.18
bb.18: bb.18:
%62 = SLLG %81, _, 1 %62 = SLLG %81, %noreg, 1
%64 = LA %62, 0, %63 %64 = LA %62, 0, %63
%65 = LG undef %66, 0, _ :: (load 8) %65 = LG undef %66, 0, %noreg :: (load 8)
%67 = LGF undef %68, 0, _ :: (load 4) %67 = LGF undef %68, 0, %noreg :: (load 4)
MVC undef %69, 0, 2, %64, 0 :: (store 2), (load 2) MVC undef %69, 0, 2, %64, 0 :: (store 2), (load 2)
%70 = COPY %81 %70 = COPY %81
%70 = OILL64 %70, 3, implicit-def dead %cc %70 = OILL64 %70, 3, implicit-def dead %cc
%71 = LA %70, 2, _ %71 = LA %70, 2, %noreg
%72 = SLLG %71, _, 1 %72 = SLLG %71, %noreg, 1
%73 = LHMux %72, 0, %63 :: (load 2) %73 = LHMux %72, 0, %63 :: (load 2)
%74 = LA %70, 2, %67 %74 = LA %70, 2, %67
%75 = SLLG %74, _, 1 %75 = SLLG %74, %noreg, 1
%76 = LG %65, 0, _ :: (load 8) %76 = LG %65, 0, %noreg :: (load 8)
STHMux %73, %76, 0, %75 :: (store 2) STHMux %73, %76, 0, %75 :: (store 2)
%77 = LG undef %78, 0, _ :: (load 8) %77 = LG undef %78, 0, %noreg :: (load 8)
%79 = LHRL @rec_mbY8x8 :: (load 2) %79 = LHRL @rec_mbY8x8 :: (load 2)
STHMux %79, %77, 0, _ :: (store 2) STHMux %79, %77, 0, %noreg :: (store 2)
%80 = LHMux %72, 0, %63 :: (load 2) %80 = LHMux %72, 0, %63 :: (load 2)
STHMux %80, %77, 0, %75 :: (store 2) STHMux %80, %77, 0, %75 :: (store 2)
%81 = OILL64 %81, 7, implicit-def dead %cc %81 = OILL64 %81, 7, implicit-def dead %cc
%82 = SLLG %81, _, 1 %82 = SLLG %81, %noreg, 1
%83 = LHMux %82, 0, %63 :: (load 2) %83 = LHMux %82, 0, %63 :: (load 2)
STHMux %83, %77, 0, _ :: (store 2) STHMux %83, %77, 0, %noreg :: (store 2)
%84 = LA %62, 64, %63 %84 = LA %62, 64, %63
MVC undef %85, 0, 2, %84, 0 :: (store 2), (load 2) MVC undef %85, 0, 2, %84, 0 :: (store 2), (load 2)
%86 = SLLG %70, _, 1 %86 = SLLG %70, %noreg, 1
%87 = LHMux %86, 64, %63 :: (load 2) %87 = LHMux %86, 64, %63 :: (load 2)
%88 = SLLG %67, _, 3 %88 = SLLG %67, %noreg, 3
%89 = LG %65, 16, %88 :: (load 8) %89 = LG %65, 16, %88 :: (load 8)
%90 = LA %70, 0, %67 %90 = LA %70, 0, %67
%91 = SLLG %90, _, 1 %91 = SLLG %90, %noreg, 1
STHMux %87, %89, 0, %91 :: (store 2) STHMux %87, %89, 0, %91 :: (store 2)
%92 = LA %72, 64, %63 %92 = LA %72, 64, %63
MVC undef %93, 0, 2, %92, 0 :: (store 2), (load 2) MVC undef %93, 0, 2, %92, 0 :: (store 2), (load 2)
%94 = LA %86, 6, %63 %94 = LA %86, 6, %63
MVC undef %95, 0, 2, %94, 0 :: (store 2), (load 2) MVC undef %95, 0, 2, %94, 0 :: (store 2), (load 2)
%96 = LA %82, 0, %63 %96 = LA %82, 0, %63
MVC undef %97, 0, 2, %96, 0 :: (store 2), (load 2) MVC undef %97, 0, 2, %96, 0 :: (store 2), (load 2)
bb.19: bb.19:
successors: %bb.20(0x04000000), %bb.11(0x7c000000) successors: %bb.20(0x04000000), %bb.11(0x7c000000)
%98 = LGH %7, 0, _ :: (load 2) %98 = LGH %7, 0, %noreg :: (load 2)
%99 = LGH undef %100, 0, _ :: (load 2) %99 = LGH undef %100, 0, %noreg :: (load 2)
ADJCALLSTACKDOWN 0, 0 ADJCALLSTACKDOWN 0, 0
%101 = LGFR %120.subreg_l32 %101 = LGFR %120.subreg_l32
%102 = LGFR %18 %102 = LGFR %18
%r2d = COPY %101 %r2d = COPY %101
%r3d = COPY %102 %r3d = COPY %102
%r4d = LGHI 0 %r4d = LGHI 0
%r5d = COPY %98 %r5d = COPY %98
%r6d = COPY %99 %r6d = COPY %99
CallBRASL @SetRefAndMotionVectors, killed %r2d, killed %r3d, killed %r4d, killed %r5d, killed %r6d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc CallBRASL @SetRefAndMotionVectors, killed %r2d, killed %r3d, killed %r4d, killed %r5d, killed %r6d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc
ADJCALLSTACKUP 0, 0 ADJCALLSTACKUP 0, 0
ADJCALLSTACKDOWN 0, 0 ADJCALLSTACKDOWN 0, 0
CallBRASL @reset_coding_state, undef %r2d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc CallBRASL @reset_coding_state, undef %r2d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc
ADJCALLSTACKUP 0, 0 ADJCALLSTACKUP 0, 0
%120 = LA %120, 1, _ %120 = LA %120, 1, %noreg
CGHI %120, 4, implicit-def %cc CGHI %120, 4, implicit-def %cc
BRC 14, 6, %bb.11, implicit killed %cc BRC 14, 6, %bb.11, implicit killed %cc
J %bb.20 J %bb.20
bb.20: bb.20:
successors: %bb.22(0x00000001), %bb.21(0x7fffffff) successors: %bb.22(0x00000001), %bb.21(0x7fffffff)
MVHI undef %105, 0, 0 :: (store 4) MVHI undef %105, 0, 0 :: (store 4)
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines bb.28:
J %bb.30 J %bb.30
bb.29: bb.29:
%130 = IMPLICIT_DEF %130 = IMPLICIT_DEF
bb.30: bb.30:
successors: %bb.33(0x00000001), %bb.31(0x7fffffff) successors: %bb.33(0x00000001), %bb.31(0x7fffffff)
VST64 %130, undef %117, 0, _ :: (store 8) VST64 %130, undef %117, 0, %noreg :: (store 8)
CHIMux undef %118, 2, implicit-def %cc CHIMux undef %118, 2, implicit-def %cc
BRC 14, 8, %bb.33, implicit killed %cc BRC 14, 8, %bb.33, implicit killed %cc
J %bb.31 J %bb.31
bb.31: bb.31:
successors: %bb.32(0x00000001), %bb.34(0x7fffffff) successors: %bb.32(0x00000001), %bb.34(0x7fffffff)
CHIMux undef %119, 1, implicit-def %cc CHIMux undef %119, 1, implicit-def %cc
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines bb.42:
BRC 14, 6, %bb.45, implicit killed %cc BRC 14, 6, %bb.45, implicit killed %cc
J %bb.43 J %bb.43
bb.43: bb.43:
bb.44: bb.44:
bb.45: bb.45:
%0 = LG undef %22, 0, _ :: (load 8) %0 = LG undef %22, 0, %noreg :: (load 8)
%38 = LHIMux 0 %38 = LHIMux 0
STRL %38, @bi_pred_me :: (store 4) STRL %38, @bi_pred_me :: (store 4)
%120 = LGHI 0 %120 = LGHI 0
%41 = LARL @best8x8fwref %41 = LARL @best8x8fwref
%42 = LARL @best8x8mode %42 = LARL @best8x8mode
%63 = LARL @rec_mbY8x8 %63 = LARL @rec_mbY8x8
%126 = IIFMux 2147483647 %126 = IIFMux 2147483647
%124 = LHIMux 0 %124 = LHIMux 0
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/SystemZ/fp-cmp-07.mir

Show All 32 Lines bb.0.entry:
LTEBRCompare %f0s, %f0s, implicit-def %cc LTEBRCompare %f0s, %f0s, implicit-def %cc
%f2s = LER %f0s %f2s = LER %f0s
INLINEASM $"blah $0", 1, 9, %f2s INLINEASM $"blah $0", 1, 9, %f2s
CondReturn 15, 4, implicit %f0s, implicit %cc CondReturn 15, 4, implicit %f0s, implicit %cc
bb.1.store: bb.1.store:
liveins: %f0s, %r2d liveins: %f0s, %r2d
STE %f0s, killed %r2d, 0, _ :: (store 4 into %ir.dest) STE %f0s, killed %r2d, 0, %noreg :: (store 4 into %ir.dest)
Return implicit %f0s Return implicit %f0s
... ...

llvm/trunk/test/CodeGen/SystemZ/fp-conv-17.mir

Show First 20 Lines • Show All 123 Lines • ▼ Show 20 Linesliveins:
- { reg: '%r2d', virtual-reg: '%0' } - { reg: '%r2d', virtual-reg: '%0' }
- { reg: '%r3d', virtual-reg: '%1' } - { reg: '%r3d', virtual-reg: '%1' }
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %r2d, %r3d liveins: %r2d, %r3d
%1 = COPY %r3d %1 = COPY %r3d
%0 = COPY %r2d %0 = COPY %r2d
%2 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %2 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%3 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %3 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%4 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %4 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%5 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %5 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%6 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %6 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%7 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %7 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%8 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %8 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%9 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %9 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%10 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %10 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%11 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %11 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%12 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %12 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%13 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %13 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%14 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %14 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%15 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %15 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%16 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %16 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%17 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %17 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
%18 = LE %1, 0, _ :: (volatile load 4 from %ir.ptr2) %18 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
STE %2, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %2, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %3, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %3, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %4, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %4, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %5, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %5, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %6, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %6, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %7, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %7, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %8, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %8, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %9, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %9, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %10, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %10, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %11, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %11, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %12, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %12, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %13, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %13, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %14, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %14, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %15, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %15, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %16, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %16, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %17, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %17, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
STE %18, %1, 0, _ :: (volatile store 4 into %ir.ptr2) STE %18, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
%19 = LDEBR %2 %19 = LDEBR %2
STD %19, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %19, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%20 = LDEBR %3 %20 = LDEBR %3
STD %20, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %20, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%21 = LDEBR %4 %21 = LDEBR %4
STD %21, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %21, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%22 = LDEBR %5 %22 = LDEBR %5
STD %22, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %22, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%23 = LDEBR %6 %23 = LDEBR %6
STD %23, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %23, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%24 = LDEBR %7 %24 = LDEBR %7
STD %24, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %24, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%25 = LDEBR %8 %25 = LDEBR %8
STD %25, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %25, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%26 = LDEBR %9 %26 = LDEBR %9
STD %26, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %26, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%27 = LDEBR %10 %27 = LDEBR %10
STD %27, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %27, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%28 = LDEBR %11 %28 = LDEBR %11
STD %28, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %28, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%29 = LDEBR %12 %29 = LDEBR %12
STD %29, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %29, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%30 = LDEBR %13 %30 = LDEBR %13
STD %30, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %30, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%31 = LDEBR %14 %31 = LDEBR %14
STD %31, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %31, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%32 = LDEBR %15 %32 = LDEBR %15
STD %32, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %32, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%33 = LDEBR %16 %33 = LDEBR %16
STD %33, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %33, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%34 = LDEBR %17 %34 = LDEBR %17
STD %34, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %34, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
%35 = LDEBR %18 %35 = LDEBR %18
STD %35, %0, 0, _ :: (volatile store 8 into %ir.ptr1) STD %35, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
Return Return
... ...

llvm/trunk/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir

Show All 23 Lines
# CHECK-NOT: %r0q<imp-use,kill> # CHECK-NOT: %r0q<imp-use,kill>
# CHECK-NEXT: %r2d = COPY %r1d # CHECK-NEXT: %r2d = COPY %r1d
# CHECK-NEXT: LARL # CHECK-NEXT: LARL
body: | body: |
bb.0: bb.0:
%0.subreg_hl32 = COPY %0.subreg_l32 %0.subreg_hl32 = COPY %0.subreg_l32
%1 = COPY %0.subreg_l64 %1 = COPY %0.subreg_l64
%2 = LARL @g_167 %2 = LARL @g_167
STC %1.subreg_l32, %2, 8, _ STC %1.subreg_l32, %2, 8, %noreg
... ...

llvm/trunk/test/CodeGen/Thumb/machine-cse-physreg.mir

Show All 15 Linesregisters:
- { id: 2, class: tgpr } - { id: 2, class: tgpr }
- { id: 3, class: tgpr } - { id: 3, class: tgpr }
liveins: liveins:
- { reg: '%r0', virtual-reg: '%0' } - { reg: '%r0', virtual-reg: '%0' }
body: | body: |
bb.0: bb.0:
liveins: %r0 liveins: %r0
%0 = COPY %r0 %0 = COPY %r0
%1, %cpsr = tLSLri %0, 2, 14, _ %1, %cpsr = tLSLri %0, 2, 14, %noreg
tCMPi8 %0, 5, 14, _, implicit-def %cpsr tCMPi8 %0, 5, 14, %noreg, implicit-def %cpsr
tBcc %bb.8, 8, %cpsr tBcc %bb.8, 8, %cpsr
bb.1: bb.1:
%2, %cpsr = tLSLri %0, 2, 14, _ %2, %cpsr = tLSLri %0, 2, 14, %noreg
bb.8: bb.8:
liveins: %cpsr liveins: %cpsr
%3 = COPY %cpsr %3 = COPY %cpsr
tSTRi killed %3, %0, 0, 14, _ tSTRi killed %3, %0, 0, 14, %noreg
... ...

llvm/trunk/test/CodeGen/Thumb/tbb-reuse.mir

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
# r1 is redefined in the middle of the recognizable jump sequence - it shouldn't be clobbered! # r1 is redefined in the middle of the recognizable jump sequence - it shouldn't be clobbered!
# CHECK-NOT: tTBB_JT # CHECK-NOT: tTBB_JT
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.2.default(0x19999998), %bb.1.entry(0x66666668) successors: %bb.2.default(0x19999998), %bb.1.entry(0x66666668)
liveins: %r0, %r7, %lr liveins: %r0, %r7, %lr
frame-setup tPUSH 14, _, killed %r7, killed %lr, implicit-def %sp, implicit %sp frame-setup tPUSH 14, %noreg, killed %r7, killed %lr, implicit-def %sp, implicit %sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset %lr, -4 frame-setup CFI_INSTRUCTION offset %lr, -4
frame-setup CFI_INSTRUCTION offset %r7, -8 frame-setup CFI_INSTRUCTION offset %r7, -8
%r1, dead %cpsr = tSUBi3 %r0, 1, 14, _ %r1, dead %cpsr = tSUBi3 %r0, 1, 14, %noreg
tCMPi8 %r1, 3, 14, _, implicit-def %cpsr tCMPi8 %r1, 3, 14, %noreg, implicit-def %cpsr
tBcc %bb.2.default, 8, killed %cpsr tBcc %bb.2.default, 8, killed %cpsr
bb.1.entry: bb.1.entry:
successors: %bb.3.lab1(0x20000000), %bb.4.lab2(0x20000000), %bb.5.lab3(0x20000000), %bb.6.lab4(0x20000000) successors: %bb.3.lab1(0x20000000), %bb.4.lab2(0x20000000), %bb.5.lab3(0x20000000), %bb.6.lab4(0x20000000)
liveins: %r0, %r1 liveins: %r0, %r1
%r1, dead %cpsr = tLSLri killed %r1, 2, 14, _ %r1, dead %cpsr = tLSLri killed %r1, 2, 14, %noreg
%r2 = tLEApcrelJT %jump-table.0, 14, _ %r2 = tLEApcrelJT %jump-table.0, 14, %noreg
%r2 = tLDRr killed %r1, killed %r2, 14, _ :: (load 4 from jump-table) %r2 = tLDRr killed %r1, killed %r2, 14, %noreg :: (load 4 from jump-table)
%r1, dead %cpsr = tLSLri %r2, 2, 14, _ %r1, dead %cpsr = tLSLri %r2, 2, 14, %noreg
tBR_JTr killed %r2, %jump-table.0 tBR_JTr killed %r2, %jump-table.0
bb.2.default: bb.2.default:
tBL 14, _, @exit0, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp tBL 14, %noreg, @exit0, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp tPOP_RET 14, %noreg, def %r7, def %pc, implicit-def %sp, implicit %sp
bb.3.lab1: bb.3.lab1:
liveins: %r0,%r1 liveins: %r0,%r1
tBL 14, _, @exit1, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit-def %sp tBL 14, %noreg, @exit1, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit-def %sp
tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp tPOP_RET 14, %noreg, def %r7, def %pc, implicit-def %sp, implicit %sp
bb.4.lab2: bb.4.lab2:
tBL 14, _, @exit2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp tBL 14, %noreg, @exit2, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp tPOP_RET 14, %noreg, def %r7, def %pc, implicit-def %sp, implicit %sp
bb.5.lab3: bb.5.lab3:
tBL 14, _, @exit3, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp tBL 14, %noreg, @exit3, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp tPOP_RET 14, %noreg, def %r7, def %pc, implicit-def %sp, implicit %sp
bb.6.lab4: bb.6.lab4:
tBL 14, _, @exit4, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp tBL 14, %noreg, @exit4, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
tPOP_RET 14, _, def %r7, def %pc, implicit-def %sp, implicit %sp tPOP_RET 14, %noreg, def %r7, def %pc, implicit-def %sp, implicit %sp
... ...

llvm/trunk/test/CodeGen/Thumb2/bicbfi.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64" target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv7--linux-gnueabihf" target triple = "thumbv7--linux-gnueabihf"
; CHECK-LABEL: f: ; CHECK-LABEL: f:
; CHECK: bic ; CHECK: bic
define void @f(i32* nocapture %b, i32* nocapture %c, i32 %a) { define void @f(i32* nocapture %b, i32* nocapture %c, i32 %a) {
%1 = and i32 %a, -4096 %1 = and i32 %a, -4096
store i32 %1, i32* %c, align 4 store i32 %1, i32* %c, align 4
%2 = and i32 %a, 4095 %2 = and i32 %a, 4095
%3 = or i32 %2, 4096 %3 = or i32 %2, 4096
%4 = load i32, i32* %b, align 4 %4 = load i32, i32* %b, align 4
%5 = add nsw i32 %4, %3 %5 = add nsw i32 %4, %3
store i32 %5, i32* %b, align 4 store i32 %5, i32* %b, align 4
ret void ret void
} }
No newline at end of file

llvm/trunk/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir

# RUN: llc -mtriple=thumbv7 -start-before=if-converter -o - %s | FileCheck %s # RUN: llc -mtriple=thumbv7 -start-before=if-converter -o - %s | FileCheck %s
--- ---
name: NeonVdupMul name: NeonVdupMul
body: | body: |
bb.0: bb.0:
successors: %bb.2, %bb.1 successors: %bb.2, %bb.1
liveins: %d0, %r0, %r1 liveins: %d0, %r0, %r1
t2CMPri killed %r1, 0, 14, _, implicit-def %cpsr t2CMPri killed %r1, 0, 14, %noreg, implicit-def %cpsr
t2Bcc %bb.2, 0, killed %cpsr t2Bcc %bb.2, 0, killed %cpsr
bb.1: bb.1:
liveins: %d0, %r0 liveins: %d0, %r0
%d16 = VDUP32d killed %r0, 14, _ %d16 = VDUP32d killed %r0, 14, %noreg
; Verify that the neon instructions haven't been conditionalized: ; Verify that the neon instructions haven't been conditionalized:
; CHECK-LABEL: NeonVdupMul ; CHECK-LABEL: NeonVdupMul
; CHECK: vdup.32 ; CHECK: vdup.32
; CHECK: vmul.i32 ; CHECK: vmul.i32
%d0 = VMULv2i32 killed %d16, killed %d0, 14, _ %d0 = VMULv2i32 killed %d16, killed %d0, 14, %noreg
bb.2: bb.2:
liveins: %d0 liveins: %d0
tBX_RET 14, _, implicit %d0 tBX_RET 14, %noreg, implicit %d0
... ...
--- ---
name: NeonVmovVfpLdr name: NeonVmovVfpLdr
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1, %bb.2 successors: %bb.1, %bb.2
liveins: %r0, %r1 liveins: %r0, %r1
t2CMPri killed %r1, 0, 14, _, implicit-def %cpsr t2CMPri killed %r1, 0, 14, %noreg, implicit-def %cpsr
t2Bcc %bb.2, 1, killed %cpsr t2Bcc %bb.2, 1, killed %cpsr
bb.1: bb.1:
%d0 = VMOVv2i32 0, 14, _ %d0 = VMOVv2i32 0, 14, %noreg
tBX_RET 14, _, implicit %d0 tBX_RET 14, %noreg, implicit %d0
bb.2: bb.2:
liveins: %r0 liveins: %r0
%d0 = VLDRD killed %r0, 0, 14, _ %d0 = VLDRD killed %r0, 0, 14, %noreg
; Verify that the neon instruction VMOVv2i32 hasn't been conditionalized, ; Verify that the neon instruction VMOVv2i32 hasn't been conditionalized,
; but the VLDR instruction that is available both in the VFP and Advanced ; but the VLDR instruction that is available both in the VFP and Advanced
; SIMD extensions has. ; SIMD extensions has.
; CHECK-LABEL: NeonVmovVfpLdr ; CHECK-LABEL: NeonVmovVfpLdr
; CHECK-DAG: vmov.i32 d0, #0x0 ; CHECK-DAG: vmov.i32 d0, #0x0
; CHECK-DAG: vldr{{ne|eq}} d0, [r0] ; CHECK-DAG: vldr{{ne|eq}} d0, [r0]
tBX_RET 14, _, implicit %d0 tBX_RET 14, %noreg, implicit %d0
... ...

llvm/trunk/test/CodeGen/Thumb2/tbb-removeadd.mir

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
# CHECK: tMOVi8 # CHECK: tMOVi8
# CHECK: t2TBB_JT # CHECK: t2TBB_JT
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.6.sw.epilog(0x0ccccccb), %bb.1.entry(0x73333335) successors: %bb.6.sw.epilog(0x0ccccccb), %bb.1.entry(0x73333335)
liveins: %r0, %r1 liveins: %r0, %r1
tCMPi8 %r0, 4, 14, _, implicit-def %cpsr tCMPi8 %r0, 4, 14, %noreg, implicit-def %cpsr
t2Bcc %bb.6.sw.epilog, 8, killed %cpsr t2Bcc %bb.6.sw.epilog, 8, killed %cpsr
bb.1.entry: bb.1.entry:
successors: %bb.2.sw.bb(0x1c71c71c), %bb.3.sw.bb1(0x1c71c71c), %bb.5.sw.epilog.sink.split(0x1c71c71c), %bb.6.sw.epilog(0x0e38e38e), %bb.4.sw.bb3(0x1c71c71c) successors: %bb.2.sw.bb(0x1c71c71c), %bb.3.sw.bb1(0x1c71c71c), %bb.5.sw.epilog.sink.split(0x1c71c71c), %bb.6.sw.epilog(0x0e38e38e), %bb.4.sw.bb3(0x1c71c71c)
liveins: %r0, %r1 liveins: %r0, %r1
%r2 = t2LEApcrelJT %jump-table.0, 14, _ %r2 = t2LEApcrelJT %jump-table.0, 14, %noreg
%r3 = t2ADDrs killed %r2, %r0, 18, 14, _, _ %r3 = t2ADDrs killed %r2, %r0, 18, 14, %noreg, %noreg
%r2, dead %cpsr = tMOVi8 1, 14, _ %r2, dead %cpsr = tMOVi8 1, 14, %noreg
t2BR_JT killed %r3, killed %r0, %jump-table.0 t2BR_JT killed %r3, killed %r0, %jump-table.0
bb.2.sw.bb: bb.2.sw.bb:
successors: %bb.5.sw.epilog.sink.split(0x80000000) successors: %bb.5.sw.epilog.sink.split(0x80000000)
liveins: %r1 liveins: %r1
%r2, dead %cpsr = tMOVi8 0, 14, _ %r2, dead %cpsr = tMOVi8 0, 14, %noreg
t2B %bb.5.sw.epilog.sink.split, 14, _ t2B %bb.5.sw.epilog.sink.split, 14, %noreg
bb.3.sw.bb1: bb.3.sw.bb1:
successors: %bb.5.sw.epilog.sink.split(0x80000000) successors: %bb.5.sw.epilog.sink.split(0x80000000)
liveins: %r1 liveins: %r1
%r0, dead %cpsr = tMOVi8 0, 14, _ %r0, dead %cpsr = tMOVi8 0, 14, %noreg
%r2, dead %cpsr = tMOVi8 1, 14, _ %r2, dead %cpsr = tMOVi8 1, 14, %noreg
tSTRi killed %r0, %r1, 0, 14, _ :: (store 4 into %ir.p) tSTRi killed %r0, %r1, 0, 14, %noreg :: (store 4 into %ir.p)
t2B %bb.5.sw.epilog.sink.split, 14, _ t2B %bb.5.sw.epilog.sink.split, 14, %noreg
bb.4.sw.bb3: bb.4.sw.bb3:
successors: %bb.5.sw.epilog.sink.split(0x80000000) successors: %bb.5.sw.epilog.sink.split(0x80000000)
liveins: %r1 liveins: %r1
%r2, dead %cpsr = tMOVi8 2, 14, _ %r2, dead %cpsr = tMOVi8 2, 14, %noreg
bb.5.sw.epilog.sink.split: bb.5.sw.epilog.sink.split:
successors: %bb.6.sw.epilog(0x80000000) successors: %bb.6.sw.epilog(0x80000000)
liveins: %r1, %r2 liveins: %r1, %r2
tSTRi killed %r2, killed %r1, 0, 14, _ :: (store 4 into %ir.p) tSTRi killed %r2, killed %r1, 0, 14, %noreg :: (store 4 into %ir.p)
bb.6.sw.epilog: bb.6.sw.epilog:
tBX_RET 14, _ tBX_RET 14, %noreg
... ...

llvm/trunk/test/CodeGen/X86/GlobalISel/select-GV.mir

Show All 35 Lines
# #
# X32ABI: registers: # X32ABI: registers:
# X32ABI-NEXT: - { id: 0, class: low32_addr_access, preferred-register: '' } # X32ABI-NEXT: - { id: 0, class: low32_addr_access, preferred-register: '' }
# X32ABI-NEXT: - { id: 1, class: gr32, preferred-register: '' } # X32ABI-NEXT: - { id: 1, class: gr32, preferred-register: '' }
registers: registers:
- { id: 0, class: gpr, preferred-register: '' } - { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' }
# X64: %0:gr64 = IMPLICIT_DEF # X64: %0:gr64 = IMPLICIT_DEF
# X64-NEXT: %1:gr64 = LEA64r _, 1, _, @g_int, _ # X64-NEXT: %1:gr64 = LEA64r %noreg, 1, %noreg, @g_int, %noreg
# X64-NEXT: MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into `i32** undef`) # X64-NEXT: MOV64mr %0, 1, %noreg, 0, %noreg, %1 :: (store 8 into `i32** undef`)
# X64-NEXT: RET 0 # X64-NEXT: RET 0
# #
# X64_DARWIN_PIC: %0:gr64 = IMPLICIT_DEF # X64_DARWIN_PIC: %0:gr64 = IMPLICIT_DEF
# X64_DARWIN_PIC-NEXT: %1:gr64 = LEA64r %rip, 1, _, @g_int, _ # X64_DARWIN_PIC-NEXT: %1:gr64 = LEA64r %rip, 1, %noreg, @g_int, %noreg
# X64_DARWIN_PIC-NEXT: MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into `i32** undef`) # X64_DARWIN_PIC-NEXT: MOV64mr %0, 1, %noreg, 0, %noreg, %1 :: (store 8 into `i32** undef`)
# X64_DARWIN_PIC-NEXT: RET 0 # X64_DARWIN_PIC-NEXT: RET 0
# #
# X32: %0:gr32 = IMPLICIT_DEF # X32: %0:gr32 = IMPLICIT_DEF
# X32-NEXT: %1:gr32 = LEA32r _, 1, _, @g_int, _ # X32-NEXT: %1:gr32 = LEA32r %noreg, 1, %noreg, @g_int, %noreg
# X32-NEXT: MOV32mr %0, 1, _, 0, _, %1 :: (store 8 into `i32** undef`) # X32-NEXT: MOV32mr %0, 1, %noreg, 0, %noreg, %1 :: (store 8 into `i32** undef`)
# X32-NEXT: RET 0 # X32-NEXT: RET 0
# #
# X32ABI: %0:low32_addr_access = IMPLICIT_DEF # X32ABI: %0:low32_addr_access = IMPLICIT_DEF
# X32ABI-NEXT: %1:gr32 = LEA64_32r _, 1, _, @g_int, _ # X32ABI-NEXT: %1:gr32 = LEA64_32r %noreg, 1, %noreg, @g_int, %noreg
# X32ABI-NEXT: MOV32mr %0, 1, _, 0, _, %1 :: (store 8 into `i32** undef`) # X32ABI-NEXT: MOV32mr %0, 1, %noreg, 0, %noreg, %1 :: (store 8 into `i32** undef`)
# X32ABI-NEXT: RET 0 # X32ABI-NEXT: RET 0
body: | body: |
bb.1.entry: bb.1.entry:
liveins: %rdi liveins: %rdi
%0(p0) = IMPLICIT_DEF %0(p0) = IMPLICIT_DEF
%1(p0) = G_GLOBAL_VALUE @g_int %1(p0) = G_GLOBAL_VALUE @g_int
G_STORE %1(p0), %0(p0) :: (store 8 into `i32** undef`) G_STORE %1(p0), %0(p0) :: (store 8 into `i32** undef`)
Show All 11 Lines
# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } # X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# #
# X32ALL: registers: # X32ALL: registers:
# X32ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' } # X32ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
# X32ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' } # X32ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
registers: registers:
- { id: 0, class: gpr, preferred-register: '' } - { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' }
# X64: %1:gr64 = LEA64r _, 1, _, @g_int, _ # X64: %1:gr64 = LEA64r %noreg, 1, %noreg, @g_int, %noreg
# X64-NEXT: %0:gr32 = MOV32rm %1, 1, _, 0, _ :: (load 4 from @g_int) # X64-NEXT: %0:gr32 = MOV32rm %1, 1, %noreg, 0, %noreg :: (load 4 from @g_int)
# X64-NEXT: %eax = COPY %0 # X64-NEXT: %eax = COPY %0
# X64-NEXT: RET 0, implicit %eax # X64-NEXT: RET 0, implicit %eax
# #
# X64_DARWIN_PIC: %1:gr64 = LEA64r %rip, 1, _, @g_int, _ # X64_DARWIN_PIC: %1:gr64 = LEA64r %rip, 1, %noreg, @g_int, %noreg
# X64_DARWIN_PIC-NEXT: %0:gr32 = MOV32rm %1, 1, _, 0, _ :: (load 4 from @g_int) # X64_DARWIN_PIC-NEXT: %0:gr32 = MOV32rm %1, 1, %noreg, 0, %noreg :: (load 4 from @g_int)
# X64_DARWIN_PIC-NEXT: %eax = COPY %0 # X64_DARWIN_PIC-NEXT: %eax = COPY %0
# X64_DARWIN_PIC-NEXT: RET 0, implicit %eax # X64_DARWIN_PIC-NEXT: RET 0, implicit %eax
# #
# X32: %1:gr32 = LEA32r _, 1, _, @g_int, _ # X32: %1:gr32 = LEA32r %noreg, 1, %noreg, @g_int, %noreg
# X32-NEXT: %0:gr32 = MOV32rm %1, 1, _, 0, _ :: (load 4 from @g_int) # X32-NEXT: %0:gr32 = MOV32rm %1, 1, %noreg, 0, %noreg :: (load 4 from @g_int)
# X32-NEXT: %eax = COPY %0 # X32-NEXT: %eax = COPY %0
# X32-NEXT: RET 0, implicit %eax # X32-NEXT: RET 0, implicit %eax
# #
# X32ABI: %1:gr32 = LEA64_32r _, 1, _, @g_int, _ # X32ABI: %1:gr32 = LEA64_32r %noreg, 1, %noreg, @g_int, %noreg
# X32ABI-NEXT: %0:gr32 = MOV32rm %1, 1, _, 0, _ :: (load 4 from @g_int) # X32ABI-NEXT: %0:gr32 = MOV32rm %1, 1, %noreg, 0, %noreg :: (load 4 from @g_int)
# X32ABI-NEXT: %eax = COPY %0 # X32ABI-NEXT: %eax = COPY %0
# X32ABI-NEXT: RET 0, implicit %eax # X32ABI-NEXT: RET 0, implicit %eax
body: | body: |
bb.1.entry: bb.1.entry:
%1(p0) = G_GLOBAL_VALUE @g_int %1(p0) = G_GLOBAL_VALUE @g_int
%0(s32) = G_LOAD %1(p0) :: (load 4 from @g_int) %0(s32) = G_LOAD %1(p0) :: (load 4 from @g_int)
%eax = COPY %0(s32) %eax = COPY %0(s32)
RET 0, implicit %eax RET 0, implicit %eax
... ...

llvm/trunk/test/CodeGen/X86/GlobalISel/select-constant.mir

Show First 20 Lines • Show All 171 Lines • ▼ Show 20 Linesregisters:
- { id: 1, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
; CHECK-LABEL: name: main ; CHECK-LABEL: name: main
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 0 ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64 = MOV64ri32 0
; CHECK: MOV64mr [[COPY]], 1, _, 0, _, [[MOV64ri32_]] :: (store 8 into %ir.data) ; CHECK: MOV64mr [[COPY]], 1, %noreg, 0, %noreg, [[MOV64ri32_]] :: (store 8 into %ir.data)
; CHECK: RET 0 ; CHECK: RET 0
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(p0) = G_CONSTANT i64 0 %1(p0) = G_CONSTANT i64 0
G_STORE %1(p0), %0(p0) :: (store 8 into %ir.data) G_STORE %1(p0), %0(p0) :: (store 8 into %ir.data)
RET 0 RET 0
... ...

llvm/trunk/test/CodeGen/X86/GlobalISel/select-fconstant.mir

Show All 19 Lines
# #
# CHECK32-LABEL: name: test_float # CHECK32-LABEL: name: test_float
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vecr, preferred-register: '' } - { id: 0, class: vecr, preferred-register: '' }
# CHECK_SMALL64: %0:fr32 = MOVSSrm %rip, 1, _, %const.0, _ # CHECK_SMALL64: %0:fr32 = MOVSSrm %rip, 1, %noreg, %const.0, %noreg
# CHECK_SMALL64-NEXT: %xmm0 = COPY %0 # CHECK_SMALL64-NEXT: %xmm0 = COPY %0
# CHECK_SMALL64-NEXT: RET 0, implicit %xmm0 # CHECK_SMALL64-NEXT: RET 0, implicit %xmm0
# #
# CHECK_LARGE64: %1:gr64 = MOV64ri %const.0 # CHECK_LARGE64: %1:gr64 = MOV64ri %const.0
# CHECK_LARGE64-NEXT: %0:fr32 = MOVSSrm %1, 1, _, 0, _ :: (load 8 from constant-pool, align 32) # CHECK_LARGE64-NEXT: %0:fr32 = MOVSSrm %1, 1, %noreg, 0, %noreg :: (load 8 from constant-pool, align 32)
# CHECK_LARGE64-NEXT: %xmm0 = COPY %0 # CHECK_LARGE64-NEXT: %xmm0 = COPY %0
# CHECK_LARGE64-NEXT: RET 0, implicit %xmm0 # CHECK_LARGE64-NEXT: RET 0, implicit %xmm0
# #
# CHECK32: %0:fr32 = MOVSSrm _, 1, _, %const.0, _ # CHECK32: %0:fr32 = MOVSSrm %noreg, 1, %noreg, %const.0, %noreg
# CHECK32-NEXT: %xmm0 = COPY %0 # CHECK32-NEXT: %xmm0 = COPY %0
# CHECK32-NEXT: RET 0, implicit %xmm0 # CHECK32-NEXT: RET 0, implicit %xmm0
body: | body: |
bb.1.entry: bb.1.entry:
%0(s32) = G_FCONSTANT float 5.500000e+00 %0(s32) = G_FCONSTANT float 5.500000e+00
%xmm0 = COPY %0(s32) %xmm0 = COPY %0(s32)
RET 0, implicit %xmm0 RET 0, implicit %xmm0
Show All 13 Lines
# CHECK_LARGE64: registers: # CHECK_LARGE64: registers:
# CHECK_LARGE64-NEXT: - { id: 0, class: fr64, preferred-register: '' } # CHECK_LARGE64-NEXT: - { id: 0, class: fr64, preferred-register: '' }
# CHECK_LARGE64-NEXT: - { id: 1, class: gr64, preferred-register: '' } # CHECK_LARGE64-NEXT: - { id: 1, class: gr64, preferred-register: '' }
# #
# CHECK32: registers: # CHECK32: registers:
# CHECK32-NEXT: - { id: 0, class: fr64, preferred-register: '' } # CHECK32-NEXT: - { id: 0, class: fr64, preferred-register: '' }
registers: registers:
- { id: 0, class: vecr, preferred-register: '' } - { id: 0, class: vecr, preferred-register: '' }
# CHECK_SMALL64: %0:fr64 = MOVSDrm %rip, 1, _, %const.0, _ # CHECK_SMALL64: %0:fr64 = MOVSDrm %rip, 1, %noreg, %const.0, %noreg
# CHECK_SMALL64-NEXT: %xmm0 = COPY %0 # CHECK_SMALL64-NEXT: %xmm0 = COPY %0
# CHECK_SMALL64-NEXT: RET 0, implicit %xmm0 # CHECK_SMALL64-NEXT: RET 0, implicit %xmm0
# #
# CHECK_LARGE64: %1:gr64 = MOV64ri %const.0 # CHECK_LARGE64: %1:gr64 = MOV64ri %const.0
# CHECK_LARGE64-NEXT: %0:fr64 = MOVSDrm %1, 1, _, 0, _ :: (load 8 from constant-pool, align 64) # CHECK_LARGE64-NEXT: %0:fr64 = MOVSDrm %1, 1, %noreg, 0, %noreg :: (load 8 from constant-pool, align 64)
# CHECK_LARGE64-NEXT: %xmm0 = COPY %0 # CHECK_LARGE64-NEXT: %xmm0 = COPY %0
# CHECK_LARGE64-NEXT: RET 0, implicit %xmm0 # CHECK_LARGE64-NEXT: RET 0, implicit %xmm0
# #
# CHECK32: %0:fr64 = MOVSDrm _, 1, _, %const.0, _ # CHECK32: %0:fr64 = MOVSDrm %noreg, 1, %noreg, %const.0, %noreg
# CHECK32-NEXT: %xmm0 = COPY %0 # CHECK32-NEXT: %xmm0 = COPY %0
# CHECK32-NEXT: RET 0, implicit %xmm0 # CHECK32-NEXT: RET 0, implicit %xmm0
body: | body: |
bb.1.entry: bb.1.entry:
%0(s64) = G_FCONSTANT double 5.500000e+00 %0(s64) = G_FCONSTANT double 5.500000e+00
%xmm0 = COPY %0(s64) %xmm0 = COPY %0(s64)
RET 0, implicit %xmm0 RET 0, implicit %xmm0
... ...

llvm/trunk/test/CodeGen/X86/GlobalISel/select-frameIndex.mir

Show All 18 Lines
# CHECK-X32: - { id: 0, class: gr32 } # CHECK-X32: - { id: 0, class: gr32 }
# CHECK-X32ABI: - { id: 0, class: gr32 } # CHECK-X32ABI: - { id: 0, class: gr32 }
# CHECK-X64: - { id: 0, class: gr64 } # CHECK-X64: - { id: 0, class: gr64 }
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
stack: stack:
- { id: 0, name: ptr1, offset: 0, size: 4, alignment: 4 } - { id: 0, name: ptr1, offset: 0, size: 4, alignment: 4 }
# CHECK-X32: %0 = LEA32r %stack.0.ptr1, 1, _, 0, _ # CHECK-X32: %0 = LEA32r %stack.0.ptr1, 1, %noreg, 0, %noreg
# CHECK-X32ABI: %0 = LEA64_32r %stack.0.ptr1, 1, _, 0, _ # CHECK-X32ABI: %0 = LEA64_32r %stack.0.ptr1, 1, %noreg, 0, %noreg
# CHECK-X64: %0 = LEA64r %stack.0.ptr1, 1, _, 0, _ # CHECK-X64: %0 = LEA64r %stack.0.ptr1, 1, %noreg, 0, %noreg
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
%0(p0) = G_FRAME_INDEX %stack.0.ptr1 %0(p0) = G_FRAME_INDEX %stack.0.ptr1
%eax = COPY %0(p0) %eax = COPY %0(p0)
RET 0, implicit %eax RET 0, implicit %eax
... ...

llvm/trunk/test/CodeGen/X86/GlobalISel/select-gep.mir

Show All 18 Linesregisters:
- { id: 2, class: gpr } - { id: 2, class: gpr }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
; CHECK-LABEL: name: test_gep_i32 ; CHECK-LABEL: name: test_gep_i32
; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64_nosp = MOV64ri32 20 ; CHECK: [[MOV64ri32_:%[0-9]+]]:gr64_nosp = MOV64ri32 20
; CHECK: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri32_]], 0, _ ; CHECK: [[LEA64r:%[0-9]+]]:gr64 = LEA64r [[COPY]], 1, [[MOV64ri32_]], 0, %noreg
; CHECK: %rax = COPY [[LEA64r]] ; CHECK: %rax = COPY [[LEA64r]]
; CHECK: RET 0, implicit %rax ; CHECK: RET 0, implicit %rax
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(s64) = G_CONSTANT i64 20 %1(s64) = G_CONSTANT i64 20
%2(p0) = G_GEP %0, %1(s64) %2(p0) = G_GEP %0, %1(s64)
%rax = COPY %2(p0) %rax = COPY %2(p0)
RET 0, implicit %rax RET 0, implicit %rax
... ...

llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Linesregisters:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
fixedStack: fixedStack:
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
; ALL-LABEL: name: test_load_i8 ; ALL-LABEL: name: test_load_i8
; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0) ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, %noreg, 0, %noreg :: (invariant load 4 from %fixed-stack.0, align 0)
; ALL: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[MOV32rm]], 1, _, 0, _ :: (load 1 from %ir.p1) ; ALL: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm [[MOV32rm]], 1, %noreg, 0, %noreg :: (load 1 from %ir.p1)
; ALL: %al = COPY [[MOV8rm]] ; ALL: %al = COPY [[MOV8rm]]
; ALL: RET 0, implicit %al ; ALL: RET 0, implicit %al
%1(p0) = G_FRAME_INDEX %fixed-stack.0 %1(p0) = G_FRAME_INDEX %fixed-stack.0
%0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
%2(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1) %2(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1)
%al = COPY %2(s8) %al = COPY %2(s8)
RET 0, implicit %al RET 0, implicit %al
... ...
--- ---
name: test_load_i16 name: test_load_i16
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
fixedStack: fixedStack:
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
; ALL-LABEL: name: test_load_i16 ; ALL-LABEL: name: test_load_i16
; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0) ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, %noreg, 0, %noreg :: (invariant load 4 from %fixed-stack.0, align 0)
; ALL: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[MOV32rm]], 1, _, 0, _ :: (load 2 from %ir.p1) ; ALL: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm [[MOV32rm]], 1, %noreg, 0, %noreg :: (load 2 from %ir.p1)
; ALL: %ax = COPY [[MOV16rm]] ; ALL: %ax = COPY [[MOV16rm]]
; ALL: RET 0, implicit %ax ; ALL: RET 0, implicit %ax
%1(p0) = G_FRAME_INDEX %fixed-stack.0 %1(p0) = G_FRAME_INDEX %fixed-stack.0
%0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
%2(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1) %2(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1)
%ax = COPY %2(s16) %ax = COPY %2(s16)
RET 0, implicit %ax RET 0, implicit %ax
... ...
--- ---
name: test_load_i32 name: test_load_i32
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
fixedStack: fixedStack:
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
; ALL-LABEL: name: test_load_i32 ; ALL-LABEL: name: test_load_i32
; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0) ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, %noreg, 0, %noreg :: (invariant load 4 from %fixed-stack.0, align 0)
; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm [[MOV32rm]], 1, _, 0, _ :: (load 4 from %ir.p1) ; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm [[MOV32rm]], 1, %noreg, 0, %noreg :: (load 4 from %ir.p1)
; ALL: %eax = COPY [[MOV32rm1]] ; ALL: %eax = COPY [[MOV32rm1]]
; ALL: RET 0, implicit %eax ; ALL: RET 0, implicit %eax
%1(p0) = G_FRAME_INDEX %fixed-stack.0 %1(p0) = G_FRAME_INDEX %fixed-stack.0
%0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
%2(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1) %2(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
%eax = COPY %2(s32) %eax = COPY %2(s32)
RET 0, implicit %eax RET 0, implicit %eax
Show All 9 Linesregisters:
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
fixedStack: fixedStack:
- { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- { id: 1, offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false } - { id: 1, offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
; ALL-LABEL: name: test_store_i8 ; ALL-LABEL: name: test_store_i8
; ALL: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 1 from %fixed-stack.0, align 0) ; ALL: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm %fixed-stack.0, 1, %noreg, 0, %noreg :: (invariant load 1 from %fixed-stack.0, align 0)
; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0) ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, %noreg, 0, %noreg :: (invariant load 4 from %fixed-stack.1, align 0)
; ALL: MOV8mr [[MOV32rm]], 1, _, 0, _, [[MOV8rm]] :: (store 1 into %ir.p1) ; ALL: MOV8mr [[MOV32rm]], 1, %noreg, 0, %noreg, [[MOV8rm]] :: (store 1 into %ir.p1)
; ALL: %eax = COPY [[MOV32rm]] ; ALL: %eax = COPY [[MOV32rm]]
; ALL: RET 0, implicit %eax ; ALL: RET 0, implicit %eax
%2(p0) = G_FRAME_INDEX %fixed-stack.1 %2(p0) = G_FRAME_INDEX %fixed-stack.1
%0(s8) = G_LOAD %2(p0) :: (invariant load 1 from %fixed-stack.1, align 0) %0(s8) = G_LOAD %2(p0) :: (invariant load 1 from %fixed-stack.1, align 0)
%3(p0) = G_FRAME_INDEX %fixed-stack.0 %3(p0) = G_FRAME_INDEX %fixed-stack.0
%1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0) %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
G_STORE %0(s8), %1(p0) :: (store 1 into %ir.p1) G_STORE %0(s8), %1(p0) :: (store 1 into %ir.p1)
%eax = COPY %1(p0) %eax = COPY %1(p0)
Show All 11 Linesregisters:
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
fixedStack: fixedStack:
- { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- { id: 1, offset: 0, size: 2, alignment: 16, isImmutable: true, isAliased: false } - { id: 1, offset: 0, size: 2, alignment: 16, isImmutable: true, isAliased: false }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
; ALL-LABEL: name: test_store_i16 ; ALL-LABEL: name: test_store_i16
; ALL: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 2 from %fixed-stack.0, align 0) ; ALL: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm %fixed-stack.0, 1, %noreg, 0, %noreg :: (invariant load 2 from %fixed-stack.0, align 0)
; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0) ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, %noreg, 0, %noreg :: (invariant load 4 from %fixed-stack.1, align 0)
; ALL: MOV16mr [[MOV32rm]], 1, _, 0, _, [[MOV16rm]] :: (store 2 into %ir.p1) ; ALL: MOV16mr [[MOV32rm]], 1, %noreg, 0, %noreg, [[MOV16rm]] :: (store 2 into %ir.p1)
; ALL: %eax = COPY [[MOV32rm]] ; ALL: %eax = COPY [[MOV32rm]]
; ALL: RET 0, implicit %eax ; ALL: RET 0, implicit %eax
%2(p0) = G_FRAME_INDEX %fixed-stack.1 %2(p0) = G_FRAME_INDEX %fixed-stack.1
%0(s16) = G_LOAD %2(p0) :: (invariant load 2 from %fixed-stack.1, align 0) %0(s16) = G_LOAD %2(p0) :: (invariant load 2 from %fixed-stack.1, align 0)
%3(p0) = G_FRAME_INDEX %fixed-stack.0 %3(p0) = G_FRAME_INDEX %fixed-stack.0
%1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0) %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
G_STORE %0(s16), %1(p0) :: (store 2 into %ir.p1) G_STORE %0(s16), %1(p0) :: (store 2 into %ir.p1)
%eax = COPY %1(p0) %eax = COPY %1(p0)
Show All 11 Linesregisters:
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
fixedStack: fixedStack:
- { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } - { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
; ALL-LABEL: name: test_store_i32 ; ALL-LABEL: name: test_store_i32
; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0) ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, %noreg, 0, %noreg :: (invariant load 4 from %fixed-stack.0, align 0)
; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0) ; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, %noreg, 0, %noreg :: (invariant load 4 from %fixed-stack.1, align 0)
; ALL: MOV32mr [[MOV32rm1]], 1, _, 0, _, [[MOV32rm]] :: (store 4 into %ir.p1) ; ALL: MOV32mr [[MOV32rm1]], 1, %noreg, 0, %noreg, [[MOV32rm]] :: (store 4 into %ir.p1)
; ALL: %eax = COPY [[MOV32rm1]] ; ALL: %eax = COPY [[MOV32rm1]]
; ALL: RET 0, implicit %eax ; ALL: RET 0, implicit %eax
%2(p0) = G_FRAME_INDEX %fixed-stack.1 %2(p0) = G_FRAME_INDEX %fixed-stack.1
%0(s32) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0) %0(s32) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
%3(p0) = G_FRAME_INDEX %fixed-stack.0 %3(p0) = G_FRAME_INDEX %fixed-stack.0
%1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0) %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1) G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
%eax = COPY %1(p0) %eax = COPY %1(p0)
Show All 9 Linesregisters:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
fixedStack: fixedStack:
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
; ALL-LABEL: name: test_load_ptr ; ALL-LABEL: name: test_load_ptr
; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0) ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, %noreg, 0, %noreg :: (invariant load 4 from %fixed-stack.0, align 0)
; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm [[MOV32rm]], 1, _, 0, _ :: (load 4 from %ir.ptr1) ; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm [[MOV32rm]], 1, %noreg, 0, %noreg :: (load 4 from %ir.ptr1)
; ALL: %eax = COPY [[MOV32rm1]] ; ALL: %eax = COPY [[MOV32rm1]]
; ALL: RET 0, implicit %eax ; ALL: RET 0, implicit %eax
%1(p0) = G_FRAME_INDEX %fixed-stack.0 %1(p0) = G_FRAME_INDEX %fixed-stack.0
%0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0) %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
%2(p0) = G_LOAD %0(p0) :: (load 4 from %ir.ptr1) %2(p0) = G_LOAD %0(p0) :: (load 4 from %ir.ptr1)
%eax = COPY %2(p0) %eax = COPY %2(p0)
RET 0, implicit %eax RET 0, implicit %eax
Show All 9 Linesregisters:
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
fixedStack: fixedStack:
- { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false } - { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
; ALL-LABEL: name: test_store_ptr ; ALL-LABEL: name: test_store_ptr
; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0) ; ALL: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, %noreg, 0, %noreg :: (invariant load 4 from %fixed-stack.0, align 0)
; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0) ; ALL: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, %noreg, 0, %noreg :: (invariant load 4 from %fixed-stack.1, align 0)
; ALL: MOV32mr [[MOV32rm]], 1, _, 0, _, [[MOV32rm1]] :: (store 4 into %ir.ptr1) ; ALL: MOV32mr [[MOV32rm]], 1, %noreg, 0, %noreg, [[MOV32rm1]] :: (store 4 into %ir.ptr1)
; ALL: RET 0 ; ALL: RET 0
%2(p0) = G_FRAME_INDEX %fixed-stack.1 %2(p0) = G_FRAME_INDEX %fixed-stack.1
%0(p0) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0) %0(p0) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
%3(p0) = G_FRAME_INDEX %fixed-stack.0 %3(p0) = G_FRAME_INDEX %fixed-stack.0
%1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0) %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
G_STORE %1(p0), %0(p0) :: (store 4 into %ir.ptr1) G_STORE %1(p0), %0(p0) :: (store 4 into %ir.ptr1)
RET 0 RET 0
... ...

llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
# ALL: - { id: 0, class: gr64, preferred-register: '' } # ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr8, preferred-register: '' } # ALL: - { id: 1, class: gr8, preferred-register: '' }
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# ALL: %0:gr64 = COPY %rdi # ALL: %0:gr64 = COPY %rdi
# ALL: %1:gr8 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.p1) # ALL: %1:gr8 = MOV8rm %0, 1, %noreg, 0, %noreg :: (load 1 from %ir.p1)
# ALL: %al = COPY %1 # ALL: %al = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1) %1(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1)
%al = COPY %1(s8) %al = COPY %1(s8)
RET 0, implicit %al RET 0, implicit %al
... ...
--- ---
# ALL-LABEL: name: test_load_i16 # ALL-LABEL: name: test_load_i16
name: test_load_i16 name: test_load_i16
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
# ALL: - { id: 0, class: gr64, preferred-register: '' } # ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr16, preferred-register: '' } # ALL: - { id: 1, class: gr16, preferred-register: '' }
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# ALL: %0:gr64 = COPY %rdi # ALL: %0:gr64 = COPY %rdi
# ALL: %1:gr16 = MOV16rm %0, 1, _, 0, _ :: (load 2 from %ir.p1) # ALL: %1:gr16 = MOV16rm %0, 1, %noreg, 0, %noreg :: (load 2 from %ir.p1)
# ALL: %ax = COPY %1 # ALL: %ax = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1) %1(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1)
%ax = COPY %1(s16) %ax = COPY %1(s16)
RET 0, implicit %ax RET 0, implicit %ax
... ...
--- ---
# ALL-LABEL: name: test_load_i32 # ALL-LABEL: name: test_load_i32
name: test_load_i32 name: test_load_i32
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
# ALL: - { id: 0, class: gr64, preferred-register: '' } # ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr32, preferred-register: '' } # ALL: - { id: 1, class: gr32, preferred-register: '' }
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# ALL: %0:gr64 = COPY %rdi # ALL: %0:gr64 = COPY %rdi
# ALL: %1:gr32 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1) # ALL: %1:gr32 = MOV32rm %0, 1, %noreg, 0, %noreg :: (load 4 from %ir.p1)
# ALL: %eax = COPY %1 # ALL: %eax = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1) %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
%eax = COPY %1(s32) %eax = COPY %1(s32)
RET 0, implicit %eax RET 0, implicit %eax
... ...
--- ---
# ALL-LABEL: name: test_load_i64 # ALL-LABEL: name: test_load_i64
name: test_load_i64 name: test_load_i64
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
# ALL: - { id: 0, class: gr64, preferred-register: '' } # ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' } # ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# ALL: %0:gr64 = COPY %rdi # ALL: %0:gr64 = COPY %rdi
# ALL: %1:gr64 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1) # ALL: %1:gr64 = MOV64rm %0, 1, %noreg, 0, %noreg :: (load 8 from %ir.p1)
# ALL: %rax = COPY %1 # ALL: %rax = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1) %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
%rax = COPY %1(s64) %rax = COPY %1(s64)
RET 0, implicit %rax RET 0, implicit %rax
... ...
--- ---
# ALL-LABEL: name: test_load_float # ALL-LABEL: name: test_load_float
name: test_load_float name: test_load_float
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
# ALL: - { id: 0, class: gr64, preferred-register: '' } # ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr32, preferred-register: '' } # ALL: - { id: 1, class: gr32, preferred-register: '' }
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# ALL: %0:gr64 = COPY %rdi # ALL: %0:gr64 = COPY %rdi
# ALL: %1:gr32 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1) # ALL: %1:gr32 = MOV32rm %0, 1, %noreg, 0, %noreg :: (load 4 from %ir.p1)
# ALL: %xmm0 = COPY %1 # ALL: %xmm0 = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1) %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
%xmm0 = COPY %1(s32) %xmm0 = COPY %1(s32)
RET 0, implicit %xmm0 RET 0, implicit %xmm0
... ...
--- ---
# ALL-LABEL: name: test_load_float_vecreg # ALL-LABEL: name: test_load_float_vecreg
name: test_load_float_vecreg name: test_load_float_vecreg
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: vecr } - { id: 1, class: vecr }
# ALL: %0:gr64 = COPY %rdi # ALL: %0:gr64 = COPY %rdi
# SSE: %1:fr32 = MOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1) # SSE: %1:fr32 = MOVSSrm %0, 1, %noreg, 0, %noreg :: (load 4 from %ir.p1)
# AVX: %1:fr32 = VMOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1) # AVX: %1:fr32 = VMOVSSrm %0, 1, %noreg, 0, %noreg :: (load 4 from %ir.p1)
# AVX512ALL: %1:fr32x = VMOVSSZrm %0, 1, _, 0, _ :: (load 4 from %ir.p1) # AVX512ALL: %1:fr32x = VMOVSSZrm %0, 1, %noreg, 0, %noreg :: (load 4 from %ir.p1)
# ALL: %xmm0 = COPY %1 # ALL: %xmm0 = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1) %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
%xmm0 = COPY %1(s32) %xmm0 = COPY %1(s32)
RET 0, implicit %xmm0 RET 0, implicit %xmm0
... ...
--- ---
# ALL-LABEL: name: test_load_double # ALL-LABEL: name: test_load_double
name: test_load_double name: test_load_double
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
# ALL: - { id: 0, class: gr64, preferred-register: '' } # ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' } # ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# ALL: %0:gr64 = COPY %rdi # ALL: %0:gr64 = COPY %rdi
# ALL: %1:gr64 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1) # ALL: %1:gr64 = MOV64rm %0, 1, %noreg, 0, %noreg :: (load 8 from %ir.p1)
# ALL: %xmm0 = COPY %1 # ALL: %xmm0 = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1) %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
%xmm0 = COPY %1(s64) %xmm0 = COPY %1(s64)
RET 0, implicit %xmm0 RET 0, implicit %xmm0
... ...
--- ---
# ALL-LABEL: name: test_load_double_vecreg # ALL-LABEL: name: test_load_double_vecreg
name: test_load_double_vecreg name: test_load_double_vecreg
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: vecr } - { id: 1, class: vecr }
# ALL: %0:gr64 = COPY %rdi # ALL: %0:gr64 = COPY %rdi
# SSE: %1:fr64 = MOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1) # SSE: %1:fr64 = MOVSDrm %0, 1, %noreg, 0, %noreg :: (load 8 from %ir.p1)
# AVX: %1:fr64 = VMOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1) # AVX: %1:fr64 = VMOVSDrm %0, 1, %noreg, 0, %noreg :: (load 8 from %ir.p1)
# AVX512ALL: %1:fr64x = VMOVSDZrm %0, 1, _, 0, _ :: (load 8 from %ir.p1) # AVX512ALL: %1:fr64x = VMOVSDZrm %0, 1, %noreg, 0, %noreg :: (load 8 from %ir.p1)
# ALL: %xmm0 = COPY %1 # ALL: %xmm0 = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1) %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
%xmm0 = COPY %1(s64) %xmm0 = COPY %1(s64)
RET 0, implicit %xmm0 RET 0, implicit %xmm0
... ...
--- ---
# ALL-LABEL: name: test_store_i32 # ALL-LABEL: name: test_store_i32
name: test_store_i32 name: test_store_i32
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
# ALL: - { id: 0, class: gr32, preferred-register: '' } # ALL: - { id: 0, class: gr32, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' } # ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# ALL: %0:gr32 = COPY %edi # ALL: %0:gr32 = COPY %edi
# ALL: %1:gr64 = COPY %rsi # ALL: %1:gr64 = COPY %rsi
# ALL: MOV32mr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1) # ALL: MOV32mr %1, 1, %noreg, 0, %noreg, %0 :: (store 4 into %ir.p1)
# ALL: %rax = COPY %1 # ALL: %rax = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %edi, %rsi liveins: %edi, %rsi
%0(s32) = COPY %edi %0(s32) = COPY %edi
%1(p0) = COPY %rsi %1(p0) = COPY %rsi
G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1) G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
Show All 9 Lines
regBankSelected: true regBankSelected: true
registers: registers:
# ALL: - { id: 0, class: gr64, preferred-register: '' } # ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' } # ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# ALL: %0:gr64 = COPY %rdi # ALL: %0:gr64 = COPY %rdi
# ALL: %1:gr64 = COPY %rsi # ALL: %1:gr64 = COPY %rsi
# ALL: MOV64mr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1) # ALL: MOV64mr %1, 1, %noreg, 0, %noreg, %0 :: (store 8 into %ir.p1)
# ALL: %rax = COPY %1 # ALL: %rax = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %rsi liveins: %rdi, %rsi
%0(s64) = COPY %rdi %0(s64) = COPY %rdi
%1(p0) = COPY %rsi %1(p0) = COPY %rsi
G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1) G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
Show All 10 Lines
registers: registers:
- { id: 0, class: vecr } - { id: 0, class: vecr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
# NO_AVX512F: %0:fr32 = COPY %xmm0 # NO_AVX512F: %0:fr32 = COPY %xmm0
# AVX512ALL: %0:fr32x = COPY %xmm0 # AVX512ALL: %0:fr32x = COPY %xmm0
# ALL: %1:gr64 = COPY %rdi # ALL: %1:gr64 = COPY %rdi
# ALL: %2:gr32 = COPY %0 # ALL: %2:gr32 = COPY %0
# ALL: MOV32mr %1, 1, _, 0, _, %2 :: (store 4 into %ir.p1) # ALL: MOV32mr %1, 1, %noreg, 0, %noreg, %2 :: (store 4 into %ir.p1)
# ALL: %rax = COPY %1 # ALL: %rax = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %xmm0 liveins: %rdi, %xmm0
%0(s32) = COPY %xmm0 %0(s32) = COPY %xmm0
%1(p0) = COPY %rdi %1(p0) = COPY %rdi
%2(s32) = COPY %0(s32) %2(s32) = COPY %0(s32)
Show All 9 Lines
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: vecr } - { id: 0, class: vecr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# NO_AVX512F: %0:fr32 = COPY %xmm0 # NO_AVX512F: %0:fr32 = COPY %xmm0
# AVX512ALL: %0:fr32x = COPY %xmm0 # AVX512ALL: %0:fr32x = COPY %xmm0
# ALL: %1:gr64 = COPY %rdi # ALL: %1:gr64 = COPY %rdi
# SSE: MOVSSmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1) # SSE: MOVSSmr %1, 1, %noreg, 0, %noreg, %0 :: (store 4 into %ir.p1)
# AVX: VMOVSSmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1) # AVX: VMOVSSmr %1, 1, %noreg, 0, %noreg, %0 :: (store 4 into %ir.p1)
# AVX512ALL: VMOVSSZmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1) # AVX512ALL: VMOVSSZmr %1, 1, %noreg, 0, %noreg, %0 :: (store 4 into %ir.p1)
# ALL: %rax = COPY %1 # ALL: %rax = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %xmm0 liveins: %rdi, %xmm0
%0(s32) = COPY %xmm0 %0(s32) = COPY %xmm0
%1(p0) = COPY %rdi %1(p0) = COPY %rdi
G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1) G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
Show All 10 Lines
registers: registers:
- { id: 0, class: vecr } - { id: 0, class: vecr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
# NO_AVX512X: %0:fr64 = COPY %xmm0 # NO_AVX512X: %0:fr64 = COPY %xmm0
# AVX512ALL: %0:fr64x = COPY %xmm0 # AVX512ALL: %0:fr64x = COPY %xmm0
# ALL: %1:gr64 = COPY %rdi # ALL: %1:gr64 = COPY %rdi
# ALL: %2:gr64 = COPY %0 # ALL: %2:gr64 = COPY %0
# ALL: MOV64mr %1, 1, _, 0, _, %2 :: (store 8 into %ir.p1) # ALL: MOV64mr %1, 1, %noreg, 0, %noreg, %2 :: (store 8 into %ir.p1)
# ALL: %rax = COPY %1 # ALL: %rax = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %xmm0 liveins: %rdi, %xmm0
%0(s64) = COPY %xmm0 %0(s64) = COPY %xmm0
%1(p0) = COPY %rdi %1(p0) = COPY %rdi
%2(s64) = COPY %0(s64) %2(s64) = COPY %0(s64)
Show All 9 Lines
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: vecr } - { id: 0, class: vecr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# NO_AVX512F: %0:fr64 = COPY %xmm0 # NO_AVX512F: %0:fr64 = COPY %xmm0
# AVX512ALL: %0:fr64x = COPY %xmm0 # AVX512ALL: %0:fr64x = COPY %xmm0
# ALL: %1:gr64 = COPY %rdi # ALL: %1:gr64 = COPY %rdi
# SSE: MOVSDmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1) # SSE: MOVSDmr %1, 1, %noreg, 0, %noreg, %0 :: (store 8 into %ir.p1)
# AVX: VMOVSDmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1) # AVX: VMOVSDmr %1, 1, %noreg, 0, %noreg, %0 :: (store 8 into %ir.p1)
# AVX512ALL: VMOVSDZmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1) # AVX512ALL: VMOVSDZmr %1, 1, %noreg, 0, %noreg, %0 :: (store 8 into %ir.p1)
# ALL: %rax = COPY %1 # ALL: %rax = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %xmm0 liveins: %rdi, %xmm0
%0(s64) = COPY %xmm0 %0(s64) = COPY %xmm0
%1(p0) = COPY %rdi %1(p0) = COPY %rdi
G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1) G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
%rax = COPY %1(p0) %rax = COPY %1(p0)
RET 0, implicit %rax RET 0, implicit %rax
... ...
--- ---
# ALL-LABEL: name: test_load_ptr # ALL-LABEL: name: test_load_ptr
name: test_load_ptr name: test_load_ptr
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
# ALL: - { id: 0, class: gr64, preferred-register: '' } # ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' } # ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# ALL: %1:gr64 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.ptr1) # ALL: %1:gr64 = MOV64rm %0, 1, %noreg, 0, %noreg :: (load 8 from %ir.ptr1)
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(p0) = G_LOAD %0(p0) :: (load 8 from %ir.ptr1) %1(p0) = G_LOAD %0(p0) :: (load 8 from %ir.ptr1)
%rax = COPY %1(p0) %rax = COPY %1(p0)
RET 0, implicit %rax RET 0, implicit %rax
... ...
--- ---
# ALL-LABEL: name: test_store_ptr # ALL-LABEL: name: test_store_ptr
name: test_store_ptr name: test_store_ptr
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
selected: false selected: false
registers: registers:
# ALL: - { id: 0, class: gr64, preferred-register: '' } # ALL: - { id: 0, class: gr64, preferred-register: '' }
# ALL: - { id: 1, class: gr64, preferred-register: '' } # ALL: - { id: 1, class: gr64, preferred-register: '' }
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# ALL: MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into %ir.ptr1) # ALL: MOV64mr %0, 1, %noreg, 0, %noreg, %1 :: (store 8 into %ir.ptr1)
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %rsi liveins: %rdi, %rsi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(p0) = COPY %rsi %1(p0) = COPY %rsi
G_STORE %1(p0), %0(p0) :: (store 8 into %ir.ptr1) G_STORE %1(p0), %0(p0) :: (store 8 into %ir.ptr1)
RET 0 RET 0
Show All 14 Lines
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
- { id: 4, class: gpr } - { id: 4, class: gpr }
# ALL: %0:gr64 = COPY %rdi # ALL: %0:gr64 = COPY %rdi
# ALL-NEXT: %1:gr32 = COPY %esi # ALL-NEXT: %1:gr32 = COPY %esi
# ALL-NEXT: MOV32mr %0, 1, _, 20, _, %1 :: (store 4 into %ir.arrayidx) # ALL-NEXT: MOV32mr %0, 1, %noreg, 20, %noreg, %1 :: (store 4 into %ir.arrayidx)
# ALL-NEXT: %4:gr32 = MOV32rm %0, 1, _, 20, _ :: (load 4 from %ir.arrayidx) # ALL-NEXT: %4:gr32 = MOV32rm %0, 1, %noreg, 20, %noreg :: (load 4 from %ir.arrayidx)
# ALL-NEXT: %eax = COPY %4 # ALL-NEXT: %eax = COPY %4
# ALL-NEXT: RET 0, implicit %eax # ALL-NEXT: RET 0, implicit %eax
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %esi, %rdi liveins: %esi, %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(s32) = COPY %esi %1(s32) = COPY %esi
Show All 21 Linesregisters:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
- { id: 2, class: gpr } - { id: 2, class: gpr }
- { id: 3, class: gpr } - { id: 3, class: gpr }
- { id: 4, class: gpr } - { id: 4, class: gpr }
# ALL: %0:gr64 = COPY %rdi # ALL: %0:gr64 = COPY %rdi
# ALL-NEXT: %1:gr32 = COPY %esi # ALL-NEXT: %1:gr32 = COPY %esi
# ALL-NEXT: %2:gr64_nosp = MOV64ri 228719476720 # ALL-NEXT: %2:gr64_nosp = MOV64ri 228719476720
# ALL-NEXT: %3:gr64 = LEA64r %0, 1, %2, 0, _ # ALL-NEXT: %3:gr64 = LEA64r %0, 1, %2, 0, %noreg
# ALL-NEXT: MOV32mr %3, 1, _, 0, _, %1 :: (store 4 into %ir.arrayidx) # ALL-NEXT: MOV32mr %3, 1, %noreg, 0, %noreg, %1 :: (store 4 into %ir.arrayidx)
# ALL-NEXT: %4:gr32 = MOV32rm %3, 1, _, 0, _ :: (load 4 from %ir.arrayidx) # ALL-NEXT: %4:gr32 = MOV32rm %3, 1, %noreg, 0, %noreg :: (load 4 from %ir.arrayidx)
# ALL-NEXT: %eax = COPY %4 # ALL-NEXT: %eax = COPY %4
# ALL-NEXT: RET 0, implicit %eax # ALL-NEXT: RET 0, implicit %eax
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %esi, %rdi liveins: %esi, %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(s32) = COPY %esi %1(s32) = COPY %esi
%2(s64) = G_CONSTANT i64 228719476720 %2(s64) = G_CONSTANT i64 228719476720
%3(p0) = G_GEP %0, %2(s64) %3(p0) = G_GEP %0, %2(s64)
G_STORE %1(s32), %3(p0) :: (store 4 into %ir.arrayidx) G_STORE %1(s32), %3(p0) :: (store 4 into %ir.arrayidx)
%4(s32) = G_LOAD %3(p0) :: (load 4 from %ir.arrayidx) %4(s32) = G_LOAD %3(p0) :: (load 4 from %ir.arrayidx)
%eax = COPY %4(s32) %eax = COPY %4(s32)
RET 0, implicit %eax RET 0, implicit %eax
... ...

llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v128.mir

Show All 29 Lines
name: test_load_v4i32_noalign name: test_load_v4i32_noalign
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: vecr } - { id: 1, class: vecr }
# ALL: %0:gr64 = COPY %rdi # ALL: %0:gr64 = COPY %rdi
# SSE: %1:vr128 = MOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1) # SSE: %1:vr128 = MOVUPSrm %0, 1, %noreg, 0, %noreg :: (load 16 from %ir.p1, align 1)
# AVX: %1:vr128 = VMOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1) # AVX: %1:vr128 = VMOVUPSrm %0, 1, %noreg, 0, %noreg :: (load 16 from %ir.p1, align 1)
# AVX512F: %1:vr128x = VMOVUPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1) # AVX512F: %1:vr128x = VMOVUPSZ128rm_NOVLX %0, 1, %noreg, 0, %noreg :: (load 16 from %ir.p1, align 1)
# AVX512VL: %1:vr128x = VMOVUPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1) # AVX512VL: %1:vr128x = VMOVUPSZ128rm %0, 1, %noreg, 0, %noreg :: (load 16 from %ir.p1, align 1)
# ALL: %xmm0 = COPY %1 # ALL: %xmm0 = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1) %1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1)
%xmm0 = COPY %1(<4 x s32>) %xmm0 = COPY %1(<4 x s32>)
RET 0, implicit %xmm0 RET 0, implicit %xmm0
... ...
--- ---
# ALL-LABEL: name: test_load_v4i32_align # ALL-LABEL: name: test_load_v4i32_align
name: test_load_v4i32_align name: test_load_v4i32_align
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: vecr } - { id: 1, class: vecr }
# ALL: %0:gr64 = COPY %rdi # ALL: %0:gr64 = COPY %rdi
# SSE: %1:vr128 = MOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1) # SSE: %1:vr128 = MOVAPSrm %0, 1, %noreg, 0, %noreg :: (load 16 from %ir.p1)
# AVX: %1:vr128 = VMOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1) # AVX: %1:vr128 = VMOVAPSrm %0, 1, %noreg, 0, %noreg :: (load 16 from %ir.p1)
# AVX512F: %1:vr128x = VMOVAPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1) # AVX512F: %1:vr128x = VMOVAPSZ128rm_NOVLX %0, 1, %noreg, 0, %noreg :: (load 16 from %ir.p1)
# AVX512VL: %1:vr128x = VMOVAPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1) # AVX512VL: %1:vr128x = VMOVAPSZ128rm %0, 1, %noreg, 0, %noreg :: (load 16 from %ir.p1)
# ALL: %xmm0 = COPY %1 # ALL: %xmm0 = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1) %1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1)
%xmm0 = COPY %1(<4 x s32>) %xmm0 = COPY %1(<4 x s32>)
RET 0, implicit %xmm0 RET 0, implicit %xmm0
... ...
--- ---
# ALL-LABEL: name: test_store_v4i32_align # ALL-LABEL: name: test_store_v4i32_align
name: test_store_v4i32_align name: test_store_v4i32_align
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: vecr } - { id: 0, class: vecr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# NO_AVX512F: %0:vr128 = COPY %xmm0 # NO_AVX512F: %0:vr128 = COPY %xmm0
# AVX512ALL: %0:vr128x = COPY %xmm0 # AVX512ALL: %0:vr128x = COPY %xmm0
# ALL: %1:gr64 = COPY %rdi # ALL: %1:gr64 = COPY %rdi
# SSE: MOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1) # SSE: MOVAPSmr %1, 1, %noreg, 0, %noreg, %0 :: (store 16 into %ir.p1)
# AVX: VMOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1) # AVX: VMOVAPSmr %1, 1, %noreg, 0, %noreg, %0 :: (store 16 into %ir.p1)
# AVX512F: VMOVAPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1) # AVX512F: VMOVAPSZ128mr_NOVLX %1, 1, %noreg, 0, %noreg, %0 :: (store 16 into %ir.p1)
# AVX512VL: VMOVAPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1) # AVX512VL: VMOVAPSZ128mr %1, 1, %noreg, 0, %noreg, %0 :: (store 16 into %ir.p1)
# ALL: %rax = COPY %1 # ALL: %rax = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %xmm0 liveins: %rdi, %xmm0
%0(<4 x s32>) = COPY %xmm0 %0(<4 x s32>) = COPY %xmm0
%1(p0) = COPY %rdi %1(p0) = COPY %rdi
G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 16) G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 16)
%rax = COPY %1(p0) %rax = COPY %1(p0)
RET 0, implicit %rax RET 0, implicit %rax
... ...
--- ---
# ALL-LABEL: name: test_store_v4i32_noalign # ALL-LABEL: name: test_store_v4i32_noalign
name: test_store_v4i32_noalign name: test_store_v4i32_noalign
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: vecr } - { id: 0, class: vecr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# NO_AVX512F: %0:vr128 = COPY %xmm0 # NO_AVX512F: %0:vr128 = COPY %xmm0
# AVX512ALL: %0:vr128x = COPY %xmm0 # AVX512ALL: %0:vr128x = COPY %xmm0
# ALL: %1:gr64 = COPY %rdi # ALL: %1:gr64 = COPY %rdi
# SSE: MOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1) # SSE: MOVUPSmr %1, 1, %noreg, 0, %noreg, %0 :: (store 16 into %ir.p1, align 1)
# AVX: VMOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1) # AVX: VMOVUPSmr %1, 1, %noreg, 0, %noreg, %0 :: (store 16 into %ir.p1, align 1)
# AVX512F: VMOVUPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1) # AVX512F: VMOVUPSZ128mr_NOVLX %1, 1, %noreg, 0, %noreg, %0 :: (store 16 into %ir.p1, align 1)
# AVX512VL: VMOVUPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1) # AVX512VL: VMOVUPSZ128mr %1, 1, %noreg, 0, %noreg, %0 :: (store 16 into %ir.p1, align 1)
# ALL: %rax = COPY %1 # ALL: %rax = COPY %1
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %xmm0 liveins: %rdi, %xmm0
%0(<4 x s32>) = COPY %xmm0 %0(<4 x s32>) = COPY %xmm0
%1(p0) = COPY %rdi %1(p0) = COPY %rdi
G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 1) G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 1)
%rax = COPY %1(p0) %rax = COPY %1(p0)
RET 0, implicit %rax RET 0, implicit %rax
... ...

llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v256.mir

Show All 37 Lines
# #
# AVX512ALL: registers: # AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' } # AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } # AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: vecr } - { id: 1, class: vecr }
# NO_AVX512F: %0:gr64 = COPY %rdi # NO_AVX512F: %0:gr64 = COPY %rdi
# NO_AVX512F-NEXT: %1:vr256 = VMOVUPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1) # NO_AVX512F-NEXT: %1:vr256 = VMOVUPSYrm %0, 1, %noreg, 0, %noreg :: (load 32 from %ir.p1, align 1)
# NO_AVX512F-NEXT: %ymm0 = COPY %1 # NO_AVX512F-NEXT: %ymm0 = COPY %1
# NO_AVX512F-NEXT: RET 0, implicit %ymm0 # NO_AVX512F-NEXT: RET 0, implicit %ymm0
# #
# AVX512F: %0:gr64 = COPY %rdi # AVX512F: %0:gr64 = COPY %rdi
# AVX512F-NEXT: %1:vr256x = VMOVUPSZ256rm_NOVLX %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1) # AVX512F-NEXT: %1:vr256x = VMOVUPSZ256rm_NOVLX %0, 1, %noreg, 0, %noreg :: (load 32 from %ir.p1, align 1)
# AVX512F-NEXT: %ymm0 = COPY %1 # AVX512F-NEXT: %ymm0 = COPY %1
# AVX512F-NEXT: RET 0, implicit %ymm0 # AVX512F-NEXT: RET 0, implicit %ymm0
# #
# AVX512VL: %0:gr64 = COPY %rdi # AVX512VL: %0:gr64 = COPY %rdi
# AVX512VL-NEXT: %1:vr256x = VMOVUPSZ256rm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1) # AVX512VL-NEXT: %1:vr256x = VMOVUPSZ256rm %0, 1, %noreg, 0, %noreg :: (load 32 from %ir.p1, align 1)
# AVX512VL-NEXT: %ymm0 = COPY %1 # AVX512VL-NEXT: %ymm0 = COPY %1
# AVX512VL-NEXT: RET 0, implicit %ymm0 # AVX512VL-NEXT: RET 0, implicit %ymm0
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(<8 x s32>) = G_LOAD %0(p0) :: (load 32 from %ir.p1, align 1) %1(<8 x s32>) = G_LOAD %0(p0) :: (load 32 from %ir.p1, align 1)
%ymm0 = COPY %1(<8 x s32>) %ymm0 = COPY %1(<8 x s32>)
RET 0, implicit %ymm0 RET 0, implicit %ymm0
... ...
--- ---
name: test_load_v8i32_align name: test_load_v8i32_align
# ALL-LABEL: name: test_load_v8i32_align # ALL-LABEL: name: test_load_v8i32_align
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: vecr } - { id: 1, class: vecr }
# NO_AVX512F: %0:gr64 = COPY %rdi # NO_AVX512F: %0:gr64 = COPY %rdi
# NO_AVX512F-NEXT: %1:vr256 = VMOVAPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1) # NO_AVX512F-NEXT: %1:vr256 = VMOVAPSYrm %0, 1, %noreg, 0, %noreg :: (load 32 from %ir.p1)
# NO_AVX512F-NEXT: %ymm0 = COPY %1 # NO_AVX512F-NEXT: %ymm0 = COPY %1
# NO_AVX512F-NEXT: RET 0, implicit %ymm0 # NO_AVX512F-NEXT: RET 0, implicit %ymm0
# #
# AVX512F: %0:gr64 = COPY %rdi # AVX512F: %0:gr64 = COPY %rdi
# AVX512F-NEXT: %1:vr256x = VMOVAPSZ256rm_NOVLX %0, 1, _, 0, _ :: (load 32 from %ir.p1) # AVX512F-NEXT: %1:vr256x = VMOVAPSZ256rm_NOVLX %0, 1, %noreg, 0, %noreg :: (load 32 from %ir.p1)
# AVX512F-NEXT: %ymm0 = COPY %1 # AVX512F-NEXT: %ymm0 = COPY %1
# AVX512F-NEXT: RET 0, implicit %ymm0 # AVX512F-NEXT: RET 0, implicit %ymm0
# #
# AVX512VL: %0:gr64 = COPY %rdi # AVX512VL: %0:gr64 = COPY %rdi
# AVX512VL-NEXT: %1:vr256x = VMOVAPSZ256rm %0, 1, _, 0, _ :: (load 32 from %ir.p1) # AVX512VL-NEXT: %1:vr256x = VMOVAPSZ256rm %0, 1, %noreg, 0, %noreg :: (load 32 from %ir.p1)
# AVX512VL-NEXT: %ymm0 = COPY %1 # AVX512VL-NEXT: %ymm0 = COPY %1
# AVX512VL-NEXT: RET 0, implicit %ymm0 # AVX512VL-NEXT: RET 0, implicit %ymm0
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(<8 x s32>) = G_LOAD %0(p0) :: (load 32 from %ir.p1) %1(<8 x s32>) = G_LOAD %0(p0) :: (load 32 from %ir.p1)
Show All 14 Lines
# AVX512ALL: registers: # AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } # AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } # AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
registers: registers:
- { id: 0, class: vecr } - { id: 0, class: vecr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# NO_AVX512F: %0:vr256 = COPY %ymm0 # NO_AVX512F: %0:vr256 = COPY %ymm0
# NO_AVX512F-NEXT: %1:gr64 = COPY %rdi # NO_AVX512F-NEXT: %1:gr64 = COPY %rdi
# NO_AVX512F-NEXT: VMOVUPSYmr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1) # NO_AVX512F-NEXT: VMOVUPSYmr %1, 1, %noreg, 0, %noreg, %0 :: (store 32 into %ir.p1, align 1)
# NO_AVX512F-NEXT: RET 0 # NO_AVX512F-NEXT: RET 0
# #
# AVX512F: %0:vr256x = COPY %ymm0 # AVX512F: %0:vr256x = COPY %ymm0
# AVX512F-NEXT: %1:gr64 = COPY %rdi # AVX512F-NEXT: %1:gr64 = COPY %rdi
# AVX512F-NEXT: VMOVUPSZ256mr_NOVLX %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1) # AVX512F-NEXT: VMOVUPSZ256mr_NOVLX %1, 1, %noreg, 0, %noreg, %0 :: (store 32 into %ir.p1, align 1)
# AVX512F-NEXT: RET 0 # AVX512F-NEXT: RET 0
# #
# AVX512VL: %0:vr256x = COPY %ymm0 # AVX512VL: %0:vr256x = COPY %ymm0
# AVX512VL-NEXT: %1:gr64 = COPY %rdi # AVX512VL-NEXT: %1:gr64 = COPY %rdi
# AVX512VL-NEXT: VMOVUPSZ256mr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1) # AVX512VL-NEXT: VMOVUPSZ256mr %1, 1, %noreg, 0, %noreg, %0 :: (store 32 into %ir.p1, align 1)
# AVX512VL-NEXT: RET 0 # AVX512VL-NEXT: RET 0
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %ymm0 liveins: %rdi, %ymm0
%0(<8 x s32>) = COPY %ymm0 %0(<8 x s32>) = COPY %ymm0
%1(p0) = COPY %rdi %1(p0) = COPY %rdi
G_STORE %0(<8 x s32>), %1(p0) :: (store 32 into %ir.p1, align 1) G_STORE %0(<8 x s32>), %1(p0) :: (store 32 into %ir.p1, align 1)
Show All 13 Lines
# AVX512ALL: registers: # AVX512ALL: registers:
# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } # AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' } # AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
registers: registers:
- { id: 0, class: vecr } - { id: 0, class: vecr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
# NO_AVX512F: %0:vr256 = COPY %ymm0 # NO_AVX512F: %0:vr256 = COPY %ymm0
# NO_AVX512F-NEXT: %1:gr64 = COPY %rdi # NO_AVX512F-NEXT: %1:gr64 = COPY %rdi
# NO_AVX512F-NEXT: VMOVAPSYmr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1) # NO_AVX512F-NEXT: VMOVAPSYmr %1, 1, %noreg, 0, %noreg, %0 :: (store 32 into %ir.p1)
# NO_AVX512F-NEXT: RET 0 # NO_AVX512F-NEXT: RET 0
# #
# AVX512F: %0:vr256x = COPY %ymm0 # AVX512F: %0:vr256x = COPY %ymm0
# AVX512F-NEXT: %1:gr64 = COPY %rdi # AVX512F-NEXT: %1:gr64 = COPY %rdi
# AVX512F-NEXT: VMOVAPSZ256mr_NOVLX %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1) # AVX512F-NEXT: VMOVAPSZ256mr_NOVLX %1, 1, %noreg, 0, %noreg, %0 :: (store 32 into %ir.p1)
# AVX512F-NEXT: RET 0 # AVX512F-NEXT: RET 0
# #
# AVX512VL: %0:vr256x = COPY %ymm0 # AVX512VL: %0:vr256x = COPY %ymm0
# AVX512VL-NEXT: %1:gr64 = COPY %rdi # AVX512VL-NEXT: %1:gr64 = COPY %rdi
# AVX512VL-NEXT: VMOVAPSZ256mr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1) # AVX512VL-NEXT: VMOVAPSZ256mr %1, 1, %noreg, 0, %noreg, %0 :: (store 32 into %ir.p1)
# AVX512VL-NEXT: RET 0 # AVX512VL-NEXT: RET 0
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %ymm0 liveins: %rdi, %ymm0
%0(<8 x s32>) = COPY %ymm0 %0(<8 x s32>) = COPY %ymm0
%1(p0) = COPY %rdi %1(p0) = COPY %rdi
G_STORE %0(<8 x s32>), %1(p0) :: (store 32 into %ir.p1) G_STORE %0(<8 x s32>), %1(p0) :: (store 32 into %ir.p1)
RET 0 RET 0
... ...

llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v512.mir

Show All 30 Linesregisters:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: vecr } - { id: 1, class: vecr }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
; AVX512F-LABEL: name: test_load_v16i32_noalign ; AVX512F-LABEL: name: test_load_v16i32_noalign
; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, _, 0, _ :: (load 64 from %ir.p1, align 1) ; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, %noreg, 0, %noreg :: (load 64 from %ir.p1, align 1)
; AVX512F: %zmm0 = COPY [[VMOVUPSZrm]] ; AVX512F: %zmm0 = COPY [[VMOVUPSZrm]]
; AVX512F: RET 0, implicit %zmm0 ; AVX512F: RET 0, implicit %zmm0
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1) %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1)
%zmm0 = COPY %1(<16 x s32>) %zmm0 = COPY %1(<16 x s32>)
RET 0, implicit %zmm0 RET 0, implicit %zmm0
... ...
--- ---
name: test_load_v16i32_align name: test_load_v16i32_align
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: gpr } - { id: 0, class: gpr }
- { id: 1, class: vecr } - { id: 1, class: vecr }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi liveins: %rdi
; AVX512F-LABEL: name: test_load_v16i32_align ; AVX512F-LABEL: name: test_load_v16i32_align
; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, _, 0, _ :: (load 64 from %ir.p1, align 32) ; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, %noreg, 0, %noreg :: (load 64 from %ir.p1, align 32)
; AVX512F: %zmm0 = COPY [[VMOVUPSZrm]] ; AVX512F: %zmm0 = COPY [[VMOVUPSZrm]]
; AVX512F: RET 0, implicit %zmm0 ; AVX512F: RET 0, implicit %zmm0
%0(p0) = COPY %rdi %0(p0) = COPY %rdi
%1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 32) %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 32)
%zmm0 = COPY %1(<16 x s32>) %zmm0 = COPY %1(<16 x s32>)
RET 0, implicit %zmm0 RET 0, implicit %zmm0
... ...
--- ---
name: test_store_v16i32_noalign name: test_store_v16i32_noalign
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: vecr } - { id: 0, class: vecr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %zmm0 liveins: %rdi, %zmm0
; AVX512F-LABEL: name: test_store_v16i32_noalign ; AVX512F-LABEL: name: test_store_v16i32_noalign
; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0 ; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY %rdi ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY %rdi
; AVX512F: VMOVUPSZmr [[COPY1]], 1, _, 0, _, [[COPY]] :: (store 64 into %ir.p1, align 1) ; AVX512F: VMOVUPSZmr [[COPY1]], 1, %noreg, 0, %noreg, [[COPY]] :: (store 64 into %ir.p1, align 1)
; AVX512F: RET 0 ; AVX512F: RET 0
%0(<16 x s32>) = COPY %zmm0 %0(<16 x s32>) = COPY %zmm0
%1(p0) = COPY %rdi %1(p0) = COPY %rdi
G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1) G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1)
RET 0 RET 0
... ...
--- ---
name: test_store_v16i32_align name: test_store_v16i32_align
alignment: 4 alignment: 4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
registers: registers:
- { id: 0, class: vecr } - { id: 0, class: vecr }
- { id: 1, class: gpr } - { id: 1, class: gpr }
body: | body: |
bb.1 (%ir-block.0): bb.1 (%ir-block.0):
liveins: %rdi, %zmm0 liveins: %rdi, %zmm0
; AVX512F-LABEL: name: test_store_v16i32_align ; AVX512F-LABEL: name: test_store_v16i32_align
; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0 ; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY %zmm0
; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY %rdi ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY %rdi
; AVX512F: VMOVUPSZmr [[COPY1]], 1, _, 0, _, [[COPY]] :: (store 64 into %ir.p1, align 32) ; AVX512F: VMOVUPSZmr [[COPY1]], 1, %noreg, 0, %noreg, [[COPY]] :: (store 64 into %ir.p1, align 32)
; AVX512F: RET 0 ; AVX512F: RET 0
%0(<16 x s32>) = COPY %zmm0 %0(<16 x s32>) = COPY %zmm0
%1(p0) = COPY %rdi %1(p0) = COPY %rdi
G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 32) G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 32)
RET 0 RET 0
... ...

llvm/trunk/test/CodeGen/X86/block-placement.mir

Show All 40 Lines
# CHECK: name: f # CHECK: name: f
name: f name: f
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%esi' } - { reg: '%esi' }
# CHECK: %eax = FAULTING_OP 1, %bb.3.null, 1684, killed %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr) # CHECK: %eax = FAULTING_OP 1, %bb.3.null, 1684, killed %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.ptr)
# CHECK-NEXT: JMP_1 %bb.2.not_null # CHECK-NEXT: JMP_1 %bb.2.not_null
# CHECK: bb.3.null: # CHECK: bb.3.null:
# CHECK: bb.4.right: # CHECK: bb.4.right:
# CHECK: bb.2.not_null: # CHECK: bb.2.not_null:
body: | body: |
bb.0.entry: bb.0.entry:
successors: %bb.1.left(0x7ffff800), %bb.3.right(0x00000800) successors: %bb.1.left(0x7ffff800), %bb.3.right(0x00000800)
liveins: %esi, %rdi liveins: %esi, %rdi
frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
TEST8ri %sil, 1, implicit-def %eflags, implicit killed %esi TEST8ri %sil, 1, implicit-def %eflags, implicit killed %esi
JE_1 %bb.3.right, implicit killed %eflags JE_1 %bb.3.right, implicit killed %eflags
bb.1.left: bb.1.left:
successors: %bb.2.null(0x7ffff800), %bb.4.not_null(0x00000800) successors: %bb.2.null(0x7ffff800), %bb.4.not_null(0x00000800)
liveins: %rdi liveins: %rdi
%eax = FAULTING_OP 1, %bb.2.null, 1684, killed %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr) %eax = FAULTING_OP 1, %bb.2.null, 1684, killed %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.ptr)
JMP_1 %bb.4.not_null JMP_1 %bb.4.not_null
bb.4.not_null: bb.4.not_null:
liveins: %rdi, %eax liveins: %rdi, %eax
%rcx = POP64r implicit-def %rsp, implicit %rsp %rcx = POP64r implicit-def %rsp, implicit %rsp
RETQ %eax RETQ %eax
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llvm/trunk/test/CodeGen/X86/conditional-tailcall-samedest.mir

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines bb.1.entry:
liveins: %eflags liveins: %eflags
JE_1 %bb.4.sw.bb2, implicit killed %eflags JE_1 %bb.4.sw.bb2, implicit killed %eflags
JMP_1 %bb.5.sw.epilog JMP_1 %bb.5.sw.epilog
bb.2.sw.bb: bb.2.sw.bb:
successors: %bb.3.init.check.i(0x00000800), %bb.6.return(0x7ffff800) successors: %bb.3.init.check.i(0x00000800), %bb.6.return(0x7ffff800)
%al = ACQUIRE_MOV8rm %rip, 1, _, @static_local_guard, _ :: (volatile load acquire 1 from `i8* bitcast (i64* @static_local_guard to i8*)`, align 8) %al = ACQUIRE_MOV8rm %rip, 1, %noreg, @static_local_guard, %noreg :: (volatile load acquire 1 from `i8* bitcast (i64* @static_local_guard to i8*)`, align 8)
TEST8rr killed %al, %al, implicit-def %eflags TEST8rr killed %al, %al, implicit-def %eflags
JNE_1 %bb.6.return, implicit killed %eflags JNE_1 %bb.6.return, implicit killed %eflags
JMP_1 %bb.3.init.check.i JMP_1 %bb.3.init.check.i
bb.3.init.check.i: bb.3.init.check.i:
dead %edi = MOV32ri64 @static_local_guard, implicit-def %rdi dead %edi = MOV32ri64 @static_local_guard, implicit-def %rdi
TCRETURNdi64 @initialize_static_local, 0, csr_64, implicit %rsp, implicit %rdi TCRETURNdi64 @initialize_static_local, 0, csr_64, implicit %rsp, implicit %rdi
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llvm/trunk/test/CodeGen/X86/domain-reassignment.mir

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines bb.3.exit:
%2 = PHI %1, %bb.2.else, %0, %bb.1.if %2 = PHI %1, %bb.2.else, %0, %bb.1.if
%17 = IMPLICIT_DEF %17 = IMPLICIT_DEF
%16 = INSERT_SUBREG %17, %2, 1 %16 = INSERT_SUBREG %17, %2, 1
%18 = COPY %16 %18 = COPY %16
%19 = COPY %6 %19 = COPY %6
%21 = IMPLICIT_DEF %21 = IMPLICIT_DEF
%20 = VMOVSSZrrk %19, killed %18, killed %21, %5 %20 = VMOVSSZrrk %19, killed %18, killed %21, %5
%22 = COPY %20 %22 = COPY %20
VMOVSSZmr %4, 1, _, 0, _, killed %22 :: (store 4 into %ir.fptr) VMOVSSZmr %4, 1, %noreg, 0, %noreg, killed %22 :: (store 4 into %ir.fptr)
RET 0 RET 0
... ...
--- ---
name: test_8bitops name: test_8bitops
# CHECK-LABEL: name: test_8bitops # CHECK-LABEL: name: test_8bitops
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
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%18 = ADD8rr %17, %14, implicit-def dead %eflags %18 = ADD8rr %17, %14, implicit-def dead %eflags
; CHECK: %9:vk32 = COPY %18 ; CHECK: %9:vk32 = COPY %18
; CHECK: %10:vk8wm = COPY %9 ; CHECK: %10:vk8wm = COPY %9
%8 = IMPLICIT_DEF %8 = IMPLICIT_DEF
%9 = INSERT_SUBREG %8, %18, 1 %9 = INSERT_SUBREG %8, %18, 1
%10 = COPY %9 %10 = COPY %9
%11 = VMOVAPDZrrk %2, killed %10, %1 %11 = VMOVAPDZrrk %2, killed %10, %1
VMOVAPDZmr %0, 1, _, 0, _, killed %11 VMOVAPDZmr %0, 1, %noreg, 0, %noreg, killed %11
; CHECK: KTESTBrr %18, %18, implicit-def %eflags ; CHECK: KTESTBrr %18, %18, implicit-def %eflags
TEST8rr %18, %18, implicit-def %eflags TEST8rr %18, %18, implicit-def %eflags
JE_1 %bb.1, implicit %eflags JE_1 %bb.1, implicit %eflags
JMP_1 %bb.2 JMP_1 %bb.2
bb.1: bb.1:
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%17 = XOR16rr %16, %12, implicit-def dead %eflags %17 = XOR16rr %16, %12, implicit-def dead %eflags
; CHECK: %9:vk32 = COPY %17 ; CHECK: %9:vk32 = COPY %17
; CHECK: %10:vk16wm = COPY %9 ; CHECK: %10:vk16wm = COPY %9
%8 = IMPLICIT_DEF %8 = IMPLICIT_DEF
%9 = INSERT_SUBREG %8, %17, 3 %9 = INSERT_SUBREG %8, %17, 3
%10 = COPY %9 %10 = COPY %9
%11 = VMOVAPSZrrk %2, killed %10, %1 %11 = VMOVAPSZrrk %2, killed %10, %1
VMOVAPSZmr %0, 1, _, 0, _, killed %11 VMOVAPSZmr %0, 1, %noreg, 0, %noreg, killed %11
; CHECK: KTESTWrr %17, %17, implicit-def %eflags ; CHECK: KTESTWrr %17, %17, implicit-def %eflags
TEST16rr %17, %17, implicit-def %eflags TEST16rr %17, %17, implicit-def %eflags
JE_1 %bb.1, implicit %eflags JE_1 %bb.1, implicit %eflags
JMP_1 %bb.2 JMP_1 %bb.2
bb.1: bb.1:
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body: | body: |
bb.0: bb.0:
liveins: %rdi, %zmm0, %zmm1 liveins: %rdi, %zmm0, %zmm1
%0 = COPY %rdi %0 = COPY %rdi
%1 = COPY %zmm0 %1 = COPY %zmm0
%2 = COPY %zmm1 %2 = COPY %zmm1
; CHECK: %5:vk32 = KMOVDkm %0, 1, _, 0, _ ; CHECK: %5:vk32 = KMOVDkm %0, 1, %noreg, 0, %noreg
; CHECK: %6:vk32 = KSHIFTRDri %5, 2 ; CHECK: %6:vk32 = KSHIFTRDri %5, 2
; CHECK: %7:vk32 = KSHIFTLDri %6, 1 ; CHECK: %7:vk32 = KSHIFTLDri %6, 1
; CHECK: %8:vk32 = KNOTDrr %7 ; CHECK: %8:vk32 = KNOTDrr %7
; CHECK: %9:vk32 = KORDrr %8, %6 ; CHECK: %9:vk32 = KORDrr %8, %6
; CHECK: %10:vk32 = KANDDrr %9, %7 ; CHECK: %10:vk32 = KANDDrr %9, %7
; CHECK: %11:vk32 = KXORDrr %10, %6 ; CHECK: %11:vk32 = KXORDrr %10, %6
; CHECK: %12:vk32 = KANDNDrr %11, %9 ; CHECK: %12:vk32 = KANDNDrr %11, %9
; CHECK: %13:vk32 = KADDDrr %12, %11 ; CHECK: %13:vk32 = KADDDrr %12, %11
%5 = MOV32rm %0, 1, _, 0, _ %5 = MOV32rm %0, 1, %noreg, 0, %noreg
%6 = SHR32ri %5, 2, implicit-def dead %eflags %6 = SHR32ri %5, 2, implicit-def dead %eflags
%7 = SHL32ri %6, 1, implicit-def dead %eflags %7 = SHL32ri %6, 1, implicit-def dead %eflags
%8 = NOT32r %7 %8 = NOT32r %7
%9 = OR32rr %8, %6, implicit-def dead %eflags %9 = OR32rr %8, %6, implicit-def dead %eflags
%10 = AND32rr %9, %7, implicit-def dead %eflags %10 = AND32rr %9, %7, implicit-def dead %eflags
%11 = XOR32rr %10, %6, implicit-def dead %eflags %11 = XOR32rr %10, %6, implicit-def dead %eflags
%12 = ANDN32rr %11, %9, implicit-def dead %eflags %12 = ANDN32rr %11, %9, implicit-def dead %eflags
%13 = ADD32rr %12, %11, implicit-def dead %eflags %13 = ADD32rr %12, %11, implicit-def dead %eflags
; CHECK: %3:vk32wm = COPY %13 ; CHECK: %3:vk32wm = COPY %13
%3 = COPY %13 %3 = COPY %13
%4 = VMOVDQU16Zrrk %2, killed %3, %1 %4 = VMOVDQU16Zrrk %2, killed %3, %1
VMOVDQA32Zmr %0, 1, _, 0, _, killed %4 VMOVDQA32Zmr %0, 1, %noreg, 0, %noreg, killed %4
; CHECK: KTESTDrr %13, %13, implicit-def %eflags ; CHECK: KTESTDrr %13, %13, implicit-def %eflags
TEST32rr %13, %13, implicit-def %eflags TEST32rr %13, %13, implicit-def %eflags
JE_1 %bb.1, implicit %eflags JE_1 %bb.1, implicit %eflags
JMP_1 %bb.2 JMP_1 %bb.2
bb.1: bb.1:
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
liveins: %rdi, %zmm0, %zmm1 liveins: %rdi, %zmm0, %zmm1
%0 = COPY %rdi %0 = COPY %rdi
%1 = COPY %zmm0 %1 = COPY %zmm0
%2 = COPY %zmm1 %2 = COPY %zmm1
; CHECK: %5:vk64 = KMOVQkm %0, 1, _, 0, _ ; CHECK: %5:vk64 = KMOVQkm %0, 1, %noreg, 0, %noreg
; CHECK: %6:vk64 = KSHIFTRQri %5, 2 ; CHECK: %6:vk64 = KSHIFTRQri %5, 2
; CHECK: %7:vk64 = KSHIFTLQri %6, 1 ; CHECK: %7:vk64 = KSHIFTLQri %6, 1
; CHECK: %8:vk64 = KNOTQrr %7 ; CHECK: %8:vk64 = KNOTQrr %7
; CHECK: %9:vk64 = KORQrr %8, %6 ; CHECK: %9:vk64 = KORQrr %8, %6
; CHECK: %10:vk64 = KANDQrr %9, %7 ; CHECK: %10:vk64 = KANDQrr %9, %7
; CHECK: %11:vk64 = KXORQrr %10, %6 ; CHECK: %11:vk64 = KXORQrr %10, %6
; CHECK: %12:vk64 = KANDNQrr %11, %9 ; CHECK: %12:vk64 = KANDNQrr %11, %9
; CHECK: %13:vk64 = KADDQrr %12, %11 ; CHECK: %13:vk64 = KADDQrr %12, %11
%5 = MOV64rm %0, 1, _, 0, _ %5 = MOV64rm %0, 1, %noreg, 0, %noreg
%6 = SHR64ri %5, 2, implicit-def dead %eflags %6 = SHR64ri %5, 2, implicit-def dead %eflags
%7 = SHL64ri %6, 1, implicit-def dead %eflags %7 = SHL64ri %6, 1, implicit-def dead %eflags
%8 = NOT64r %7 %8 = NOT64r %7
%9 = OR64rr %8, %6, implicit-def dead %eflags %9 = OR64rr %8, %6, implicit-def dead %eflags
%10 = AND64rr %9, %7, implicit-def dead %eflags %10 = AND64rr %9, %7, implicit-def dead %eflags
%11 = XOR64rr %10, %6, implicit-def dead %eflags %11 = XOR64rr %10, %6, implicit-def dead %eflags
%12 = ANDN64rr %11, %9, implicit-def dead %eflags %12 = ANDN64rr %11, %9, implicit-def dead %eflags
%13 = ADD64rr %12, %11, implicit-def dead %eflags %13 = ADD64rr %12, %11, implicit-def dead %eflags
; CHECK: %3:vk64wm = COPY %13 ; CHECK: %3:vk64wm = COPY %13
%3 = COPY %13 %3 = COPY %13
%4 = VMOVDQU8Zrrk %2, killed %3, %1 %4 = VMOVDQU8Zrrk %2, killed %3, %1
VMOVDQA32Zmr %0, 1, _, 0, _, killed %4 VMOVDQA32Zmr %0, 1, %noreg, 0, %noreg, killed %4
; CHECK: KTESTQrr %13, %13, implicit-def %eflags ; CHECK: KTESTQrr %13, %13, implicit-def %eflags
TEST64rr %13, %13, implicit-def %eflags TEST64rr %13, %13, implicit-def %eflags
JE_1 %bb.1, implicit %eflags JE_1 %bb.1, implicit %eflags
JMP_1 %bb.2 JMP_1 %bb.2
bb.1: bb.1:
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body: | body: |
bb.0: bb.0:
liveins: %rdi, %zmm0, %zmm1 liveins: %rdi, %zmm0, %zmm1
%0 = COPY %rdi %0 = COPY %rdi
%1 = COPY %zmm0 %1 = COPY %zmm0
%2 = COPY %zmm1 %2 = COPY %zmm1
; CHECK: %7:vk8 = KMOVBkm %0, 1, _, 0, _ ; CHECK: %7:vk8 = KMOVBkm %0, 1, %noreg, 0, %noreg
; CHECK: %5:vk16 = COPY %7 ; CHECK: %5:vk16 = COPY %7
; CHECK: %6:vk16 = KNOTWrr %5 ; CHECK: %6:vk16 = KNOTWrr %5
%5 = MOVZX16rm8 %0, 1, _, 0, _ %5 = MOVZX16rm8 %0, 1, %noreg, 0, %noreg
%6 = NOT16r %5 %6 = NOT16r %5
; CHECK: %3:vk16wm = COPY %6 ; CHECK: %3:vk16wm = COPY %6
%3 = COPY %6 %3 = COPY %6
%4 = VMOVAPSZrrk %2, killed %3, %1 %4 = VMOVAPSZrrk %2, killed %3, %1
VMOVAPSZmr %0, 1, _, 0, _, killed %4 VMOVAPSZmr %0, 1, %noreg, 0, %noreg, killed %4
RET 0 RET 0
... ...
--- ---
name: test_32bitext name: test_32bitext
# CHECK-LABEL: name: test_32bitext # CHECK-LABEL: name: test_32bitext
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
Show All 37 Lines
body: | body: |
bb.0: bb.0:
liveins: %rdi, %zmm0, %zmm1 liveins: %rdi, %zmm0, %zmm1
%0 = COPY %rdi %0 = COPY %rdi
%1 = COPY %zmm0 %1 = COPY %zmm0
%2 = COPY %zmm1 %2 = COPY %zmm1
; CHECK: %8:vk8 = KMOVBkm %0, 1, _, 0, _ ; CHECK: %8:vk8 = KMOVBkm %0, 1, %noreg, 0, %noreg
; CHECK: %5:vk32 = COPY %8 ; CHECK: %5:vk32 = COPY %8
; CHECK: %9:vk16 = KMOVWkm %0, 1, _, 0, _ ; CHECK: %9:vk16 = KMOVWkm %0, 1, %noreg, 0, %noreg
; CHECK: %6:vk32 = COPY %9 ; CHECK: %6:vk32 = COPY %9
; CHECK: %7:vk32 = KADDDrr %5, %6 ; CHECK: %7:vk32 = KADDDrr %5, %6
%5 = MOVZX32rm8 %0, 1, _, 0, _ %5 = MOVZX32rm8 %0, 1, %noreg, 0, %noreg
%6 = MOVZX32rm16 %0, 1, _, 0, _ %6 = MOVZX32rm16 %0, 1, %noreg, 0, %noreg
%7 = ADD32rr %5, %6, implicit-def dead %eflags %7 = ADD32rr %5, %6, implicit-def dead %eflags
; CHECK: %3:vk64wm = COPY %7 ; CHECK: %3:vk64wm = COPY %7
%3 = COPY %7 %3 = COPY %7
%4 = VMOVDQU16Zrrk %2, killed %3, %1 %4 = VMOVDQU16Zrrk %2, killed %3, %1
VMOVDQA32Zmr %0, 1, _, 0, _, killed %4 VMOVDQA32Zmr %0, 1, %noreg, 0, %noreg, killed %4
RET 0 RET 0
... ...
--- ---
name: test_64bitext name: test_64bitext
# CHECK-LABEL: name: test_64bitext # CHECK-LABEL: name: test_64bitext
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
Show All 37 Lines
body: | body: |
bb.0: bb.0:
liveins: %rdi, %zmm0, %zmm1 liveins: %rdi, %zmm0, %zmm1
%0 = COPY %rdi %0 = COPY %rdi
%1 = COPY %zmm0 %1 = COPY %zmm0
%2 = COPY %zmm1 %2 = COPY %zmm1
; CHECK: %8:vk8 = KMOVBkm %0, 1, _, 0, _ ; CHECK: %8:vk8 = KMOVBkm %0, 1, %noreg, 0, %noreg
; CHECK: %5:vk64 = COPY %8 ; CHECK: %5:vk64 = COPY %8
; CHECK: %9:vk16 = KMOVWkm %0, 1, _, 0, _ ; CHECK: %9:vk16 = KMOVWkm %0, 1, %noreg, 0, %noreg
; CHECK: %6:vk64 = COPY %9 ; CHECK: %6:vk64 = COPY %9
; CHECK: %7:vk64 = KADDQrr %5, %6 ; CHECK: %7:vk64 = KADDQrr %5, %6
%5 = MOVZX64rm8 %0, 1, _, 0, _ %5 = MOVZX64rm8 %0, 1, %noreg, 0, %noreg
%6 = MOVZX64rm16 %0, 1, _, 0, _ %6 = MOVZX64rm16 %0, 1, %noreg, 0, %noreg
%7 = ADD64rr %5, %6, implicit-def dead %eflags %7 = ADD64rr %5, %6, implicit-def dead %eflags
; CHECK: %3:vk64wm = COPY %7 ; CHECK: %3:vk64wm = COPY %7
%3 = COPY %7 %3 = COPY %7
%4 = VMOVDQU8Zrrk %2, killed %3, %1 %4 = VMOVDQU8Zrrk %2, killed %3, %1
VMOVDQA32Zmr %0, 1, _, 0, _, killed %4 VMOVDQA32Zmr %0, 1, %noreg, 0, %noreg, killed %4
RET 0 RET 0
... ...

llvm/trunk/test/CodeGen/X86/dynamic-alloca-lifetime.ll

Show All 35 Linesif.else130: ; preds = %bb1
call void @llvm.lifetime.start.p0i8(i64 8192, i8* %tmp25) #0 call void @llvm.lifetime.start.p0i8(i64 8192, i8* %tmp25) #0
call void @llvm.lifetime.end.p0i8(i64 8192, i8* %tmp25) #0 call void @llvm.lifetime.end.p0i8(i64 8192, i8* %tmp25) #0
br label %end1 br label %end1
} }
declare void @bar() declare void @bar()
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { ssp } attributes #1 = { ssp }
No newline at end of file

llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show All 11 Lines
... ...
--- ---
# CHECK-LABEL: name: evex_z256_to_vex_test # CHECK-LABEL: name: evex_z256_to_vex_test
# CHECK: bb.0: # CHECK: bb.0:
name: evex_z256_to_vex_test name: evex_z256_to_vex_test
body: | body: |
bb.0: bb.0:
; CHECK: VMOVAPDYmr %rdi, 1, _, 0, _, %ymm0 ; CHECK: VMOVAPDYmr %rdi, 1, %noreg, 0, %noreg, %ymm0
VMOVAPDZ256mr %rdi, 1, _, 0, _, %ymm0 VMOVAPDZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm0
; CHECK: %ymm0 = VMOVAPDYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMOVAPDYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMOVAPDZ256rm %rip, 1, _, %rax, _ %ymm0 = VMOVAPDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMOVAPDYrr %ymm0 ; CHECK: %ymm0 = VMOVAPDYrr %ymm0
%ymm0 = VMOVAPDZ256rr %ymm0 %ymm0 = VMOVAPDZ256rr %ymm0
; CHECK: %ymm0 = VMOVAPDYrr_REV %ymm0 ; CHECK: %ymm0 = VMOVAPDYrr_REV %ymm0
%ymm0 = VMOVAPDZ256rr_REV %ymm0 %ymm0 = VMOVAPDZ256rr_REV %ymm0
; CHECK: VMOVAPSYmr %rdi, 1, _, 0, _, %ymm0 ; CHECK: VMOVAPSYmr %rdi, 1, %noreg, 0, %noreg, %ymm0
VMOVAPSZ256mr %rdi, 1, _, 0, _, %ymm0 VMOVAPSZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm0
; CHECK: %ymm0 = VMOVAPSYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMOVAPSYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMOVAPSZ256rm %rip, 1, _, %rax, _ %ymm0 = VMOVAPSZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMOVAPSYrr %ymm0 ; CHECK: %ymm0 = VMOVAPSYrr %ymm0
%ymm0 = VMOVAPSZ256rr %ymm0 %ymm0 = VMOVAPSZ256rr %ymm0
; CHECK: %ymm0 = VMOVAPSYrr_REV %ymm0 ; CHECK: %ymm0 = VMOVAPSYrr_REV %ymm0
%ymm0 = VMOVAPSZ256rr_REV %ymm0 %ymm0 = VMOVAPSZ256rr_REV %ymm0
; CHECK: %ymm0 = VMOVDDUPYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMOVDDUPYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMOVDDUPZ256rm %rip, 1, _, %rax, _ %ymm0 = VMOVDDUPZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMOVDDUPYrr %ymm0 ; CHECK: %ymm0 = VMOVDDUPYrr %ymm0
%ymm0 = VMOVDDUPZ256rr %ymm0 %ymm0 = VMOVDDUPZ256rr %ymm0
; CHECK: VMOVDQAYmr %rdi, 1, _, 0, _, %ymm0 ; CHECK: VMOVDQAYmr %rdi, 1, %noreg, 0, %noreg, %ymm0
VMOVDQA32Z256mr %rdi, 1, _, 0, _, %ymm0 VMOVDQA32Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm0
; CHECK: %ymm0 = VMOVDQAYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMOVDQAYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMOVDQA32Z256rm %rip, 1, _, %rax, _ %ymm0 = VMOVDQA32Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMOVDQAYrr %ymm0 ; CHECK: %ymm0 = VMOVDQAYrr %ymm0
%ymm0 = VMOVDQA32Z256rr %ymm0 %ymm0 = VMOVDQA32Z256rr %ymm0
; CHECK: %ymm0 = VMOVDQAYrr_REV %ymm0 ; CHECK: %ymm0 = VMOVDQAYrr_REV %ymm0
%ymm0 = VMOVDQA32Z256rr_REV %ymm0 %ymm0 = VMOVDQA32Z256rr_REV %ymm0
; CHECK: VMOVDQAYmr %rdi, 1, _, 0, _, %ymm0 ; CHECK: VMOVDQAYmr %rdi, 1, %noreg, 0, %noreg, %ymm0
VMOVDQA64Z256mr %rdi, 1, _, 0, _, %ymm0 VMOVDQA64Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm0
; CHECK: %ymm0 = VMOVDQAYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMOVDQAYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMOVDQA64Z256rm %rip, 1, _, %rax, _ %ymm0 = VMOVDQA64Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMOVDQAYrr %ymm0 ; CHECK: %ymm0 = VMOVDQAYrr %ymm0
%ymm0 = VMOVDQA64Z256rr %ymm0 %ymm0 = VMOVDQA64Z256rr %ymm0
; CHECK: %ymm0 = VMOVDQAYrr_REV %ymm0 ; CHECK: %ymm0 = VMOVDQAYrr_REV %ymm0
%ymm0 = VMOVDQA64Z256rr_REV %ymm0 %ymm0 = VMOVDQA64Z256rr_REV %ymm0
; CHECK: VMOVDQUYmr %rdi, 1, _, 0, _, %ymm0 ; CHECK: VMOVDQUYmr %rdi, 1, %noreg, 0, %noreg, %ymm0
VMOVDQU16Z256mr %rdi, 1, _, 0, _, %ymm0 VMOVDQU16Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm0
; CHECK: %ymm0 = VMOVDQUYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMOVDQUYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMOVDQU16Z256rm %rip, 1, _, %rax, _ %ymm0 = VMOVDQU16Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMOVDQUYrr %ymm0 ; CHECK: %ymm0 = VMOVDQUYrr %ymm0
%ymm0 = VMOVDQU16Z256rr %ymm0 %ymm0 = VMOVDQU16Z256rr %ymm0
; CHECK: %ymm0 = VMOVDQUYrr_REV %ymm0 ; CHECK: %ymm0 = VMOVDQUYrr_REV %ymm0
%ymm0 = VMOVDQU16Z256rr_REV %ymm0 %ymm0 = VMOVDQU16Z256rr_REV %ymm0
; CHECK: VMOVDQUYmr %rdi, 1, _, 0, _, %ymm0 ; CHECK: VMOVDQUYmr %rdi, 1, %noreg, 0, %noreg, %ymm0
VMOVDQU32Z256mr %rdi, 1, _, 0, _, %ymm0 VMOVDQU32Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm0
; CHECK: %ymm0 = VMOVDQUYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMOVDQUYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMOVDQU32Z256rm %rip, 1, _, %rax, _ %ymm0 = VMOVDQU32Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMOVDQUYrr %ymm0 ; CHECK: %ymm0 = VMOVDQUYrr %ymm0
%ymm0 = VMOVDQU32Z256rr %ymm0 %ymm0 = VMOVDQU32Z256rr %ymm0
; CHECK: %ymm0 = VMOVDQUYrr_REV %ymm0 ; CHECK: %ymm0 = VMOVDQUYrr_REV %ymm0
%ymm0 = VMOVDQU32Z256rr_REV %ymm0 %ymm0 = VMOVDQU32Z256rr_REV %ymm0
; CHECK: VMOVDQUYmr %rdi, 1, _, 0, _, %ymm0 ; CHECK: VMOVDQUYmr %rdi, 1, %noreg, 0, %noreg, %ymm0
VMOVDQU64Z256mr %rdi, 1, _, 0, _, %ymm0 VMOVDQU64Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm0
; CHECK: %ymm0 = VMOVDQUYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMOVDQUYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMOVDQU64Z256rm %rip, 1, _, %rax, _ %ymm0 = VMOVDQU64Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMOVDQUYrr %ymm0 ; CHECK: %ymm0 = VMOVDQUYrr %ymm0
%ymm0 = VMOVDQU64Z256rr %ymm0 %ymm0 = VMOVDQU64Z256rr %ymm0
; CHECK: %ymm0 = VMOVDQUYrr_REV %ymm0 ; CHECK: %ymm0 = VMOVDQUYrr_REV %ymm0
%ymm0 = VMOVDQU64Z256rr_REV %ymm0 %ymm0 = VMOVDQU64Z256rr_REV %ymm0
; CHECK: VMOVDQUYmr %rdi, 1, _, 0, _, %ymm0 ; CHECK: VMOVDQUYmr %rdi, 1, %noreg, 0, %noreg, %ymm0
VMOVDQU8Z256mr %rdi, 1, _, 0, _, %ymm0 VMOVDQU8Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm0
; CHECK: %ymm0 = VMOVDQUYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMOVDQUYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMOVDQU8Z256rm %rip, 1, _, %rax, _ %ymm0 = VMOVDQU8Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMOVDQUYrr %ymm0 ; CHECK: %ymm0 = VMOVDQUYrr %ymm0
%ymm0 = VMOVDQU8Z256rr %ymm0 %ymm0 = VMOVDQU8Z256rr %ymm0
; CHECK: %ymm0 = VMOVDQUYrr_REV %ymm0 ; CHECK: %ymm0 = VMOVDQUYrr_REV %ymm0
%ymm0 = VMOVDQU8Z256rr_REV %ymm0 %ymm0 = VMOVDQU8Z256rr_REV %ymm0
; CHECK: %ymm0 = VMOVNTDQAYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMOVNTDQAYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMOVNTDQAZ256rm %rip, 1, _, %rax, _ %ymm0 = VMOVNTDQAZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: VMOVNTDQYmr %rdi, 1, _, 0, _, %ymm0 ; CHECK: VMOVNTDQYmr %rdi, 1, %noreg, 0, %noreg, %ymm0
VMOVNTDQZ256mr %rdi, 1, _, 0, _, %ymm0 VMOVNTDQZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm0
; CHECK: VMOVNTPDYmr %rdi, 1, _, 0, _, %ymm0 ; CHECK: VMOVNTPDYmr %rdi, 1, %noreg, 0, %noreg, %ymm0
VMOVNTPDZ256mr %rdi, 1, _, 0, _, %ymm0 VMOVNTPDZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm0
; CHECK: VMOVNTPSYmr %rdi, 1, _, 0, _, %ymm0 ; CHECK: VMOVNTPSYmr %rdi, 1, %noreg, 0, %noreg, %ymm0
VMOVNTPSZ256mr %rdi, 1, _, 0, _, %ymm0 VMOVNTPSZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm0
; CHECK: %ymm0 = VMOVSHDUPYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMOVSHDUPYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMOVSHDUPZ256rm %rip, 1, _, %rax, _ %ymm0 = VMOVSHDUPZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMOVSHDUPYrr %ymm0 ; CHECK: %ymm0 = VMOVSHDUPYrr %ymm0
%ymm0 = VMOVSHDUPZ256rr %ymm0 %ymm0 = VMOVSHDUPZ256rr %ymm0
; CHECK: %ymm0 = VMOVSLDUPYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMOVSLDUPYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMOVSLDUPZ256rm %rip, 1, _, %rax, _ %ymm0 = VMOVSLDUPZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMOVSLDUPYrr %ymm0 ; CHECK: %ymm0 = VMOVSLDUPYrr %ymm0
%ymm0 = VMOVSLDUPZ256rr %ymm0 %ymm0 = VMOVSLDUPZ256rr %ymm0
; CHECK: VMOVUPDYmr %rdi, 1, _, 0, _, %ymm0 ; CHECK: VMOVUPDYmr %rdi, 1, %noreg, 0, %noreg, %ymm0
VMOVUPDZ256mr %rdi, 1, _, 0, _, %ymm0 VMOVUPDZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm0
; CHECK: %ymm0 = VMOVUPDYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMOVUPDYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMOVUPDZ256rm %rip, 1, _, %rax, _ %ymm0 = VMOVUPDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMOVUPDYrr %ymm0 ; CHECK: %ymm0 = VMOVUPDYrr %ymm0
%ymm0 = VMOVUPDZ256rr %ymm0 %ymm0 = VMOVUPDZ256rr %ymm0
; CHECK: %ymm0 = VMOVUPDYrr_REV %ymm0 ; CHECK: %ymm0 = VMOVUPDYrr_REV %ymm0
%ymm0 = VMOVUPDZ256rr_REV %ymm0 %ymm0 = VMOVUPDZ256rr_REV %ymm0
; CHECK: VMOVUPSYmr %rdi, 1, _, 0, _, %ymm0 ; CHECK: VMOVUPSYmr %rdi, 1, %noreg, 0, %noreg, %ymm0
VMOVUPSZ256mr %rdi, 1, _, 0, _, %ymm0 VMOVUPSZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm0
; CHECK: %ymm0 = VPANDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPANDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPANDDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPANDDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPANDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPANDYrr %ymm0, %ymm1
%ymm0 = VPANDDZ256rr %ymm0, %ymm1 %ymm0 = VPANDDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPANDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPANDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPANDQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPANDQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPANDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPANDYrr %ymm0, %ymm1
%ymm0 = VPANDQZ256rr %ymm0, %ymm1 %ymm0 = VPANDQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPANDNYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPANDNYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPANDNDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPANDNDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPANDNYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPANDNYrr %ymm0, %ymm1
%ymm0 = VPANDNDZ256rr %ymm0, %ymm1 %ymm0 = VPANDNDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPANDNYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPANDNYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPANDNQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPANDNQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPANDNYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPANDNYrr %ymm0, %ymm1
%ymm0 = VPANDNQZ256rr %ymm0, %ymm1 %ymm0 = VPANDNQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPAVGBYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPAVGBYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPAVGBZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPAVGBZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPAVGBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPAVGBYrr %ymm0, %ymm1
%ymm0 = VPAVGBZ256rr %ymm0, %ymm1 %ymm0 = VPAVGBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPAVGWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPAVGWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPAVGWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPAVGWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPAVGWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPAVGWYrr %ymm0, %ymm1
%ymm0 = VPAVGWZ256rr %ymm0, %ymm1 %ymm0 = VPAVGWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPADDBYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPADDBYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPADDBZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPADDBZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPADDBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPADDBYrr %ymm0, %ymm1
%ymm0 = VPADDBZ256rr %ymm0, %ymm1 %ymm0 = VPADDBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPADDDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPADDDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPADDDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPADDDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPADDDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPADDDYrr %ymm0, %ymm1
%ymm0 = VPADDDZ256rr %ymm0, %ymm1 %ymm0 = VPADDDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPADDQYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPADDQYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPADDQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPADDQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPADDQYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPADDQYrr %ymm0, %ymm1
%ymm0 = VPADDQZ256rr %ymm0, %ymm1 %ymm0 = VPADDQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPADDSBYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPADDSBYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPADDSBZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPADDSBZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPADDSBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPADDSBYrr %ymm0, %ymm1
%ymm0 = VPADDSBZ256rr %ymm0, %ymm1 %ymm0 = VPADDSBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPADDSWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPADDSWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPADDSWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPADDSWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPADDSWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPADDSWYrr %ymm0, %ymm1
%ymm0 = VPADDSWZ256rr %ymm0, %ymm1 %ymm0 = VPADDSWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPADDUSBYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPADDUSBYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPADDUSBZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPADDUSBZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPADDUSBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPADDUSBYrr %ymm0, %ymm1
%ymm0 = VPADDUSBZ256rr %ymm0, %ymm1 %ymm0 = VPADDUSBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPADDUSWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPADDUSWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPADDUSWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPADDUSWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPADDUSWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPADDUSWYrr %ymm0, %ymm1
%ymm0 = VPADDUSWZ256rr %ymm0, %ymm1 %ymm0 = VPADDUSWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPADDWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPADDWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPADDWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPADDWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPADDWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPADDWYrr %ymm0, %ymm1
%ymm0 = VPADDWZ256rr %ymm0, %ymm1 %ymm0 = VPADDWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VMULPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMULPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMULPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VMULPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMULPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VMULPDYrr %ymm0, %ymm1
%ymm0 = VMULPDZ256rr %ymm0, %ymm1 %ymm0 = VMULPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VMULPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMULPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMULPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VMULPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMULPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VMULPSYrr %ymm0, %ymm1
%ymm0 = VMULPSZ256rr %ymm0, %ymm1 %ymm0 = VMULPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VORPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VORPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VORPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VORPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VORPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VORPDYrr %ymm0, %ymm1
%ymm0 = VORPDZ256rr %ymm0, %ymm1 %ymm0 = VORPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VORPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VORPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VORPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VORPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VORPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VORPSYrr %ymm0, %ymm1
%ymm0 = VORPSZ256rr %ymm0, %ymm1 %ymm0 = VORPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMADDUBSWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMADDUBSWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMADDUBSWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMADDUBSWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMADDUBSWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMADDUBSWYrr %ymm0, %ymm1
%ymm0 = VPMADDUBSWZ256rr %ymm0, %ymm1 %ymm0 = VPMADDUBSWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMADDWDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMADDWDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMADDWDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMADDWDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMADDWDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMADDWDYrr %ymm0, %ymm1
%ymm0 = VPMADDWDZ256rr %ymm0, %ymm1 %ymm0 = VPMADDWDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMAXSBYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMAXSBYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMAXSBZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMAXSBZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMAXSBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMAXSBYrr %ymm0, %ymm1
%ymm0 = VPMAXSBZ256rr %ymm0, %ymm1 %ymm0 = VPMAXSBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMAXSDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMAXSDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMAXSDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMAXSDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMAXSDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMAXSDYrr %ymm0, %ymm1
%ymm0 = VPMAXSDZ256rr %ymm0, %ymm1 %ymm0 = VPMAXSDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMAXSWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMAXSWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMAXSWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMAXSWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMAXSWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMAXSWYrr %ymm0, %ymm1
%ymm0 = VPMAXSWZ256rr %ymm0, %ymm1 %ymm0 = VPMAXSWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMAXUBYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMAXUBYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMAXUBZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMAXUBZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMAXUBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMAXUBYrr %ymm0, %ymm1
%ymm0 = VPMAXUBZ256rr %ymm0, %ymm1 %ymm0 = VPMAXUBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMAXUDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMAXUDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMAXUDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMAXUDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMAXUDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMAXUDYrr %ymm0, %ymm1
%ymm0 = VPMAXUDZ256rr %ymm0, %ymm1 %ymm0 = VPMAXUDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMAXUWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMAXUWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMAXUWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMAXUWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMAXUWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMAXUWYrr %ymm0, %ymm1
%ymm0 = VPMAXUWZ256rr %ymm0, %ymm1 %ymm0 = VPMAXUWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMINSBYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMINSBYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMINSBZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMINSBZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMINSBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMINSBYrr %ymm0, %ymm1
%ymm0 = VPMINSBZ256rr %ymm0, %ymm1 %ymm0 = VPMINSBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMINSDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMINSDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMINSDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMINSDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMINSDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMINSDYrr %ymm0, %ymm1
%ymm0 = VPMINSDZ256rr %ymm0, %ymm1 %ymm0 = VPMINSDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMINSWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMINSWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMINSWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMINSWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMINSWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMINSWYrr %ymm0, %ymm1
%ymm0 = VPMINSWZ256rr %ymm0, %ymm1 %ymm0 = VPMINSWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMINUBYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMINUBYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMINUBZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMINUBZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMINUBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMINUBYrr %ymm0, %ymm1
%ymm0 = VPMINUBZ256rr %ymm0, %ymm1 %ymm0 = VPMINUBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMINUDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMINUDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMINUDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMINUDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMINUDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMINUDYrr %ymm0, %ymm1
%ymm0 = VPMINUDZ256rr %ymm0, %ymm1 %ymm0 = VPMINUDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMINUWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMINUWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMINUWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMINUWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMINUWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMINUWYrr %ymm0, %ymm1
%ymm0 = VPMINUWZ256rr %ymm0, %ymm1 %ymm0 = VPMINUWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMULDQYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMULDQYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMULDQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMULDQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMULDQYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMULDQYrr %ymm0, %ymm1
%ymm0 = VPMULDQZ256rr %ymm0, %ymm1 %ymm0 = VPMULDQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMULHRSWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMULHRSWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMULHRSWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMULHRSWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMULHRSWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMULHRSWYrr %ymm0, %ymm1
%ymm0 = VPMULHRSWZ256rr %ymm0, %ymm1 %ymm0 = VPMULHRSWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMULHUWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMULHUWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMULHUWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMULHUWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMULHUWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMULHUWYrr %ymm0, %ymm1
%ymm0 = VPMULHUWZ256rr %ymm0, %ymm1 %ymm0 = VPMULHUWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMULHWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMULHWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMULHWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMULHWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMULHWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMULHWYrr %ymm0, %ymm1
%ymm0 = VPMULHWZ256rr %ymm0, %ymm1 %ymm0 = VPMULHWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMULLDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMULLDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMULLDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMULLDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMULLDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMULLDYrr %ymm0, %ymm1
%ymm0 = VPMULLDZ256rr %ymm0, %ymm1 %ymm0 = VPMULLDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMULLWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMULLWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMULLWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMULLWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMULLWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMULLWYrr %ymm0, %ymm1
%ymm0 = VPMULLWZ256rr %ymm0, %ymm1 %ymm0 = VPMULLWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPMULUDQYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMULUDQYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMULUDQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPMULUDQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMULUDQYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPMULUDQYrr %ymm0, %ymm1
%ymm0 = VPMULUDQZ256rr %ymm0, %ymm1 %ymm0 = VPMULUDQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPORYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPORYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPORDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPORDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPORYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPORYrr %ymm0, %ymm1
%ymm0 = VPORDZ256rr %ymm0, %ymm1 %ymm0 = VPORDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPORYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPORYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPORQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPORQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPORYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPORYrr %ymm0, %ymm1
%ymm0 = VPORQZ256rr %ymm0, %ymm1 %ymm0 = VPORQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPSUBBYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSUBBYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSUBBZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSUBBZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSUBBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPSUBBYrr %ymm0, %ymm1
%ymm0 = VPSUBBZ256rr %ymm0, %ymm1 %ymm0 = VPSUBBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPSUBDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSUBDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSUBDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSUBDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSUBDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPSUBDYrr %ymm0, %ymm1
%ymm0 = VPSUBDZ256rr %ymm0, %ymm1 %ymm0 = VPSUBDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPSUBQYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSUBQYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSUBQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSUBQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSUBQYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPSUBQYrr %ymm0, %ymm1
%ymm0 = VPSUBQZ256rr %ymm0, %ymm1 %ymm0 = VPSUBQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPSUBSBYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSUBSBYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSUBSBZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSUBSBZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSUBSBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPSUBSBYrr %ymm0, %ymm1
%ymm0 = VPSUBSBZ256rr %ymm0, %ymm1 %ymm0 = VPSUBSBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPSUBSWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSUBSWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSUBSWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSUBSWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSUBSWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPSUBSWYrr %ymm0, %ymm1
%ymm0 = VPSUBSWZ256rr %ymm0, %ymm1 %ymm0 = VPSUBSWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPSUBUSBYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSUBUSBYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSUBUSBZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSUBUSBZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSUBUSBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPSUBUSBYrr %ymm0, %ymm1
%ymm0 = VPSUBUSBZ256rr %ymm0, %ymm1 %ymm0 = VPSUBUSBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPSUBUSWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSUBUSWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSUBUSWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSUBUSWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSUBUSWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPSUBUSWYrr %ymm0, %ymm1
%ymm0 = VPSUBUSWZ256rr %ymm0, %ymm1 %ymm0 = VPSUBUSWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPSUBWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSUBWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSUBWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSUBWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSUBWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPSUBWYrr %ymm0, %ymm1
%ymm0 = VPSUBWZ256rr %ymm0, %ymm1 %ymm0 = VPSUBWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPXORYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPXORYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPXORDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPXORDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPXORYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPXORYrr %ymm0, %ymm1
%ymm0 = VPXORDZ256rr %ymm0, %ymm1 %ymm0 = VPXORDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPXORYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPXORYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPXORQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPXORQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPXORYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPXORYrr %ymm0, %ymm1
%ymm0 = VPXORQZ256rr %ymm0, %ymm1 %ymm0 = VPXORQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VADDPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VADDPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VADDPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VADDPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VADDPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VADDPDYrr %ymm0, %ymm1
%ymm0 = VADDPDZ256rr %ymm0, %ymm1 %ymm0 = VADDPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VADDPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VADDPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VADDPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VADDPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VADDPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VADDPSYrr %ymm0, %ymm1
%ymm0 = VADDPSZ256rr %ymm0, %ymm1 %ymm0 = VADDPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VANDNPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VANDNPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VANDNPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VANDNPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VANDNPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VANDNPDYrr %ymm0, %ymm1
%ymm0 = VANDNPDZ256rr %ymm0, %ymm1 %ymm0 = VANDNPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VANDNPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VANDNPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VANDNPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VANDNPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VANDNPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VANDNPSYrr %ymm0, %ymm1
%ymm0 = VANDNPSZ256rr %ymm0, %ymm1 %ymm0 = VANDNPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VANDPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VANDPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VANDPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VANDPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VANDPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VANDPDYrr %ymm0, %ymm1
%ymm0 = VANDPDZ256rr %ymm0, %ymm1 %ymm0 = VANDPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VANDPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VANDPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VANDPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VANDPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VANDPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VANDPSYrr %ymm0, %ymm1
%ymm0 = VANDPSZ256rr %ymm0, %ymm1 %ymm0 = VANDPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VDIVPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VDIVPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VDIVPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VDIVPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VDIVPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VDIVPDYrr %ymm0, %ymm1
%ymm0 = VDIVPDZ256rr %ymm0, %ymm1 %ymm0 = VDIVPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VDIVPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VDIVPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VDIVPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VDIVPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VDIVPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VDIVPSYrr %ymm0, %ymm1
%ymm0 = VDIVPSZ256rr %ymm0, %ymm1 %ymm0 = VDIVPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VMAXCPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMAXCPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMAXCPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VMAXCPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMAXCPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VMAXCPDYrr %ymm0, %ymm1
%ymm0 = VMAXCPDZ256rr %ymm0, %ymm1 %ymm0 = VMAXCPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VMAXCPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMAXCPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMAXCPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VMAXCPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMAXCPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VMAXCPSYrr %ymm0, %ymm1
%ymm0 = VMAXCPSZ256rr %ymm0, %ymm1 %ymm0 = VMAXCPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VMAXCPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMAXCPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMAXPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VMAXPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMAXCPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VMAXCPDYrr %ymm0, %ymm1
%ymm0 = VMAXPDZ256rr %ymm0, %ymm1 %ymm0 = VMAXPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VMAXCPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMAXCPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMAXPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VMAXPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMAXCPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VMAXCPSYrr %ymm0, %ymm1
%ymm0 = VMAXPSZ256rr %ymm0, %ymm1 %ymm0 = VMAXPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VMINCPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMINCPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMINCPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VMINCPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMINCPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VMINCPDYrr %ymm0, %ymm1
%ymm0 = VMINCPDZ256rr %ymm0, %ymm1 %ymm0 = VMINCPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VMINCPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMINCPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMINCPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VMINCPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMINCPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VMINCPSYrr %ymm0, %ymm1
%ymm0 = VMINCPSZ256rr %ymm0, %ymm1 %ymm0 = VMINCPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VMINCPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMINCPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMINPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VMINPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMINCPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VMINCPDYrr %ymm0, %ymm1
%ymm0 = VMINPDZ256rr %ymm0, %ymm1 %ymm0 = VMINPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VMINCPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VMINCPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VMINPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VMINPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VMINCPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VMINCPSYrr %ymm0, %ymm1
%ymm0 = VMINPSZ256rr %ymm0, %ymm1 %ymm0 = VMINPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VXORPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VXORPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VXORPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VXORPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VXORPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VXORPDYrr %ymm0, %ymm1
%ymm0 = VXORPDZ256rr %ymm0, %ymm1 %ymm0 = VXORPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VXORPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VXORPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VXORPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VXORPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VXORPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VXORPSYrr %ymm0, %ymm1
%ymm0 = VXORPSZ256rr %ymm0, %ymm1 %ymm0 = VXORPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPACKSSDWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPACKSSDWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPACKSSDWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPACKSSDWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPACKSSDWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPACKSSDWYrr %ymm0, %ymm1
%ymm0 = VPACKSSDWZ256rr %ymm0, %ymm1 %ymm0 = VPACKSSDWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPACKSSWBYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPACKSSWBYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPACKSSWBZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPACKSSWBZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPACKSSWBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPACKSSWBYrr %ymm0, %ymm1
%ymm0 = VPACKSSWBZ256rr %ymm0, %ymm1 %ymm0 = VPACKSSWBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPACKUSDWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPACKUSDWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPACKUSDWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPACKUSDWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPACKUSDWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPACKUSDWYrr %ymm0, %ymm1
%ymm0 = VPACKUSDWZ256rr %ymm0, %ymm1 %ymm0 = VPACKUSDWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPACKUSWBYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPACKUSWBYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPACKUSWBZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPACKUSWBZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPACKUSWBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPACKUSWBYrr %ymm0, %ymm1
%ymm0 = VPACKUSWBZ256rr %ymm0, %ymm1 %ymm0 = VPACKUSWBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VUNPCKHPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VUNPCKHPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VUNPCKHPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VUNPCKHPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VUNPCKHPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VUNPCKHPDYrr %ymm0, %ymm1
%ymm0 = VUNPCKHPDZ256rr %ymm0, %ymm1 %ymm0 = VUNPCKHPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VUNPCKHPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VUNPCKHPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VUNPCKHPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VUNPCKHPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VUNPCKHPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VUNPCKHPSYrr %ymm0, %ymm1
%ymm0 = VUNPCKHPSZ256rr %ymm0, %ymm1 %ymm0 = VUNPCKHPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VUNPCKLPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VUNPCKLPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VUNPCKLPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VUNPCKLPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VUNPCKLPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VUNPCKLPDYrr %ymm0, %ymm1
%ymm0 = VUNPCKLPDZ256rr %ymm0, %ymm1 %ymm0 = VUNPCKLPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VUNPCKLPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VUNPCKLPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VUNPCKLPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VUNPCKLPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VUNPCKLPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VUNPCKLPSYrr %ymm0, %ymm1
%ymm0 = VUNPCKLPSZ256rr %ymm0, %ymm1 %ymm0 = VUNPCKLPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VSUBPDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VSUBPDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VSUBPDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VSUBPDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VSUBPDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VSUBPDYrr %ymm0, %ymm1
%ymm0 = VSUBPDZ256rr %ymm0, %ymm1 %ymm0 = VSUBPDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VSUBPSYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VSUBPSYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VSUBPSZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VSUBPSZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VSUBPSYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VSUBPSYrr %ymm0, %ymm1
%ymm0 = VSUBPSZ256rr %ymm0, %ymm1 %ymm0 = VSUBPSZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPUNPCKHBWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPUNPCKHBWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPUNPCKHBWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPUNPCKHBWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPUNPCKHBWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPUNPCKHBWYrr %ymm0, %ymm1
%ymm0 = VPUNPCKHBWZ256rr %ymm0, %ymm1 %ymm0 = VPUNPCKHBWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPUNPCKHDQYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPUNPCKHDQYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPUNPCKHDQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPUNPCKHDQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPUNPCKHDQYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPUNPCKHDQYrr %ymm0, %ymm1
%ymm0 = VPUNPCKHDQZ256rr %ymm0, %ymm1 %ymm0 = VPUNPCKHDQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPUNPCKHQDQYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPUNPCKHQDQYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPUNPCKHQDQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPUNPCKHQDQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPUNPCKHQDQYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPUNPCKHQDQYrr %ymm0, %ymm1
%ymm0 = VPUNPCKHQDQZ256rr %ymm0, %ymm1 %ymm0 = VPUNPCKHQDQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPUNPCKHWDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPUNPCKHWDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPUNPCKHWDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPUNPCKHWDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPUNPCKHWDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPUNPCKHWDYrr %ymm0, %ymm1
%ymm0 = VPUNPCKHWDZ256rr %ymm0, %ymm1 %ymm0 = VPUNPCKHWDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPUNPCKLBWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPUNPCKLBWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPUNPCKLBWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPUNPCKLBWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPUNPCKLBWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPUNPCKLBWYrr %ymm0, %ymm1
%ymm0 = VPUNPCKLBWZ256rr %ymm0, %ymm1 %ymm0 = VPUNPCKLBWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPUNPCKLDQYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPUNPCKLDQYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPUNPCKLDQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPUNPCKLDQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPUNPCKLDQYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPUNPCKLDQYrr %ymm0, %ymm1
%ymm0 = VPUNPCKLDQZ256rr %ymm0, %ymm1 %ymm0 = VPUNPCKLDQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPUNPCKLQDQYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPUNPCKLQDQYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPUNPCKLQDQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPUNPCKLQDQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPUNPCKLQDQYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPUNPCKLQDQYrr %ymm0, %ymm1
%ymm0 = VPUNPCKLQDQZ256rr %ymm0, %ymm1 %ymm0 = VPUNPCKLQDQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPUNPCKLWDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPUNPCKLWDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPUNPCKLWDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPUNPCKLWDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPUNPCKLWDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPUNPCKLWDYrr %ymm0, %ymm1
%ymm0 = VPUNPCKLWDZ256rr %ymm0, %ymm1 %ymm0 = VPUNPCKLWDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VFMADD132PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMADD132PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMADD132PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMADD132PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMADD132PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMADD132PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMADD132PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMADD132PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMADD132PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMADD132PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMADD132PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMADD132PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMADD132PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMADD132PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMADD132PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMADD132PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMADD213PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMADD213PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMADD213PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMADD213PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMADD213PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMADD213PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMADD213PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMADD213PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMADD213PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMADD213PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMADD213PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMADD213PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMADD213PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMADD213PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMADD213PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMADD213PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMADD231PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMADD231PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMADD231PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMADD231PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMADD231PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMADD231PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMADD231PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMADD231PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMADD231PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMADD231PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMADD231PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMADD231PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMADD231PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMADD231PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMADD231PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMADD231PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMADDSUB132PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMADDSUB132PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMADDSUB132PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMADDSUB132PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMADDSUB132PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMADDSUB132PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMADDSUB132PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMADDSUB132PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMADDSUB132PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMADDSUB132PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMADDSUB132PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMADDSUB132PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMADDSUB132PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMADDSUB132PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMADDSUB132PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMADDSUB132PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMADDSUB213PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMADDSUB213PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMADDSUB213PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMADDSUB213PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMADDSUB213PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMADDSUB213PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMADDSUB213PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMADDSUB213PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMADDSUB213PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMADDSUB213PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMADDSUB213PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMADDSUB213PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMADDSUB213PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMADDSUB213PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMADDSUB213PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMADDSUB213PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMADDSUB231PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMADDSUB231PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMADDSUB231PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMADDSUB231PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMADDSUB231PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMADDSUB231PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMADDSUB231PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMADDSUB231PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMADDSUB231PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMADDSUB231PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMADDSUB231PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMADDSUB231PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMADDSUB231PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMADDSUB231PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMADDSUB231PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMADDSUB231PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMSUB132PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMSUB132PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMSUB132PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMSUB132PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMSUB132PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMSUB132PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMSUB132PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMSUB132PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMSUB132PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMSUB132PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMSUB132PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMSUB132PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMSUB132PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMSUB132PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMSUB132PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMSUB132PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMSUB213PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMSUB213PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMSUB213PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMSUB213PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMSUB213PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMSUB213PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMSUB213PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMSUB213PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMSUB213PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMSUB213PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMSUB213PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMSUB213PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMSUB213PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMSUB213PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMSUB213PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMSUB213PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMSUB231PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMSUB231PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMSUB231PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMSUB231PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMSUB231PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMSUB231PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMSUB231PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMSUB231PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMSUB231PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMSUB231PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMSUB231PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMSUB231PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMSUB231PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMSUB231PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMSUB231PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMSUB231PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMSUBADD132PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMSUBADD132PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMSUBADD132PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMSUBADD132PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMSUBADD132PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMSUBADD132PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMSUBADD132PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMSUBADD132PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMSUBADD132PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMSUBADD132PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMSUBADD132PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMSUBADD132PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMSUBADD132PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMSUBADD132PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMSUBADD132PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMSUBADD132PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMSUBADD213PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMSUBADD213PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMSUBADD213PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMSUBADD213PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMSUBADD213PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMSUBADD213PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMSUBADD213PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMSUBADD213PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMSUBADD213PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMSUBADD213PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMSUBADD213PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMSUBADD213PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMSUBADD213PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMSUBADD213PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMSUBADD213PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMSUBADD213PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMSUBADD231PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMSUBADD231PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMSUBADD231PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMSUBADD231PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMSUBADD231PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMSUBADD231PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMSUBADD231PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMSUBADD231PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFMSUBADD231PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFMSUBADD231PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFMSUBADD231PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFMSUBADD231PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFMSUBADD231PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFMSUBADD231PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFMSUBADD231PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFMSUBADD231PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFNMADD132PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFNMADD132PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFNMADD132PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFNMADD132PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFNMADD132PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFNMADD132PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFNMADD132PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFNMADD132PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFNMADD132PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFNMADD132PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFNMADD132PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFNMADD132PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFNMADD132PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFNMADD132PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFNMADD132PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFNMADD132PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFNMADD213PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFNMADD213PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFNMADD213PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFNMADD213PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFNMADD213PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFNMADD213PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFNMADD213PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFNMADD213PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFNMADD213PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFNMADD213PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFNMADD213PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFNMADD213PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFNMADD213PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFNMADD213PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFNMADD213PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFNMADD213PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFNMADD231PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFNMADD231PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFNMADD231PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFNMADD231PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFNMADD231PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFNMADD231PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFNMADD231PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFNMADD231PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFNMADD231PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFNMADD231PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFNMADD231PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFNMADD231PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFNMADD231PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFNMADD231PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFNMADD231PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFNMADD231PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFNMSUB132PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFNMSUB132PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFNMSUB132PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFNMSUB132PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFNMSUB132PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFNMSUB132PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFNMSUB132PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFNMSUB132PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFNMSUB132PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFNMSUB132PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFNMSUB132PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFNMSUB132PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFNMSUB132PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFNMSUB132PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFNMSUB132PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFNMSUB132PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFNMSUB213PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFNMSUB213PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFNMSUB213PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFNMSUB213PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFNMSUB213PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFNMSUB213PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFNMSUB213PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFNMSUB213PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFNMSUB213PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFNMSUB213PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFNMSUB213PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFNMSUB213PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFNMSUB213PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFNMSUB213PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFNMSUB213PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFNMSUB213PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFNMSUB231PDYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFNMSUB231PDYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFNMSUB231PDZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFNMSUB231PDZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFNMSUB231PDYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFNMSUB231PDYr %ymm0, %ymm1, %ymm2
%ymm0 = VFNMSUB231PDZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFNMSUB231PDZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VFNMSUB231PSYm %ymm0, %ymm0, %rsi, 1, _, 0, _ ; CHECK: %ymm0 = VFNMSUB231PSYm %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
%ymm0 = VFNMSUB231PSZ256m %ymm0, %ymm0, %rsi, 1, _, 0, _ %ymm0 = VFNMSUB231PSZ256m %ymm0, %ymm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VFNMSUB231PSYr %ymm0, %ymm1, %ymm2 ; CHECK: %ymm0 = VFNMSUB231PSYr %ymm0, %ymm1, %ymm2
%ymm0 = VFNMSUB231PSZ256r %ymm0, %ymm1, %ymm2 %ymm0 = VFNMSUB231PSZ256r %ymm0, %ymm1, %ymm2
; CHECK: %ymm0 = VPSRADYri %ymm0, 7 ; CHECK: %ymm0 = VPSRADYri %ymm0, 7
%ymm0 = VPSRADZ256ri %ymm0, 7 %ymm0 = VPSRADZ256ri %ymm0, 7
; CHECK: %ymm0 = VPSRADYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSRADYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSRADZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSRADZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSRADYrr %ymm0, %xmm1 ; CHECK: %ymm0 = VPSRADYrr %ymm0, %xmm1
%ymm0 = VPSRADZ256rr %ymm0, %xmm1 %ymm0 = VPSRADZ256rr %ymm0, %xmm1
; CHECK: %ymm0 = VPSRAVDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSRAVDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSRAVDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSRAVDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSRAVDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPSRAVDYrr %ymm0, %ymm1
%ymm0 = VPSRAVDZ256rr %ymm0, %ymm1 %ymm0 = VPSRAVDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPSRAWYri %ymm0, 7 ; CHECK: %ymm0 = VPSRAWYri %ymm0, 7
%ymm0 = VPSRAWZ256ri %ymm0, 7 %ymm0 = VPSRAWZ256ri %ymm0, 7
; CHECK: %ymm0 = VPSRAWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSRAWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSRAWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSRAWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSRAWYrr %ymm0, %xmm1 ; CHECK: %ymm0 = VPSRAWYrr %ymm0, %xmm1
%ymm0 = VPSRAWZ256rr %ymm0, %xmm1 %ymm0 = VPSRAWZ256rr %ymm0, %xmm1
; CHECK: %ymm0 = VPSRLDQYri %ymm0, %ymm1 ; CHECK: %ymm0 = VPSRLDQYri %ymm0, %ymm1
%ymm0 = VPSRLDQZ256rr %ymm0, %ymm1 %ymm0 = VPSRLDQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPSRLDYri %ymm0, 7 ; CHECK: %ymm0 = VPSRLDYri %ymm0, 7
%ymm0 = VPSRLDZ256ri %ymm0, 7 %ymm0 = VPSRLDZ256ri %ymm0, 7
; CHECK: %ymm0 = VPSRLDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSRLDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSRLDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSRLDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSRLDYrr %ymm0, %xmm1 ; CHECK: %ymm0 = VPSRLDYrr %ymm0, %xmm1
%ymm0 = VPSRLDZ256rr %ymm0, %xmm1 %ymm0 = VPSRLDZ256rr %ymm0, %xmm1
; CHECK: %ymm0 = VPSRLQYri %ymm0, 7 ; CHECK: %ymm0 = VPSRLQYri %ymm0, 7
%ymm0 = VPSRLQZ256ri %ymm0, 7 %ymm0 = VPSRLQZ256ri %ymm0, 7
; CHECK: %ymm0 = VPSRLQYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSRLQYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSRLQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSRLQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSRLQYrr %ymm0, %xmm1 ; CHECK: %ymm0 = VPSRLQYrr %ymm0, %xmm1
%ymm0 = VPSRLQZ256rr %ymm0, %xmm1 %ymm0 = VPSRLQZ256rr %ymm0, %xmm1
; CHECK: %ymm0 = VPSRLVDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSRLVDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSRLVDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSRLVDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSRLVDYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPSRLVDYrr %ymm0, %ymm1
%ymm0 = VPSRLVDZ256rr %ymm0, %ymm1 %ymm0 = VPSRLVDZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPSRLVQYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSRLVQYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSRLVQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSRLVQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSRLVQYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPSRLVQYrr %ymm0, %ymm1
%ymm0 = VPSRLVQZ256rr %ymm0, %ymm1 %ymm0 = VPSRLVQZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPSRLWYri %ymm0, 7 ; CHECK: %ymm0 = VPSRLWYri %ymm0, 7
%ymm0 = VPSRLWZ256ri %ymm0, 7 %ymm0 = VPSRLWZ256ri %ymm0, 7
; CHECK: %ymm0 = VPSRLWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSRLWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSRLWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSRLWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSRLWYrr %ymm0, %xmm1 ; CHECK: %ymm0 = VPSRLWYrr %ymm0, %xmm1
%ymm0 = VPSRLWZ256rr %ymm0, %xmm1 %ymm0 = VPSRLWZ256rr %ymm0, %xmm1
; CHECK: %ymm0 = VPMOVSXBDYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMOVSXBDYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMOVSXBDZ256rm %rip, 1, _, %rax, _ %ymm0 = VPMOVSXBDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMOVSXBDYrr %xmm0 ; CHECK: %ymm0 = VPMOVSXBDYrr %xmm0
%ymm0 = VPMOVSXBDZ256rr %xmm0 %ymm0 = VPMOVSXBDZ256rr %xmm0
; CHECK: %ymm0 = VPMOVSXBQYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMOVSXBQYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMOVSXBQZ256rm %rip, 1, _, %rax, _ %ymm0 = VPMOVSXBQZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMOVSXBQYrr %xmm0 ; CHECK: %ymm0 = VPMOVSXBQYrr %xmm0
%ymm0 = VPMOVSXBQZ256rr %xmm0 %ymm0 = VPMOVSXBQZ256rr %xmm0
; CHECK: %ymm0 = VPMOVSXBWYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMOVSXBWYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMOVSXBWZ256rm %rip, 1, _, %rax, _ %ymm0 = VPMOVSXBWZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMOVSXBWYrr %xmm0 ; CHECK: %ymm0 = VPMOVSXBWYrr %xmm0
%ymm0 = VPMOVSXBWZ256rr %xmm0 %ymm0 = VPMOVSXBWZ256rr %xmm0
; CHECK: %ymm0 = VPMOVSXDQYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMOVSXDQYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMOVSXDQZ256rm %rip, 1, _, %rax, _ %ymm0 = VPMOVSXDQZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMOVSXDQYrr %xmm0 ; CHECK: %ymm0 = VPMOVSXDQYrr %xmm0
%ymm0 = VPMOVSXDQZ256rr %xmm0 %ymm0 = VPMOVSXDQZ256rr %xmm0
; CHECK: %ymm0 = VPMOVSXWDYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMOVSXWDYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMOVSXWDZ256rm %rip, 1, _, %rax, _ %ymm0 = VPMOVSXWDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMOVSXWDYrr %xmm0 ; CHECK: %ymm0 = VPMOVSXWDYrr %xmm0
%ymm0 = VPMOVSXWDZ256rr %xmm0 %ymm0 = VPMOVSXWDZ256rr %xmm0
; CHECK: %ymm0 = VPMOVSXWQYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMOVSXWQYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMOVSXWQZ256rm %rip, 1, _, %rax, _ %ymm0 = VPMOVSXWQZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMOVSXWQYrr %xmm0 ; CHECK: %ymm0 = VPMOVSXWQYrr %xmm0
%ymm0 = VPMOVSXWQZ256rr %xmm0 %ymm0 = VPMOVSXWQZ256rr %xmm0
; CHECK: %ymm0 = VPMOVZXBDYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMOVZXBDYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMOVZXBDZ256rm %rip, 1, _, %rax, _ %ymm0 = VPMOVZXBDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMOVZXBDYrr %xmm0 ; CHECK: %ymm0 = VPMOVZXBDYrr %xmm0
%ymm0 = VPMOVZXBDZ256rr %xmm0 %ymm0 = VPMOVZXBDZ256rr %xmm0
; CHECK: %ymm0 = VPMOVZXBQYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMOVZXBQYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMOVZXBQZ256rm %rip, 1, _, %rax, _ %ymm0 = VPMOVZXBQZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMOVZXBQYrr %xmm0 ; CHECK: %ymm0 = VPMOVZXBQYrr %xmm0
%ymm0 = VPMOVZXBQZ256rr %xmm0 %ymm0 = VPMOVZXBQZ256rr %xmm0
; CHECK: %ymm0 = VPMOVZXBWYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMOVZXBWYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMOVZXBWZ256rm %rip, 1, _, %rax, _ %ymm0 = VPMOVZXBWZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMOVZXBWYrr %xmm0 ; CHECK: %ymm0 = VPMOVZXBWYrr %xmm0
%ymm0 = VPMOVZXBWZ256rr %xmm0 %ymm0 = VPMOVZXBWZ256rr %xmm0
; CHECK: %ymm0 = VPMOVZXDQYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMOVZXDQYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMOVZXDQZ256rm %rip, 1, _, %rax, _ %ymm0 = VPMOVZXDQZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMOVZXDQYrr %xmm0 ; CHECK: %ymm0 = VPMOVZXDQYrr %xmm0
%ymm0 = VPMOVZXDQZ256rr %xmm0 %ymm0 = VPMOVZXDQZ256rr %xmm0
; CHECK: %ymm0 = VPMOVZXWDYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMOVZXWDYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMOVZXWDZ256rm %rip, 1, _, %rax, _ %ymm0 = VPMOVZXWDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMOVZXWDYrr %xmm0 ; CHECK: %ymm0 = VPMOVZXWDYrr %xmm0
%ymm0 = VPMOVZXWDZ256rr %xmm0 %ymm0 = VPMOVZXWDZ256rr %xmm0
; CHECK: %ymm0 = VPMOVZXWQYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPMOVZXWQYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPMOVZXWQZ256rm %rip, 1, _, %rax, _ %ymm0 = VPMOVZXWQZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPMOVZXWQYrr %xmm0 ; CHECK: %ymm0 = VPMOVZXWQYrr %xmm0
%ymm0 = VPMOVZXWQZ256rr %xmm0 %ymm0 = VPMOVZXWQZ256rr %xmm0
; CHECK: %ymm0 = VBROADCASTF128 %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VBROADCASTF128 %rip, 1, %noreg, %rax, %noreg
%ymm0 = VBROADCASTF32X4Z256rm %rip, 1, _, %rax, _ %ymm0 = VBROADCASTF32X4Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VBROADCASTSDYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VBROADCASTSDYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VBROADCASTF32X2Z256m %rip, 1, _, %rax, _ %ymm0 = VBROADCASTF32X2Z256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VBROADCASTSDYrr %xmm0 ; CHECK: %ymm0 = VBROADCASTSDYrr %xmm0
%ymm0 = VBROADCASTF32X2Z256r %xmm0 %ymm0 = VBROADCASTF32X2Z256r %xmm0
; CHECK: %ymm0 = VBROADCASTSDYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VBROADCASTSDYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VBROADCASTSDZ256m %rip, 1, _, %rax, _ %ymm0 = VBROADCASTSDZ256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VBROADCASTSDYrr %xmm0 ; CHECK: %ymm0 = VBROADCASTSDYrr %xmm0
%ymm0 = VBROADCASTSDZ256r %xmm0 %ymm0 = VBROADCASTSDZ256r %xmm0
; CHECK: %ymm0 = VBROADCASTSSYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VBROADCASTSSYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VBROADCASTSSZ256m %rip, 1, _, %rax, _ %ymm0 = VBROADCASTSSZ256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VBROADCASTSSYrr %xmm0 ; CHECK: %ymm0 = VBROADCASTSSYrr %xmm0
%ymm0 = VBROADCASTSSZ256r %xmm0 %ymm0 = VBROADCASTSSZ256r %xmm0
; CHECK: %ymm0 = VPBROADCASTBYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPBROADCASTBYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPBROADCASTBZ256m %rip, 1, _, %rax, _ %ymm0 = VPBROADCASTBZ256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPBROADCASTBYrr %xmm0 ; CHECK: %ymm0 = VPBROADCASTBYrr %xmm0
%ymm0 = VPBROADCASTBZ256r %xmm0 %ymm0 = VPBROADCASTBZ256r %xmm0
; CHECK: %ymm0 = VPBROADCASTDYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPBROADCASTDYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPBROADCASTDZ256m %rip, 1, _, %rax, _ %ymm0 = VPBROADCASTDZ256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPBROADCASTDYrr %xmm0 ; CHECK: %ymm0 = VPBROADCASTDYrr %xmm0
%ymm0 = VPBROADCASTDZ256r %xmm0 %ymm0 = VPBROADCASTDZ256r %xmm0
; CHECK: %ymm0 = VPBROADCASTWYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPBROADCASTWYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPBROADCASTWZ256m %rip, 1, _, %rax, _ %ymm0 = VPBROADCASTWZ256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPBROADCASTWYrr %xmm0 ; CHECK: %ymm0 = VPBROADCASTWYrr %xmm0
%ymm0 = VPBROADCASTWZ256r %xmm0 %ymm0 = VPBROADCASTWZ256r %xmm0
; CHECK: %ymm0 = VBROADCASTI128 %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VBROADCASTI128 %rip, 1, %noreg, %rax, %noreg
%ymm0 = VBROADCASTI32X4Z256rm %rip, 1, _, %rax, _ %ymm0 = VBROADCASTI32X4Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPBROADCASTQYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPBROADCASTQYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VBROADCASTI32X2Z256m %rip, 1, _, %rax, _ %ymm0 = VBROADCASTI32X2Z256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPBROADCASTQYrr %xmm0 ; CHECK: %ymm0 = VPBROADCASTQYrr %xmm0
%ymm0 = VBROADCASTI32X2Z256r %xmm0 %ymm0 = VBROADCASTI32X2Z256r %xmm0
; CHECK: %ymm0 = VPBROADCASTQYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPBROADCASTQYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPBROADCASTQZ256m %rip, 1, _, %rax, _ %ymm0 = VPBROADCASTQZ256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPBROADCASTQYrr %xmm0 ; CHECK: %ymm0 = VPBROADCASTQYrr %xmm0
%ymm0 = VPBROADCASTQZ256r %xmm0 %ymm0 = VPBROADCASTQZ256r %xmm0
; CHECK: %ymm0 = VPABSBYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPABSBYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPABSBZ256rm %rip, 1, _, %rax, _ %ymm0 = VPABSBZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPABSBYrr %ymm0 ; CHECK: %ymm0 = VPABSBYrr %ymm0
%ymm0 = VPABSBZ256rr %ymm0 %ymm0 = VPABSBZ256rr %ymm0
; CHECK: %ymm0 = VPABSDYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPABSDYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPABSDZ256rm %rip, 1, _, %rax, _ %ymm0 = VPABSDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPABSDYrr %ymm0 ; CHECK: %ymm0 = VPABSDYrr %ymm0
%ymm0 = VPABSDZ256rr %ymm0 %ymm0 = VPABSDZ256rr %ymm0
; CHECK: %ymm0 = VPABSWYrm %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPABSWYrm %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPABSWZ256rm %rip, 1, _, %rax, _ %ymm0 = VPABSWZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPABSWYrr %ymm0 ; CHECK: %ymm0 = VPABSWYrr %ymm0
%ymm0 = VPABSWZ256rr %ymm0 %ymm0 = VPABSWZ256rr %ymm0
; CHECK: %ymm0 = VPSADBWYrm %ymm0, 1, _, %rax, _, _ ; CHECK: %ymm0 = VPSADBWYrm %ymm0, 1, %noreg, %rax, %noreg, %noreg
%ymm0 = VPSADBWZ256rm %ymm0, 1, _, %rax, _, _ %ymm0 = VPSADBWZ256rm %ymm0, 1, %noreg, %rax, %noreg, %noreg
; CHECK: %ymm0 = VPSADBWYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPSADBWYrr %ymm0, %ymm1
%ymm0 = VPSADBWZ256rr %ymm0, %ymm1 %ymm0 = VPSADBWZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPERMDYrm %ymm0, %rdi, 1, _, 0, _ ; CHECK: %ymm0 = VPERMDYrm %ymm0, %rdi, 1, %noreg, 0, %noreg
%ymm0 = VPERMDZ256rm %ymm0, %rdi, 1, _, 0, _ %ymm0 = VPERMDZ256rm %ymm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VPERMDYrr %ymm1, %ymm0 ; CHECK: %ymm0 = VPERMDYrr %ymm1, %ymm0
%ymm0 = VPERMDZ256rr %ymm1, %ymm0 %ymm0 = VPERMDZ256rr %ymm1, %ymm0
; CHECK: %ymm0 = VPERMILPDYmi %rdi, 1, _, 0, _, _ ; CHECK: %ymm0 = VPERMILPDYmi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm0 = VPERMILPDZ256mi %rdi, 1, _, 0, _, _ %ymm0 = VPERMILPDZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm0 = VPERMILPDYri %ymm0, 7 ; CHECK: %ymm0 = VPERMILPDYri %ymm0, 7
%ymm0 = VPERMILPDZ256ri %ymm0, 7 %ymm0 = VPERMILPDZ256ri %ymm0, 7
; CHECK: %ymm0 = VPERMILPDYrm %ymm0, %rdi, 1, _, 0, _ ; CHECK: %ymm0 = VPERMILPDYrm %ymm0, %rdi, 1, %noreg, 0, %noreg
%ymm0 = VPERMILPDZ256rm %ymm0, %rdi, 1, _, 0, _ %ymm0 = VPERMILPDZ256rm %ymm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VPERMILPDYrr %ymm1, %ymm0 ; CHECK: %ymm0 = VPERMILPDYrr %ymm1, %ymm0
%ymm0 = VPERMILPDZ256rr %ymm1, %ymm0 %ymm0 = VPERMILPDZ256rr %ymm1, %ymm0
; CHECK: %ymm0 = VPERMILPSYmi %rdi, 1, _, 0, _, _ ; CHECK: %ymm0 = VPERMILPSYmi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm0 = VPERMILPSZ256mi %rdi, 1, _, 0, _, _ %ymm0 = VPERMILPSZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm0 = VPERMILPSYri %ymm0, 7 ; CHECK: %ymm0 = VPERMILPSYri %ymm0, 7
%ymm0 = VPERMILPSZ256ri %ymm0, 7 %ymm0 = VPERMILPSZ256ri %ymm0, 7
; CHECK: %ymm0 = VPERMILPSYrm %ymm0, %rdi, 1, _, 0, _ ; CHECK: %ymm0 = VPERMILPSYrm %ymm0, %rdi, 1, %noreg, 0, %noreg
%ymm0 = VPERMILPSZ256rm %ymm0, %rdi, 1, _, 0, _ %ymm0 = VPERMILPSZ256rm %ymm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VPERMILPSYrr %ymm1, %ymm0 ; CHECK: %ymm0 = VPERMILPSYrr %ymm1, %ymm0
%ymm0 = VPERMILPSZ256rr %ymm1, %ymm0 %ymm0 = VPERMILPSZ256rr %ymm1, %ymm0
; CHECK: %ymm0 = VPERMPDYmi %rdi, 1, _, 0, _, _ ; CHECK: %ymm0 = VPERMPDYmi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm0 = VPERMPDZ256mi %rdi, 1, _, 0, _, _ %ymm0 = VPERMPDZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm0 = VPERMPDYri %ymm0, 7 ; CHECK: %ymm0 = VPERMPDYri %ymm0, 7
%ymm0 = VPERMPDZ256ri %ymm0, 7 %ymm0 = VPERMPDZ256ri %ymm0, 7
; CHECK: %ymm0 = VPERMPSYrm %ymm0, %rdi, 1, _, 0, _ ; CHECK: %ymm0 = VPERMPSYrm %ymm0, %rdi, 1, %noreg, 0, %noreg
%ymm0 = VPERMPSZ256rm %ymm0, %rdi, 1, _, 0, _ %ymm0 = VPERMPSZ256rm %ymm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VPERMPSYrr %ymm1, %ymm0 ; CHECK: %ymm0 = VPERMPSYrr %ymm1, %ymm0
%ymm0 = VPERMPSZ256rr %ymm1, %ymm0 %ymm0 = VPERMPSZ256rr %ymm1, %ymm0
; CHECK: %ymm0 = VPERMQYmi %rdi, 1, _, 0, _, _ ; CHECK: %ymm0 = VPERMQYmi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm0 = VPERMQZ256mi %rdi, 1, _, 0, _, _ %ymm0 = VPERMQZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm0 = VPERMQYri %ymm0, 7 ; CHECK: %ymm0 = VPERMQYri %ymm0, 7
%ymm0 = VPERMQZ256ri %ymm0, 7 %ymm0 = VPERMQZ256ri %ymm0, 7
; CHECK: %ymm0 = VPSLLDQYri %ymm0, 14 ; CHECK: %ymm0 = VPSLLDQYri %ymm0, 14
%ymm0 = VPSLLDQZ256rr %ymm0, 14 %ymm0 = VPSLLDQZ256rr %ymm0, 14
; CHECK: %ymm0 = VPSLLDYri %ymm0, 7 ; CHECK: %ymm0 = VPSLLDYri %ymm0, 7
%ymm0 = VPSLLDZ256ri %ymm0, 7 %ymm0 = VPSLLDZ256ri %ymm0, 7
; CHECK: %ymm0 = VPSLLDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSLLDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSLLDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSLLDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSLLDYrr %ymm0, 14 ; CHECK: %ymm0 = VPSLLDYrr %ymm0, 14
%ymm0 = VPSLLDZ256rr %ymm0, 14 %ymm0 = VPSLLDZ256rr %ymm0, 14
; CHECK: %ymm0 = VPSLLQYri %ymm0, 7 ; CHECK: %ymm0 = VPSLLQYri %ymm0, 7
%ymm0 = VPSLLQZ256ri %ymm0, 7 %ymm0 = VPSLLQZ256ri %ymm0, 7
; CHECK: %ymm0 = VPSLLQYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSLLQYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSLLQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSLLQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSLLQYrr %ymm0, 14 ; CHECK: %ymm0 = VPSLLQYrr %ymm0, 14
%ymm0 = VPSLLQZ256rr %ymm0, 14 %ymm0 = VPSLLQZ256rr %ymm0, 14
; CHECK: %ymm0 = VPSLLVDYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSLLVDYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSLLVDZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSLLVDZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSLLVDYrr %ymm0, 14 ; CHECK: %ymm0 = VPSLLVDYrr %ymm0, 14
%ymm0 = VPSLLVDZ256rr %ymm0, 14 %ymm0 = VPSLLVDZ256rr %ymm0, 14
; CHECK: %ymm0 = VPSLLVQYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSLLVQYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSLLVQZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSLLVQZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSLLVQYrr %ymm0, 14 ; CHECK: %ymm0 = VPSLLVQYrr %ymm0, 14
%ymm0 = VPSLLVQZ256rr %ymm0, 14 %ymm0 = VPSLLVQZ256rr %ymm0, 14
; CHECK: %ymm0 = VPSLLWYri %ymm0, 7 ; CHECK: %ymm0 = VPSLLWYri %ymm0, 7
%ymm0 = VPSLLWZ256ri %ymm0, 7 %ymm0 = VPSLLWZ256ri %ymm0, 7
; CHECK: %ymm0 = VPSLLWYrm %ymm0, %rip, 1, _, %rax, _ ; CHECK: %ymm0 = VPSLLWYrm %ymm0, %rip, 1, %noreg, %rax, %noreg
%ymm0 = VPSLLWZ256rm %ymm0, %rip, 1, _, %rax, _ %ymm0 = VPSLLWZ256rm %ymm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm0 = VPSLLWYrr %ymm0, 14 ; CHECK: %ymm0 = VPSLLWYrr %ymm0, 14
%ymm0 = VPSLLWZ256rr %ymm0, 14 %ymm0 = VPSLLWZ256rr %ymm0, 14
; CHECK: %ymm0 = VCVTDQ2PDYrm %rdi, %ymm0, 1, _, 0 ; CHECK: %ymm0 = VCVTDQ2PDYrm %rdi, %ymm0, 1, %noreg, 0
%ymm0 = VCVTDQ2PDZ256rm %rdi, %ymm0, 1, _, 0 %ymm0 = VCVTDQ2PDZ256rm %rdi, %ymm0, 1, %noreg, 0
; CHECK: %ymm0 = VCVTDQ2PDYrr %xmm0 ; CHECK: %ymm0 = VCVTDQ2PDYrr %xmm0
%ymm0 = VCVTDQ2PDZ256rr %xmm0 %ymm0 = VCVTDQ2PDZ256rr %xmm0
; CHECK: %ymm0 = VCVTDQ2PSYrm %rdi, %ymm0, 1, _, 0 ; CHECK: %ymm0 = VCVTDQ2PSYrm %rdi, %ymm0, 1, %noreg, 0
%ymm0 = VCVTDQ2PSZ256rm %rdi, %ymm0, 1, _, 0 %ymm0 = VCVTDQ2PSZ256rm %rdi, %ymm0, 1, %noreg, 0
; CHECK: %ymm0 = VCVTDQ2PSYrr %ymm0 ; CHECK: %ymm0 = VCVTDQ2PSYrr %ymm0
%ymm0 = VCVTDQ2PSZ256rr %ymm0 %ymm0 = VCVTDQ2PSZ256rr %ymm0
; CHECK: %xmm0 = VCVTPD2DQYrm %rdi, %ymm0, 1, _, 0 ; CHECK: %xmm0 = VCVTPD2DQYrm %rdi, %ymm0, 1, %noreg, 0
%xmm0 = VCVTPD2DQZ256rm %rdi, %ymm0, 1, _, 0 %xmm0 = VCVTPD2DQZ256rm %rdi, %ymm0, 1, %noreg, 0
; CHECK: %xmm0 = VCVTPD2DQYrr %ymm0 ; CHECK: %xmm0 = VCVTPD2DQYrr %ymm0
%xmm0 = VCVTPD2DQZ256rr %ymm0 %xmm0 = VCVTPD2DQZ256rr %ymm0
; CHECK: %xmm0 = VCVTPD2PSYrm %rdi, %ymm0, 1, _, 0 ; CHECK: %xmm0 = VCVTPD2PSYrm %rdi, %ymm0, 1, %noreg, 0
%xmm0 = VCVTPD2PSZ256rm %rdi, %ymm0, 1, _, 0 %xmm0 = VCVTPD2PSZ256rm %rdi, %ymm0, 1, %noreg, 0
; CHECK: %xmm0 = VCVTPD2PSYrr %ymm0 ; CHECK: %xmm0 = VCVTPD2PSYrr %ymm0
%xmm0 = VCVTPD2PSZ256rr %ymm0 %xmm0 = VCVTPD2PSZ256rr %ymm0
; CHECK: %ymm0 = VCVTPS2DQYrm %rdi, %ymm0, 1, _, 0 ; CHECK: %ymm0 = VCVTPS2DQYrm %rdi, %ymm0, 1, %noreg, 0
%ymm0 = VCVTPS2DQZ256rm %rdi, %ymm0, 1, _, 0 %ymm0 = VCVTPS2DQZ256rm %rdi, %ymm0, 1, %noreg, 0
; CHECK: %ymm0 = VCVTPS2DQYrr %ymm0 ; CHECK: %ymm0 = VCVTPS2DQYrr %ymm0
%ymm0 = VCVTPS2DQZ256rr %ymm0 %ymm0 = VCVTPS2DQZ256rr %ymm0
; CHECK: %ymm0 = VCVTPS2PDYrm %rdi, %ymm0, 1, _, 0 ; CHECK: %ymm0 = VCVTPS2PDYrm %rdi, %ymm0, 1, %noreg, 0
%ymm0 = VCVTPS2PDZ256rm %rdi, %ymm0, 1, _, 0 %ymm0 = VCVTPS2PDZ256rm %rdi, %ymm0, 1, %noreg, 0
; CHECK: %ymm0 = VCVTPS2PDYrr %xmm0 ; CHECK: %ymm0 = VCVTPS2PDYrr %xmm0
%ymm0 = VCVTPS2PDZ256rr %xmm0 %ymm0 = VCVTPS2PDZ256rr %xmm0
; CHECK: VCVTPS2PHYmr %rdi, %ymm0, 1, _, 0, _, _ ; CHECK: VCVTPS2PHYmr %rdi, %ymm0, 1, %noreg, 0, %noreg, %noreg
VCVTPS2PHZ256mr %rdi, %ymm0, 1, _, 0, _, _ VCVTPS2PHZ256mr %rdi, %ymm0, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm0 = VCVTPS2PHYrr %ymm0, _ ; CHECK: %xmm0 = VCVTPS2PHYrr %ymm0, %noreg
%xmm0 = VCVTPS2PHZ256rr %ymm0, _ %xmm0 = VCVTPS2PHZ256rr %ymm0, %noreg
; CHECK: %ymm0 = VCVTPH2PSYrm %rdi, %ymm0, 1, _, 0 ; CHECK: %ymm0 = VCVTPH2PSYrm %rdi, %ymm0, 1, %noreg, 0
%ymm0 = VCVTPH2PSZ256rm %rdi, %ymm0, 1, _, 0 %ymm0 = VCVTPH2PSZ256rm %rdi, %ymm0, 1, %noreg, 0
; CHECK: %ymm0 = VCVTPH2PSYrr %xmm0 ; CHECK: %ymm0 = VCVTPH2PSYrr %xmm0
%ymm0 = VCVTPH2PSZ256rr %xmm0 %ymm0 = VCVTPH2PSZ256rr %xmm0
; CHECK: %xmm0 = VCVTTPD2DQYrm %rdi, %ymm0, 1, _, 0 ; CHECK: %xmm0 = VCVTTPD2DQYrm %rdi, %ymm0, 1, %noreg, 0
%xmm0 = VCVTTPD2DQZ256rm %rdi, %ymm0, 1, _, 0 %xmm0 = VCVTTPD2DQZ256rm %rdi, %ymm0, 1, %noreg, 0
; CHECK: %xmm0 = VCVTTPD2DQYrr %ymm0 ; CHECK: %xmm0 = VCVTTPD2DQYrr %ymm0
%xmm0 = VCVTTPD2DQZ256rr %ymm0 %xmm0 = VCVTTPD2DQZ256rr %ymm0
; CHECK: %ymm0 = VCVTTPS2DQYrm %rdi, %ymm0, 1, _, 0 ; CHECK: %ymm0 = VCVTTPS2DQYrm %rdi, %ymm0, 1, %noreg, 0
%ymm0 = VCVTTPS2DQZ256rm %rdi, %ymm0, 1, _, 0 %ymm0 = VCVTTPS2DQZ256rm %rdi, %ymm0, 1, %noreg, 0
; CHECK: %ymm0 = VCVTTPS2DQYrr %ymm0 ; CHECK: %ymm0 = VCVTTPS2DQYrr %ymm0
%ymm0 = VCVTTPS2DQZ256rr %ymm0 %ymm0 = VCVTTPS2DQZ256rr %ymm0
; CHECK: %ymm0 = VSQRTPDYm %rdi, _, _, _, _ ; CHECK: %ymm0 = VSQRTPDYm %rdi, %noreg, %noreg, %noreg, %noreg
%ymm0 = VSQRTPDZ256m %rdi, _, _, _, _ %ymm0 = VSQRTPDZ256m %rdi, %noreg, %noreg, %noreg, %noreg
; CHECK: %ymm0 = VSQRTPDYr %ymm0 ; CHECK: %ymm0 = VSQRTPDYr %ymm0
%ymm0 = VSQRTPDZ256r %ymm0 %ymm0 = VSQRTPDZ256r %ymm0
; CHECK: %ymm0 = VSQRTPSYm %rdi, _, _, _, _ ; CHECK: %ymm0 = VSQRTPSYm %rdi, %noreg, %noreg, %noreg, %noreg
%ymm0 = VSQRTPSZ256m %rdi, _, _, _, _ %ymm0 = VSQRTPSZ256m %rdi, %noreg, %noreg, %noreg, %noreg
; CHECK: %ymm0 = VSQRTPSYr %ymm0 ; CHECK: %ymm0 = VSQRTPSYr %ymm0
%ymm0 = VSQRTPSZ256r %ymm0 %ymm0 = VSQRTPSZ256r %ymm0
; CHECK: %ymm0 = VPALIGNRYrmi %ymm0, %rdi, _, _, _, _, _ ; CHECK: %ymm0 = VPALIGNRYrmi %ymm0, %rdi, %noreg, %noreg, %noreg, %noreg, %noreg
%ymm0 = VPALIGNRZ256rmi %ymm0, %rdi, _, _, _, _, _ %ymm0 = VPALIGNRZ256rmi %ymm0, %rdi, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %ymm0 = VPALIGNRYrri %ymm0, %ymm1, _ ; CHECK: %ymm0 = VPALIGNRYrri %ymm0, %ymm1, %noreg
%ymm0 = VPALIGNRZ256rri %ymm0, %ymm1, _ %ymm0 = VPALIGNRZ256rri %ymm0, %ymm1, %noreg
; CHECK: %ymm0 = VMOVUPSYrm %rdi, 1, _, 0, _ ; CHECK: %ymm0 = VMOVUPSYrm %rdi, 1, %noreg, 0, %noreg
%ymm0 = VMOVUPSZ256rm %rdi, 1, _, 0, _ %ymm0 = VMOVUPSZ256rm %rdi, 1, %noreg, 0, %noreg
; CHECK: %ymm0 = VMOVUPSYrr %ymm0 ; CHECK: %ymm0 = VMOVUPSYrr %ymm0
%ymm0 = VMOVUPSZ256rr %ymm0 %ymm0 = VMOVUPSZ256rr %ymm0
; CHECK: %ymm0 = VMOVUPSYrr_REV %ymm0 ; CHECK: %ymm0 = VMOVUPSYrr_REV %ymm0
%ymm0 = VMOVUPSZ256rr_REV %ymm0 %ymm0 = VMOVUPSZ256rr_REV %ymm0
; CHECK: %ymm0 = VPSHUFBYrm %ymm0, _, _, _, _, _ ; CHECK: %ymm0 = VPSHUFBYrm %ymm0, %noreg, %noreg, %noreg, %noreg, %noreg
%ymm0 = VPSHUFBZ256rm %ymm0, _, _, _, _, _ %ymm0 = VPSHUFBZ256rm %ymm0, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %ymm0 = VPSHUFBYrr %ymm0, %ymm1 ; CHECK: %ymm0 = VPSHUFBYrr %ymm0, %ymm1
%ymm0 = VPSHUFBZ256rr %ymm0, %ymm1 %ymm0 = VPSHUFBZ256rr %ymm0, %ymm1
; CHECK: %ymm0 = VPSHUFDYmi %rdi, 1, _, 0, _, _ ; CHECK: %ymm0 = VPSHUFDYmi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm0 = VPSHUFDZ256mi %rdi, 1, _, 0, _, _ %ymm0 = VPSHUFDZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm0 = VPSHUFDYri %ymm0, -24 ; CHECK: %ymm0 = VPSHUFDYri %ymm0, -24
%ymm0 = VPSHUFDZ256ri %ymm0, -24 %ymm0 = VPSHUFDZ256ri %ymm0, -24
; CHECK: %ymm0 = VPSHUFHWYmi %rdi, 1, _, 0, _, _ ; CHECK: %ymm0 = VPSHUFHWYmi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm0 = VPSHUFHWZ256mi %rdi, 1, _, 0, _, _ %ymm0 = VPSHUFHWZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm0 = VPSHUFHWYri %ymm0, -24 ; CHECK: %ymm0 = VPSHUFHWYri %ymm0, -24
%ymm0 = VPSHUFHWZ256ri %ymm0, -24 %ymm0 = VPSHUFHWZ256ri %ymm0, -24
; CHECK: %ymm0 = VPSHUFLWYmi %rdi, 1, _, 0, _, _ ; CHECK: %ymm0 = VPSHUFLWYmi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm0 = VPSHUFLWZ256mi %rdi, 1, _, 0, _, _ %ymm0 = VPSHUFLWZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm0 = VPSHUFLWYri %ymm0, -24 ; CHECK: %ymm0 = VPSHUFLWYri %ymm0, -24
%ymm0 = VPSHUFLWZ256ri %ymm0, -24 %ymm0 = VPSHUFLWZ256ri %ymm0, -24
; CHECK: %ymm0 = VSHUFPDYrmi %ymm0, _, _, _, _, _, _ ; CHECK: %ymm0 = VSHUFPDYrmi %ymm0, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
%ymm0 = VSHUFPDZ256rmi %ymm0, _, _, _, _, _, _ %ymm0 = VSHUFPDZ256rmi %ymm0, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %ymm0 = VSHUFPDYrri %ymm0, _, _ ; CHECK: %ymm0 = VSHUFPDYrri %ymm0, %noreg, %noreg
%ymm0 = VSHUFPDZ256rri %ymm0, _, _ %ymm0 = VSHUFPDZ256rri %ymm0, %noreg, %noreg
; CHECK: %ymm0 = VSHUFPSYrmi %ymm0, _, _, _, _, _, _ ; CHECK: %ymm0 = VSHUFPSYrmi %ymm0, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
%ymm0 = VSHUFPSZ256rmi %ymm0, _, _, _, _, _, _ %ymm0 = VSHUFPSZ256rmi %ymm0, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %ymm0 = VSHUFPSYrri %ymm0, _, _ ; CHECK: %ymm0 = VSHUFPSYrri %ymm0, %noreg, %noreg
%ymm0 = VSHUFPSZ256rri %ymm0, _, _ %ymm0 = VSHUFPSZ256rri %ymm0, %noreg, %noreg
RET 0, %zmm0, %zmm1 RET 0, %zmm0, %zmm1
... ...
--- ---
# CHECK-LABEL: name: evex_z128_to_vex_test # CHECK-LABEL: name: evex_z128_to_vex_test
# CHECK: bb.0: # CHECK: bb.0:
name: evex_z128_to_vex_test name: evex_z128_to_vex_test
body: | body: |
bb.0: bb.0:
; CHECK: VMOVAPDmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVAPDmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVAPDZ128mr %rdi, 1, _, 0, _, %xmm0 VMOVAPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVAPDrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMOVAPDrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMOVAPDZ128rm %rip, 1, _, %rax, _ %xmm0 = VMOVAPDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMOVAPDrr %xmm0 ; CHECK: %xmm0 = VMOVAPDrr %xmm0
%xmm0 = VMOVAPDZ128rr %xmm0 %xmm0 = VMOVAPDZ128rr %xmm0
; CHECK: VMOVAPSmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVAPSmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVAPSZ128mr %rdi, 1, _, 0, _, %xmm0 VMOVAPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVAPSrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMOVAPSrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMOVAPSZ128rm %rip, 1, _, %rax, _ %xmm0 = VMOVAPSZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMOVAPSrr %xmm0 ; CHECK: %xmm0 = VMOVAPSrr %xmm0
%xmm0 = VMOVAPSZ128rr %xmm0 %xmm0 = VMOVAPSZ128rr %xmm0
; CHECK: VMOVDQAmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVDQAmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVDQA32Z128mr %rdi, 1, _, 0, _, %xmm0 VMOVDQA32Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVDQArm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMOVDQArm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMOVDQA32Z128rm %rip, 1, _, %rax, _ %xmm0 = VMOVDQA32Z128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMOVDQArr %xmm0 ; CHECK: %xmm0 = VMOVDQArr %xmm0
%xmm0 = VMOVDQA32Z128rr %xmm0 %xmm0 = VMOVDQA32Z128rr %xmm0
; CHECK: VMOVDQAmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVDQAmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVDQA64Z128mr %rdi, 1, _, 0, _, %xmm0 VMOVDQA64Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVDQArm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMOVDQArm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMOVDQA64Z128rm %rip, 1, _, %rax, _ %xmm0 = VMOVDQA64Z128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMOVDQArr %xmm0 ; CHECK: %xmm0 = VMOVDQArr %xmm0
%xmm0 = VMOVDQA64Z128rr %xmm0 %xmm0 = VMOVDQA64Z128rr %xmm0
; CHECK: VMOVDQUmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVDQUmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVDQU16Z128mr %rdi, 1, _, 0, _, %xmm0 VMOVDQU16Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVDQUrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMOVDQUrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMOVDQU16Z128rm %rip, 1, _, %rax, _ %xmm0 = VMOVDQU16Z128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMOVDQUrr %xmm0 ; CHECK: %xmm0 = VMOVDQUrr %xmm0
%xmm0 = VMOVDQU16Z128rr %xmm0 %xmm0 = VMOVDQU16Z128rr %xmm0
; CHECK: VMOVDQUmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVDQUmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVDQU32Z128mr %rdi, 1, _, 0, _, %xmm0 VMOVDQU32Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVDQUrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMOVDQUrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMOVDQU32Z128rm %rip, 1, _, %rax, _ %xmm0 = VMOVDQU32Z128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMOVDQUrr %xmm0 ; CHECK: %xmm0 = VMOVDQUrr %xmm0
%xmm0 = VMOVDQU32Z128rr %xmm0 %xmm0 = VMOVDQU32Z128rr %xmm0
; CHECK: VMOVDQUmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVDQUmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVDQU64Z128mr %rdi, 1, _, 0, _, %xmm0 VMOVDQU64Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVDQUrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMOVDQUrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMOVDQU64Z128rm %rip, 1, _, %rax, _ %xmm0 = VMOVDQU64Z128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMOVDQUrr %xmm0 ; CHECK: %xmm0 = VMOVDQUrr %xmm0
%xmm0 = VMOVDQU64Z128rr %xmm0 %xmm0 = VMOVDQU64Z128rr %xmm0
; CHECK: VMOVDQUmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVDQUmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVDQU8Z128mr %rdi, 1, _, 0, _, %xmm0 VMOVDQU8Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVDQUrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMOVDQUrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMOVDQU8Z128rm %rip, 1, _, %rax, _ %xmm0 = VMOVDQU8Z128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMOVDQUrr %xmm0 ; CHECK: %xmm0 = VMOVDQUrr %xmm0
%xmm0 = VMOVDQU8Z128rr %xmm0 %xmm0 = VMOVDQU8Z128rr %xmm0
; CHECK: %xmm0 = VMOVDQUrr_REV %xmm0 ; CHECK: %xmm0 = VMOVDQUrr_REV %xmm0
%xmm0 = VMOVDQU8Z128rr_REV %xmm0 %xmm0 = VMOVDQU8Z128rr_REV %xmm0
; CHECK: %xmm0 = VMOVNTDQArm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMOVNTDQArm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMOVNTDQAZ128rm %rip, 1, _, %rax, _ %xmm0 = VMOVNTDQAZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: VMOVUPDmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVUPDmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVUPDZ128mr %rdi, 1, _, 0, _, %xmm0 VMOVUPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVUPDrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMOVUPDrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMOVUPDZ128rm %rip, 1, _, %rax, _ %xmm0 = VMOVUPDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMOVUPDrr %xmm0 ; CHECK: %xmm0 = VMOVUPDrr %xmm0
%xmm0 = VMOVUPDZ128rr %xmm0 %xmm0 = VMOVUPDZ128rr %xmm0
; CHECK: %xmm0 = VMOVUPDrr_REV %xmm0 ; CHECK: %xmm0 = VMOVUPDrr_REV %xmm0
%xmm0 = VMOVUPDZ128rr_REV %xmm0 %xmm0 = VMOVUPDZ128rr_REV %xmm0
; CHECK: VMOVUPSmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVUPSmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVUPSZ128mr %rdi, 1, _, 0, _, %xmm0 VMOVUPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVUPSrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMOVUPSrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMOVUPSZ128rm %rip, 1, _, %rax, _ %xmm0 = VMOVUPSZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMOVUPSrr %xmm0 ; CHECK: %xmm0 = VMOVUPSrr %xmm0
%xmm0 = VMOVUPSZ128rr %xmm0 %xmm0 = VMOVUPSZ128rr %xmm0
; CHECK: %xmm0 = VMOVUPSrr_REV %xmm0 ; CHECK: %xmm0 = VMOVUPSrr_REV %xmm0
%xmm0 = VMOVUPSZ128rr_REV %xmm0 %xmm0 = VMOVUPSZ128rr_REV %xmm0
; CHECK: VMOVNTDQmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVNTDQmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVNTDQZ128mr %rdi, 1, _, 0, _, %xmm0 VMOVNTDQZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: VMOVNTPDmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVNTPDmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVNTPDZ128mr %rdi, 1, _, 0, _, %xmm0 VMOVNTPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: VMOVNTPSmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVNTPSmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVNTPSZ128mr %rdi, 1, _, 0, _, %xmm0 VMOVNTPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVAPDrr_REV %xmm0 ; CHECK: %xmm0 = VMOVAPDrr_REV %xmm0
%xmm0 = VMOVAPDZ128rr_REV %xmm0 %xmm0 = VMOVAPDZ128rr_REV %xmm0
; CHECK: %xmm0 = VMOVAPSrr_REV %xmm0 ; CHECK: %xmm0 = VMOVAPSrr_REV %xmm0
%xmm0 = VMOVAPSZ128rr_REV %xmm0 %xmm0 = VMOVAPSZ128rr_REV %xmm0
; CHECK: %xmm0 = VMOVDQArr_REV %xmm0 ; CHECK: %xmm0 = VMOVDQArr_REV %xmm0
%xmm0 = VMOVDQA32Z128rr_REV %xmm0 %xmm0 = VMOVDQA32Z128rr_REV %xmm0
; CHECK: %xmm0 = VMOVDQArr_REV %xmm0 ; CHECK: %xmm0 = VMOVDQArr_REV %xmm0
%xmm0 = VMOVDQA64Z128rr_REV %xmm0 %xmm0 = VMOVDQA64Z128rr_REV %xmm0
; CHECK: %xmm0 = VMOVDQUrr_REV %xmm0 ; CHECK: %xmm0 = VMOVDQUrr_REV %xmm0
%xmm0 = VMOVDQU16Z128rr_REV %xmm0 %xmm0 = VMOVDQU16Z128rr_REV %xmm0
; CHECK: %xmm0 = VMOVDQUrr_REV %xmm0 ; CHECK: %xmm0 = VMOVDQUrr_REV %xmm0
%xmm0 = VMOVDQU32Z128rr_REV %xmm0 %xmm0 = VMOVDQU32Z128rr_REV %xmm0
; CHECK: %xmm0 = VMOVDQUrr_REV %xmm0 ; CHECK: %xmm0 = VMOVDQUrr_REV %xmm0
%xmm0 = VMOVDQU64Z128rr_REV %xmm0 %xmm0 = VMOVDQU64Z128rr_REV %xmm0
; CHECK: %xmm0 = VPMOVSXBDrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMOVSXBDrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMOVSXBDZ128rm %rip, 1, _, %rax, _ %xmm0 = VPMOVSXBDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMOVSXBDrr %xmm0 ; CHECK: %xmm0 = VPMOVSXBDrr %xmm0
%xmm0 = VPMOVSXBDZ128rr %xmm0 %xmm0 = VPMOVSXBDZ128rr %xmm0
; CHECK: %xmm0 = VPMOVSXBQrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMOVSXBQrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMOVSXBQZ128rm %rip, 1, _, %rax, _ %xmm0 = VPMOVSXBQZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMOVSXBQrr %xmm0 ; CHECK: %xmm0 = VPMOVSXBQrr %xmm0
%xmm0 = VPMOVSXBQZ128rr %xmm0 %xmm0 = VPMOVSXBQZ128rr %xmm0
; CHECK: %xmm0 = VPMOVSXBWrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMOVSXBWrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMOVSXBWZ128rm %rip, 1, _, %rax, _ %xmm0 = VPMOVSXBWZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMOVSXBWrr %xmm0 ; CHECK: %xmm0 = VPMOVSXBWrr %xmm0
%xmm0 = VPMOVSXBWZ128rr %xmm0 %xmm0 = VPMOVSXBWZ128rr %xmm0
; CHECK: %xmm0 = VPMOVSXDQrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMOVSXDQrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMOVSXDQZ128rm %rip, 1, _, %rax, _ %xmm0 = VPMOVSXDQZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMOVSXDQrr %xmm0 ; CHECK: %xmm0 = VPMOVSXDQrr %xmm0
%xmm0 = VPMOVSXDQZ128rr %xmm0 %xmm0 = VPMOVSXDQZ128rr %xmm0
; CHECK: %xmm0 = VPMOVSXWDrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMOVSXWDrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMOVSXWDZ128rm %rip, 1, _, %rax, _ %xmm0 = VPMOVSXWDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMOVSXWDrr %xmm0 ; CHECK: %xmm0 = VPMOVSXWDrr %xmm0
%xmm0 = VPMOVSXWDZ128rr %xmm0 %xmm0 = VPMOVSXWDZ128rr %xmm0
; CHECK: %xmm0 = VPMOVSXWQrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMOVSXWQrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMOVSXWQZ128rm %rip, 1, _, %rax, _ %xmm0 = VPMOVSXWQZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMOVSXWQrr %xmm0 ; CHECK: %xmm0 = VPMOVSXWQrr %xmm0
%xmm0 = VPMOVSXWQZ128rr %xmm0 %xmm0 = VPMOVSXWQZ128rr %xmm0
; CHECK: %xmm0 = VPMOVZXBDrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMOVZXBDrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMOVZXBDZ128rm %rip, 1, _, %rax, _ %xmm0 = VPMOVZXBDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMOVZXBDrr %xmm0 ; CHECK: %xmm0 = VPMOVZXBDrr %xmm0
%xmm0 = VPMOVZXBDZ128rr %xmm0 %xmm0 = VPMOVZXBDZ128rr %xmm0
; CHECK: %xmm0 = VPMOVZXBQrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMOVZXBQrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMOVZXBQZ128rm %rip, 1, _, %rax, _ %xmm0 = VPMOVZXBQZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMOVZXBQrr %xmm0 ; CHECK: %xmm0 = VPMOVZXBQrr %xmm0
%xmm0 = VPMOVZXBQZ128rr %xmm0 %xmm0 = VPMOVZXBQZ128rr %xmm0
; CHECK: %xmm0 = VPMOVZXBWrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMOVZXBWrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMOVZXBWZ128rm %rip, 1, _, %rax, _ %xmm0 = VPMOVZXBWZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMOVZXBWrr %xmm0 ; CHECK: %xmm0 = VPMOVZXBWrr %xmm0
%xmm0 = VPMOVZXBWZ128rr %xmm0 %xmm0 = VPMOVZXBWZ128rr %xmm0
; CHECK: %xmm0 = VPMOVZXDQrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMOVZXDQrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMOVZXDQZ128rm %rip, 1, _, %rax, _ %xmm0 = VPMOVZXDQZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMOVZXDQrr %xmm0 ; CHECK: %xmm0 = VPMOVZXDQrr %xmm0
%xmm0 = VPMOVZXDQZ128rr %xmm0 %xmm0 = VPMOVZXDQZ128rr %xmm0
; CHECK: %xmm0 = VPMOVZXWDrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMOVZXWDrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMOVZXWDZ128rm %rip, 1, _, %rax, _ %xmm0 = VPMOVZXWDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMOVZXWDrr %xmm0 ; CHECK: %xmm0 = VPMOVZXWDrr %xmm0
%xmm0 = VPMOVZXWDZ128rr %xmm0 %xmm0 = VPMOVZXWDZ128rr %xmm0
; CHECK: %xmm0 = VPMOVZXWQrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMOVZXWQrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMOVZXWQZ128rm %rip, 1, _, %rax, _ %xmm0 = VPMOVZXWQZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMOVZXWQrr %xmm0 ; CHECK: %xmm0 = VPMOVZXWQrr %xmm0
%xmm0 = VPMOVZXWQZ128rr %xmm0 %xmm0 = VPMOVZXWQZ128rr %xmm0
; CHECK: VMOVHPDmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVHPDmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVHPDZ128mr %rdi, 1, _, 0, _, %xmm0 VMOVHPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVHPDrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VMOVHPDrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VMOVHPDZ128rm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VMOVHPDZ128rm %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: VMOVHPSmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVHPSmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVHPSZ128mr %rdi, 1, _, 0, _, %xmm0 VMOVHPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVHPSrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VMOVHPSrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VMOVHPSZ128rm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VMOVHPSZ128rm %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: VMOVLPDmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVLPDmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVLPDZ128mr %rdi, 1, _, 0, _, %xmm0 VMOVLPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVLPDrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VMOVLPDrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VMOVLPDZ128rm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VMOVLPDZ128rm %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: VMOVLPSmr %rdi, 1, _, 0, _, %xmm0 ; CHECK: VMOVLPSmr %rdi, 1, %noreg, 0, %noreg, %xmm0
VMOVLPSZ128mr %rdi, 1, _, 0, _, %xmm0 VMOVLPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm0
; CHECK: %xmm0 = VMOVLPSrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VMOVLPSrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VMOVLPSZ128rm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VMOVLPSZ128rm %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VMAXCPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMAXCPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMAXCPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMAXCPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMAXCPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMAXCPDrr %xmm0, %xmm1
%xmm0 = VMAXCPDZ128rr %xmm0, %xmm1 %xmm0 = VMAXCPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VMAXCPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMAXCPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMAXCPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMAXCPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMAXCPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMAXCPSrr %xmm0, %xmm1
%xmm0 = VMAXCPSZ128rr %xmm0, %xmm1 %xmm0 = VMAXCPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VMAXCPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMAXCPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMAXPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMAXPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMAXCPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMAXCPDrr %xmm0, %xmm1
%xmm0 = VMAXPDZ128rr %xmm0, %xmm1 %xmm0 = VMAXPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VMAXCPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMAXCPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMAXPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMAXPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMAXCPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMAXCPSrr %xmm0, %xmm1
%xmm0 = VMAXPSZ128rr %xmm0, %xmm1 %xmm0 = VMAXPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VMINCPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMINCPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMINCPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMINCPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMINCPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMINCPDrr %xmm0, %xmm1
%xmm0 = VMINCPDZ128rr %xmm0, %xmm1 %xmm0 = VMINCPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VMINCPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMINCPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMINCPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMINCPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMINCPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMINCPSrr %xmm0, %xmm1
%xmm0 = VMINCPSZ128rr %xmm0, %xmm1 %xmm0 = VMINCPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VMINCPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMINCPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMINPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMINPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMINCPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMINCPDrr %xmm0, %xmm1
%xmm0 = VMINPDZ128rr %xmm0, %xmm1 %xmm0 = VMINPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VMINCPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMINCPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMINPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMINPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMINCPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMINCPSrr %xmm0, %xmm1
%xmm0 = VMINPSZ128rr %xmm0, %xmm1 %xmm0 = VMINPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VMULPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMULPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMULPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMULPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMULPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMULPDrr %xmm0, %xmm1
%xmm0 = VMULPDZ128rr %xmm0, %xmm1 %xmm0 = VMULPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VMULPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMULPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMULPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMULPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMULPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMULPSrr %xmm0, %xmm1
%xmm0 = VMULPSZ128rr %xmm0, %xmm1 %xmm0 = VMULPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VORPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VORPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VORPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VORPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VORPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VORPDrr %xmm0, %xmm1
%xmm0 = VORPDZ128rr %xmm0, %xmm1 %xmm0 = VORPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VORPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VORPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VORPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VORPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VORPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VORPSrr %xmm0, %xmm1
%xmm0 = VORPSZ128rr %xmm0, %xmm1 %xmm0 = VORPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPADDBrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPADDBrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPADDBZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPADDBZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPADDBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPADDBrr %xmm0, %xmm1
%xmm0 = VPADDBZ128rr %xmm0, %xmm1 %xmm0 = VPADDBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPADDDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPADDDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPADDDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPADDDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPADDDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPADDDrr %xmm0, %xmm1
%xmm0 = VPADDDZ128rr %xmm0, %xmm1 %xmm0 = VPADDDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPADDQrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPADDQrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPADDQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPADDQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPADDQrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPADDQrr %xmm0, %xmm1
%xmm0 = VPADDQZ128rr %xmm0, %xmm1 %xmm0 = VPADDQZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPADDSBrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPADDSBrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPADDSBZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPADDSBZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPADDSBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPADDSBrr %xmm0, %xmm1
%xmm0 = VPADDSBZ128rr %xmm0, %xmm1 %xmm0 = VPADDSBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPADDSWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPADDSWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPADDSWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPADDSWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPADDSWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPADDSWrr %xmm0, %xmm1
%xmm0 = VPADDSWZ128rr %xmm0, %xmm1 %xmm0 = VPADDSWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPADDUSBrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPADDUSBrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPADDUSBZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPADDUSBZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPADDUSBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPADDUSBrr %xmm0, %xmm1
%xmm0 = VPADDUSBZ128rr %xmm0, %xmm1 %xmm0 = VPADDUSBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPADDUSWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPADDUSWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPADDUSWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPADDUSWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPADDUSWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPADDUSWrr %xmm0, %xmm1
%xmm0 = VPADDUSWZ128rr %xmm0, %xmm1 %xmm0 = VPADDUSWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPADDWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPADDWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPADDWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPADDWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPADDWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPADDWrr %xmm0, %xmm1
%xmm0 = VPADDWZ128rr %xmm0, %xmm1 %xmm0 = VPADDWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPANDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPANDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPANDDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPANDDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPANDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPANDrr %xmm0, %xmm1
%xmm0 = VPANDDZ128rr %xmm0, %xmm1 %xmm0 = VPANDDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPANDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPANDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPANDQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPANDQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPANDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPANDrr %xmm0, %xmm1
%xmm0 = VPANDQZ128rr %xmm0, %xmm1 %xmm0 = VPANDQZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPANDNrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPANDNrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPANDNDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPANDNDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPANDNrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPANDNrr %xmm0, %xmm1
%xmm0 = VPANDNDZ128rr %xmm0, %xmm1 %xmm0 = VPANDNDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPANDNrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPANDNrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPANDNQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPANDNQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPANDNrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPANDNrr %xmm0, %xmm1
%xmm0 = VPANDNQZ128rr %xmm0, %xmm1 %xmm0 = VPANDNQZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPAVGBrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPAVGBrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPAVGBZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPAVGBZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPAVGBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPAVGBrr %xmm0, %xmm1
%xmm0 = VPAVGBZ128rr %xmm0, %xmm1 %xmm0 = VPAVGBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPAVGWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPAVGWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPAVGWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPAVGWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPAVGWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPAVGWrr %xmm0, %xmm1
%xmm0 = VPAVGWZ128rr %xmm0, %xmm1 %xmm0 = VPAVGWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMAXSBrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMAXSBrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMAXSBZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMAXSBZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMAXSBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMAXSBrr %xmm0, %xmm1
%xmm0 = VPMAXSBZ128rr %xmm0, %xmm1 %xmm0 = VPMAXSBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMAXSDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMAXSDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMAXSDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMAXSDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMAXSDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMAXSDrr %xmm0, %xmm1
%xmm0 = VPMAXSDZ128rr %xmm0, %xmm1 %xmm0 = VPMAXSDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMAXSWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMAXSWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMAXSWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMAXSWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMAXSWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMAXSWrr %xmm0, %xmm1
%xmm0 = VPMAXSWZ128rr %xmm0, %xmm1 %xmm0 = VPMAXSWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMAXUBrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMAXUBrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMAXUBZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMAXUBZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMAXUBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMAXUBrr %xmm0, %xmm1
%xmm0 = VPMAXUBZ128rr %xmm0, %xmm1 %xmm0 = VPMAXUBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMAXUDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMAXUDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMAXUDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMAXUDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMAXUDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMAXUDrr %xmm0, %xmm1
%xmm0 = VPMAXUDZ128rr %xmm0, %xmm1 %xmm0 = VPMAXUDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMAXUWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMAXUWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMAXUWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMAXUWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMAXUWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMAXUWrr %xmm0, %xmm1
%xmm0 = VPMAXUWZ128rr %xmm0, %xmm1 %xmm0 = VPMAXUWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMINSBrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMINSBrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMINSBZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMINSBZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMINSBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMINSBrr %xmm0, %xmm1
%xmm0 = VPMINSBZ128rr %xmm0, %xmm1 %xmm0 = VPMINSBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMINSDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMINSDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMINSDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMINSDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMINSDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMINSDrr %xmm0, %xmm1
%xmm0 = VPMINSDZ128rr %xmm0, %xmm1 %xmm0 = VPMINSDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMINSWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMINSWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMINSWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMINSWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMINSWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMINSWrr %xmm0, %xmm1
%xmm0 = VPMINSWZ128rr %xmm0, %xmm1 %xmm0 = VPMINSWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMINUBrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMINUBrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMINUBZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMINUBZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMINUBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMINUBrr %xmm0, %xmm1
%xmm0 = VPMINUBZ128rr %xmm0, %xmm1 %xmm0 = VPMINUBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMINUDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMINUDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMINUDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMINUDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMINUDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMINUDrr %xmm0, %xmm1
%xmm0 = VPMINUDZ128rr %xmm0, %xmm1 %xmm0 = VPMINUDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMINUWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMINUWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMINUWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMINUWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMINUWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMINUWrr %xmm0, %xmm1
%xmm0 = VPMINUWZ128rr %xmm0, %xmm1 %xmm0 = VPMINUWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMULDQrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMULDQrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMULDQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMULDQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMULDQrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMULDQrr %xmm0, %xmm1
%xmm0 = VPMULDQZ128rr %xmm0, %xmm1 %xmm0 = VPMULDQZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMULHRSWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMULHRSWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMULHRSWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMULHRSWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMULHRSWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMULHRSWrr %xmm0, %xmm1
%xmm0 = VPMULHRSWZ128rr %xmm0, %xmm1 %xmm0 = VPMULHRSWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMULHUWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMULHUWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMULHUWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMULHUWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMULHUWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMULHUWrr %xmm0, %xmm1
%xmm0 = VPMULHUWZ128rr %xmm0, %xmm1 %xmm0 = VPMULHUWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMULHWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMULHWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMULHWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMULHWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMULHWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMULHWrr %xmm0, %xmm1
%xmm0 = VPMULHWZ128rr %xmm0, %xmm1 %xmm0 = VPMULHWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMULLDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMULLDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMULLDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMULLDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMULLDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMULLDrr %xmm0, %xmm1
%xmm0 = VPMULLDZ128rr %xmm0, %xmm1 %xmm0 = VPMULLDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMULLWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMULLWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMULLWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMULLWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMULLWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMULLWrr %xmm0, %xmm1
%xmm0 = VPMULLWZ128rr %xmm0, %xmm1 %xmm0 = VPMULLWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMULUDQrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMULUDQrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMULUDQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMULUDQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMULUDQrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMULUDQrr %xmm0, %xmm1
%xmm0 = VPMULUDQZ128rr %xmm0, %xmm1 %xmm0 = VPMULUDQZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPORrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPORrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPORDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPORDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPORrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPORrr %xmm0, %xmm1
%xmm0 = VPORDZ128rr %xmm0, %xmm1 %xmm0 = VPORDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPORrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPORrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPORQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPORQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPORrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPORrr %xmm0, %xmm1
%xmm0 = VPORQZ128rr %xmm0, %xmm1 %xmm0 = VPORQZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPSUBBrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSUBBrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSUBBZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSUBBZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSUBBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPSUBBrr %xmm0, %xmm1
%xmm0 = VPSUBBZ128rr %xmm0, %xmm1 %xmm0 = VPSUBBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPSUBDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSUBDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSUBDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSUBDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSUBDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPSUBDrr %xmm0, %xmm1
%xmm0 = VPSUBDZ128rr %xmm0, %xmm1 %xmm0 = VPSUBDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPSUBQrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSUBQrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSUBQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSUBQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSUBQrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPSUBQrr %xmm0, %xmm1
%xmm0 = VPSUBQZ128rr %xmm0, %xmm1 %xmm0 = VPSUBQZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPSUBSBrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSUBSBrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSUBSBZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSUBSBZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSUBSBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPSUBSBrr %xmm0, %xmm1
%xmm0 = VPSUBSBZ128rr %xmm0, %xmm1 %xmm0 = VPSUBSBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPSUBSWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSUBSWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSUBSWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSUBSWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSUBSWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPSUBSWrr %xmm0, %xmm1
%xmm0 = VPSUBSWZ128rr %xmm0, %xmm1 %xmm0 = VPSUBSWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPSUBUSBrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSUBUSBrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSUBUSBZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSUBUSBZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSUBUSBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPSUBUSBrr %xmm0, %xmm1
%xmm0 = VPSUBUSBZ128rr %xmm0, %xmm1 %xmm0 = VPSUBUSBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPSUBUSWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSUBUSWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSUBUSWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSUBUSWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSUBUSWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPSUBUSWrr %xmm0, %xmm1
%xmm0 = VPSUBUSWZ128rr %xmm0, %xmm1 %xmm0 = VPSUBUSWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPSUBWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSUBWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSUBWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSUBWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSUBWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPSUBWrr %xmm0, %xmm1
%xmm0 = VPSUBWZ128rr %xmm0, %xmm1 %xmm0 = VPSUBWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VADDPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VADDPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VADDPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VADDPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VADDPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VADDPDrr %xmm0, %xmm1
%xmm0 = VADDPDZ128rr %xmm0, %xmm1 %xmm0 = VADDPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VADDPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VADDPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VADDPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VADDPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VADDPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VADDPSrr %xmm0, %xmm1
%xmm0 = VADDPSZ128rr %xmm0, %xmm1 %xmm0 = VADDPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VANDNPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VANDNPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VANDNPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VANDNPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VANDNPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VANDNPDrr %xmm0, %xmm1
%xmm0 = VANDNPDZ128rr %xmm0, %xmm1 %xmm0 = VANDNPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VANDNPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VANDNPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VANDNPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VANDNPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VANDNPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VANDNPSrr %xmm0, %xmm1
%xmm0 = VANDNPSZ128rr %xmm0, %xmm1 %xmm0 = VANDNPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VANDPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VANDPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VANDPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VANDPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VANDPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VANDPDrr %xmm0, %xmm1
%xmm0 = VANDPDZ128rr %xmm0, %xmm1 %xmm0 = VANDPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VANDPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VANDPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VANDPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VANDPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VANDPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VANDPSrr %xmm0, %xmm1
%xmm0 = VANDPSZ128rr %xmm0, %xmm1 %xmm0 = VANDPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VDIVPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VDIVPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VDIVPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VDIVPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VDIVPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VDIVPDrr %xmm0, %xmm1
%xmm0 = VDIVPDZ128rr %xmm0, %xmm1 %xmm0 = VDIVPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VDIVPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VDIVPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VDIVPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VDIVPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VDIVPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VDIVPSrr %xmm0, %xmm1
%xmm0 = VDIVPSZ128rr %xmm0, %xmm1 %xmm0 = VDIVPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPXORrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPXORrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPXORDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPXORDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPXORrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPXORrr %xmm0, %xmm1
%xmm0 = VPXORDZ128rr %xmm0, %xmm1 %xmm0 = VPXORDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPXORrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPXORrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPXORQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPXORQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPXORrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPXORrr %xmm0, %xmm1
%xmm0 = VPXORQZ128rr %xmm0, %xmm1 %xmm0 = VPXORQZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VSUBPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VSUBPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VSUBPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VSUBPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VSUBPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VSUBPDrr %xmm0, %xmm1
%xmm0 = VSUBPDZ128rr %xmm0, %xmm1 %xmm0 = VSUBPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VSUBPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VSUBPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VSUBPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VSUBPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VSUBPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VSUBPSrr %xmm0, %xmm1
%xmm0 = VSUBPSZ128rr %xmm0, %xmm1 %xmm0 = VSUBPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VXORPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VXORPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VXORPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VXORPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VXORPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VXORPDrr %xmm0, %xmm1
%xmm0 = VXORPDZ128rr %xmm0, %xmm1 %xmm0 = VXORPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VXORPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VXORPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VXORPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VXORPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VXORPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VXORPSrr %xmm0, %xmm1
%xmm0 = VXORPSZ128rr %xmm0, %xmm1 %xmm0 = VXORPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMADDUBSWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMADDUBSWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMADDUBSWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMADDUBSWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMADDUBSWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMADDUBSWrr %xmm0, %xmm1
%xmm0 = VPMADDUBSWZ128rr %xmm0, %xmm1 %xmm0 = VPMADDUBSWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPMADDWDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPMADDWDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPMADDWDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPMADDWDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPMADDWDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPMADDWDrr %xmm0, %xmm1
%xmm0 = VPMADDWDZ128rr %xmm0, %xmm1 %xmm0 = VPMADDWDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPACKSSDWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPACKSSDWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPACKSSDWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPACKSSDWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPACKSSDWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPACKSSDWrr %xmm0, %xmm1
%xmm0 = VPACKSSDWZ128rr %xmm0, %xmm1 %xmm0 = VPACKSSDWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPACKSSWBrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPACKSSWBrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPACKSSWBZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPACKSSWBZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPACKSSWBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPACKSSWBrr %xmm0, %xmm1
%xmm0 = VPACKSSWBZ128rr %xmm0, %xmm1 %xmm0 = VPACKSSWBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPACKUSDWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPACKUSDWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPACKUSDWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPACKUSDWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPACKUSDWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPACKUSDWrr %xmm0, %xmm1
%xmm0 = VPACKUSDWZ128rr %xmm0, %xmm1 %xmm0 = VPACKUSDWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPACKUSWBrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPACKUSWBrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPACKUSWBZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPACKUSWBZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPACKUSWBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPACKUSWBrr %xmm0, %xmm1
%xmm0 = VPACKUSWBZ128rr %xmm0, %xmm1 %xmm0 = VPACKUSWBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPUNPCKHBWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPUNPCKHBWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPUNPCKHBWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPUNPCKHBWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPUNPCKHBWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPUNPCKHBWrr %xmm0, %xmm1
%xmm0 = VPUNPCKHBWZ128rr %xmm0, %xmm1 %xmm0 = VPUNPCKHBWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPUNPCKHDQrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPUNPCKHDQrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPUNPCKHDQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPUNPCKHDQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPUNPCKHDQrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPUNPCKHDQrr %xmm0, %xmm1
%xmm0 = VPUNPCKHDQZ128rr %xmm0, %xmm1 %xmm0 = VPUNPCKHDQZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPUNPCKHQDQrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPUNPCKHQDQrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPUNPCKHQDQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPUNPCKHQDQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPUNPCKHQDQrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPUNPCKHQDQrr %xmm0, %xmm1
%xmm0 = VPUNPCKHQDQZ128rr %xmm0, %xmm1 %xmm0 = VPUNPCKHQDQZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPUNPCKHWDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPUNPCKHWDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPUNPCKHWDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPUNPCKHWDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPUNPCKHWDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPUNPCKHWDrr %xmm0, %xmm1
%xmm0 = VPUNPCKHWDZ128rr %xmm0, %xmm1 %xmm0 = VPUNPCKHWDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPUNPCKLBWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPUNPCKLBWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPUNPCKLBWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPUNPCKLBWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPUNPCKLBWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPUNPCKLBWrr %xmm0, %xmm1
%xmm0 = VPUNPCKLBWZ128rr %xmm0, %xmm1 %xmm0 = VPUNPCKLBWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPUNPCKLDQrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPUNPCKLDQrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPUNPCKLDQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPUNPCKLDQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPUNPCKLDQrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPUNPCKLDQrr %xmm0, %xmm1
%xmm0 = VPUNPCKLDQZ128rr %xmm0, %xmm1 %xmm0 = VPUNPCKLDQZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPUNPCKLQDQrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPUNPCKLQDQrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPUNPCKLQDQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPUNPCKLQDQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPUNPCKLQDQrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPUNPCKLQDQrr %xmm0, %xmm1
%xmm0 = VPUNPCKLQDQZ128rr %xmm0, %xmm1 %xmm0 = VPUNPCKLQDQZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPUNPCKLWDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPUNPCKLWDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPUNPCKLWDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPUNPCKLWDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPUNPCKLWDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPUNPCKLWDrr %xmm0, %xmm1
%xmm0 = VPUNPCKLWDZ128rr %xmm0, %xmm1 %xmm0 = VPUNPCKLWDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VUNPCKHPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VUNPCKHPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VUNPCKHPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VUNPCKHPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VUNPCKHPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VUNPCKHPDrr %xmm0, %xmm1
%xmm0 = VUNPCKHPDZ128rr %xmm0, %xmm1 %xmm0 = VUNPCKHPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VUNPCKHPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VUNPCKHPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VUNPCKHPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VUNPCKHPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VUNPCKHPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VUNPCKHPSrr %xmm0, %xmm1
%xmm0 = VUNPCKHPSZ128rr %xmm0, %xmm1 %xmm0 = VUNPCKHPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VUNPCKLPDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VUNPCKLPDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VUNPCKLPDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VUNPCKLPDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VUNPCKLPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VUNPCKLPDrr %xmm0, %xmm1
%xmm0 = VUNPCKLPDZ128rr %xmm0, %xmm1 %xmm0 = VUNPCKLPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VUNPCKLPSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VUNPCKLPSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VUNPCKLPSZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VUNPCKLPSZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VUNPCKLPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VUNPCKLPSrr %xmm0, %xmm1
%xmm0 = VUNPCKLPSZ128rr %xmm0, %xmm1 %xmm0 = VUNPCKLPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VFMADD132PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD132PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD132PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD132PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD132PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD132PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD132PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD132PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD132PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD132PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD132PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD132PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD132PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD132PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD132PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD132PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD213PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD213PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD213PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD213PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD213PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD213PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD213PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD213PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD213PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD213PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD213PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD213PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD213PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD213PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD213PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD213PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD231PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD231PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD231PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD231PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD231PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD231PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD231PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD231PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD231PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD231PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD231PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD231PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD231PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD231PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD231PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD231PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADDSUB132PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADDSUB132PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADDSUB132PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADDSUB132PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADDSUB132PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADDSUB132PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADDSUB132PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMADDSUB132PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADDSUB132PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADDSUB132PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADDSUB132PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADDSUB132PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADDSUB132PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADDSUB132PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADDSUB132PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMADDSUB132PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADDSUB213PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADDSUB213PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADDSUB213PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADDSUB213PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADDSUB213PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADDSUB213PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADDSUB213PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMADDSUB213PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADDSUB213PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADDSUB213PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADDSUB213PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADDSUB213PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADDSUB213PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADDSUB213PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADDSUB213PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMADDSUB213PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADDSUB231PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADDSUB231PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADDSUB231PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADDSUB231PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADDSUB231PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADDSUB231PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADDSUB231PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMADDSUB231PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADDSUB231PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADDSUB231PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADDSUB231PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADDSUB231PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADDSUB231PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADDSUB231PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADDSUB231PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMADDSUB231PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB132PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB132PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB132PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB132PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB132PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB132PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB132PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB132PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB132PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB132PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB132PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB132PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB132PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB132PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB132PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB132PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB213PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB213PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB213PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB213PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB213PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB213PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB213PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB213PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB213PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB213PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB213PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB213PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB213PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB213PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB213PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB213PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB231PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB231PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB231PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB231PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB231PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB231PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB231PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB231PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB231PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB231PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB231PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB231PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB231PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB231PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB231PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB231PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUBADD132PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUBADD132PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUBADD132PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUBADD132PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUBADD132PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUBADD132PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUBADD132PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUBADD132PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUBADD132PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUBADD132PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUBADD132PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUBADD132PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUBADD132PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUBADD132PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUBADD132PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUBADD132PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUBADD213PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUBADD213PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUBADD213PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUBADD213PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUBADD213PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUBADD213PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUBADD213PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUBADD213PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUBADD213PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUBADD213PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUBADD213PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUBADD213PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUBADD213PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUBADD213PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUBADD213PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUBADD213PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUBADD231PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUBADD231PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUBADD231PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUBADD231PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUBADD231PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUBADD231PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUBADD231PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUBADD231PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUBADD231PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUBADD231PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUBADD231PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUBADD231PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUBADD231PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUBADD231PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUBADD231PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUBADD231PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD132PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD132PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD132PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD132PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD132PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD132PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD132PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD132PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD132PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD132PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD132PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD132PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD132PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD132PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD132PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD132PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD213PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD213PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD213PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD213PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD213PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD213PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD213PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD213PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD213PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD213PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD213PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD213PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD213PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD213PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD213PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD213PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD231PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD231PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD231PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD231PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD231PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD231PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD231PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD231PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD231PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD231PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD231PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD231PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD231PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD231PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD231PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD231PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB132PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB132PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB132PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB132PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB132PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB132PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB132PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB132PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB132PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB132PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB132PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB132PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB132PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB132PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB132PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB132PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB213PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB213PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB213PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB213PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB213PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB213PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB213PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB213PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB213PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB213PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB213PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB213PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB213PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB213PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB213PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB213PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB231PDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB231PDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB231PDZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB231PDZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB231PDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB231PDr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB231PDZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB231PDZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB231PSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB231PSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB231PSZ128m %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB231PSZ128m %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB231PSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB231PSr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB231PSZ128r %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB231PSZ128r %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VPSLLDri %xmm0, 7 ; CHECK: %xmm0 = VPSLLDri %xmm0, 7
%xmm0 = VPSLLDZ128ri %xmm0, 7 %xmm0 = VPSLLDZ128ri %xmm0, 7
; CHECK: %xmm0 = VPSLLDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSLLDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSLLDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSLLDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSLLDrr %xmm0, 14 ; CHECK: %xmm0 = VPSLLDrr %xmm0, 14
%xmm0 = VPSLLDZ128rr %xmm0, 14 %xmm0 = VPSLLDZ128rr %xmm0, 14
; CHECK: %xmm0 = VPSLLQri %xmm0, 7 ; CHECK: %xmm0 = VPSLLQri %xmm0, 7
%xmm0 = VPSLLQZ128ri %xmm0, 7 %xmm0 = VPSLLQZ128ri %xmm0, 7
; CHECK: %xmm0 = VPSLLQrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSLLQrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSLLQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSLLQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSLLQrr %xmm0, 14 ; CHECK: %xmm0 = VPSLLQrr %xmm0, 14
%xmm0 = VPSLLQZ128rr %xmm0, 14 %xmm0 = VPSLLQZ128rr %xmm0, 14
; CHECK: %xmm0 = VPSLLVDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSLLVDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSLLVDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSLLVDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSLLVDrr %xmm0, 14 ; CHECK: %xmm0 = VPSLLVDrr %xmm0, 14
%xmm0 = VPSLLVDZ128rr %xmm0, 14 %xmm0 = VPSLLVDZ128rr %xmm0, 14
; CHECK: %xmm0 = VPSLLVQrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSLLVQrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSLLVQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSLLVQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSLLVQrr %xmm0, 14 ; CHECK: %xmm0 = VPSLLVQrr %xmm0, 14
%xmm0 = VPSLLVQZ128rr %xmm0, 14 %xmm0 = VPSLLVQZ128rr %xmm0, 14
; CHECK: %xmm0 = VPSLLWri %xmm0, 7 ; CHECK: %xmm0 = VPSLLWri %xmm0, 7
%xmm0 = VPSLLWZ128ri %xmm0, 7 %xmm0 = VPSLLWZ128ri %xmm0, 7
; CHECK: %xmm0 = VPSLLWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSLLWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSLLWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSLLWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSLLWrr %xmm0, 14 ; CHECK: %xmm0 = VPSLLWrr %xmm0, 14
%xmm0 = VPSLLWZ128rr %xmm0, 14 %xmm0 = VPSLLWZ128rr %xmm0, 14
; CHECK: %xmm0 = VPSRADri %xmm0, 7 ; CHECK: %xmm0 = VPSRADri %xmm0, 7
%xmm0 = VPSRADZ128ri %xmm0, 7 %xmm0 = VPSRADZ128ri %xmm0, 7
; CHECK: %xmm0 = VPSRADrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSRADrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSRADZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSRADZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSRADrr %xmm0, 14 ; CHECK: %xmm0 = VPSRADrr %xmm0, 14
%xmm0 = VPSRADZ128rr %xmm0, 14 %xmm0 = VPSRADZ128rr %xmm0, 14
; CHECK: %xmm0 = VPSRAVDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSRAVDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSRAVDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSRAVDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSRAVDrr %xmm0, 14 ; CHECK: %xmm0 = VPSRAVDrr %xmm0, 14
%xmm0 = VPSRAVDZ128rr %xmm0, 14 %xmm0 = VPSRAVDZ128rr %xmm0, 14
; CHECK: %xmm0 = VPSRAWri %xmm0, 7 ; CHECK: %xmm0 = VPSRAWri %xmm0, 7
%xmm0 = VPSRAWZ128ri %xmm0, 7 %xmm0 = VPSRAWZ128ri %xmm0, 7
; CHECK: %xmm0 = VPSRAWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSRAWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSRAWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSRAWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSRAWrr %xmm0, 14 ; CHECK: %xmm0 = VPSRAWrr %xmm0, 14
%xmm0 = VPSRAWZ128rr %xmm0, 14 %xmm0 = VPSRAWZ128rr %xmm0, 14
; CHECK: %xmm0 = VPSRLDQri %xmm0, 14 ; CHECK: %xmm0 = VPSRLDQri %xmm0, 14
%xmm0 = VPSRLDQZ128rr %xmm0, 14 %xmm0 = VPSRLDQZ128rr %xmm0, 14
; CHECK: %xmm0 = VPSRLDri %xmm0, 7 ; CHECK: %xmm0 = VPSRLDri %xmm0, 7
%xmm0 = VPSRLDZ128ri %xmm0, 7 %xmm0 = VPSRLDZ128ri %xmm0, 7
; CHECK: %xmm0 = VPSRLDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSRLDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSRLDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSRLDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSRLDrr %xmm0, 14 ; CHECK: %xmm0 = VPSRLDrr %xmm0, 14
%xmm0 = VPSRLDZ128rr %xmm0, 14 %xmm0 = VPSRLDZ128rr %xmm0, 14
; CHECK: %xmm0 = VPSRLQri %xmm0, 7 ; CHECK: %xmm0 = VPSRLQri %xmm0, 7
%xmm0 = VPSRLQZ128ri %xmm0, 7 %xmm0 = VPSRLQZ128ri %xmm0, 7
; CHECK: %xmm0 = VPSRLQrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSRLQrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSRLQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSRLQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSRLQrr %xmm0, 14 ; CHECK: %xmm0 = VPSRLQrr %xmm0, 14
%xmm0 = VPSRLQZ128rr %xmm0, 14 %xmm0 = VPSRLQZ128rr %xmm0, 14
; CHECK: %xmm0 = VPSRLVDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSRLVDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSRLVDZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSRLVDZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSRLVDrr %xmm0, 14 ; CHECK: %xmm0 = VPSRLVDrr %xmm0, 14
%xmm0 = VPSRLVDZ128rr %xmm0, 14 %xmm0 = VPSRLVDZ128rr %xmm0, 14
; CHECK: %xmm0 = VPSRLVQrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSRLVQrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSRLVQZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSRLVQZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSRLVQrr %xmm0, 14 ; CHECK: %xmm0 = VPSRLVQrr %xmm0, 14
%xmm0 = VPSRLVQZ128rr %xmm0, 14 %xmm0 = VPSRLVQZ128rr %xmm0, 14
; CHECK: %xmm0 = VPSRLWri %xmm0, 7 ; CHECK: %xmm0 = VPSRLWri %xmm0, 7
%xmm0 = VPSRLWZ128ri %xmm0, 7 %xmm0 = VPSRLWZ128ri %xmm0, 7
; CHECK: %xmm0 = VPSRLWrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPSRLWrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPSRLWZ128rm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VPSRLWZ128rm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPSRLWrr %xmm0, 14 ; CHECK: %xmm0 = VPSRLWrr %xmm0, 14
%xmm0 = VPSRLWZ128rr %xmm0, 14 %xmm0 = VPSRLWZ128rr %xmm0, 14
; CHECK: %xmm0 = VPERMILPDmi %rdi, 1, _, 0, _, _ ; CHECK: %xmm0 = VPERMILPDmi %rdi, 1, %noreg, 0, %noreg, %noreg
%xmm0 = VPERMILPDZ128mi %rdi, 1, _, 0, _, _ %xmm0 = VPERMILPDZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm0 = VPERMILPDri %xmm0, 9 ; CHECK: %xmm0 = VPERMILPDri %xmm0, 9
%xmm0 = VPERMILPDZ128ri %xmm0, 9 %xmm0 = VPERMILPDZ128ri %xmm0, 9
; CHECK: %xmm0 = VPERMILPDrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VPERMILPDrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VPERMILPDZ128rm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VPERMILPDZ128rm %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VPERMILPDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPERMILPDrr %xmm0, %xmm1
%xmm0 = VPERMILPDZ128rr %xmm0, %xmm1 %xmm0 = VPERMILPDZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPERMILPSmi %rdi, 1, _, 0, _, _ ; CHECK: %xmm0 = VPERMILPSmi %rdi, 1, %noreg, 0, %noreg, %noreg
%xmm0 = VPERMILPSZ128mi %rdi, 1, _, 0, _, _ %xmm0 = VPERMILPSZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm0 = VPERMILPSri %xmm0, 9 ; CHECK: %xmm0 = VPERMILPSri %xmm0, 9
%xmm0 = VPERMILPSZ128ri %xmm0, 9 %xmm0 = VPERMILPSZ128ri %xmm0, 9
; CHECK: %xmm0 = VPERMILPSrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VPERMILPSrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VPERMILPSZ128rm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VPERMILPSZ128rm %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VPERMILPSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPERMILPSrr %xmm0, %xmm1
%xmm0 = VPERMILPSZ128rr %xmm0, %xmm1 %xmm0 = VPERMILPSZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VCVTPH2PSrm %rdi, %xmm0, 1, _, 0 ; CHECK: %xmm0 = VCVTPH2PSrm %rdi, %xmm0, 1, %noreg, 0
%xmm0 = VCVTPH2PSZ128rm %rdi, %xmm0, 1, _, 0 %xmm0 = VCVTPH2PSZ128rm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %xmm0 = VCVTPH2PSrr %xmm0 ; CHECK: %xmm0 = VCVTPH2PSrr %xmm0
%xmm0 = VCVTPH2PSZ128rr %xmm0 %xmm0 = VCVTPH2PSZ128rr %xmm0
; CHECK: %xmm0 = VCVTDQ2PDrm %rdi, %xmm0, 1, _, 0 ; CHECK: %xmm0 = VCVTDQ2PDrm %rdi, %xmm0, 1, %noreg, 0
%xmm0 = VCVTDQ2PDZ128rm %rdi, %xmm0, 1, _, 0 %xmm0 = VCVTDQ2PDZ128rm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %xmm0 = VCVTDQ2PDrr %xmm0 ; CHECK: %xmm0 = VCVTDQ2PDrr %xmm0
%xmm0 = VCVTDQ2PDZ128rr %xmm0 %xmm0 = VCVTDQ2PDZ128rr %xmm0
; CHECK: %xmm0 = VCVTDQ2PSrm %rdi, %xmm0, 1, _, 0 ; CHECK: %xmm0 = VCVTDQ2PSrm %rdi, %xmm0, 1, %noreg, 0
%xmm0 = VCVTDQ2PSZ128rm %rdi, %xmm0, 1, _, 0 %xmm0 = VCVTDQ2PSZ128rm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %xmm0 = VCVTDQ2PSrr %xmm0 ; CHECK: %xmm0 = VCVTDQ2PSrr %xmm0
%xmm0 = VCVTDQ2PSZ128rr %xmm0 %xmm0 = VCVTDQ2PSZ128rr %xmm0
; CHECK: %xmm0 = VCVTPD2DQrm %rdi, %xmm0, 1, _, 0 ; CHECK: %xmm0 = VCVTPD2DQrm %rdi, %xmm0, 1, %noreg, 0
%xmm0 = VCVTPD2DQZ128rm %rdi, %xmm0, 1, _, 0 %xmm0 = VCVTPD2DQZ128rm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %xmm0 = VCVTPD2DQrr %xmm0 ; CHECK: %xmm0 = VCVTPD2DQrr %xmm0
%xmm0 = VCVTPD2DQZ128rr %xmm0 %xmm0 = VCVTPD2DQZ128rr %xmm0
; CHECK: %xmm0 = VCVTPD2PSrm %rdi, %xmm0, 1, _, 0 ; CHECK: %xmm0 = VCVTPD2PSrm %rdi, %xmm0, 1, %noreg, 0
%xmm0 = VCVTPD2PSZ128rm %rdi, %xmm0, 1, _, 0 %xmm0 = VCVTPD2PSZ128rm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %xmm0 = VCVTPD2PSrr %xmm0 ; CHECK: %xmm0 = VCVTPD2PSrr %xmm0
%xmm0 = VCVTPD2PSZ128rr %xmm0 %xmm0 = VCVTPD2PSZ128rr %xmm0
; CHECK: %xmm0 = VCVTPS2DQrm %rdi, %xmm0, 1, _, 0 ; CHECK: %xmm0 = VCVTPS2DQrm %rdi, %xmm0, 1, %noreg, 0
%xmm0 = VCVTPS2DQZ128rm %rdi, %xmm0, 1, _, 0 %xmm0 = VCVTPS2DQZ128rm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %xmm0 = VCVTPS2DQrr %xmm0 ; CHECK: %xmm0 = VCVTPS2DQrr %xmm0
%xmm0 = VCVTPS2DQZ128rr %xmm0 %xmm0 = VCVTPS2DQZ128rr %xmm0
; CHECK: %xmm0 = VCVTPS2PDrm %rdi, %xmm0, 1, _, 0 ; CHECK: %xmm0 = VCVTPS2PDrm %rdi, %xmm0, 1, %noreg, 0
%xmm0 = VCVTPS2PDZ128rm %rdi, %xmm0, 1, _, 0 %xmm0 = VCVTPS2PDZ128rm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %xmm0 = VCVTPS2PDrr %xmm0 ; CHECK: %xmm0 = VCVTPS2PDrr %xmm0
%xmm0 = VCVTPS2PDZ128rr %xmm0 %xmm0 = VCVTPS2PDZ128rr %xmm0
; CHECK: %xmm0 = VCVTTPD2DQrm %rdi, %xmm0, 1, _, 0 ; CHECK: %xmm0 = VCVTTPD2DQrm %rdi, %xmm0, 1, %noreg, 0
%xmm0 = VCVTTPD2DQZ128rm %rdi, %xmm0, 1, _, 0 %xmm0 = VCVTTPD2DQZ128rm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %xmm0 = VCVTTPD2DQrr %xmm0 ; CHECK: %xmm0 = VCVTTPD2DQrr %xmm0
%xmm0 = VCVTTPD2DQZ128rr %xmm0 %xmm0 = VCVTTPD2DQZ128rr %xmm0
; CHECK: %xmm0 = VCVTTPS2DQrm %rdi, %xmm0, 1, _, 0 ; CHECK: %xmm0 = VCVTTPS2DQrm %rdi, %xmm0, 1, %noreg, 0
%xmm0 = VCVTTPS2DQZ128rm %rdi, %xmm0, 1, _, 0 %xmm0 = VCVTTPS2DQZ128rm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %xmm0 = VCVTTPS2DQrr %xmm0 ; CHECK: %xmm0 = VCVTTPS2DQrr %xmm0
%xmm0 = VCVTTPS2DQZ128rr %xmm0 %xmm0 = VCVTTPS2DQZ128rr %xmm0
; CHECK: %xmm0 = VSQRTPDm %rdi, _, _, _, _ ; CHECK: %xmm0 = VSQRTPDm %rdi, %noreg, %noreg, %noreg, %noreg
%xmm0 = VSQRTPDZ128m %rdi, _, _, _, _ %xmm0 = VSQRTPDZ128m %rdi, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VSQRTPDr %xmm0 ; CHECK: %xmm0 = VSQRTPDr %xmm0
%xmm0 = VSQRTPDZ128r %xmm0 %xmm0 = VSQRTPDZ128r %xmm0
; CHECK: %xmm0 = VSQRTPSm %rdi, _, _, _, _ ; CHECK: %xmm0 = VSQRTPSm %rdi, %noreg, %noreg, %noreg, %noreg
%xmm0 = VSQRTPSZ128m %rdi, _, _, _, _ %xmm0 = VSQRTPSZ128m %rdi, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VSQRTPSr %xmm0 ; CHECK: %xmm0 = VSQRTPSr %xmm0
%xmm0 = VSQRTPSZ128r %xmm0 %xmm0 = VSQRTPSZ128r %xmm0
; CHECK: %xmm0 = VMOVDDUPrm %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VMOVDDUPrm %rdi, 1, %noreg, 0, %noreg
%xmm0 = VMOVDDUPZ128rm %rdi, 1, _, 0, _ %xmm0 = VMOVDDUPZ128rm %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VMOVDDUPrr %xmm0 ; CHECK: %xmm0 = VMOVDDUPrr %xmm0
%xmm0 = VMOVDDUPZ128rr %xmm0 %xmm0 = VMOVDDUPZ128rr %xmm0
; CHECK: %xmm0 = VMOVSHDUPrm %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VMOVSHDUPrm %rdi, 1, %noreg, 0, %noreg
%xmm0 = VMOVSHDUPZ128rm %rdi, 1, _, 0, _ %xmm0 = VMOVSHDUPZ128rm %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VMOVSHDUPrr %xmm0 ; CHECK: %xmm0 = VMOVSHDUPrr %xmm0
%xmm0 = VMOVSHDUPZ128rr %xmm0 %xmm0 = VMOVSHDUPZ128rr %xmm0
; CHECK: %xmm0 = VMOVSLDUPrm %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VMOVSLDUPrm %rdi, 1, %noreg, 0, %noreg
%xmm0 = VMOVSLDUPZ128rm %rdi, 1, _, 0, _ %xmm0 = VMOVSLDUPZ128rm %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VMOVSLDUPrr %xmm0 ; CHECK: %xmm0 = VMOVSLDUPrr %xmm0
%xmm0 = VMOVSLDUPZ128rr %xmm0 %xmm0 = VMOVSLDUPZ128rr %xmm0
; CHECK: %xmm0 = VPSHUFBrm %xmm0, _, _, _, _, _ ; CHECK: %xmm0 = VPSHUFBrm %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm0 = VPSHUFBZ128rm %xmm0, _, _, _, _, _ %xmm0 = VPSHUFBZ128rm %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VPSHUFBrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPSHUFBrr %xmm0, %xmm1
%xmm0 = VPSHUFBZ128rr %xmm0, %xmm1 %xmm0 = VPSHUFBZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VPSHUFDmi %rdi, 1, _, 0, _, _ ; CHECK: %xmm0 = VPSHUFDmi %rdi, 1, %noreg, 0, %noreg, %noreg
%xmm0 = VPSHUFDZ128mi %rdi, 1, _, 0, _, _ %xmm0 = VPSHUFDZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm0 = VPSHUFDri %xmm0, -24 ; CHECK: %xmm0 = VPSHUFDri %xmm0, -24
%xmm0 = VPSHUFDZ128ri %xmm0, -24 %xmm0 = VPSHUFDZ128ri %xmm0, -24
; CHECK: %xmm0 = VPSHUFHWmi %rdi, 1, _, 0, _, _ ; CHECK: %xmm0 = VPSHUFHWmi %rdi, 1, %noreg, 0, %noreg, %noreg
%xmm0 = VPSHUFHWZ128mi %rdi, 1, _, 0, _, _ %xmm0 = VPSHUFHWZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm0 = VPSHUFHWri %xmm0, -24 ; CHECK: %xmm0 = VPSHUFHWri %xmm0, -24
%xmm0 = VPSHUFHWZ128ri %xmm0, -24 %xmm0 = VPSHUFHWZ128ri %xmm0, -24
; CHECK: %xmm0 = VPSHUFLWmi %rdi, 1, _, 0, _, _ ; CHECK: %xmm0 = VPSHUFLWmi %rdi, 1, %noreg, 0, %noreg, %noreg
%xmm0 = VPSHUFLWZ128mi %rdi, 1, _, 0, _, _ %xmm0 = VPSHUFLWZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm0 = VPSHUFLWri %xmm0, -24 ; CHECK: %xmm0 = VPSHUFLWri %xmm0, -24
%xmm0 = VPSHUFLWZ128ri %xmm0, -24 %xmm0 = VPSHUFLWZ128ri %xmm0, -24
; CHECK: %xmm0 = VPSLLDQri %xmm0, %xmm1 ; CHECK: %xmm0 = VPSLLDQri %xmm0, %xmm1
%xmm0 = VPSLLDQZ128rr %xmm0, %xmm1 %xmm0 = VPSLLDQZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VSHUFPDrmi %xmm0, _, _, _, _, _, _ ; CHECK: %xmm0 = VSHUFPDrmi %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm0 = VSHUFPDZ128rmi %xmm0, _, _, _, _, _, _ %xmm0 = VSHUFPDZ128rmi %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VSHUFPDrri %xmm0, _, _ ; CHECK: %xmm0 = VSHUFPDrri %xmm0, %noreg, %noreg
%xmm0 = VSHUFPDZ128rri %xmm0, _, _ %xmm0 = VSHUFPDZ128rri %xmm0, %noreg, %noreg
; CHECK: %xmm0 = VSHUFPSrmi %xmm0, _, _, _, _, _, _ ; CHECK: %xmm0 = VSHUFPSrmi %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm0 = VSHUFPSZ128rmi %xmm0, _, _, _, _, _, _ %xmm0 = VSHUFPSZ128rmi %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VSHUFPSrri %xmm0, _, _ ; CHECK: %xmm0 = VSHUFPSrri %xmm0, %noreg, %noreg
%xmm0 = VSHUFPSZ128rri %xmm0, _, _ %xmm0 = VSHUFPSZ128rri %xmm0, %noreg, %noreg
; CHECK: %xmm0 = VPSADBWrm %xmm0, 1, _, %rax, _, _ ; CHECK: %xmm0 = VPSADBWrm %xmm0, 1, %noreg, %rax, %noreg, %noreg
%xmm0 = VPSADBWZ128rm %xmm0, 1, _, %rax, _, _ %xmm0 = VPSADBWZ128rm %xmm0, 1, %noreg, %rax, %noreg, %noreg
; CHECK: %xmm0 = VPSADBWrr %xmm0, %xmm1 ; CHECK: %xmm0 = VPSADBWrr %xmm0, %xmm1
%xmm0 = VPSADBWZ128rr %xmm0, %xmm1 %xmm0 = VPSADBWZ128rr %xmm0, %xmm1
; CHECK: %xmm0 = VBROADCASTSSrm %rip, _, _, _, _ ; CHECK: %xmm0 = VBROADCASTSSrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm0 = VBROADCASTSSZ128m %rip, _, _, _, _ %xmm0 = VBROADCASTSSZ128m %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VBROADCASTSSrr %xmm0 ; CHECK: %xmm0 = VBROADCASTSSrr %xmm0
%xmm0 = VBROADCASTSSZ128r %xmm0 %xmm0 = VBROADCASTSSZ128r %xmm0
; CHECK: %xmm0 = VPBROADCASTBrm %rip, _, _, _, _ ; CHECK: %xmm0 = VPBROADCASTBrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm0 = VPBROADCASTBZ128m %rip, _, _, _, _ %xmm0 = VPBROADCASTBZ128m %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VPBROADCASTBrr %xmm0 ; CHECK: %xmm0 = VPBROADCASTBrr %xmm0
%xmm0 = VPBROADCASTBZ128r %xmm0 %xmm0 = VPBROADCASTBZ128r %xmm0
; CHECK: %xmm0 = VPBROADCASTDrm %rip, _, _, _, _ ; CHECK: %xmm0 = VPBROADCASTDrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm0 = VPBROADCASTDZ128m %rip, _, _, _, _ %xmm0 = VPBROADCASTDZ128m %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VPBROADCASTDrr %xmm0 ; CHECK: %xmm0 = VPBROADCASTDrr %xmm0
%xmm0 = VPBROADCASTDZ128r %xmm0 %xmm0 = VPBROADCASTDZ128r %xmm0
; CHECK: %xmm0 = VPBROADCASTQrm %rip, _, _, _, _ ; CHECK: %xmm0 = VPBROADCASTQrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm0 = VPBROADCASTQZ128m %rip, _, _, _, _ %xmm0 = VPBROADCASTQZ128m %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VPBROADCASTQrr %xmm0 ; CHECK: %xmm0 = VPBROADCASTQrr %xmm0
%xmm0 = VPBROADCASTQZ128r %xmm0 %xmm0 = VPBROADCASTQZ128r %xmm0
; CHECK: %xmm0 = VPBROADCASTWrm %rip, _, _, _, _ ; CHECK: %xmm0 = VPBROADCASTWrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm0 = VPBROADCASTWZ128m %rip, _, _, _, _ %xmm0 = VPBROADCASTWZ128m %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VPBROADCASTWrr %xmm0 ; CHECK: %xmm0 = VPBROADCASTWrr %xmm0
%xmm0 = VPBROADCASTWZ128r %xmm0 %xmm0 = VPBROADCASTWZ128r %xmm0
; CHECK: %xmm0 = VPBROADCASTQrm %rip, _, _, _, _ ; CHECK: %xmm0 = VPBROADCASTQrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm0 = VBROADCASTI32X2Z128m %rip, _, _, _, _ %xmm0 = VBROADCASTI32X2Z128m %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VPBROADCASTQrr %xmm0 ; CHECK: %xmm0 = VPBROADCASTQrr %xmm0
%xmm0 = VBROADCASTI32X2Z128r %xmm0 %xmm0 = VBROADCASTI32X2Z128r %xmm0
; CHECK: %xmm0 = VCVTPS2PHrr %xmm0, 2 ; CHECK: %xmm0 = VCVTPS2PHrr %xmm0, 2
%xmm0 = VCVTPS2PHZ128rr %xmm0, 2 %xmm0 = VCVTPS2PHZ128rr %xmm0, 2
; CHECK: VCVTPS2PHmr %rdi, %xmm0, 1, _, 0, _, _ ; CHECK: VCVTPS2PHmr %rdi, %xmm0, 1, %noreg, 0, %noreg, %noreg
VCVTPS2PHZ128mr %rdi, %xmm0, 1, _, 0, _, _ VCVTPS2PHZ128mr %rdi, %xmm0, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm0 = VPABSBrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPABSBrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPABSBZ128rm %rip, 1, _, %rax, _ %xmm0 = VPABSBZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPABSBrr %xmm0 ; CHECK: %xmm0 = VPABSBrr %xmm0
%xmm0 = VPABSBZ128rr %xmm0 %xmm0 = VPABSBZ128rr %xmm0
; CHECK: %xmm0 = VPABSDrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPABSDrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPABSDZ128rm %rip, 1, _, %rax, _ %xmm0 = VPABSDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPABSDrr %xmm0 ; CHECK: %xmm0 = VPABSDrr %xmm0
%xmm0 = VPABSDZ128rr %xmm0 %xmm0 = VPABSDZ128rr %xmm0
; CHECK: %xmm0 = VPABSWrm %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VPABSWrm %rip, 1, %noreg, %rax, %noreg
%xmm0 = VPABSWZ128rm %rip, 1, _, %rax, _ %xmm0 = VPABSWZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VPABSWrr %xmm0 ; CHECK: %xmm0 = VPABSWrr %xmm0
%xmm0 = VPABSWZ128rr %xmm0 %xmm0 = VPABSWZ128rr %xmm0
; CHECK: %xmm0 = VPALIGNRrmi %xmm0, _, _, _, _, _, _ ; CHECK: %xmm0 = VPALIGNRrmi %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm0 = VPALIGNRZ128rmi %xmm0, _, _, _, _, _, _ %xmm0 = VPALIGNRZ128rmi %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VPALIGNRrri %xmm0, %xmm1, 15 ; CHECK: %xmm0 = VPALIGNRrri %xmm0, %xmm1, 15
%xmm0 = VPALIGNRZ128rri %xmm0, %xmm1, 15 %xmm0 = VPALIGNRZ128rri %xmm0, %xmm1, 15
RET 0, %zmm0, %zmm1 RET 0, %zmm0, %zmm1
... ...
--- ---
# CHECK-LABEL: name: evex_scalar_to_vex_test # CHECK-LABEL: name: evex_scalar_to_vex_test
# CHECK: bb.0: # CHECK: bb.0:
name: evex_scalar_to_vex_test name: evex_scalar_to_vex_test
body: | body: |
bb.0: bb.0:
; CHECK: %xmm0 = VADDSDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VADDSDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VADDSDZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VADDSDZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VADDSDrm_Int %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VADDSDrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VADDSDZrm_Int %xmm0, %rip, 1, _, %rax, _ %xmm0 = VADDSDZrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VADDSDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VADDSDrr %xmm0, %xmm1
%xmm0 = VADDSDZrr %xmm0, %xmm1 %xmm0 = VADDSDZrr %xmm0, %xmm1
; CHECK: %xmm0 = VADDSDrr_Int %xmm0, %xmm1 ; CHECK: %xmm0 = VADDSDrr_Int %xmm0, %xmm1
%xmm0 = VADDSDZrr_Int %xmm0, %xmm1 %xmm0 = VADDSDZrr_Int %xmm0, %xmm1
; CHECK: %xmm0 = VADDSSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VADDSSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VADDSSZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VADDSSZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VADDSSrm_Int %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VADDSSrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VADDSSZrm_Int %xmm0, %rip, 1, _, %rax, _ %xmm0 = VADDSSZrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VADDSSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VADDSSrr %xmm0, %xmm1
%xmm0 = VADDSSZrr %xmm0, %xmm1 %xmm0 = VADDSSZrr %xmm0, %xmm1
; CHECK: %xmm0 = VADDSSrr_Int %xmm0, %xmm1 ; CHECK: %xmm0 = VADDSSrr_Int %xmm0, %xmm1
%xmm0 = VADDSSZrr_Int %xmm0, %xmm1 %xmm0 = VADDSSZrr_Int %xmm0, %xmm1
; CHECK: %xmm0 = VDIVSDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VDIVSDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VDIVSDZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VDIVSDZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VDIVSDrm_Int %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VDIVSDrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VDIVSDZrm_Int %xmm0, %rip, 1, _, %rax, _ %xmm0 = VDIVSDZrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VDIVSDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VDIVSDrr %xmm0, %xmm1
%xmm0 = VDIVSDZrr %xmm0, %xmm1 %xmm0 = VDIVSDZrr %xmm0, %xmm1
; CHECK: %xmm0 = VDIVSDrr_Int %xmm0, %xmm1 ; CHECK: %xmm0 = VDIVSDrr_Int %xmm0, %xmm1
%xmm0 = VDIVSDZrr_Int %xmm0, %xmm1 %xmm0 = VDIVSDZrr_Int %xmm0, %xmm1
; CHECK: %xmm0 = VDIVSSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VDIVSSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VDIVSSZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VDIVSSZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VDIVSSrm_Int %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VDIVSSrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VDIVSSZrm_Int %xmm0, %rip, 1, _, %rax, _ %xmm0 = VDIVSSZrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VDIVSSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VDIVSSrr %xmm0, %xmm1
%xmm0 = VDIVSSZrr %xmm0, %xmm1 %xmm0 = VDIVSSZrr %xmm0, %xmm1
; CHECK: %xmm0 = VDIVSSrr_Int %xmm0, %xmm1 ; CHECK: %xmm0 = VDIVSSrr_Int %xmm0, %xmm1
%xmm0 = VDIVSSZrr_Int %xmm0, %xmm1 %xmm0 = VDIVSSZrr_Int %xmm0, %xmm1
; CHECK: %xmm0 = VMAXCSDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMAXCSDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMAXCSDZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMAXCSDZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMAXCSDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMAXCSDrr %xmm0, %xmm1
%xmm0 = VMAXCSDZrr %xmm0, %xmm1 %xmm0 = VMAXCSDZrr %xmm0, %xmm1
; CHECK: %xmm0 = VMAXCSSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMAXCSSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMAXCSSZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMAXCSSZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMAXCSSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMAXCSSrr %xmm0, %xmm1
%xmm0 = VMAXCSSZrr %xmm0, %xmm1 %xmm0 = VMAXCSSZrr %xmm0, %xmm1
; CHECK: %xmm0 = VMAXCSDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMAXCSDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMAXSDZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMAXSDZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMAXSDrm_Int %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMAXSDrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMAXSDZrm_Int %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMAXSDZrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMAXCSDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMAXCSDrr %xmm0, %xmm1
%xmm0 = VMAXSDZrr %xmm0, %xmm1 %xmm0 = VMAXSDZrr %xmm0, %xmm1
; CHECK: %xmm0 = VMAXSDrr_Int %xmm0, %xmm1 ; CHECK: %xmm0 = VMAXSDrr_Int %xmm0, %xmm1
%xmm0 = VMAXSDZrr_Int %xmm0, %xmm1 %xmm0 = VMAXSDZrr_Int %xmm0, %xmm1
; CHECK: %xmm0 = VMAXCSSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMAXCSSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMAXSSZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMAXSSZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMAXSSrm_Int %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMAXSSrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMAXSSZrm_Int %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMAXSSZrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMAXCSSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMAXCSSrr %xmm0, %xmm1
%xmm0 = VMAXSSZrr %xmm0, %xmm1 %xmm0 = VMAXSSZrr %xmm0, %xmm1
; CHECK: %xmm0 = VMAXSSrr_Int %xmm0, %xmm1 ; CHECK: %xmm0 = VMAXSSrr_Int %xmm0, %xmm1
%xmm0 = VMAXSSZrr_Int %xmm0, %xmm1 %xmm0 = VMAXSSZrr_Int %xmm0, %xmm1
; CHECK: %xmm0 = VMINCSDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMINCSDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMINCSDZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMINCSDZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMINCSDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMINCSDrr %xmm0, %xmm1
%xmm0 = VMINCSDZrr %xmm0, %xmm1 %xmm0 = VMINCSDZrr %xmm0, %xmm1
; CHECK: %xmm0 = VMINCSSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMINCSSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMINCSSZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMINCSSZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMINCSSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMINCSSrr %xmm0, %xmm1
%xmm0 = VMINCSSZrr %xmm0, %xmm1 %xmm0 = VMINCSSZrr %xmm0, %xmm1
; CHECK: %xmm0 = VMINCSDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMINCSDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMINSDZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMINSDZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMINSDrm_Int %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMINSDrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMINSDZrm_Int %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMINSDZrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMINCSDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMINCSDrr %xmm0, %xmm1
%xmm0 = VMINSDZrr %xmm0, %xmm1 %xmm0 = VMINSDZrr %xmm0, %xmm1
; CHECK: %xmm0 = VMINSDrr_Int %xmm0, %xmm1 ; CHECK: %xmm0 = VMINSDrr_Int %xmm0, %xmm1
%xmm0 = VMINSDZrr_Int %xmm0, %xmm1 %xmm0 = VMINSDZrr_Int %xmm0, %xmm1
; CHECK: %xmm0 = VMINCSSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMINCSSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMINSSZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMINSSZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMINSSrm_Int %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMINSSrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMINSSZrm_Int %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMINSSZrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMINCSSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMINCSSrr %xmm0, %xmm1
%xmm0 = VMINSSZrr %xmm0, %xmm1 %xmm0 = VMINSSZrr %xmm0, %xmm1
; CHECK: %xmm0 = VMINSSrr_Int %xmm0, %xmm1 ; CHECK: %xmm0 = VMINSSrr_Int %xmm0, %xmm1
%xmm0 = VMINSSZrr_Int %xmm0, %xmm1 %xmm0 = VMINSSZrr_Int %xmm0, %xmm1
; CHECK: %xmm0 = VMULSDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMULSDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMULSDZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMULSDZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMULSDrm_Int %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMULSDrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMULSDZrm_Int %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMULSDZrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMULSDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMULSDrr %xmm0, %xmm1
%xmm0 = VMULSDZrr %xmm0, %xmm1 %xmm0 = VMULSDZrr %xmm0, %xmm1
; CHECK: %xmm0 = VMULSDrr_Int %xmm0, %xmm1 ; CHECK: %xmm0 = VMULSDrr_Int %xmm0, %xmm1
%xmm0 = VMULSDZrr_Int %xmm0, %xmm1 %xmm0 = VMULSDZrr_Int %xmm0, %xmm1
; CHECK: %xmm0 = VMULSSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMULSSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMULSSZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMULSSZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMULSSrm_Int %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VMULSSrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VMULSSZrm_Int %xmm0, %rip, 1, _, %rax, _ %xmm0 = VMULSSZrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VMULSSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VMULSSrr %xmm0, %xmm1
%xmm0 = VMULSSZrr %xmm0, %xmm1 %xmm0 = VMULSSZrr %xmm0, %xmm1
; CHECK: %xmm0 = VMULSSrr_Int %xmm0, %xmm1 ; CHECK: %xmm0 = VMULSSrr_Int %xmm0, %xmm1
%xmm0 = VMULSSZrr_Int %xmm0, %xmm1 %xmm0 = VMULSSZrr_Int %xmm0, %xmm1
; CHECK: %xmm0 = VSUBSDrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VSUBSDrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VSUBSDZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VSUBSDZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VSUBSDrm_Int %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VSUBSDrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VSUBSDZrm_Int %xmm0, %rip, 1, _, %rax, _ %xmm0 = VSUBSDZrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VSUBSDrr %xmm0, %xmm1 ; CHECK: %xmm0 = VSUBSDrr %xmm0, %xmm1
%xmm0 = VSUBSDZrr %xmm0, %xmm1 %xmm0 = VSUBSDZrr %xmm0, %xmm1
; CHECK: %xmm0 = VSUBSDrr_Int %xmm0, %xmm1 ; CHECK: %xmm0 = VSUBSDrr_Int %xmm0, %xmm1
%xmm0 = VSUBSDZrr_Int %xmm0, %xmm1 %xmm0 = VSUBSDZrr_Int %xmm0, %xmm1
; CHECK: %xmm0 = VSUBSSrm %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VSUBSSrm %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VSUBSSZrm %xmm0, %rip, 1, _, %rax, _ %xmm0 = VSUBSSZrm %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VSUBSSrm_Int %xmm0, %rip, 1, _, %rax, _ ; CHECK: %xmm0 = VSUBSSrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
%xmm0 = VSUBSSZrm_Int %xmm0, %rip, 1, _, %rax, _ %xmm0 = VSUBSSZrm_Int %xmm0, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm0 = VSUBSSrr %xmm0, %xmm1 ; CHECK: %xmm0 = VSUBSSrr %xmm0, %xmm1
%xmm0 = VSUBSSZrr %xmm0, %xmm1 %xmm0 = VSUBSSZrr %xmm0, %xmm1
; CHECK: %xmm0 = VSUBSSrr_Int %xmm0, %xmm1 ; CHECK: %xmm0 = VSUBSSrr_Int %xmm0, %xmm1
%xmm0 = VSUBSSZrr_Int %xmm0, %xmm1 %xmm0 = VSUBSSZrr_Int %xmm0, %xmm1
; CHECK: %xmm0 = VFMADD132SDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD132SDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD132SDZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD132SDZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD132SDm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD132SDm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD132SDZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD132SDZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD132SDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD132SDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD132SDZr %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD132SDZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD132SDr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD132SDr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD132SDZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD132SDZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD132SSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD132SSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD132SSZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD132SSZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD132SSm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD132SSm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD132SSZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD132SSZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD132SSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD132SSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD132SSZr %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD132SSZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD132SSr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD132SSr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD132SSZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD132SSZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD213SDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD213SDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD213SDZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD213SDZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD213SDm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD213SDm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD213SDZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD213SDZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD213SDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD213SDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD213SDZr %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD213SDZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD213SDr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD213SDr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD213SDZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD213SDZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD213SSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD213SSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD213SSZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD213SSZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD213SSm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD213SSm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD213SSZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD213SSZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD213SSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD213SSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD213SSZr %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD213SSZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD213SSr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD213SSr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD213SSZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD213SSZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD231SDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD231SDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD231SDZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD231SDZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD231SDm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD231SDm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD231SDZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD231SDZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD231SDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD231SDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD231SDZr %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD231SDZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD231SDr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD231SDr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD231SDZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD231SDZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD231SSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD231SSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD231SSZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD231SSZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD231SSm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMADD231SSm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMADD231SSZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMADD231SSZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMADD231SSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD231SSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD231SSZr %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD231SSZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMADD231SSr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMADD231SSr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFMADD231SSZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFMADD231SSZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB132SDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB132SDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB132SDZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB132SDZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB132SDm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB132SDm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB132SDZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB132SDZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB132SDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB132SDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB132SDZr %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB132SDZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB132SDr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB132SDr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB132SDZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB132SDZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB132SSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB132SSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB132SSZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB132SSZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB132SSm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB132SSm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB132SSZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB132SSZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB132SSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB132SSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB132SSZr %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB132SSZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB132SSr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB132SSr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB132SSZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB132SSZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB213SDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB213SDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB213SDZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB213SDZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB213SDm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB213SDm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB213SDZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB213SDZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB213SDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB213SDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB213SDZr %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB213SDZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB213SDr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB213SDr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB213SDZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB213SDZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB213SSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB213SSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB213SSZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB213SSZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB213SSm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB213SSm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB213SSZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB213SSZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB213SSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB213SSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB213SSZr %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB213SSZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB213SSr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB213SSr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB213SSZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB213SSZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB231SDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB231SDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB231SDZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB231SDZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB231SDm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB231SDm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB231SDZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB231SDZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB231SDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB231SDr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB231SDZr %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB231SDZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB231SDr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB231SDr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB231SDZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB231SDZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB231SSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB231SSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB231SSZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB231SSZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB231SSm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFMSUB231SSm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFMSUB231SSZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFMSUB231SSZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFMSUB231SSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB231SSr %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB231SSZr %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB231SSZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFMSUB231SSr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFMSUB231SSr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFMSUB231SSZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFMSUB231SSZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD132SDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD132SDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD132SDZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD132SDZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD132SDm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD132SDm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD132SDZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD132SDZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD132SDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD132SDr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD132SDZr %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD132SDZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD132SDr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD132SDr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD132SDZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD132SDZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD132SSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD132SSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD132SSZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD132SSZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD132SSm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD132SSm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD132SSZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD132SSZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD132SSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD132SSr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD132SSZr %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD132SSZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD132SSr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD132SSr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD132SSZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD132SSZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD213SDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD213SDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD213SDZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD213SDZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD213SDm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD213SDm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD213SDZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD213SDZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD213SDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD213SDr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD213SDZr %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD213SDZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD213SDr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD213SDr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD213SDZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD213SDZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD213SSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD213SSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD213SSZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD213SSZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD213SSm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD213SSm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD213SSZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD213SSZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD213SSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD213SSr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD213SSZr %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD213SSZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD213SSr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD213SSr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD213SSZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD213SSZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD231SDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD231SDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD231SDZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD231SDZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD231SDm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD231SDm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD231SDZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD231SDZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD231SDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD231SDr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD231SDZr %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD231SDZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD231SDr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD231SDr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD231SDZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD231SDZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD231SSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD231SSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD231SSZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD231SSZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD231SSm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMADD231SSm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMADD231SSZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMADD231SSZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMADD231SSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD231SSr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD231SSZr %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD231SSZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMADD231SSr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMADD231SSr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFNMADD231SSZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFNMADD231SSZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB132SDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB132SDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB132SDZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB132SDZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB132SDm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB132SDm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB132SDZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB132SDZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB132SDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB132SDr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB132SDZr %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB132SDZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB132SDr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB132SDr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB132SDZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB132SDZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB132SSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB132SSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB132SSZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB132SSZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB132SSm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB132SSm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB132SSZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB132SSZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB132SSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB132SSr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB132SSZr %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB132SSZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB132SSr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB132SSr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB132SSZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB132SSZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB213SDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB213SDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB213SDZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB213SDZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB213SDm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB213SDm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB213SDZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB213SDZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB213SDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB213SDr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB213SDZr %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB213SDZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB213SDr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB213SDr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB213SDZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB213SDZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB213SSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB213SSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB213SSZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB213SSZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB213SSm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB213SSm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB213SSZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB213SSZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB213SSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB213SSr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB213SSZr %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB213SSZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB213SSr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB213SSr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB213SSZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB213SSZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB231SDm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB231SDm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB231SDZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB231SDZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB231SDm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB231SDm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB231SDZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB231SDZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB231SDr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB231SDr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB231SDZr %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB231SDZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB231SDr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB231SDr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB231SDZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB231SDZr_Int %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB231SSm %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB231SSm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB231SSZm %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB231SSZm %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB231SSm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ ; CHECK: %xmm0 = VFNMSUB231SSm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
%xmm0 = VFNMSUB231SSZm_Int %xmm0, %xmm0, %rsi, 1, _, 0, _ %xmm0 = VFNMSUB231SSZm_Int %xmm0, %xmm0, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VFNMSUB231SSr %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB231SSr %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB231SSZr %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB231SSZr %xmm0, %xmm1, %xmm2
; CHECK: %xmm0 = VFNMSUB231SSr_Int %xmm0, %xmm1, %xmm2 ; CHECK: %xmm0 = VFNMSUB231SSr_Int %xmm0, %xmm1, %xmm2
%xmm0 = VFNMSUB231SSZr_Int %xmm0, %xmm1, %xmm2 %xmm0 = VFNMSUB231SSZr_Int %xmm0, %xmm1, %xmm2
; CHECK: VPEXTRBmr %rdi, 1, _, 0, _, %xmm0, 3 ; CHECK: VPEXTRBmr %rdi, 1, %noreg, 0, %noreg, %xmm0, 3
VPEXTRBZmr %rdi, 1, _, 0, _, %xmm0, 3 VPEXTRBZmr %rdi, 1, %noreg, 0, %noreg, %xmm0, 3
; CHECK: %eax = VPEXTRBrr %xmm0, 1 ; CHECK: %eax = VPEXTRBrr %xmm0, 1
%eax = VPEXTRBZrr %xmm0, 1 %eax = VPEXTRBZrr %xmm0, 1
; CHECK: VPEXTRDmr %rdi, 1, _, 0, _, %xmm0, 3 ; CHECK: VPEXTRDmr %rdi, 1, %noreg, 0, %noreg, %xmm0, 3
VPEXTRDZmr %rdi, 1, _, 0, _, %xmm0, 3 VPEXTRDZmr %rdi, 1, %noreg, 0, %noreg, %xmm0, 3
; CHECK: %eax = VPEXTRDrr %xmm0, 1 ; CHECK: %eax = VPEXTRDrr %xmm0, 1
%eax = VPEXTRDZrr %xmm0, 1 %eax = VPEXTRDZrr %xmm0, 1
; CHECK: VPEXTRQmr %rdi, 1, _, 0, _, %xmm0, 3 ; CHECK: VPEXTRQmr %rdi, 1, %noreg, 0, %noreg, %xmm0, 3
VPEXTRQZmr %rdi, 1, _, 0, _, %xmm0, 3 VPEXTRQZmr %rdi, 1, %noreg, 0, %noreg, %xmm0, 3
; CHECK: %rax = VPEXTRQrr %xmm0, 1 ; CHECK: %rax = VPEXTRQrr %xmm0, 1
%rax = VPEXTRQZrr %xmm0, 1 %rax = VPEXTRQZrr %xmm0, 1
; CHECK: VPEXTRWmr %rdi, 1, _, 0, _, %xmm0, 3 ; CHECK: VPEXTRWmr %rdi, 1, %noreg, 0, %noreg, %xmm0, 3
VPEXTRWZmr %rdi, 1, _, 0, _, %xmm0, 3 VPEXTRWZmr %rdi, 1, %noreg, 0, %noreg, %xmm0, 3
; CHECK: %eax = VPEXTRWri %xmm0, 1 ; CHECK: %eax = VPEXTRWri %xmm0, 1
%eax = VPEXTRWZrr %xmm0, 1 %eax = VPEXTRWZrr %xmm0, 1
; CHECK: %eax = VPEXTRWrr_REV %xmm0, 1 ; CHECK: %eax = VPEXTRWrr_REV %xmm0, 1
%eax = VPEXTRWZrr_REV %xmm0, 1 %eax = VPEXTRWZrr_REV %xmm0, 1
; CHECK: %xmm0 = VPINSRBrm %xmm0, %rsi, 1, _, 0, _, 3 ; CHECK: %xmm0 = VPINSRBrm %xmm0, %rsi, 1, %noreg, 0, %noreg, 3
%xmm0 = VPINSRBZrm %xmm0, %rsi, 1, _, 0, _, 3 %xmm0 = VPINSRBZrm %xmm0, %rsi, 1, %noreg, 0, %noreg, 3
; CHECK: %xmm0 = VPINSRBrr %xmm0, %edi, 5 ; CHECK: %xmm0 = VPINSRBrr %xmm0, %edi, 5
%xmm0 = VPINSRBZrr %xmm0, %edi, 5 %xmm0 = VPINSRBZrr %xmm0, %edi, 5
; CHECK: %xmm0 = VPINSRDrm %xmm0, %rsi, 1, _, 0, _, 3 ; CHECK: %xmm0 = VPINSRDrm %xmm0, %rsi, 1, %noreg, 0, %noreg, 3
%xmm0 = VPINSRDZrm %xmm0, %rsi, 1, _, 0, _, 3 %xmm0 = VPINSRDZrm %xmm0, %rsi, 1, %noreg, 0, %noreg, 3
; CHECK: %xmm0 = VPINSRDrr %xmm0, %edi, 5 ; CHECK: %xmm0 = VPINSRDrr %xmm0, %edi, 5
%xmm0 = VPINSRDZrr %xmm0, %edi, 5 %xmm0 = VPINSRDZrr %xmm0, %edi, 5
; CHECK: %xmm0 = VPINSRQrm %xmm0, %rsi, 1, _, 0, _, 3 ; CHECK: %xmm0 = VPINSRQrm %xmm0, %rsi, 1, %noreg, 0, %noreg, 3
%xmm0 = VPINSRQZrm %xmm0, %rsi, 1, _, 0, _, 3 %xmm0 = VPINSRQZrm %xmm0, %rsi, 1, %noreg, 0, %noreg, 3
; CHECK: %xmm0 = VPINSRQrr %xmm0, %rdi, 5 ; CHECK: %xmm0 = VPINSRQrr %xmm0, %rdi, 5
%xmm0 = VPINSRQZrr %xmm0, %rdi, 5 %xmm0 = VPINSRQZrr %xmm0, %rdi, 5
; CHECK: %xmm0 = VPINSRWrmi %xmm0, %rsi, 1, _, 0, _, 3 ; CHECK: %xmm0 = VPINSRWrmi %xmm0, %rsi, 1, %noreg, 0, %noreg, 3
%xmm0 = VPINSRWZrm %xmm0, %rsi, 1, _, 0, _, 3 %xmm0 = VPINSRWZrm %xmm0, %rsi, 1, %noreg, 0, %noreg, 3
; CHECK: %xmm0 = VPINSRWrri %xmm0, %edi, 5 ; CHECK: %xmm0 = VPINSRWrri %xmm0, %edi, 5
%xmm0 = VPINSRWZrr %xmm0, %edi, 5 %xmm0 = VPINSRWZrr %xmm0, %edi, 5
; CHECK: %xmm0 = VSQRTSDm %xmm0, _, _, _, _, _ ; CHECK: %xmm0 = VSQRTSDm %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm0 = VSQRTSDZm %xmm0, _, _, _, _, _ %xmm0 = VSQRTSDZm %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VSQRTSDm_Int %xmm0, _, _, _, _, _ ; CHECK: %xmm0 = VSQRTSDm_Int %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm0 = VSQRTSDZm_Int %xmm0, _, _, _, _, _ %xmm0 = VSQRTSDZm_Int %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VSQRTSDr %xmm0, _ ; CHECK: %xmm0 = VSQRTSDr %xmm0, %noreg
%xmm0 = VSQRTSDZr %xmm0, _ %xmm0 = VSQRTSDZr %xmm0, %noreg
; CHECK: %xmm0 = VSQRTSDr_Int %xmm0, _ ; CHECK: %xmm0 = VSQRTSDr_Int %xmm0, %noreg
%xmm0 = VSQRTSDZr_Int %xmm0, _ %xmm0 = VSQRTSDZr_Int %xmm0, %noreg
; CHECK: %xmm0 = VSQRTSSm %xmm0, _, _, _, _, _ ; CHECK: %xmm0 = VSQRTSSm %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm0 = VSQRTSSZm %xmm0, _, _, _, _, _ %xmm0 = VSQRTSSZm %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VSQRTSSm_Int %xmm0, _, _, _, _, _ ; CHECK: %xmm0 = VSQRTSSm_Int %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm0 = VSQRTSSZm_Int %xmm0, _, _, _, _, _ %xmm0 = VSQRTSSZm_Int %xmm0, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VSQRTSSr %xmm0, _ ; CHECK: %xmm0 = VSQRTSSr %xmm0, %noreg
%xmm0 = VSQRTSSZr %xmm0, _ %xmm0 = VSQRTSSZr %xmm0, %noreg
; CHECK: %xmm0 = VSQRTSSr_Int %xmm0, _ ; CHECK: %xmm0 = VSQRTSSr_Int %xmm0, %noreg
%xmm0 = VSQRTSSZr_Int %xmm0, _ %xmm0 = VSQRTSSZr_Int %xmm0, %noreg
; CHECK: %rdi = VCVTSD2SI64rr %xmm0 ; CHECK: %rdi = VCVTSD2SI64rr %xmm0
%rdi = VCVTSD2SI64Zrr %xmm0 %rdi = VCVTSD2SI64Zrr %xmm0
; CHECK: %edi = VCVTSD2SIrr %xmm0 ; CHECK: %edi = VCVTSD2SIrr %xmm0
%edi = VCVTSD2SIZrr %xmm0 %edi = VCVTSD2SIZrr %xmm0
; CHECK: %xmm0 = VCVTSD2SSrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VCVTSD2SSrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSD2SSZrm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSD2SSZrm %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = Int_VCVTSD2SSrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = Int_VCVTSD2SSrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSD2SSZrm_Int %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSD2SSZrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VCVTSD2SSrr %xmm0, _ ; CHECK: %xmm0 = VCVTSD2SSrr %xmm0, %noreg
%xmm0 = VCVTSD2SSZrr %xmm0, _ %xmm0 = VCVTSD2SSZrr %xmm0, %noreg
; CHECK: %xmm0 = Int_VCVTSD2SSrr %xmm0, _ ; CHECK: %xmm0 = Int_VCVTSD2SSrr %xmm0, %noreg
%xmm0 = VCVTSD2SSZrr_Int %xmm0, _ %xmm0 = VCVTSD2SSZrr_Int %xmm0, %noreg
; CHECK: %xmm0 = VCVTSI2SDrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VCVTSI2SDrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI2SDZrm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSI2SDZrm %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = Int_VCVTSI2SDrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = Int_VCVTSI2SDrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI2SDZrm_Int %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSI2SDZrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VCVTSI2SDrr %xmm0, _ ; CHECK: %xmm0 = VCVTSI2SDrr %xmm0, %noreg
%xmm0 = VCVTSI2SDZrr %xmm0, _ %xmm0 = VCVTSI2SDZrr %xmm0, %noreg
; CHECK: %xmm0 = Int_VCVTSI2SDrr %xmm0, _ ; CHECK: %xmm0 = Int_VCVTSI2SDrr %xmm0, %noreg
%xmm0 = VCVTSI2SDZrr_Int %xmm0, _ %xmm0 = VCVTSI2SDZrr_Int %xmm0, %noreg
; CHECK: %xmm0 = VCVTSI2SSrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VCVTSI2SSrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI2SSZrm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSI2SSZrm %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = Int_VCVTSI2SSrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = Int_VCVTSI2SSrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI2SSZrm_Int %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSI2SSZrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VCVTSI2SSrr %xmm0, _ ; CHECK: %xmm0 = VCVTSI2SSrr %xmm0, %noreg
%xmm0 = VCVTSI2SSZrr %xmm0, _ %xmm0 = VCVTSI2SSZrr %xmm0, %noreg
; CHECK: %xmm0 = Int_VCVTSI2SSrr %xmm0, _ ; CHECK: %xmm0 = Int_VCVTSI2SSrr %xmm0, %noreg
%xmm0 = VCVTSI2SSZrr_Int %xmm0, _ %xmm0 = VCVTSI2SSZrr_Int %xmm0, %noreg
; CHECK: %xmm0 = VCVTSI2SD64rm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VCVTSI2SD64rm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI642SDZrm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSI642SDZrm %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = Int_VCVTSI2SD64rm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = Int_VCVTSI2SD64rm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI642SDZrm_Int %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSI642SDZrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VCVTSI2SD64rr %xmm0, _ ; CHECK: %xmm0 = VCVTSI2SD64rr %xmm0, %noreg
%xmm0 = VCVTSI642SDZrr %xmm0, _ %xmm0 = VCVTSI642SDZrr %xmm0, %noreg
; CHECK: %xmm0 = Int_VCVTSI2SD64rr %xmm0, _ ; CHECK: %xmm0 = Int_VCVTSI2SD64rr %xmm0, %noreg
%xmm0 = VCVTSI642SDZrr_Int %xmm0, _ %xmm0 = VCVTSI642SDZrr_Int %xmm0, %noreg
; CHECK: %xmm0 = VCVTSI2SS64rm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VCVTSI2SS64rm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI642SSZrm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSI642SSZrm %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = Int_VCVTSI2SS64rm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = Int_VCVTSI2SS64rm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSI642SSZrm_Int %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSI642SSZrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VCVTSI2SS64rr %xmm0, _ ; CHECK: %xmm0 = VCVTSI2SS64rr %xmm0, %noreg
%xmm0 = VCVTSI642SSZrr %xmm0, _ %xmm0 = VCVTSI642SSZrr %xmm0, %noreg
; CHECK: %xmm0 = Int_VCVTSI2SS64rr %xmm0, _ ; CHECK: %xmm0 = Int_VCVTSI2SS64rr %xmm0, %noreg
%xmm0 = VCVTSI642SSZrr_Int %xmm0, _ %xmm0 = VCVTSI642SSZrr_Int %xmm0, %noreg
; CHECK: %xmm0 = VCVTSS2SDrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = VCVTSS2SDrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSS2SDZrm %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSS2SDZrm %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = Int_VCVTSS2SDrm %xmm0, %rdi, 1, _, 0, _ ; CHECK: %xmm0 = Int_VCVTSS2SDrm %xmm0, %rdi, 1, %noreg, 0, %noreg
%xmm0 = VCVTSS2SDZrm_Int %xmm0, %rdi, 1, _, 0, _ %xmm0 = VCVTSS2SDZrm_Int %xmm0, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm0 = VCVTSS2SDrr %xmm0, _ ; CHECK: %xmm0 = VCVTSS2SDrr %xmm0, %noreg
%xmm0 = VCVTSS2SDZrr %xmm0, _ %xmm0 = VCVTSS2SDZrr %xmm0, %noreg
; CHECK: %xmm0 = Int_VCVTSS2SDrr %xmm0, _ ; CHECK: %xmm0 = Int_VCVTSS2SDrr %xmm0, %noreg
%xmm0 = VCVTSS2SDZrr_Int %xmm0, _ %xmm0 = VCVTSS2SDZrr_Int %xmm0, %noreg
; CHECK: %rdi = VCVTSS2SI64rm %rdi, %xmm0, 1, _, 0 ; CHECK: %rdi = VCVTSS2SI64rm %rdi, %xmm0, 1, %noreg, 0
%rdi = VCVTSS2SI64Zrm %rdi, %xmm0, 1, _, 0 %rdi = VCVTSS2SI64Zrm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %rdi = VCVTSS2SI64rr %xmm0 ; CHECK: %rdi = VCVTSS2SI64rr %xmm0
%rdi = VCVTSS2SI64Zrr %xmm0 %rdi = VCVTSS2SI64Zrr %xmm0
; CHECK: %edi = VCVTSS2SIrm %rdi, %xmm0, 1, _, 0 ; CHECK: %edi = VCVTSS2SIrm %rdi, %xmm0, 1, %noreg, 0
%edi = VCVTSS2SIZrm %rdi, %xmm0, 1, _, 0 %edi = VCVTSS2SIZrm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %edi = VCVTSS2SIrr %xmm0 ; CHECK: %edi = VCVTSS2SIrr %xmm0
%edi = VCVTSS2SIZrr %xmm0 %edi = VCVTSS2SIZrr %xmm0
; CHECK: %rdi = VCVTTSD2SI64rm %rdi, %xmm0, 1, _, 0 ; CHECK: %rdi = VCVTTSD2SI64rm %rdi, %xmm0, 1, %noreg, 0
%rdi = VCVTTSD2SI64Zrm %rdi, %xmm0, 1, _, 0 %rdi = VCVTTSD2SI64Zrm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %rdi = Int_VCVTTSD2SI64rm %rdi, %xmm0, 1, _, 0 ; CHECK: %rdi = Int_VCVTTSD2SI64rm %rdi, %xmm0, 1, %noreg, 0
%rdi = VCVTTSD2SI64Zrm_Int %rdi, %xmm0, 1, _, 0 %rdi = VCVTTSD2SI64Zrm_Int %rdi, %xmm0, 1, %noreg, 0
; CHECK: %rdi = VCVTTSD2SI64rr %xmm0 ; CHECK: %rdi = VCVTTSD2SI64rr %xmm0
%rdi = VCVTTSD2SI64Zrr %xmm0 %rdi = VCVTTSD2SI64Zrr %xmm0
; CHECK: %rdi = Int_VCVTTSD2SI64rr %xmm0 ; CHECK: %rdi = Int_VCVTTSD2SI64rr %xmm0
%rdi = VCVTTSD2SI64Zrr_Int %xmm0 %rdi = VCVTTSD2SI64Zrr_Int %xmm0
; CHECK: %edi = VCVTTSD2SIrm %rdi, %xmm0, 1, _, 0 ; CHECK: %edi = VCVTTSD2SIrm %rdi, %xmm0, 1, %noreg, 0
%edi = VCVTTSD2SIZrm %rdi, %xmm0, 1, _, 0 %edi = VCVTTSD2SIZrm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %edi = Int_VCVTTSD2SIrm %rdi, %xmm0, 1, _, 0 ; CHECK: %edi = Int_VCVTTSD2SIrm %rdi, %xmm0, 1, %noreg, 0
%edi = VCVTTSD2SIZrm_Int %rdi, %xmm0, 1, _, 0 %edi = VCVTTSD2SIZrm_Int %rdi, %xmm0, 1, %noreg, 0
; CHECK: %edi = VCVTTSD2SIrr %xmm0 ; CHECK: %edi = VCVTTSD2SIrr %xmm0
%edi = VCVTTSD2SIZrr %xmm0 %edi = VCVTTSD2SIZrr %xmm0
; CHECK: %edi = Int_VCVTTSD2SIrr %xmm0 ; CHECK: %edi = Int_VCVTTSD2SIrr %xmm0
%edi = VCVTTSD2SIZrr_Int %xmm0 %edi = VCVTTSD2SIZrr_Int %xmm0
; CHECK: %rdi = VCVTTSS2SI64rm %rdi, %xmm0, 1, _, 0 ; CHECK: %rdi = VCVTTSS2SI64rm %rdi, %xmm0, 1, %noreg, 0
%rdi = VCVTTSS2SI64Zrm %rdi, %xmm0, 1, _, 0 %rdi = VCVTTSS2SI64Zrm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %rdi = Int_VCVTTSS2SI64rm %rdi, %xmm0, 1, _, 0 ; CHECK: %rdi = Int_VCVTTSS2SI64rm %rdi, %xmm0, 1, %noreg, 0
%rdi = VCVTTSS2SI64Zrm_Int %rdi, %xmm0, 1, _, 0 %rdi = VCVTTSS2SI64Zrm_Int %rdi, %xmm0, 1, %noreg, 0
; CHECK: %rdi = VCVTTSS2SI64rr %xmm0 ; CHECK: %rdi = VCVTTSS2SI64rr %xmm0
%rdi = VCVTTSS2SI64Zrr %xmm0 %rdi = VCVTTSS2SI64Zrr %xmm0
; CHECK: %rdi = Int_VCVTTSS2SI64rr %xmm0 ; CHECK: %rdi = Int_VCVTTSS2SI64rr %xmm0
%rdi = VCVTTSS2SI64Zrr_Int %xmm0 %rdi = VCVTTSS2SI64Zrr_Int %xmm0
; CHECK: %edi = VCVTTSS2SIrm %rdi, %xmm0, 1, _, 0 ; CHECK: %edi = VCVTTSS2SIrm %rdi, %xmm0, 1, %noreg, 0
%edi = VCVTTSS2SIZrm %rdi, %xmm0, 1, _, 0 %edi = VCVTTSS2SIZrm %rdi, %xmm0, 1, %noreg, 0
; CHECK: %edi = Int_VCVTTSS2SIrm %rdi, %xmm0, 1, _, 0 ; CHECK: %edi = Int_VCVTTSS2SIrm %rdi, %xmm0, 1, %noreg, 0
%edi = VCVTTSS2SIZrm_Int %rdi, %xmm0, 1, _, 0 %edi = VCVTTSS2SIZrm_Int %rdi, %xmm0, 1, %noreg, 0
; CHECK: %edi = VCVTTSS2SIrr %xmm0 ; CHECK: %edi = VCVTTSS2SIrr %xmm0
%edi = VCVTTSS2SIZrr %xmm0 %edi = VCVTTSS2SIZrr %xmm0
; CHECK: %edi = Int_VCVTTSS2SIrr %xmm0 ; CHECK: %edi = Int_VCVTTSS2SIrr %xmm0
%edi = VCVTTSS2SIZrr_Int %xmm0 %edi = VCVTTSS2SIZrr_Int %xmm0
; CHECK: %xmm0 = VMOV64toSDrr %rdi ; CHECK: %xmm0 = VMOV64toSDrr %rdi
%xmm0 = VMOV64toSDZrr %rdi %xmm0 = VMOV64toSDZrr %rdi
; CHECK: %xmm0 = VMOVDI2SSrm %rip, _, _, _, _ ; CHECK: %xmm0 = VMOVDI2SSrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm0 = VMOVDI2SSZrm %rip, _, _, _, _ %xmm0 = VMOVDI2SSZrm %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VMOVDI2SSrr %eax ; CHECK: %xmm0 = VMOVDI2SSrr %eax
%xmm0 = VMOVDI2SSZrr %eax %xmm0 = VMOVDI2SSZrr %eax
; CHECK: VMOVSDmr %rdi, %xmm0, _, _, _, _ ; CHECK: VMOVSDmr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
VMOVSDZmr %rdi, %xmm0, _, _, _, _ VMOVSDZmr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VMOVSDrm %rip, _, _, _, _ ; CHECK: %xmm0 = VMOVSDrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm0 = VMOVSDZrm %rip, _, _, _, _ %xmm0 = VMOVSDZrm %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VMOVSDrr %xmm0, _ ; CHECK: %xmm0 = VMOVSDrr %xmm0, %noreg
%xmm0 = VMOVSDZrr %xmm0, _ %xmm0 = VMOVSDZrr %xmm0, %noreg
; CHECK: %xmm0 = VMOVSDrr_REV %xmm0, _ ; CHECK: %xmm0 = VMOVSDrr_REV %xmm0, %noreg
%xmm0 = VMOVSDZrr_REV %xmm0, _ %xmm0 = VMOVSDZrr_REV %xmm0, %noreg
; CHECK: %rax = VMOVSDto64rr %xmm0 ; CHECK: %rax = VMOVSDto64rr %xmm0
%rax = VMOVSDto64Zrr %xmm0 %rax = VMOVSDto64Zrr %xmm0
; CHECK: VMOVSDto64mr %rdi, %xmm0, _, _, _, _ ; CHECK: VMOVSDto64mr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
VMOVSDto64Zmr %rdi, %xmm0, _, _, _, _ VMOVSDto64Zmr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
; CHECK: VMOVSSmr %rdi, %xmm0, _, _, _, _ ; CHECK: VMOVSSmr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
VMOVSSZmr %rdi, %xmm0, _, _, _, _ VMOVSSZmr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VMOVSSrm %rip, _, _, _, _ ; CHECK: %xmm0 = VMOVSSrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm0 = VMOVSSZrm %rip, _, _, _, _ %xmm0 = VMOVSSZrm %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VMOVSSrr %xmm0, _ ; CHECK: %xmm0 = VMOVSSrr %xmm0, %noreg
%xmm0 = VMOVSSZrr %xmm0, _ %xmm0 = VMOVSSZrr %xmm0, %noreg
; CHECK: %xmm0 = VMOVSSrr_REV %xmm0, _ ; CHECK: %xmm0 = VMOVSSrr_REV %xmm0, %noreg
%xmm0 = VMOVSSZrr_REV %xmm0, _ %xmm0 = VMOVSSZrr_REV %xmm0, %noreg
; CHECK: VMOVSS2DImr %rdi, %xmm0, _, _, _, _ ; CHECK: VMOVSS2DImr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
VMOVSS2DIZmr %rdi, %xmm0, _, _, _, _ VMOVSS2DIZmr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
; CHECK: %eax = VMOVSS2DIrr %xmm0 ; CHECK: %eax = VMOVSS2DIrr %xmm0
%eax = VMOVSS2DIZrr %xmm0 %eax = VMOVSS2DIZrr %xmm0
; CHECK: %xmm0 = VMOV64toPQIrr %rdi ; CHECK: %xmm0 = VMOV64toPQIrr %rdi
%xmm0 = VMOV64toPQIZrr %rdi %xmm0 = VMOV64toPQIZrr %rdi
; CHECK: %xmm0 = VMOV64toPQIrm %rdi, _, _, _, _ ; CHECK: %xmm0 = VMOV64toPQIrm %rdi, %noreg, %noreg, %noreg, %noreg
%xmm0 = VMOV64toPQIZrm %rdi, _, _, _, _ %xmm0 = VMOV64toPQIZrm %rdi, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VMOV64toSDrr %rdi ; CHECK: %xmm0 = VMOV64toSDrr %rdi
%xmm0 = VMOV64toSDZrr %rdi %xmm0 = VMOV64toSDZrr %rdi
; CHECK: %xmm0 = VMOVDI2PDIrm %rip, _, _, _, _ ; CHECK: %xmm0 = VMOVDI2PDIrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm0 = VMOVDI2PDIZrm %rip, _, _, _, _ %xmm0 = VMOVDI2PDIZrm %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VMOVDI2PDIrr %edi ; CHECK: %xmm0 = VMOVDI2PDIrr %edi
%xmm0 = VMOVDI2PDIZrr %edi %xmm0 = VMOVDI2PDIZrr %edi
; CHECK: %xmm0 = VMOVLHPSrr %xmm0, _ ; CHECK: %xmm0 = VMOVLHPSrr %xmm0, %noreg
%xmm0 = VMOVLHPSZrr %xmm0, _ %xmm0 = VMOVLHPSZrr %xmm0, %noreg
; CHECK: %xmm0 = VMOVHLPSrr %xmm0, _ ; CHECK: %xmm0 = VMOVHLPSrr %xmm0, %noreg
%xmm0 = VMOVHLPSZrr %xmm0, _ %xmm0 = VMOVHLPSZrr %xmm0, %noreg
; CHECK: VMOVPDI2DImr %rdi, %xmm0, _, _, _, _ ; CHECK: VMOVPDI2DImr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
VMOVPDI2DIZmr %rdi, %xmm0, _, _, _, _ VMOVPDI2DIZmr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
; CHECK: %edi = VMOVPDI2DIrr %xmm0 ; CHECK: %edi = VMOVPDI2DIrr %xmm0
%edi = VMOVPDI2DIZrr %xmm0 %edi = VMOVPDI2DIZrr %xmm0
; CHECK: %xmm0 = VMOVPQI2QIrr %xmm0 ; CHECK: %xmm0 = VMOVPQI2QIrr %xmm0
%xmm0 = VMOVPQI2QIZrr %xmm0 %xmm0 = VMOVPQI2QIZrr %xmm0
; CHECK: VMOVPQI2QImr %rdi, %xmm0, _, _, _, _ ; CHECK: VMOVPQI2QImr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
VMOVPQI2QIZmr %rdi, %xmm0, _, _, _, _ VMOVPQI2QIZmr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
; CHECK: %rdi = VMOVPQIto64rr %xmm0 ; CHECK: %rdi = VMOVPQIto64rr %xmm0
%rdi = VMOVPQIto64Zrr %xmm0 %rdi = VMOVPQIto64Zrr %xmm0
; CHECK: VMOVPQIto64mr %rdi, %xmm0, _, _, _, _ ; CHECK: VMOVPQIto64mr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
VMOVPQIto64Zmr %rdi, %xmm0, _, _, _, _ VMOVPQIto64Zmr %rdi, %xmm0, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VMOVQI2PQIrm %rip, _, _, _, _ ; CHECK: %xmm0 = VMOVQI2PQIrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm0 = VMOVQI2PQIZrm %rip, _, _, _, _ %xmm0 = VMOVQI2PQIZrm %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VMOVZPQILo2PQIrr %xmm0 ; CHECK: %xmm0 = VMOVZPQILo2PQIrr %xmm0
%xmm0 = VMOVZPQILo2PQIZrr %xmm0 %xmm0 = VMOVZPQILo2PQIZrr %xmm0
; CHECK: Int_VCOMISDrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: Int_VCOMISDrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
Int_VCOMISDZrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags Int_VCOMISDZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: Int_VCOMISDrr %xmm0, %xmm1, implicit-def %eflags ; CHECK: Int_VCOMISDrr %xmm0, %xmm1, implicit-def %eflags
Int_VCOMISDZrr %xmm0, %xmm1, implicit-def %eflags Int_VCOMISDZrr %xmm0, %xmm1, implicit-def %eflags
; CHECK: Int_VCOMISSrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: Int_VCOMISSrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
Int_VCOMISSZrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags Int_VCOMISSZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: Int_VCOMISSrr %xmm0, %xmm1, implicit-def %eflags ; CHECK: Int_VCOMISSrr %xmm0, %xmm1, implicit-def %eflags
Int_VCOMISSZrr %xmm0, %xmm1, implicit-def %eflags Int_VCOMISSZrr %xmm0, %xmm1, implicit-def %eflags
; CHECK: Int_VUCOMISDrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: Int_VUCOMISDrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
Int_VUCOMISDZrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags Int_VUCOMISDZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: Int_VUCOMISDrr %xmm0, %xmm1, implicit-def %eflags ; CHECK: Int_VUCOMISDrr %xmm0, %xmm1, implicit-def %eflags
Int_VUCOMISDZrr %xmm0, %xmm1, implicit-def %eflags Int_VUCOMISDZrr %xmm0, %xmm1, implicit-def %eflags
; CHECK: Int_VUCOMISSrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: Int_VUCOMISSrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
Int_VUCOMISSZrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags Int_VUCOMISSZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: Int_VUCOMISSrr %xmm0, %xmm1, implicit-def %eflags ; CHECK: Int_VUCOMISSrr %xmm0, %xmm1, implicit-def %eflags
Int_VUCOMISSZrr %xmm0, %xmm1, implicit-def %eflags Int_VUCOMISSZrr %xmm0, %xmm1, implicit-def %eflags
; CHECK: VCOMISDrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: VCOMISDrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
VCOMISDZrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags VCOMISDZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: VCOMISDrr %xmm0, %xmm1, implicit-def %eflags ; CHECK: VCOMISDrr %xmm0, %xmm1, implicit-def %eflags
VCOMISDZrr %xmm0, %xmm1, implicit-def %eflags VCOMISDZrr %xmm0, %xmm1, implicit-def %eflags
; CHECK: VCOMISSrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: VCOMISSrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
VCOMISSZrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags VCOMISSZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: VCOMISSrr %xmm0, %xmm1, implicit-def %eflags ; CHECK: VCOMISSrr %xmm0, %xmm1, implicit-def %eflags
VCOMISSZrr %xmm0, %xmm1, implicit-def %eflags VCOMISSZrr %xmm0, %xmm1, implicit-def %eflags
; CHECK: VUCOMISDrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: VUCOMISDrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
VUCOMISDZrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags VUCOMISDZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: VUCOMISDrr %xmm0, %xmm1, implicit-def %eflags ; CHECK: VUCOMISDrr %xmm0, %xmm1, implicit-def %eflags
VUCOMISDZrr %xmm0, %xmm1, implicit-def %eflags VUCOMISDZrr %xmm0, %xmm1, implicit-def %eflags
; CHECK: VUCOMISSrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: VUCOMISSrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
VUCOMISSZrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags VUCOMISSZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: VUCOMISSrr %xmm0, %xmm1, implicit-def %eflags ; CHECK: VUCOMISSrr %xmm0, %xmm1, implicit-def %eflags
VUCOMISSZrr %xmm0, %xmm1, implicit-def %eflags VUCOMISSZrr %xmm0, %xmm1, implicit-def %eflags
; CHECK: VEXTRACTPSmr %rdi, 1, _, 0, _, %xmm0, _ ; CHECK: VEXTRACTPSmr %rdi, 1, %noreg, 0, %noreg, %xmm0, %noreg
VEXTRACTPSZmr %rdi, 1, _, 0, _, %xmm0, _ VEXTRACTPSZmr %rdi, 1, %noreg, 0, %noreg, %xmm0, %noreg
; CHECK: %eax = VEXTRACTPSrr %xmm0, _ ; CHECK: %eax = VEXTRACTPSrr %xmm0, %noreg
%eax = VEXTRACTPSZrr %xmm0, _ %eax = VEXTRACTPSZrr %xmm0, %noreg
; CHECK: %xmm0 = VINSERTPSrm %xmm0, %rdi, _, _, _, _, _ ; CHECK: %xmm0 = VINSERTPSrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm0 = VINSERTPSZrm %xmm0, %rdi, _, _, _, _, _ %xmm0 = VINSERTPSZrm %xmm0, %rdi, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm0 = VINSERTPSrr %xmm0, %xmm0, _ ; CHECK: %xmm0 = VINSERTPSrr %xmm0, %xmm0, %noreg
%xmm0 = VINSERTPSZrr %xmm0, %xmm0, _ %xmm0 = VINSERTPSZrr %xmm0, %xmm0, %noreg
RET 0, %zmm0, %zmm1 RET 0, %zmm0, %zmm1
... ...
--- ---
# CHECK-LABEL: name: evex_z256_to_evex_test # CHECK-LABEL: name: evex_z256_to_evex_test
# CHECK: bb.0: # CHECK: bb.0:
name: evex_z256_to_evex_test name: evex_z256_to_evex_test
body: | body: |
bb.0: bb.0:
; CHECK: VMOVAPDZ256mr %rdi, 1, _, 0, _, %ymm16 ; CHECK: VMOVAPDZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
VMOVAPDZ256mr %rdi, 1, _, 0, _, %ymm16 VMOVAPDZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
; CHECK: %ymm16 = VMOVAPDZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMOVAPDZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMOVAPDZ256rm %rip, 1, _, %rax, _ %ymm16 = VMOVAPDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMOVAPDZ256rr %ymm16 ; CHECK: %ymm16 = VMOVAPDZ256rr %ymm16
%ymm16 = VMOVAPDZ256rr %ymm16 %ymm16 = VMOVAPDZ256rr %ymm16
; CHECK: %ymm16 = VMOVAPDZ256rr_REV %ymm16 ; CHECK: %ymm16 = VMOVAPDZ256rr_REV %ymm16
%ymm16 = VMOVAPDZ256rr_REV %ymm16 %ymm16 = VMOVAPDZ256rr_REV %ymm16
; CHECK: VMOVAPSZ256mr %rdi, 1, _, 0, _, %ymm16 ; CHECK: VMOVAPSZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
VMOVAPSZ256mr %rdi, 1, _, 0, _, %ymm16 VMOVAPSZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
; CHECK: %ymm16 = VMOVAPSZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMOVAPSZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMOVAPSZ256rm %rip, 1, _, %rax, _ %ymm16 = VMOVAPSZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMOVAPSZ256rr %ymm16 ; CHECK: %ymm16 = VMOVAPSZ256rr %ymm16
%ymm16 = VMOVAPSZ256rr %ymm16 %ymm16 = VMOVAPSZ256rr %ymm16
; CHECK: %ymm16 = VMOVAPSZ256rr_REV %ymm16 ; CHECK: %ymm16 = VMOVAPSZ256rr_REV %ymm16
%ymm16 = VMOVAPSZ256rr_REV %ymm16 %ymm16 = VMOVAPSZ256rr_REV %ymm16
; CHECK: %ymm16 = VMOVDDUPZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMOVDDUPZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMOVDDUPZ256rm %rip, 1, _, %rax, _ %ymm16 = VMOVDDUPZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMOVDDUPZ256rr %ymm16 ; CHECK: %ymm16 = VMOVDDUPZ256rr %ymm16
%ymm16 = VMOVDDUPZ256rr %ymm16 %ymm16 = VMOVDDUPZ256rr %ymm16
; CHECK: VMOVDQA32Z256mr %rdi, 1, _, 0, _, %ymm16 ; CHECK: VMOVDQA32Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
VMOVDQA32Z256mr %rdi, 1, _, 0, _, %ymm16 VMOVDQA32Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
; CHECK: %ymm16 = VMOVDQA32Z256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMOVDQA32Z256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMOVDQA32Z256rm %rip, 1, _, %rax, _ %ymm16 = VMOVDQA32Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMOVDQA32Z256rr %ymm16 ; CHECK: %ymm16 = VMOVDQA32Z256rr %ymm16
%ymm16 = VMOVDQA32Z256rr %ymm16 %ymm16 = VMOVDQA32Z256rr %ymm16
; CHECK: %ymm16 = VMOVDQA32Z256rr_REV %ymm16 ; CHECK: %ymm16 = VMOVDQA32Z256rr_REV %ymm16
%ymm16 = VMOVDQA32Z256rr_REV %ymm16 %ymm16 = VMOVDQA32Z256rr_REV %ymm16
; CHECK: VMOVDQA64Z256mr %rdi, 1, _, 0, _, %ymm16 ; CHECK: VMOVDQA64Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
VMOVDQA64Z256mr %rdi, 1, _, 0, _, %ymm16 VMOVDQA64Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
; CHECK: %ymm16 = VMOVDQA64Z256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMOVDQA64Z256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMOVDQA64Z256rm %rip, 1, _, %rax, _ %ymm16 = VMOVDQA64Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMOVDQA64Z256rr %ymm16 ; CHECK: %ymm16 = VMOVDQA64Z256rr %ymm16
%ymm16 = VMOVDQA64Z256rr %ymm16 %ymm16 = VMOVDQA64Z256rr %ymm16
; CHECK: %ymm16 = VMOVDQA64Z256rr_REV %ymm16 ; CHECK: %ymm16 = VMOVDQA64Z256rr_REV %ymm16
%ymm16 = VMOVDQA64Z256rr_REV %ymm16 %ymm16 = VMOVDQA64Z256rr_REV %ymm16
; CHECK: VMOVDQU16Z256mr %rdi, 1, _, 0, _, %ymm16 ; CHECK: VMOVDQU16Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
VMOVDQU16Z256mr %rdi, 1, _, 0, _, %ymm16 VMOVDQU16Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
; CHECK: %ymm16 = VMOVDQU16Z256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMOVDQU16Z256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMOVDQU16Z256rm %rip, 1, _, %rax, _ %ymm16 = VMOVDQU16Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMOVDQU16Z256rr %ymm16 ; CHECK: %ymm16 = VMOVDQU16Z256rr %ymm16
%ymm16 = VMOVDQU16Z256rr %ymm16 %ymm16 = VMOVDQU16Z256rr %ymm16
; CHECK: %ymm16 = VMOVDQU16Z256rr_REV %ymm16 ; CHECK: %ymm16 = VMOVDQU16Z256rr_REV %ymm16
%ymm16 = VMOVDQU16Z256rr_REV %ymm16 %ymm16 = VMOVDQU16Z256rr_REV %ymm16
; CHECK: VMOVDQU32Z256mr %rdi, 1, _, 0, _, %ymm16 ; CHECK: VMOVDQU32Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
VMOVDQU32Z256mr %rdi, 1, _, 0, _, %ymm16 VMOVDQU32Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
; CHECK: %ymm16 = VMOVDQU32Z256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMOVDQU32Z256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMOVDQU32Z256rm %rip, 1, _, %rax, _ %ymm16 = VMOVDQU32Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMOVDQU32Z256rr %ymm16 ; CHECK: %ymm16 = VMOVDQU32Z256rr %ymm16
%ymm16 = VMOVDQU32Z256rr %ymm16 %ymm16 = VMOVDQU32Z256rr %ymm16
; CHECK: %ymm16 = VMOVDQU32Z256rr_REV %ymm16 ; CHECK: %ymm16 = VMOVDQU32Z256rr_REV %ymm16
%ymm16 = VMOVDQU32Z256rr_REV %ymm16 %ymm16 = VMOVDQU32Z256rr_REV %ymm16
; CHECK: VMOVDQU64Z256mr %rdi, 1, _, 0, _, %ymm16 ; CHECK: VMOVDQU64Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
VMOVDQU64Z256mr %rdi, 1, _, 0, _, %ymm16 VMOVDQU64Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
; CHECK: %ymm16 = VMOVDQU64Z256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMOVDQU64Z256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMOVDQU64Z256rm %rip, 1, _, %rax, _ %ymm16 = VMOVDQU64Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMOVDQU64Z256rr %ymm16 ; CHECK: %ymm16 = VMOVDQU64Z256rr %ymm16
%ymm16 = VMOVDQU64Z256rr %ymm16 %ymm16 = VMOVDQU64Z256rr %ymm16
; CHECK: %ymm16 = VMOVDQU64Z256rr_REV %ymm16 ; CHECK: %ymm16 = VMOVDQU64Z256rr_REV %ymm16
%ymm16 = VMOVDQU64Z256rr_REV %ymm16 %ymm16 = VMOVDQU64Z256rr_REV %ymm16
; CHECK: VMOVDQU8Z256mr %rdi, 1, _, 0, _, %ymm16 ; CHECK: VMOVDQU8Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
VMOVDQU8Z256mr %rdi, 1, _, 0, _, %ymm16 VMOVDQU8Z256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
; CHECK: %ymm16 = VMOVDQU8Z256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMOVDQU8Z256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMOVDQU8Z256rm %rip, 1, _, %rax, _ %ymm16 = VMOVDQU8Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMOVDQU8Z256rr %ymm16 ; CHECK: %ymm16 = VMOVDQU8Z256rr %ymm16
%ymm16 = VMOVDQU8Z256rr %ymm16 %ymm16 = VMOVDQU8Z256rr %ymm16
; CHECK: %ymm16 = VMOVDQU8Z256rr_REV %ymm16 ; CHECK: %ymm16 = VMOVDQU8Z256rr_REV %ymm16
%ymm16 = VMOVDQU8Z256rr_REV %ymm16 %ymm16 = VMOVDQU8Z256rr_REV %ymm16
; CHECK: %ymm16 = VMOVNTDQAZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMOVNTDQAZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMOVNTDQAZ256rm %rip, 1, _, %rax, _ %ymm16 = VMOVNTDQAZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: VMOVNTDQZ256mr %rdi, 1, _, 0, _, %ymm16 ; CHECK: VMOVNTDQZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
VMOVNTDQZ256mr %rdi, 1, _, 0, _, %ymm16 VMOVNTDQZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
; CHECK: VMOVNTPDZ256mr %rdi, 1, _, 0, _, %ymm16 ; CHECK: VMOVNTPDZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
VMOVNTPDZ256mr %rdi, 1, _, 0, _, %ymm16 VMOVNTPDZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
; CHECK: VMOVNTPSZ256mr %rdi, 1, _, 0, _, %ymm16 ; CHECK: VMOVNTPSZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
VMOVNTPSZ256mr %rdi, 1, _, 0, _, %ymm16 VMOVNTPSZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
; CHECK: %ymm16 = VMOVSHDUPZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMOVSHDUPZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMOVSHDUPZ256rm %rip, 1, _, %rax, _ %ymm16 = VMOVSHDUPZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMOVSHDUPZ256rr %ymm16 ; CHECK: %ymm16 = VMOVSHDUPZ256rr %ymm16
%ymm16 = VMOVSHDUPZ256rr %ymm16 %ymm16 = VMOVSHDUPZ256rr %ymm16
; CHECK: %ymm16 = VMOVSLDUPZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMOVSLDUPZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMOVSLDUPZ256rm %rip, 1, _, %rax, _ %ymm16 = VMOVSLDUPZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMOVSLDUPZ256rr %ymm16 ; CHECK: %ymm16 = VMOVSLDUPZ256rr %ymm16
%ymm16 = VMOVSLDUPZ256rr %ymm16 %ymm16 = VMOVSLDUPZ256rr %ymm16
; CHECK: VMOVUPDZ256mr %rdi, 1, _, 0, _, %ymm16 ; CHECK: VMOVUPDZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
VMOVUPDZ256mr %rdi, 1, _, 0, _, %ymm16 VMOVUPDZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
; CHECK: %ymm16 = VMOVUPDZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMOVUPDZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMOVUPDZ256rm %rip, 1, _, %rax, _ %ymm16 = VMOVUPDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMOVUPDZ256rr %ymm16 ; CHECK: %ymm16 = VMOVUPDZ256rr %ymm16
%ymm16 = VMOVUPDZ256rr %ymm16 %ymm16 = VMOVUPDZ256rr %ymm16
; CHECK: %ymm16 = VMOVUPDZ256rr_REV %ymm16 ; CHECK: %ymm16 = VMOVUPDZ256rr_REV %ymm16
%ymm16 = VMOVUPDZ256rr_REV %ymm16 %ymm16 = VMOVUPDZ256rr_REV %ymm16
; CHECK: VMOVUPSZ256mr %rdi, 1, _, 0, _, %ymm16 ; CHECK: VMOVUPSZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
VMOVUPSZ256mr %rdi, 1, _, 0, _, %ymm16 VMOVUPSZ256mr %rdi, 1, %noreg, 0, %noreg, %ymm16
; CHECK: %ymm16 = VPANDDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPANDDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPANDDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPANDDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPANDDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPANDDZ256rr %ymm16, %ymm1
%ymm16 = VPANDDZ256rr %ymm16, %ymm1 %ymm16 = VPANDDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPANDQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPANDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPANDQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPANDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPANDQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPANDQZ256rr %ymm16, %ymm1
%ymm16 = VPANDQZ256rr %ymm16, %ymm1 %ymm16 = VPANDQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPANDNDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPANDNDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPANDNDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPANDNDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPANDNDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPANDNDZ256rr %ymm16, %ymm1
%ymm16 = VPANDNDZ256rr %ymm16, %ymm1 %ymm16 = VPANDNDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPANDNQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPANDNQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPANDNQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPANDNQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPANDNQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPANDNQZ256rr %ymm16, %ymm1
%ymm16 = VPANDNQZ256rr %ymm16, %ymm1 %ymm16 = VPANDNQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPAVGBZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPAVGBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPAVGBZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPAVGBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPAVGBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPAVGBZ256rr %ymm16, %ymm1
%ymm16 = VPAVGBZ256rr %ymm16, %ymm1 %ymm16 = VPAVGBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPAVGWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPAVGWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPAVGWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPAVGWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPAVGWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPAVGWZ256rr %ymm16, %ymm1
%ymm16 = VPAVGWZ256rr %ymm16, %ymm1 %ymm16 = VPAVGWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPADDBZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPADDBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPADDBZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPADDBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPADDBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPADDBZ256rr %ymm16, %ymm1
%ymm16 = VPADDBZ256rr %ymm16, %ymm1 %ymm16 = VPADDBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPADDDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPADDDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPADDDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPADDDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPADDDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPADDDZ256rr %ymm16, %ymm1
%ymm16 = VPADDDZ256rr %ymm16, %ymm1 %ymm16 = VPADDDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPADDQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPADDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPADDQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPADDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPADDQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPADDQZ256rr %ymm16, %ymm1
%ymm16 = VPADDQZ256rr %ymm16, %ymm1 %ymm16 = VPADDQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPADDSBZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPADDSBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPADDSBZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPADDSBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPADDSBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPADDSBZ256rr %ymm16, %ymm1
%ymm16 = VPADDSBZ256rr %ymm16, %ymm1 %ymm16 = VPADDSBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPADDSWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPADDSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPADDSWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPADDSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPADDSWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPADDSWZ256rr %ymm16, %ymm1
%ymm16 = VPADDSWZ256rr %ymm16, %ymm1 %ymm16 = VPADDSWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPADDUSBZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPADDUSBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPADDUSBZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPADDUSBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPADDUSBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPADDUSBZ256rr %ymm16, %ymm1
%ymm16 = VPADDUSBZ256rr %ymm16, %ymm1 %ymm16 = VPADDUSBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPADDUSWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPADDUSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPADDUSWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPADDUSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPADDUSWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPADDUSWZ256rr %ymm16, %ymm1
%ymm16 = VPADDUSWZ256rr %ymm16, %ymm1 %ymm16 = VPADDUSWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPADDWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPADDWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPADDWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPADDWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPADDWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPADDWZ256rr %ymm16, %ymm1
%ymm16 = VPADDWZ256rr %ymm16, %ymm1 %ymm16 = VPADDWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VMULPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMULPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMULPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VMULPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMULPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VMULPDZ256rr %ymm16, %ymm1
%ymm16 = VMULPDZ256rr %ymm16, %ymm1 %ymm16 = VMULPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VMULPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMULPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMULPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VMULPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMULPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VMULPSZ256rr %ymm16, %ymm1
%ymm16 = VMULPSZ256rr %ymm16, %ymm1 %ymm16 = VMULPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VORPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VORPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VORPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VORPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VORPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VORPDZ256rr %ymm16, %ymm1
%ymm16 = VORPDZ256rr %ymm16, %ymm1 %ymm16 = VORPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VORPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VORPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VORPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VORPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VORPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VORPSZ256rr %ymm16, %ymm1
%ymm16 = VORPSZ256rr %ymm16, %ymm1 %ymm16 = VORPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMADDUBSWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMADDUBSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMADDUBSWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMADDUBSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMADDUBSWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMADDUBSWZ256rr %ymm16, %ymm1
%ymm16 = VPMADDUBSWZ256rr %ymm16, %ymm1 %ymm16 = VPMADDUBSWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMADDWDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMADDWDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMADDWDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMADDWDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMADDWDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMADDWDZ256rr %ymm16, %ymm1
%ymm16 = VPMADDWDZ256rr %ymm16, %ymm1 %ymm16 = VPMADDWDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMAXSBZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMAXSBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMAXSBZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMAXSBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMAXSBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMAXSBZ256rr %ymm16, %ymm1
%ymm16 = VPMAXSBZ256rr %ymm16, %ymm1 %ymm16 = VPMAXSBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMAXSDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMAXSDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMAXSDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMAXSDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMAXSDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMAXSDZ256rr %ymm16, %ymm1
%ymm16 = VPMAXSDZ256rr %ymm16, %ymm1 %ymm16 = VPMAXSDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMAXSWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMAXSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMAXSWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMAXSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMAXSWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMAXSWZ256rr %ymm16, %ymm1
%ymm16 = VPMAXSWZ256rr %ymm16, %ymm1 %ymm16 = VPMAXSWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMAXUBZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMAXUBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMAXUBZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMAXUBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMAXUBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMAXUBZ256rr %ymm16, %ymm1
%ymm16 = VPMAXUBZ256rr %ymm16, %ymm1 %ymm16 = VPMAXUBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMAXUDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMAXUDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMAXUDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMAXUDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMAXUDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMAXUDZ256rr %ymm16, %ymm1
%ymm16 = VPMAXUDZ256rr %ymm16, %ymm1 %ymm16 = VPMAXUDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMAXUWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMAXUWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMAXUWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMAXUWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMAXUWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMAXUWZ256rr %ymm16, %ymm1
%ymm16 = VPMAXUWZ256rr %ymm16, %ymm1 %ymm16 = VPMAXUWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMINSBZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMINSBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMINSBZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMINSBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMINSBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMINSBZ256rr %ymm16, %ymm1
%ymm16 = VPMINSBZ256rr %ymm16, %ymm1 %ymm16 = VPMINSBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMINSDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMINSDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMINSDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMINSDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMINSDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMINSDZ256rr %ymm16, %ymm1
%ymm16 = VPMINSDZ256rr %ymm16, %ymm1 %ymm16 = VPMINSDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMINSWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMINSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMINSWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMINSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMINSWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMINSWZ256rr %ymm16, %ymm1
%ymm16 = VPMINSWZ256rr %ymm16, %ymm1 %ymm16 = VPMINSWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMINUBZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMINUBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMINUBZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMINUBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMINUBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMINUBZ256rr %ymm16, %ymm1
%ymm16 = VPMINUBZ256rr %ymm16, %ymm1 %ymm16 = VPMINUBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMINUDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMINUDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMINUDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMINUDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMINUDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMINUDZ256rr %ymm16, %ymm1
%ymm16 = VPMINUDZ256rr %ymm16, %ymm1 %ymm16 = VPMINUDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMINUWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMINUWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMINUWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMINUWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMINUWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMINUWZ256rr %ymm16, %ymm1
%ymm16 = VPMINUWZ256rr %ymm16, %ymm1 %ymm16 = VPMINUWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMULDQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMULDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMULDQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMULDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMULDQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMULDQZ256rr %ymm16, %ymm1
%ymm16 = VPMULDQZ256rr %ymm16, %ymm1 %ymm16 = VPMULDQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMULHRSWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMULHRSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMULHRSWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMULHRSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMULHRSWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMULHRSWZ256rr %ymm16, %ymm1
%ymm16 = VPMULHRSWZ256rr %ymm16, %ymm1 %ymm16 = VPMULHRSWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMULHUWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMULHUWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMULHUWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMULHUWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMULHUWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMULHUWZ256rr %ymm16, %ymm1
%ymm16 = VPMULHUWZ256rr %ymm16, %ymm1 %ymm16 = VPMULHUWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMULHWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMULHWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMULHWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMULHWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMULHWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMULHWZ256rr %ymm16, %ymm1
%ymm16 = VPMULHWZ256rr %ymm16, %ymm1 %ymm16 = VPMULHWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMULLDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMULLDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMULLDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMULLDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMULLDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMULLDZ256rr %ymm16, %ymm1
%ymm16 = VPMULLDZ256rr %ymm16, %ymm1 %ymm16 = VPMULLDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMULLWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMULLWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMULLWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMULLWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMULLWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMULLWZ256rr %ymm16, %ymm1
%ymm16 = VPMULLWZ256rr %ymm16, %ymm1 %ymm16 = VPMULLWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPMULUDQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMULUDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMULUDQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPMULUDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMULUDQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPMULUDQZ256rr %ymm16, %ymm1
%ymm16 = VPMULUDQZ256rr %ymm16, %ymm1 %ymm16 = VPMULUDQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPORDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPORDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPORDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPORDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPORDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPORDZ256rr %ymm16, %ymm1
%ymm16 = VPORDZ256rr %ymm16, %ymm1 %ymm16 = VPORDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPORQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPORQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPORQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPORQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPORQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPORQZ256rr %ymm16, %ymm1
%ymm16 = VPORQZ256rr %ymm16, %ymm1 %ymm16 = VPORQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPSUBBZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSUBBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSUBBZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSUBBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSUBBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSUBBZ256rr %ymm16, %ymm1
%ymm16 = VPSUBBZ256rr %ymm16, %ymm1 %ymm16 = VPSUBBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPSUBDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSUBDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSUBDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSUBDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSUBDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSUBDZ256rr %ymm16, %ymm1
%ymm16 = VPSUBDZ256rr %ymm16, %ymm1 %ymm16 = VPSUBDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPSUBQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSUBQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSUBQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSUBQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSUBQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSUBQZ256rr %ymm16, %ymm1
%ymm16 = VPSUBQZ256rr %ymm16, %ymm1 %ymm16 = VPSUBQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPSUBSBZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSUBSBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSUBSBZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSUBSBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSUBSBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSUBSBZ256rr %ymm16, %ymm1
%ymm16 = VPSUBSBZ256rr %ymm16, %ymm1 %ymm16 = VPSUBSBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPSUBSWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSUBSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSUBSWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSUBSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSUBSWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSUBSWZ256rr %ymm16, %ymm1
%ymm16 = VPSUBSWZ256rr %ymm16, %ymm1 %ymm16 = VPSUBSWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPSUBUSBZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSUBUSBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSUBUSBZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSUBUSBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSUBUSBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSUBUSBZ256rr %ymm16, %ymm1
%ymm16 = VPSUBUSBZ256rr %ymm16, %ymm1 %ymm16 = VPSUBUSBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPSUBUSWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSUBUSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSUBUSWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSUBUSWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSUBUSWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSUBUSWZ256rr %ymm16, %ymm1
%ymm16 = VPSUBUSWZ256rr %ymm16, %ymm1 %ymm16 = VPSUBUSWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPSUBWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSUBWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSUBWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSUBWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSUBWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSUBWZ256rr %ymm16, %ymm1
%ymm16 = VPSUBWZ256rr %ymm16, %ymm1 %ymm16 = VPSUBWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPXORDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPXORDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPXORDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPXORDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPXORDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPXORDZ256rr %ymm16, %ymm1
%ymm16 = VPXORDZ256rr %ymm16, %ymm1 %ymm16 = VPXORDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPXORQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPXORQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPXORQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPXORQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPXORQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPXORQZ256rr %ymm16, %ymm1
%ymm16 = VPXORQZ256rr %ymm16, %ymm1 %ymm16 = VPXORQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VADDPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VADDPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VADDPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VADDPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VADDPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VADDPDZ256rr %ymm16, %ymm1
%ymm16 = VADDPDZ256rr %ymm16, %ymm1 %ymm16 = VADDPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VADDPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VADDPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VADDPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VADDPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VADDPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VADDPSZ256rr %ymm16, %ymm1
%ymm16 = VADDPSZ256rr %ymm16, %ymm1 %ymm16 = VADDPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VANDNPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VANDNPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VANDNPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VANDNPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VANDNPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VANDNPDZ256rr %ymm16, %ymm1
%ymm16 = VANDNPDZ256rr %ymm16, %ymm1 %ymm16 = VANDNPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VANDNPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VANDNPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VANDNPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VANDNPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VANDNPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VANDNPSZ256rr %ymm16, %ymm1
%ymm16 = VANDNPSZ256rr %ymm16, %ymm1 %ymm16 = VANDNPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VANDPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VANDPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VANDPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VANDPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VANDPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VANDPDZ256rr %ymm16, %ymm1
%ymm16 = VANDPDZ256rr %ymm16, %ymm1 %ymm16 = VANDPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VANDPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VANDPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VANDPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VANDPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VANDPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VANDPSZ256rr %ymm16, %ymm1
%ymm16 = VANDPSZ256rr %ymm16, %ymm1 %ymm16 = VANDPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VDIVPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VDIVPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VDIVPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VDIVPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VDIVPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VDIVPDZ256rr %ymm16, %ymm1
%ymm16 = VDIVPDZ256rr %ymm16, %ymm1 %ymm16 = VDIVPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VDIVPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VDIVPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VDIVPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VDIVPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VDIVPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VDIVPSZ256rr %ymm16, %ymm1
%ymm16 = VDIVPSZ256rr %ymm16, %ymm1 %ymm16 = VDIVPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VMAXCPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMAXCPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMAXCPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VMAXCPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMAXCPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VMAXCPDZ256rr %ymm16, %ymm1
%ymm16 = VMAXCPDZ256rr %ymm16, %ymm1 %ymm16 = VMAXCPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VMAXCPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMAXCPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMAXCPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VMAXCPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMAXCPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VMAXCPSZ256rr %ymm16, %ymm1
%ymm16 = VMAXCPSZ256rr %ymm16, %ymm1 %ymm16 = VMAXCPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VMAXPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMAXPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMAXPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VMAXPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMAXPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VMAXPDZ256rr %ymm16, %ymm1
%ymm16 = VMAXPDZ256rr %ymm16, %ymm1 %ymm16 = VMAXPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VMAXPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMAXPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMAXPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VMAXPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMAXPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VMAXPSZ256rr %ymm16, %ymm1
%ymm16 = VMAXPSZ256rr %ymm16, %ymm1 %ymm16 = VMAXPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VMINCPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMINCPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMINCPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VMINCPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMINCPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VMINCPDZ256rr %ymm16, %ymm1
%ymm16 = VMINCPDZ256rr %ymm16, %ymm1 %ymm16 = VMINCPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VMINCPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMINCPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMINCPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VMINCPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMINCPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VMINCPSZ256rr %ymm16, %ymm1
%ymm16 = VMINCPSZ256rr %ymm16, %ymm1 %ymm16 = VMINCPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VMINPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMINPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMINPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VMINPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMINPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VMINPDZ256rr %ymm16, %ymm1
%ymm16 = VMINPDZ256rr %ymm16, %ymm1 %ymm16 = VMINPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VMINPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VMINPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VMINPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VMINPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VMINPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VMINPSZ256rr %ymm16, %ymm1
%ymm16 = VMINPSZ256rr %ymm16, %ymm1 %ymm16 = VMINPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VXORPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VXORPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VXORPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VXORPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VXORPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VXORPDZ256rr %ymm16, %ymm1
%ymm16 = VXORPDZ256rr %ymm16, %ymm1 %ymm16 = VXORPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VXORPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VXORPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VXORPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VXORPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VXORPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VXORPSZ256rr %ymm16, %ymm1
%ymm16 = VXORPSZ256rr %ymm16, %ymm1 %ymm16 = VXORPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPACKSSDWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPACKSSDWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPACKSSDWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPACKSSDWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPACKSSDWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPACKSSDWZ256rr %ymm16, %ymm1
%ymm16 = VPACKSSDWZ256rr %ymm16, %ymm1 %ymm16 = VPACKSSDWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPACKSSWBZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPACKSSWBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPACKSSWBZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPACKSSWBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPACKSSWBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPACKSSWBZ256rr %ymm16, %ymm1
%ymm16 = VPACKSSWBZ256rr %ymm16, %ymm1 %ymm16 = VPACKSSWBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPACKUSDWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPACKUSDWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPACKUSDWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPACKUSDWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPACKUSDWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPACKUSDWZ256rr %ymm16, %ymm1
%ymm16 = VPACKUSDWZ256rr %ymm16, %ymm1 %ymm16 = VPACKUSDWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPACKUSWBZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPACKUSWBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPACKUSWBZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPACKUSWBZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPACKUSWBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPACKUSWBZ256rr %ymm16, %ymm1
%ymm16 = VPACKUSWBZ256rr %ymm16, %ymm1 %ymm16 = VPACKUSWBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VUNPCKHPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VUNPCKHPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VUNPCKHPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VUNPCKHPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VUNPCKHPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VUNPCKHPDZ256rr %ymm16, %ymm1
%ymm16 = VUNPCKHPDZ256rr %ymm16, %ymm1 %ymm16 = VUNPCKHPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VUNPCKHPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VUNPCKHPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VUNPCKHPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VUNPCKHPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VUNPCKHPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VUNPCKHPSZ256rr %ymm16, %ymm1
%ymm16 = VUNPCKHPSZ256rr %ymm16, %ymm1 %ymm16 = VUNPCKHPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VUNPCKLPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VUNPCKLPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VUNPCKLPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VUNPCKLPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VUNPCKLPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VUNPCKLPDZ256rr %ymm16, %ymm1
%ymm16 = VUNPCKLPDZ256rr %ymm16, %ymm1 %ymm16 = VUNPCKLPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VUNPCKLPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VUNPCKLPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VUNPCKLPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VUNPCKLPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VUNPCKLPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VUNPCKLPSZ256rr %ymm16, %ymm1
%ymm16 = VUNPCKLPSZ256rr %ymm16, %ymm1 %ymm16 = VUNPCKLPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VSUBPDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VSUBPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VSUBPDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VSUBPDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VSUBPDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VSUBPDZ256rr %ymm16, %ymm1
%ymm16 = VSUBPDZ256rr %ymm16, %ymm1 %ymm16 = VSUBPDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VSUBPSZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VSUBPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VSUBPSZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VSUBPSZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VSUBPSZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VSUBPSZ256rr %ymm16, %ymm1
%ymm16 = VSUBPSZ256rr %ymm16, %ymm1 %ymm16 = VSUBPSZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPUNPCKHBWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPUNPCKHBWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPUNPCKHBWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPUNPCKHBWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPUNPCKHBWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPUNPCKHBWZ256rr %ymm16, %ymm1
%ymm16 = VPUNPCKHBWZ256rr %ymm16, %ymm1 %ymm16 = VPUNPCKHBWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPUNPCKHDQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPUNPCKHDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPUNPCKHDQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPUNPCKHDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPUNPCKHDQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPUNPCKHDQZ256rr %ymm16, %ymm1
%ymm16 = VPUNPCKHDQZ256rr %ymm16, %ymm1 %ymm16 = VPUNPCKHDQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPUNPCKHQDQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPUNPCKHQDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPUNPCKHQDQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPUNPCKHQDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPUNPCKHQDQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPUNPCKHQDQZ256rr %ymm16, %ymm1
%ymm16 = VPUNPCKHQDQZ256rr %ymm16, %ymm1 %ymm16 = VPUNPCKHQDQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPUNPCKHWDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPUNPCKHWDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPUNPCKHWDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPUNPCKHWDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPUNPCKHWDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPUNPCKHWDZ256rr %ymm16, %ymm1
%ymm16 = VPUNPCKHWDZ256rr %ymm16, %ymm1 %ymm16 = VPUNPCKHWDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPUNPCKLBWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPUNPCKLBWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPUNPCKLBWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPUNPCKLBWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPUNPCKLBWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPUNPCKLBWZ256rr %ymm16, %ymm1
%ymm16 = VPUNPCKLBWZ256rr %ymm16, %ymm1 %ymm16 = VPUNPCKLBWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPUNPCKLDQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPUNPCKLDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPUNPCKLDQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPUNPCKLDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPUNPCKLDQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPUNPCKLDQZ256rr %ymm16, %ymm1
%ymm16 = VPUNPCKLDQZ256rr %ymm16, %ymm1 %ymm16 = VPUNPCKLDQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPUNPCKLQDQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPUNPCKLQDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPUNPCKLQDQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPUNPCKLQDQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPUNPCKLQDQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPUNPCKLQDQZ256rr %ymm16, %ymm1
%ymm16 = VPUNPCKLQDQZ256rr %ymm16, %ymm1 %ymm16 = VPUNPCKLQDQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPUNPCKLWDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPUNPCKLWDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPUNPCKLWDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPUNPCKLWDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPUNPCKLWDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPUNPCKLWDZ256rr %ymm16, %ymm1
%ymm16 = VPUNPCKLWDZ256rr %ymm16, %ymm1 %ymm16 = VPUNPCKLWDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VFMADD132PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMADD132PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMADD132PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMADD132PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMADD132PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMADD132PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMADD132PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMADD132PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMADD132PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMADD132PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMADD132PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMADD132PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMADD132PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMADD132PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMADD132PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMADD132PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMADD213PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMADD213PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMADD213PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMADD213PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMADD213PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMADD213PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMADD213PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMADD213PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMADD213PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMADD213PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMADD213PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMADD213PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMADD213PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMADD213PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMADD213PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMADD213PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMADD231PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMADD231PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMADD231PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMADD231PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMADD231PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMADD231PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMADD231PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMADD231PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMADD231PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMADD231PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMADD231PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMADD231PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMADD231PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMADD231PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMADD231PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMADD231PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMADDSUB132PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMADDSUB132PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMADDSUB132PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMADDSUB132PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMADDSUB132PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMADDSUB132PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMADDSUB132PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMADDSUB132PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMADDSUB132PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMADDSUB132PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMADDSUB132PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMADDSUB132PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMADDSUB132PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMADDSUB132PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMADDSUB132PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMADDSUB132PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMADDSUB213PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMADDSUB213PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMADDSUB213PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMADDSUB213PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMADDSUB213PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMADDSUB213PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMADDSUB213PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMADDSUB213PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMADDSUB213PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMADDSUB213PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMADDSUB213PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMADDSUB213PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMADDSUB213PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMADDSUB213PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMADDSUB213PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMADDSUB213PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMADDSUB231PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMADDSUB231PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMADDSUB231PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMADDSUB231PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMADDSUB231PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMADDSUB231PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMADDSUB231PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMADDSUB231PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMADDSUB231PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMADDSUB231PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMADDSUB231PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMADDSUB231PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMADDSUB231PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMADDSUB231PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMADDSUB231PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMADDSUB231PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMSUB132PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMSUB132PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMSUB132PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMSUB132PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMSUB132PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMSUB132PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMSUB132PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMSUB132PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMSUB132PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMSUB132PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMSUB132PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMSUB132PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMSUB132PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMSUB132PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMSUB132PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMSUB132PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMSUB213PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMSUB213PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMSUB213PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMSUB213PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMSUB213PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMSUB213PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMSUB213PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMSUB213PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMSUB213PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMSUB213PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMSUB213PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMSUB213PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMSUB213PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMSUB213PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMSUB213PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMSUB213PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMSUB231PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMSUB231PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMSUB231PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMSUB231PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMSUB231PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMSUB231PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMSUB231PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMSUB231PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMSUB231PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMSUB231PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMSUB231PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMSUB231PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMSUB231PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMSUB231PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMSUB231PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMSUB231PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMSUBADD132PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMSUBADD132PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMSUBADD132PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMSUBADD132PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMSUBADD132PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMSUBADD132PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMSUBADD132PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMSUBADD132PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMSUBADD132PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMSUBADD132PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMSUBADD132PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMSUBADD132PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMSUBADD132PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMSUBADD132PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMSUBADD132PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMSUBADD132PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMSUBADD213PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMSUBADD213PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMSUBADD213PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMSUBADD213PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMSUBADD213PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMSUBADD213PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMSUBADD213PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMSUBADD213PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMSUBADD213PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMSUBADD213PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMSUBADD213PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMSUBADD213PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMSUBADD213PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMSUBADD213PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMSUBADD213PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMSUBADD213PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMSUBADD231PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMSUBADD231PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMSUBADD231PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMSUBADD231PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMSUBADD231PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMSUBADD231PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMSUBADD231PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMSUBADD231PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFMSUBADD231PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFMSUBADD231PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFMSUBADD231PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFMSUBADD231PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFMSUBADD231PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFMSUBADD231PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFMSUBADD231PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFMSUBADD231PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFNMADD132PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFNMADD132PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFNMADD132PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFNMADD132PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFNMADD132PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFNMADD132PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFNMADD132PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFNMADD132PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFNMADD132PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFNMADD132PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFNMADD132PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFNMADD132PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFNMADD132PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFNMADD132PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFNMADD132PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFNMADD132PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFNMADD213PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFNMADD213PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFNMADD213PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFNMADD213PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFNMADD213PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFNMADD213PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFNMADD213PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFNMADD213PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFNMADD213PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFNMADD213PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFNMADD213PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFNMADD213PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFNMADD213PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFNMADD213PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFNMADD213PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFNMADD213PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFNMADD231PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFNMADD231PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFNMADD231PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFNMADD231PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFNMADD231PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFNMADD231PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFNMADD231PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFNMADD231PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFNMADD231PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFNMADD231PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFNMADD231PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFNMADD231PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFNMADD231PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFNMADD231PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFNMADD231PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFNMADD231PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFNMSUB132PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFNMSUB132PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFNMSUB132PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFNMSUB132PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFNMSUB132PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFNMSUB132PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFNMSUB132PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFNMSUB132PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFNMSUB132PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFNMSUB132PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFNMSUB132PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFNMSUB132PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFNMSUB132PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFNMSUB132PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFNMSUB132PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFNMSUB132PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFNMSUB213PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFNMSUB213PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFNMSUB213PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFNMSUB213PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFNMSUB213PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFNMSUB213PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFNMSUB213PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFNMSUB213PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFNMSUB213PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFNMSUB213PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFNMSUB213PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFNMSUB213PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFNMSUB213PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFNMSUB213PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFNMSUB213PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFNMSUB213PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFNMSUB231PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFNMSUB231PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFNMSUB231PDZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFNMSUB231PDZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFNMSUB231PDZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFNMSUB231PDZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFNMSUB231PDZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFNMSUB231PDZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VFNMSUB231PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ ; CHECK: %ymm16 = VFNMSUB231PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
%ymm16 = VFNMSUB231PSZ256m %ymm16, %ymm16, %rsi, 1, _, 0, _ %ymm16 = VFNMSUB231PSZ256m %ymm16, %ymm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VFNMSUB231PSZ256r %ymm16, %ymm1, %ymm2 ; CHECK: %ymm16 = VFNMSUB231PSZ256r %ymm16, %ymm1, %ymm2
%ymm16 = VFNMSUB231PSZ256r %ymm16, %ymm1, %ymm2 %ymm16 = VFNMSUB231PSZ256r %ymm16, %ymm1, %ymm2
; CHECK: %ymm16 = VPSRADZ256ri %ymm16, 7 ; CHECK: %ymm16 = VPSRADZ256ri %ymm16, 7
%ymm16 = VPSRADZ256ri %ymm16, 7 %ymm16 = VPSRADZ256ri %ymm16, 7
; CHECK: %ymm16 = VPSRADZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSRADZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSRADZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSRADZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSRADZ256rr %ymm16, %xmm1 ; CHECK: %ymm16 = VPSRADZ256rr %ymm16, %xmm1
%ymm16 = VPSRADZ256rr %ymm16, %xmm1 %ymm16 = VPSRADZ256rr %ymm16, %xmm1
; CHECK: %ymm16 = VPSRAVDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSRAVDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSRAVDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSRAVDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSRAVDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSRAVDZ256rr %ymm16, %ymm1
%ymm16 = VPSRAVDZ256rr %ymm16, %ymm1 %ymm16 = VPSRAVDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPSRAWZ256ri %ymm16, 7 ; CHECK: %ymm16 = VPSRAWZ256ri %ymm16, 7
%ymm16 = VPSRAWZ256ri %ymm16, 7 %ymm16 = VPSRAWZ256ri %ymm16, 7
; CHECK: %ymm16 = VPSRAWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSRAWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSRAWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSRAWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSRAWZ256rr %ymm16, %xmm1 ; CHECK: %ymm16 = VPSRAWZ256rr %ymm16, %xmm1
%ymm16 = VPSRAWZ256rr %ymm16, %xmm1 %ymm16 = VPSRAWZ256rr %ymm16, %xmm1
; CHECK: %ymm16 = VPSRLDQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSRLDQZ256rr %ymm16, %ymm1
%ymm16 = VPSRLDQZ256rr %ymm16, %ymm1 %ymm16 = VPSRLDQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPSRLDZ256ri %ymm16, 7 ; CHECK: %ymm16 = VPSRLDZ256ri %ymm16, 7
%ymm16 = VPSRLDZ256ri %ymm16, 7 %ymm16 = VPSRLDZ256ri %ymm16, 7
; CHECK: %ymm16 = VPSRLDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSRLDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSRLDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSRLDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSRLDZ256rr %ymm16, %xmm1 ; CHECK: %ymm16 = VPSRLDZ256rr %ymm16, %xmm1
%ymm16 = VPSRLDZ256rr %ymm16, %xmm1 %ymm16 = VPSRLDZ256rr %ymm16, %xmm1
; CHECK: %ymm16 = VPSRLQZ256ri %ymm16, 7 ; CHECK: %ymm16 = VPSRLQZ256ri %ymm16, 7
%ymm16 = VPSRLQZ256ri %ymm16, 7 %ymm16 = VPSRLQZ256ri %ymm16, 7
; CHECK: %ymm16 = VPSRLQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSRLQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSRLQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSRLQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSRLQZ256rr %ymm16, %xmm1 ; CHECK: %ymm16 = VPSRLQZ256rr %ymm16, %xmm1
%ymm16 = VPSRLQZ256rr %ymm16, %xmm1 %ymm16 = VPSRLQZ256rr %ymm16, %xmm1
; CHECK: %ymm16 = VPSRLVDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSRLVDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSRLVDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSRLVDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSRLVDZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSRLVDZ256rr %ymm16, %ymm1
%ymm16 = VPSRLVDZ256rr %ymm16, %ymm1 %ymm16 = VPSRLVDZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPSRLVQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSRLVQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSRLVQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSRLVQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSRLVQZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSRLVQZ256rr %ymm16, %ymm1
%ymm16 = VPSRLVQZ256rr %ymm16, %ymm1 %ymm16 = VPSRLVQZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPSRLWZ256ri %ymm16, 7 ; CHECK: %ymm16 = VPSRLWZ256ri %ymm16, 7
%ymm16 = VPSRLWZ256ri %ymm16, 7 %ymm16 = VPSRLWZ256ri %ymm16, 7
; CHECK: %ymm16 = VPSRLWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSRLWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSRLWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSRLWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSRLWZ256rr %ymm16, %xmm1 ; CHECK: %ymm16 = VPSRLWZ256rr %ymm16, %xmm1
%ymm16 = VPSRLWZ256rr %ymm16, %xmm1 %ymm16 = VPSRLWZ256rr %ymm16, %xmm1
; CHECK: %ymm16 = VPMOVSXBDZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMOVSXBDZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMOVSXBDZ256rm %rip, 1, _, %rax, _ %ymm16 = VPMOVSXBDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMOVSXBDZ256rr %xmm0 ; CHECK: %ymm16 = VPMOVSXBDZ256rr %xmm0
%ymm16 = VPMOVSXBDZ256rr %xmm0 %ymm16 = VPMOVSXBDZ256rr %xmm0
; CHECK: %ymm16 = VPMOVSXBQZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMOVSXBQZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMOVSXBQZ256rm %rip, 1, _, %rax, _ %ymm16 = VPMOVSXBQZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMOVSXBQZ256rr %xmm0 ; CHECK: %ymm16 = VPMOVSXBQZ256rr %xmm0
%ymm16 = VPMOVSXBQZ256rr %xmm0 %ymm16 = VPMOVSXBQZ256rr %xmm0
; CHECK: %ymm16 = VPMOVSXBWZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMOVSXBWZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMOVSXBWZ256rm %rip, 1, _, %rax, _ %ymm16 = VPMOVSXBWZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMOVSXBWZ256rr %xmm0 ; CHECK: %ymm16 = VPMOVSXBWZ256rr %xmm0
%ymm16 = VPMOVSXBWZ256rr %xmm0 %ymm16 = VPMOVSXBWZ256rr %xmm0
; CHECK: %ymm16 = VPMOVSXDQZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMOVSXDQZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMOVSXDQZ256rm %rip, 1, _, %rax, _ %ymm16 = VPMOVSXDQZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMOVSXDQZ256rr %xmm0 ; CHECK: %ymm16 = VPMOVSXDQZ256rr %xmm0
%ymm16 = VPMOVSXDQZ256rr %xmm0 %ymm16 = VPMOVSXDQZ256rr %xmm0
; CHECK: %ymm16 = VPMOVSXWDZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMOVSXWDZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMOVSXWDZ256rm %rip, 1, _, %rax, _ %ymm16 = VPMOVSXWDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMOVSXWDZ256rr %xmm0 ; CHECK: %ymm16 = VPMOVSXWDZ256rr %xmm0
%ymm16 = VPMOVSXWDZ256rr %xmm0 %ymm16 = VPMOVSXWDZ256rr %xmm0
; CHECK: %ymm16 = VPMOVSXWQZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMOVSXWQZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMOVSXWQZ256rm %rip, 1, _, %rax, _ %ymm16 = VPMOVSXWQZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMOVSXWQZ256rr %xmm0 ; CHECK: %ymm16 = VPMOVSXWQZ256rr %xmm0
%ymm16 = VPMOVSXWQZ256rr %xmm0 %ymm16 = VPMOVSXWQZ256rr %xmm0
; CHECK: %ymm16 = VPMOVZXBDZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMOVZXBDZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMOVZXBDZ256rm %rip, 1, _, %rax, _ %ymm16 = VPMOVZXBDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMOVZXBDZ256rr %xmm0 ; CHECK: %ymm16 = VPMOVZXBDZ256rr %xmm0
%ymm16 = VPMOVZXBDZ256rr %xmm0 %ymm16 = VPMOVZXBDZ256rr %xmm0
; CHECK: %ymm16 = VPMOVZXBQZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMOVZXBQZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMOVZXBQZ256rm %rip, 1, _, %rax, _ %ymm16 = VPMOVZXBQZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMOVZXBQZ256rr %xmm0 ; CHECK: %ymm16 = VPMOVZXBQZ256rr %xmm0
%ymm16 = VPMOVZXBQZ256rr %xmm0 %ymm16 = VPMOVZXBQZ256rr %xmm0
; CHECK: %ymm16 = VPMOVZXBWZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMOVZXBWZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMOVZXBWZ256rm %rip, 1, _, %rax, _ %ymm16 = VPMOVZXBWZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMOVZXBWZ256rr %xmm0 ; CHECK: %ymm16 = VPMOVZXBWZ256rr %xmm0
%ymm16 = VPMOVZXBWZ256rr %xmm0 %ymm16 = VPMOVZXBWZ256rr %xmm0
; CHECK: %ymm16 = VPMOVZXDQZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMOVZXDQZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMOVZXDQZ256rm %rip, 1, _, %rax, _ %ymm16 = VPMOVZXDQZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMOVZXDQZ256rr %xmm0 ; CHECK: %ymm16 = VPMOVZXDQZ256rr %xmm0
%ymm16 = VPMOVZXDQZ256rr %xmm0 %ymm16 = VPMOVZXDQZ256rr %xmm0
; CHECK: %ymm16 = VPMOVZXWDZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMOVZXWDZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMOVZXWDZ256rm %rip, 1, _, %rax, _ %ymm16 = VPMOVZXWDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMOVZXWDZ256rr %xmm0 ; CHECK: %ymm16 = VPMOVZXWDZ256rr %xmm0
%ymm16 = VPMOVZXWDZ256rr %xmm0 %ymm16 = VPMOVZXWDZ256rr %xmm0
; CHECK: %ymm16 = VPMOVZXWQZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPMOVZXWQZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPMOVZXWQZ256rm %rip, 1, _, %rax, _ %ymm16 = VPMOVZXWQZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPMOVZXWQZ256rr %xmm0 ; CHECK: %ymm16 = VPMOVZXWQZ256rr %xmm0
%ymm16 = VPMOVZXWQZ256rr %xmm0 %ymm16 = VPMOVZXWQZ256rr %xmm0
; CHECK: %ymm16 = VBROADCASTF32X2Z256m %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VBROADCASTF32X2Z256m %rip, 1, %noreg, %rax, %noreg
%ymm16 = VBROADCASTF32X2Z256m %rip, 1, _, %rax, _ %ymm16 = VBROADCASTF32X2Z256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VBROADCASTF32X2Z256r %xmm16 ; CHECK: %ymm16 = VBROADCASTF32X2Z256r %xmm16
%ymm16 = VBROADCASTF32X2Z256r %xmm16 %ymm16 = VBROADCASTF32X2Z256r %xmm16
; CHECK: %ymm16 = VBROADCASTF32X4Z256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VBROADCASTF32X4Z256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VBROADCASTF32X4Z256rm %rip, 1, _, %rax, _ %ymm16 = VBROADCASTF32X4Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VBROADCASTSDZ256m %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VBROADCASTSDZ256m %rip, 1, %noreg, %rax, %noreg
%ymm16 = VBROADCASTSDZ256m %rip, 1, _, %rax, _ %ymm16 = VBROADCASTSDZ256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VBROADCASTSDZ256r %xmm0 ; CHECK: %ymm16 = VBROADCASTSDZ256r %xmm0
%ymm16 = VBROADCASTSDZ256r %xmm0 %ymm16 = VBROADCASTSDZ256r %xmm0
; CHECK: %ymm16 = VBROADCASTSSZ256m %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VBROADCASTSSZ256m %rip, 1, %noreg, %rax, %noreg
%ymm16 = VBROADCASTSSZ256m %rip, 1, _, %rax, _ %ymm16 = VBROADCASTSSZ256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VBROADCASTSSZ256r %xmm0 ; CHECK: %ymm16 = VBROADCASTSSZ256r %xmm0
%ymm16 = VBROADCASTSSZ256r %xmm0 %ymm16 = VBROADCASTSSZ256r %xmm0
; CHECK: %ymm16 = VPBROADCASTBZ256m %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPBROADCASTBZ256m %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPBROADCASTBZ256m %rip, 1, _, %rax, _ %ymm16 = VPBROADCASTBZ256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPBROADCASTBZ256r %xmm0 ; CHECK: %ymm16 = VPBROADCASTBZ256r %xmm0
%ymm16 = VPBROADCASTBZ256r %xmm0 %ymm16 = VPBROADCASTBZ256r %xmm0
; CHECK: %ymm16 = VPBROADCASTDZ256m %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPBROADCASTDZ256m %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPBROADCASTDZ256m %rip, 1, _, %rax, _ %ymm16 = VPBROADCASTDZ256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPBROADCASTDZ256r %xmm0 ; CHECK: %ymm16 = VPBROADCASTDZ256r %xmm0
%ymm16 = VPBROADCASTDZ256r %xmm0 %ymm16 = VPBROADCASTDZ256r %xmm0
; CHECK: %ymm16 = VPBROADCASTWZ256m %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPBROADCASTWZ256m %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPBROADCASTWZ256m %rip, 1, _, %rax, _ %ymm16 = VPBROADCASTWZ256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPBROADCASTWZ256r %xmm0 ; CHECK: %ymm16 = VPBROADCASTWZ256r %xmm0
%ymm16 = VPBROADCASTWZ256r %xmm0 %ymm16 = VPBROADCASTWZ256r %xmm0
; CHECK: %ymm16 = VBROADCASTI32X4Z256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VBROADCASTI32X4Z256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VBROADCASTI32X4Z256rm %rip, 1, _, %rax, _ %ymm16 = VBROADCASTI32X4Z256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VBROADCASTI32X2Z256m %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VBROADCASTI32X2Z256m %rip, 1, %noreg, %rax, %noreg
%ymm16 = VBROADCASTI32X2Z256m %rip, 1, _, %rax, _ %ymm16 = VBROADCASTI32X2Z256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VBROADCASTI32X2Z256r %xmm16 ; CHECK: %ymm16 = VBROADCASTI32X2Z256r %xmm16
%ymm16 = VBROADCASTI32X2Z256r %xmm16 %ymm16 = VBROADCASTI32X2Z256r %xmm16
; CHECK: %ymm16 = VPBROADCASTQZ256m %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPBROADCASTQZ256m %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPBROADCASTQZ256m %rip, 1, _, %rax, _ %ymm16 = VPBROADCASTQZ256m %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPBROADCASTQZ256r %xmm0 ; CHECK: %ymm16 = VPBROADCASTQZ256r %xmm0
%ymm16 = VPBROADCASTQZ256r %xmm0 %ymm16 = VPBROADCASTQZ256r %xmm0
; CHECK: %ymm16 = VPABSBZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPABSBZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPABSBZ256rm %rip, 1, _, %rax, _ %ymm16 = VPABSBZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPABSBZ256rr %ymm16 ; CHECK: %ymm16 = VPABSBZ256rr %ymm16
%ymm16 = VPABSBZ256rr %ymm16 %ymm16 = VPABSBZ256rr %ymm16
; CHECK: %ymm16 = VPABSDZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPABSDZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPABSDZ256rm %rip, 1, _, %rax, _ %ymm16 = VPABSDZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPABSDZ256rr %ymm16 ; CHECK: %ymm16 = VPABSDZ256rr %ymm16
%ymm16 = VPABSDZ256rr %ymm16 %ymm16 = VPABSDZ256rr %ymm16
; CHECK: %ymm16 = VPABSWZ256rm %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPABSWZ256rm %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPABSWZ256rm %rip, 1, _, %rax, _ %ymm16 = VPABSWZ256rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPABSWZ256rr %ymm16 ; CHECK: %ymm16 = VPABSWZ256rr %ymm16
%ymm16 = VPABSWZ256rr %ymm16 %ymm16 = VPABSWZ256rr %ymm16
; CHECK: %ymm16 = VPSADBWZ256rm %ymm16, 1, _, %rax, _, _ ; CHECK: %ymm16 = VPSADBWZ256rm %ymm16, 1, %noreg, %rax, %noreg, %noreg
%ymm16 = VPSADBWZ256rm %ymm16, 1, _, %rax, _, _ %ymm16 = VPSADBWZ256rm %ymm16, 1, %noreg, %rax, %noreg, %noreg
; CHECK: %ymm16 = VPSADBWZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSADBWZ256rr %ymm16, %ymm1
%ymm16 = VPSADBWZ256rr %ymm16, %ymm1 %ymm16 = VPSADBWZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPERMDZ256rm %ymm16, %rdi, 1, _, 0, _ ; CHECK: %ymm16 = VPERMDZ256rm %ymm16, %rdi, 1, %noreg, 0, %noreg
%ymm16 = VPERMDZ256rm %ymm16, %rdi, 1, _, 0, _ %ymm16 = VPERMDZ256rm %ymm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VPERMDZ256rr %ymm1, %ymm16 ; CHECK: %ymm16 = VPERMDZ256rr %ymm1, %ymm16
%ymm16 = VPERMDZ256rr %ymm1, %ymm16 %ymm16 = VPERMDZ256rr %ymm1, %ymm16
; CHECK: %ymm16 = VPERMILPDZ256mi %rdi, 1, _, 0, _, _ ; CHECK: %ymm16 = VPERMILPDZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm16 = VPERMILPDZ256mi %rdi, 1, _, 0, _, _ %ymm16 = VPERMILPDZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm16 = VPERMILPDZ256ri %ymm16, 7 ; CHECK: %ymm16 = VPERMILPDZ256ri %ymm16, 7
%ymm16 = VPERMILPDZ256ri %ymm16, 7 %ymm16 = VPERMILPDZ256ri %ymm16, 7
; CHECK: %ymm16 = VPERMILPDZ256rm %ymm16, %rdi, 1, _, 0, _ ; CHECK: %ymm16 = VPERMILPDZ256rm %ymm16, %rdi, 1, %noreg, 0, %noreg
%ymm16 = VPERMILPDZ256rm %ymm16, %rdi, 1, _, 0, _ %ymm16 = VPERMILPDZ256rm %ymm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VPERMILPDZ256rr %ymm1, %ymm16 ; CHECK: %ymm16 = VPERMILPDZ256rr %ymm1, %ymm16
%ymm16 = VPERMILPDZ256rr %ymm1, %ymm16 %ymm16 = VPERMILPDZ256rr %ymm1, %ymm16
; CHECK: %ymm16 = VPERMILPSZ256mi %rdi, 1, _, 0, _, _ ; CHECK: %ymm16 = VPERMILPSZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm16 = VPERMILPSZ256mi %rdi, 1, _, 0, _, _ %ymm16 = VPERMILPSZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm16 = VPERMILPSZ256ri %ymm16, 7 ; CHECK: %ymm16 = VPERMILPSZ256ri %ymm16, 7
%ymm16 = VPERMILPSZ256ri %ymm16, 7 %ymm16 = VPERMILPSZ256ri %ymm16, 7
; CHECK: %ymm16 = VPERMILPSZ256rm %ymm16, %rdi, 1, _, 0, _ ; CHECK: %ymm16 = VPERMILPSZ256rm %ymm16, %rdi, 1, %noreg, 0, %noreg
%ymm16 = VPERMILPSZ256rm %ymm16, %rdi, 1, _, 0, _ %ymm16 = VPERMILPSZ256rm %ymm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VPERMILPSZ256rr %ymm1, %ymm16 ; CHECK: %ymm16 = VPERMILPSZ256rr %ymm1, %ymm16
%ymm16 = VPERMILPSZ256rr %ymm1, %ymm16 %ymm16 = VPERMILPSZ256rr %ymm1, %ymm16
; CHECK: %ymm16 = VPERMPDZ256mi %rdi, 1, _, 0, _, _ ; CHECK: %ymm16 = VPERMPDZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm16 = VPERMPDZ256mi %rdi, 1, _, 0, _, _ %ymm16 = VPERMPDZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm16 = VPERMPDZ256ri %ymm16, 7 ; CHECK: %ymm16 = VPERMPDZ256ri %ymm16, 7
%ymm16 = VPERMPDZ256ri %ymm16, 7 %ymm16 = VPERMPDZ256ri %ymm16, 7
; CHECK: %ymm16 = VPERMPSZ256rm %ymm16, %rdi, 1, _, 0, _ ; CHECK: %ymm16 = VPERMPSZ256rm %ymm16, %rdi, 1, %noreg, 0, %noreg
%ymm16 = VPERMPSZ256rm %ymm16, %rdi, 1, _, 0, _ %ymm16 = VPERMPSZ256rm %ymm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VPERMPSZ256rr %ymm1, %ymm16 ; CHECK: %ymm16 = VPERMPSZ256rr %ymm1, %ymm16
%ymm16 = VPERMPSZ256rr %ymm1, %ymm16 %ymm16 = VPERMPSZ256rr %ymm1, %ymm16
; CHECK: %ymm16 = VPERMQZ256mi %rdi, 1, _, 0, _, _ ; CHECK: %ymm16 = VPERMQZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm16 = VPERMQZ256mi %rdi, 1, _, 0, _, _ %ymm16 = VPERMQZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm16 = VPERMQZ256ri %ymm16, 7 ; CHECK: %ymm16 = VPERMQZ256ri %ymm16, 7
%ymm16 = VPERMQZ256ri %ymm16, 7 %ymm16 = VPERMQZ256ri %ymm16, 7
; CHECK: %ymm16 = VPSLLDQZ256rr %ymm16, 14 ; CHECK: %ymm16 = VPSLLDQZ256rr %ymm16, 14
%ymm16 = VPSLLDQZ256rr %ymm16, 14 %ymm16 = VPSLLDQZ256rr %ymm16, 14
; CHECK: %ymm16 = VPSLLDZ256ri %ymm16, 7 ; CHECK: %ymm16 = VPSLLDZ256ri %ymm16, 7
%ymm16 = VPSLLDZ256ri %ymm16, 7 %ymm16 = VPSLLDZ256ri %ymm16, 7
; CHECK: %ymm16 = VPSLLDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSLLDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSLLDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSLLDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSLLDZ256rr %ymm16, 14 ; CHECK: %ymm16 = VPSLLDZ256rr %ymm16, 14
%ymm16 = VPSLLDZ256rr %ymm16, 14 %ymm16 = VPSLLDZ256rr %ymm16, 14
; CHECK: %ymm16 = VPSLLQZ256ri %ymm16, 7 ; CHECK: %ymm16 = VPSLLQZ256ri %ymm16, 7
%ymm16 = VPSLLQZ256ri %ymm16, 7 %ymm16 = VPSLLQZ256ri %ymm16, 7
; CHECK: %ymm16 = VPSLLQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSLLQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSLLQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSLLQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSLLQZ256rr %ymm16, 14 ; CHECK: %ymm16 = VPSLLQZ256rr %ymm16, 14
%ymm16 = VPSLLQZ256rr %ymm16, 14 %ymm16 = VPSLLQZ256rr %ymm16, 14
; CHECK: %ymm16 = VPSLLVDZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSLLVDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSLLVDZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSLLVDZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSLLVDZ256rr %ymm16, 14 ; CHECK: %ymm16 = VPSLLVDZ256rr %ymm16, 14
%ymm16 = VPSLLVDZ256rr %ymm16, 14 %ymm16 = VPSLLVDZ256rr %ymm16, 14
; CHECK: %ymm16 = VPSLLVQZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSLLVQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSLLVQZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSLLVQZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSLLVQZ256rr %ymm16, 14 ; CHECK: %ymm16 = VPSLLVQZ256rr %ymm16, 14
%ymm16 = VPSLLVQZ256rr %ymm16, 14 %ymm16 = VPSLLVQZ256rr %ymm16, 14
; CHECK: %ymm16 = VPSLLWZ256ri %ymm16, 7 ; CHECK: %ymm16 = VPSLLWZ256ri %ymm16, 7
%ymm16 = VPSLLWZ256ri %ymm16, 7 %ymm16 = VPSLLWZ256ri %ymm16, 7
; CHECK: %ymm16 = VPSLLWZ256rm %ymm16, %rip, 1, _, %rax, _ ; CHECK: %ymm16 = VPSLLWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
%ymm16 = VPSLLWZ256rm %ymm16, %rip, 1, _, %rax, _ %ymm16 = VPSLLWZ256rm %ymm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %ymm16 = VPSLLWZ256rr %ymm16, 14 ; CHECK: %ymm16 = VPSLLWZ256rr %ymm16, 14
%ymm16 = VPSLLWZ256rr %ymm16, 14 %ymm16 = VPSLLWZ256rr %ymm16, 14
; CHECK: %ymm16 = VCVTDQ2PDZ256rm %rdi, %ymm16, 1, _, 0 ; CHECK: %ymm16 = VCVTDQ2PDZ256rm %rdi, %ymm16, 1, %noreg, 0
%ymm16 = VCVTDQ2PDZ256rm %rdi, %ymm16, 1, _, 0 %ymm16 = VCVTDQ2PDZ256rm %rdi, %ymm16, 1, %noreg, 0
; CHECK: %ymm16 = VCVTDQ2PDZ256rr %xmm0 ; CHECK: %ymm16 = VCVTDQ2PDZ256rr %xmm0
%ymm16 = VCVTDQ2PDZ256rr %xmm0 %ymm16 = VCVTDQ2PDZ256rr %xmm0
; CHECK: %ymm16 = VCVTDQ2PSZ256rm %rdi, %ymm16, 1, _, 0 ; CHECK: %ymm16 = VCVTDQ2PSZ256rm %rdi, %ymm16, 1, %noreg, 0
%ymm16 = VCVTDQ2PSZ256rm %rdi, %ymm16, 1, _, 0 %ymm16 = VCVTDQ2PSZ256rm %rdi, %ymm16, 1, %noreg, 0
; CHECK: %ymm16 = VCVTDQ2PSZ256rr %ymm16 ; CHECK: %ymm16 = VCVTDQ2PSZ256rr %ymm16
%ymm16 = VCVTDQ2PSZ256rr %ymm16 %ymm16 = VCVTDQ2PSZ256rr %ymm16
; CHECK: %xmm0 = VCVTPD2DQZ256rm %rdi, %ymm16, 1, _, 0 ; CHECK: %xmm0 = VCVTPD2DQZ256rm %rdi, %ymm16, 1, %noreg, 0
%xmm0 = VCVTPD2DQZ256rm %rdi, %ymm16, 1, _, 0 %xmm0 = VCVTPD2DQZ256rm %rdi, %ymm16, 1, %noreg, 0
; CHECK: %xmm0 = VCVTPD2DQZ256rr %ymm16 ; CHECK: %xmm0 = VCVTPD2DQZ256rr %ymm16
%xmm0 = VCVTPD2DQZ256rr %ymm16 %xmm0 = VCVTPD2DQZ256rr %ymm16
; CHECK: %xmm0 = VCVTPD2PSZ256rm %rdi, %ymm16, 1, _, 0 ; CHECK: %xmm0 = VCVTPD2PSZ256rm %rdi, %ymm16, 1, %noreg, 0
%xmm0 = VCVTPD2PSZ256rm %rdi, %ymm16, 1, _, 0 %xmm0 = VCVTPD2PSZ256rm %rdi, %ymm16, 1, %noreg, 0
; CHECK: %xmm0 = VCVTPD2PSZ256rr %ymm16 ; CHECK: %xmm0 = VCVTPD2PSZ256rr %ymm16
%xmm0 = VCVTPD2PSZ256rr %ymm16 %xmm0 = VCVTPD2PSZ256rr %ymm16
; CHECK: %ymm16 = VCVTPS2DQZ256rm %rdi, %ymm16, 1, _, 0 ; CHECK: %ymm16 = VCVTPS2DQZ256rm %rdi, %ymm16, 1, %noreg, 0
%ymm16 = VCVTPS2DQZ256rm %rdi, %ymm16, 1, _, 0 %ymm16 = VCVTPS2DQZ256rm %rdi, %ymm16, 1, %noreg, 0
; CHECK: %ymm16 = VCVTPS2DQZ256rr %ymm16 ; CHECK: %ymm16 = VCVTPS2DQZ256rr %ymm16
%ymm16 = VCVTPS2DQZ256rr %ymm16 %ymm16 = VCVTPS2DQZ256rr %ymm16
; CHECK: %ymm16 = VCVTPS2PDZ256rm %rdi, %ymm16, 1, _, 0 ; CHECK: %ymm16 = VCVTPS2PDZ256rm %rdi, %ymm16, 1, %noreg, 0
%ymm16 = VCVTPS2PDZ256rm %rdi, %ymm16, 1, _, 0 %ymm16 = VCVTPS2PDZ256rm %rdi, %ymm16, 1, %noreg, 0
; CHECK: %ymm16 = VCVTPS2PDZ256rr %xmm0 ; CHECK: %ymm16 = VCVTPS2PDZ256rr %xmm0
%ymm16 = VCVTPS2PDZ256rr %xmm0 %ymm16 = VCVTPS2PDZ256rr %xmm0
; CHECK: VCVTPS2PHZ256mr %rdi, %ymm16, 1, _, 0, _, _ ; CHECK: VCVTPS2PHZ256mr %rdi, %ymm16, 1, %noreg, 0, %noreg, %noreg
VCVTPS2PHZ256mr %rdi, %ymm16, 1, _, 0, _, _ VCVTPS2PHZ256mr %rdi, %ymm16, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm0 = VCVTPS2PHZ256rr %ymm16, _ ; CHECK: %xmm0 = VCVTPS2PHZ256rr %ymm16, %noreg
%xmm0 = VCVTPS2PHZ256rr %ymm16, _ %xmm0 = VCVTPS2PHZ256rr %ymm16, %noreg
; CHECK: %ymm16 = VCVTPH2PSZ256rm %rdi, %ymm16, 1, _, 0 ; CHECK: %ymm16 = VCVTPH2PSZ256rm %rdi, %ymm16, 1, %noreg, 0
%ymm16 = VCVTPH2PSZ256rm %rdi, %ymm16, 1, _, 0 %ymm16 = VCVTPH2PSZ256rm %rdi, %ymm16, 1, %noreg, 0
; CHECK: %ymm16 = VCVTPH2PSZ256rr %xmm0 ; CHECK: %ymm16 = VCVTPH2PSZ256rr %xmm0
%ymm16 = VCVTPH2PSZ256rr %xmm0 %ymm16 = VCVTPH2PSZ256rr %xmm0
; CHECK: %xmm0 = VCVTTPD2DQZ256rm %rdi, %ymm16, 1, _, 0 ; CHECK: %xmm0 = VCVTTPD2DQZ256rm %rdi, %ymm16, 1, %noreg, 0
%xmm0 = VCVTTPD2DQZ256rm %rdi, %ymm16, 1, _, 0 %xmm0 = VCVTTPD2DQZ256rm %rdi, %ymm16, 1, %noreg, 0
; CHECK: %xmm0 = VCVTTPD2DQZ256rr %ymm16 ; CHECK: %xmm0 = VCVTTPD2DQZ256rr %ymm16
%xmm0 = VCVTTPD2DQZ256rr %ymm16 %xmm0 = VCVTTPD2DQZ256rr %ymm16
; CHECK: %ymm16 = VCVTTPS2DQZ256rm %rdi, %ymm16, 1, _, 0 ; CHECK: %ymm16 = VCVTTPS2DQZ256rm %rdi, %ymm16, 1, %noreg, 0
%ymm16 = VCVTTPS2DQZ256rm %rdi, %ymm16, 1, _, 0 %ymm16 = VCVTTPS2DQZ256rm %rdi, %ymm16, 1, %noreg, 0
; CHECK: %ymm16 = VCVTTPS2DQZ256rr %ymm16 ; CHECK: %ymm16 = VCVTTPS2DQZ256rr %ymm16
%ymm16 = VCVTTPS2DQZ256rr %ymm16 %ymm16 = VCVTTPS2DQZ256rr %ymm16
; CHECK: %ymm16 = VSQRTPDZ256m %rdi, _, _, _, _ ; CHECK: %ymm16 = VSQRTPDZ256m %rdi, %noreg, %noreg, %noreg, %noreg
%ymm16 = VSQRTPDZ256m %rdi, _, _, _, _ %ymm16 = VSQRTPDZ256m %rdi, %noreg, %noreg, %noreg, %noreg
; CHECK: %ymm16 = VSQRTPDZ256r %ymm16 ; CHECK: %ymm16 = VSQRTPDZ256r %ymm16
%ymm16 = VSQRTPDZ256r %ymm16 %ymm16 = VSQRTPDZ256r %ymm16
; CHECK: %ymm16 = VSQRTPSZ256m %rdi, _, _, _, _ ; CHECK: %ymm16 = VSQRTPSZ256m %rdi, %noreg, %noreg, %noreg, %noreg
%ymm16 = VSQRTPSZ256m %rdi, _, _, _, _ %ymm16 = VSQRTPSZ256m %rdi, %noreg, %noreg, %noreg, %noreg
; CHECK: %ymm16 = VSQRTPSZ256r %ymm16 ; CHECK: %ymm16 = VSQRTPSZ256r %ymm16
%ymm16 = VSQRTPSZ256r %ymm16 %ymm16 = VSQRTPSZ256r %ymm16
; CHECK: %ymm16 = VPALIGNRZ256rmi %ymm16, %rdi, _, _, _, _, _ ; CHECK: %ymm16 = VPALIGNRZ256rmi %ymm16, %rdi, %noreg, %noreg, %noreg, %noreg, %noreg
%ymm16 = VPALIGNRZ256rmi %ymm16, %rdi, _, _, _, _, _ %ymm16 = VPALIGNRZ256rmi %ymm16, %rdi, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %ymm16 = VPALIGNRZ256rri %ymm16, %ymm1, _ ; CHECK: %ymm16 = VPALIGNRZ256rri %ymm16, %ymm1, %noreg
%ymm16 = VPALIGNRZ256rri %ymm16, %ymm1, _ %ymm16 = VPALIGNRZ256rri %ymm16, %ymm1, %noreg
; CHECK: %ymm16 = VMOVUPSZ256rm %rdi, 1, _, 0, _ ; CHECK: %ymm16 = VMOVUPSZ256rm %rdi, 1, %noreg, 0, %noreg
%ymm16 = VMOVUPSZ256rm %rdi, 1, _, 0, _ %ymm16 = VMOVUPSZ256rm %rdi, 1, %noreg, 0, %noreg
; CHECK: %ymm16 = VMOVUPSZ256rr %ymm16 ; CHECK: %ymm16 = VMOVUPSZ256rr %ymm16
%ymm16 = VMOVUPSZ256rr %ymm16 %ymm16 = VMOVUPSZ256rr %ymm16
; CHECK: %ymm16 = VMOVUPSZ256rr_REV %ymm16 ; CHECK: %ymm16 = VMOVUPSZ256rr_REV %ymm16
%ymm16 = VMOVUPSZ256rr_REV %ymm16 %ymm16 = VMOVUPSZ256rr_REV %ymm16
; CHECK: %ymm16 = VPSHUFBZ256rm %ymm16, _, _, _, _, _ ; CHECK: %ymm16 = VPSHUFBZ256rm %ymm16, %noreg, %noreg, %noreg, %noreg, %noreg
%ymm16 = VPSHUFBZ256rm %ymm16, _, _, _, _, _ %ymm16 = VPSHUFBZ256rm %ymm16, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %ymm16 = VPSHUFBZ256rr %ymm16, %ymm1 ; CHECK: %ymm16 = VPSHUFBZ256rr %ymm16, %ymm1
%ymm16 = VPSHUFBZ256rr %ymm16, %ymm1 %ymm16 = VPSHUFBZ256rr %ymm16, %ymm1
; CHECK: %ymm16 = VPSHUFDZ256mi %rdi, 1, _, 0, _, _ ; CHECK: %ymm16 = VPSHUFDZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm16 = VPSHUFDZ256mi %rdi, 1, _, 0, _, _ %ymm16 = VPSHUFDZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm16 = VPSHUFDZ256ri %ymm16, -24 ; CHECK: %ymm16 = VPSHUFDZ256ri %ymm16, -24
%ymm16 = VPSHUFDZ256ri %ymm16, -24 %ymm16 = VPSHUFDZ256ri %ymm16, -24
; CHECK: %ymm16 = VPSHUFHWZ256mi %rdi, 1, _, 0, _, _ ; CHECK: %ymm16 = VPSHUFHWZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm16 = VPSHUFHWZ256mi %rdi, 1, _, 0, _, _ %ymm16 = VPSHUFHWZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm16 = VPSHUFHWZ256ri %ymm16, -24 ; CHECK: %ymm16 = VPSHUFHWZ256ri %ymm16, -24
%ymm16 = VPSHUFHWZ256ri %ymm16, -24 %ymm16 = VPSHUFHWZ256ri %ymm16, -24
; CHECK: %ymm16 = VPSHUFLWZ256mi %rdi, 1, _, 0, _, _ ; CHECK: %ymm16 = VPSHUFLWZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
%ymm16 = VPSHUFLWZ256mi %rdi, 1, _, 0, _, _ %ymm16 = VPSHUFLWZ256mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %ymm16 = VPSHUFLWZ256ri %ymm16, -24 ; CHECK: %ymm16 = VPSHUFLWZ256ri %ymm16, -24
%ymm16 = VPSHUFLWZ256ri %ymm16, -24 %ymm16 = VPSHUFLWZ256ri %ymm16, -24
; CHECK: %ymm16 = VSHUFPDZ256rmi %ymm16, _, _, _, _, _, _ ; CHECK: %ymm16 = VSHUFPDZ256rmi %ymm16, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
%ymm16 = VSHUFPDZ256rmi %ymm16, _, _, _, _, _, _ %ymm16 = VSHUFPDZ256rmi %ymm16, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %ymm16 = VSHUFPDZ256rri %ymm16, _, _ ; CHECK: %ymm16 = VSHUFPDZ256rri %ymm16, %noreg, %noreg
%ymm16 = VSHUFPDZ256rri %ymm16, _, _ %ymm16 = VSHUFPDZ256rri %ymm16, %noreg, %noreg
; CHECK: %ymm16 = VSHUFPSZ256rmi %ymm16, _, _, _, _, _, _ ; CHECK: %ymm16 = VSHUFPSZ256rmi %ymm16, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
%ymm16 = VSHUFPSZ256rmi %ymm16, _, _, _, _, _, _ %ymm16 = VSHUFPSZ256rmi %ymm16, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %ymm16 = VSHUFPSZ256rri %ymm16, _, _ ; CHECK: %ymm16 = VSHUFPSZ256rri %ymm16, %noreg, %noreg
%ymm16 = VSHUFPSZ256rri %ymm16, _, _ %ymm16 = VSHUFPSZ256rri %ymm16, %noreg, %noreg
RET 0, %zmm0, %zmm1 RET 0, %zmm0, %zmm1
... ...
--- ---
# CHECK-LABEL: name: evex_z128_to_evex_test # CHECK-LABEL: name: evex_z128_to_evex_test
# CHECK: bb.0: # CHECK: bb.0:
name: evex_z128_to_evex_test name: evex_z128_to_evex_test
body: | body: |
bb.0: bb.0:
; CHECK: VMOVAPDZ128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVAPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVAPDZ128mr %rdi, 1, _, 0, _, %xmm16 VMOVAPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVAPDZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMOVAPDZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMOVAPDZ128rm %rip, 1, _, %rax, _ %xmm16 = VMOVAPDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMOVAPDZ128rr %xmm16 ; CHECK: %xmm16 = VMOVAPDZ128rr %xmm16
%xmm16 = VMOVAPDZ128rr %xmm16 %xmm16 = VMOVAPDZ128rr %xmm16
; CHECK: VMOVAPSZ128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVAPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVAPSZ128mr %rdi, 1, _, 0, _, %xmm16 VMOVAPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVAPSZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMOVAPSZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMOVAPSZ128rm %rip, 1, _, %rax, _ %xmm16 = VMOVAPSZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMOVAPSZ128rr %xmm16 ; CHECK: %xmm16 = VMOVAPSZ128rr %xmm16
%xmm16 = VMOVAPSZ128rr %xmm16 %xmm16 = VMOVAPSZ128rr %xmm16
; CHECK: VMOVDQA32Z128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVDQA32Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVDQA32Z128mr %rdi, 1, _, 0, _, %xmm16 VMOVDQA32Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVDQA32Z128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMOVDQA32Z128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMOVDQA32Z128rm %rip, 1, _, %rax, _ %xmm16 = VMOVDQA32Z128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMOVDQA32Z128rr %xmm16 ; CHECK: %xmm16 = VMOVDQA32Z128rr %xmm16
%xmm16 = VMOVDQA32Z128rr %xmm16 %xmm16 = VMOVDQA32Z128rr %xmm16
; CHECK: VMOVDQA64Z128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVDQA64Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVDQA64Z128mr %rdi, 1, _, 0, _, %xmm16 VMOVDQA64Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVDQA64Z128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMOVDQA64Z128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMOVDQA64Z128rm %rip, 1, _, %rax, _ %xmm16 = VMOVDQA64Z128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMOVDQA64Z128rr %xmm16 ; CHECK: %xmm16 = VMOVDQA64Z128rr %xmm16
%xmm16 = VMOVDQA64Z128rr %xmm16 %xmm16 = VMOVDQA64Z128rr %xmm16
; CHECK: VMOVDQU16Z128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVDQU16Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVDQU16Z128mr %rdi, 1, _, 0, _, %xmm16 VMOVDQU16Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVDQU16Z128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMOVDQU16Z128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMOVDQU16Z128rm %rip, 1, _, %rax, _ %xmm16 = VMOVDQU16Z128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMOVDQU16Z128rr %xmm16 ; CHECK: %xmm16 = VMOVDQU16Z128rr %xmm16
%xmm16 = VMOVDQU16Z128rr %xmm16 %xmm16 = VMOVDQU16Z128rr %xmm16
; CHECK: VMOVDQU32Z128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVDQU32Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVDQU32Z128mr %rdi, 1, _, 0, _, %xmm16 VMOVDQU32Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVDQU32Z128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMOVDQU32Z128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMOVDQU32Z128rm %rip, 1, _, %rax, _ %xmm16 = VMOVDQU32Z128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMOVDQU32Z128rr %xmm16 ; CHECK: %xmm16 = VMOVDQU32Z128rr %xmm16
%xmm16 = VMOVDQU32Z128rr %xmm16 %xmm16 = VMOVDQU32Z128rr %xmm16
; CHECK: VMOVDQU64Z128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVDQU64Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVDQU64Z128mr %rdi, 1, _, 0, _, %xmm16 VMOVDQU64Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVDQU64Z128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMOVDQU64Z128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMOVDQU64Z128rm %rip, 1, _, %rax, _ %xmm16 = VMOVDQU64Z128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMOVDQU64Z128rr %xmm16 ; CHECK: %xmm16 = VMOVDQU64Z128rr %xmm16
%xmm16 = VMOVDQU64Z128rr %xmm16 %xmm16 = VMOVDQU64Z128rr %xmm16
; CHECK: VMOVDQU8Z128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVDQU8Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVDQU8Z128mr %rdi, 1, _, 0, _, %xmm16 VMOVDQU8Z128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVDQU8Z128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMOVDQU8Z128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMOVDQU8Z128rm %rip, 1, _, %rax, _ %xmm16 = VMOVDQU8Z128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMOVDQU8Z128rr %xmm16 ; CHECK: %xmm16 = VMOVDQU8Z128rr %xmm16
%xmm16 = VMOVDQU8Z128rr %xmm16 %xmm16 = VMOVDQU8Z128rr %xmm16
; CHECK: %xmm16 = VMOVDQU8Z128rr_REV %xmm16 ; CHECK: %xmm16 = VMOVDQU8Z128rr_REV %xmm16
%xmm16 = VMOVDQU8Z128rr_REV %xmm16 %xmm16 = VMOVDQU8Z128rr_REV %xmm16
; CHECK: %xmm16 = VMOVNTDQAZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMOVNTDQAZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMOVNTDQAZ128rm %rip, 1, _, %rax, _ %xmm16 = VMOVNTDQAZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: VMOVUPDZ128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVUPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVUPDZ128mr %rdi, 1, _, 0, _, %xmm16 VMOVUPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVUPDZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMOVUPDZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMOVUPDZ128rm %rip, 1, _, %rax, _ %xmm16 = VMOVUPDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMOVUPDZ128rr %xmm16 ; CHECK: %xmm16 = VMOVUPDZ128rr %xmm16
%xmm16 = VMOVUPDZ128rr %xmm16 %xmm16 = VMOVUPDZ128rr %xmm16
; CHECK: %xmm16 = VMOVUPDZ128rr_REV %xmm16 ; CHECK: %xmm16 = VMOVUPDZ128rr_REV %xmm16
%xmm16 = VMOVUPDZ128rr_REV %xmm16 %xmm16 = VMOVUPDZ128rr_REV %xmm16
; CHECK: VMOVUPSZ128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVUPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVUPSZ128mr %rdi, 1, _, 0, _, %xmm16 VMOVUPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVUPSZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMOVUPSZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMOVUPSZ128rm %rip, 1, _, %rax, _ %xmm16 = VMOVUPSZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMOVUPSZ128rr %xmm16 ; CHECK: %xmm16 = VMOVUPSZ128rr %xmm16
%xmm16 = VMOVUPSZ128rr %xmm16 %xmm16 = VMOVUPSZ128rr %xmm16
; CHECK: %xmm16 = VMOVUPSZ128rr_REV %xmm16 ; CHECK: %xmm16 = VMOVUPSZ128rr_REV %xmm16
%xmm16 = VMOVUPSZ128rr_REV %xmm16 %xmm16 = VMOVUPSZ128rr_REV %xmm16
; CHECK: VMOVNTDQZ128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVNTDQZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVNTDQZ128mr %rdi, 1, _, 0, _, %xmm16 VMOVNTDQZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: VMOVNTPDZ128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVNTPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVNTPDZ128mr %rdi, 1, _, 0, _, %xmm16 VMOVNTPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: VMOVNTPSZ128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVNTPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVNTPSZ128mr %rdi, 1, _, 0, _, %xmm16 VMOVNTPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVAPDZ128rr_REV %xmm16 ; CHECK: %xmm16 = VMOVAPDZ128rr_REV %xmm16
%xmm16 = VMOVAPDZ128rr_REV %xmm16 %xmm16 = VMOVAPDZ128rr_REV %xmm16
; CHECK: %xmm16 = VMOVAPSZ128rr_REV %xmm16 ; CHECK: %xmm16 = VMOVAPSZ128rr_REV %xmm16
%xmm16 = VMOVAPSZ128rr_REV %xmm16 %xmm16 = VMOVAPSZ128rr_REV %xmm16
; CHECK: %xmm16 = VMOVDQA32Z128rr_REV %xmm16 ; CHECK: %xmm16 = VMOVDQA32Z128rr_REV %xmm16
%xmm16 = VMOVDQA32Z128rr_REV %xmm16 %xmm16 = VMOVDQA32Z128rr_REV %xmm16
; CHECK: %xmm16 = VMOVDQA64Z128rr_REV %xmm16 ; CHECK: %xmm16 = VMOVDQA64Z128rr_REV %xmm16
%xmm16 = VMOVDQA64Z128rr_REV %xmm16 %xmm16 = VMOVDQA64Z128rr_REV %xmm16
; CHECK: %xmm16 = VMOVDQU16Z128rr_REV %xmm16 ; CHECK: %xmm16 = VMOVDQU16Z128rr_REV %xmm16
%xmm16 = VMOVDQU16Z128rr_REV %xmm16 %xmm16 = VMOVDQU16Z128rr_REV %xmm16
; CHECK: %xmm16 = VMOVDQU32Z128rr_REV %xmm16 ; CHECK: %xmm16 = VMOVDQU32Z128rr_REV %xmm16
%xmm16 = VMOVDQU32Z128rr_REV %xmm16 %xmm16 = VMOVDQU32Z128rr_REV %xmm16
; CHECK: %xmm16 = VMOVDQU64Z128rr_REV %xmm16 ; CHECK: %xmm16 = VMOVDQU64Z128rr_REV %xmm16
%xmm16 = VMOVDQU64Z128rr_REV %xmm16 %xmm16 = VMOVDQU64Z128rr_REV %xmm16
; CHECK: %xmm16 = VPMOVSXBDZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMOVSXBDZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMOVSXBDZ128rm %rip, 1, _, %rax, _ %xmm16 = VPMOVSXBDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMOVSXBDZ128rr %xmm16 ; CHECK: %xmm16 = VPMOVSXBDZ128rr %xmm16
%xmm16 = VPMOVSXBDZ128rr %xmm16 %xmm16 = VPMOVSXBDZ128rr %xmm16
; CHECK: %xmm16 = VPMOVSXBQZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMOVSXBQZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMOVSXBQZ128rm %rip, 1, _, %rax, _ %xmm16 = VPMOVSXBQZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMOVSXBQZ128rr %xmm16 ; CHECK: %xmm16 = VPMOVSXBQZ128rr %xmm16
%xmm16 = VPMOVSXBQZ128rr %xmm16 %xmm16 = VPMOVSXBQZ128rr %xmm16
; CHECK: %xmm16 = VPMOVSXBWZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMOVSXBWZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMOVSXBWZ128rm %rip, 1, _, %rax, _ %xmm16 = VPMOVSXBWZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMOVSXBWZ128rr %xmm16 ; CHECK: %xmm16 = VPMOVSXBWZ128rr %xmm16
%xmm16 = VPMOVSXBWZ128rr %xmm16 %xmm16 = VPMOVSXBWZ128rr %xmm16
; CHECK: %xmm16 = VPMOVSXDQZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMOVSXDQZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMOVSXDQZ128rm %rip, 1, _, %rax, _ %xmm16 = VPMOVSXDQZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMOVSXDQZ128rr %xmm16 ; CHECK: %xmm16 = VPMOVSXDQZ128rr %xmm16
%xmm16 = VPMOVSXDQZ128rr %xmm16 %xmm16 = VPMOVSXDQZ128rr %xmm16
; CHECK: %xmm16 = VPMOVSXWDZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMOVSXWDZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMOVSXWDZ128rm %rip, 1, _, %rax, _ %xmm16 = VPMOVSXWDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMOVSXWDZ128rr %xmm16 ; CHECK: %xmm16 = VPMOVSXWDZ128rr %xmm16
%xmm16 = VPMOVSXWDZ128rr %xmm16 %xmm16 = VPMOVSXWDZ128rr %xmm16
; CHECK: %xmm16 = VPMOVSXWQZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMOVSXWQZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMOVSXWQZ128rm %rip, 1, _, %rax, _ %xmm16 = VPMOVSXWQZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMOVSXWQZ128rr %xmm16 ; CHECK: %xmm16 = VPMOVSXWQZ128rr %xmm16
%xmm16 = VPMOVSXWQZ128rr %xmm16 %xmm16 = VPMOVSXWQZ128rr %xmm16
; CHECK: %xmm16 = VPMOVZXBDZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMOVZXBDZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMOVZXBDZ128rm %rip, 1, _, %rax, _ %xmm16 = VPMOVZXBDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMOVZXBDZ128rr %xmm16 ; CHECK: %xmm16 = VPMOVZXBDZ128rr %xmm16
%xmm16 = VPMOVZXBDZ128rr %xmm16 %xmm16 = VPMOVZXBDZ128rr %xmm16
; CHECK: %xmm16 = VPMOVZXBQZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMOVZXBQZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMOVZXBQZ128rm %rip, 1, _, %rax, _ %xmm16 = VPMOVZXBQZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMOVZXBQZ128rr %xmm16 ; CHECK: %xmm16 = VPMOVZXBQZ128rr %xmm16
%xmm16 = VPMOVZXBQZ128rr %xmm16 %xmm16 = VPMOVZXBQZ128rr %xmm16
; CHECK: %xmm16 = VPMOVZXBWZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMOVZXBWZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMOVZXBWZ128rm %rip, 1, _, %rax, _ %xmm16 = VPMOVZXBWZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMOVZXBWZ128rr %xmm16 ; CHECK: %xmm16 = VPMOVZXBWZ128rr %xmm16
%xmm16 = VPMOVZXBWZ128rr %xmm16 %xmm16 = VPMOVZXBWZ128rr %xmm16
; CHECK: %xmm16 = VPMOVZXDQZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMOVZXDQZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMOVZXDQZ128rm %rip, 1, _, %rax, _ %xmm16 = VPMOVZXDQZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMOVZXDQZ128rr %xmm16 ; CHECK: %xmm16 = VPMOVZXDQZ128rr %xmm16
%xmm16 = VPMOVZXDQZ128rr %xmm16 %xmm16 = VPMOVZXDQZ128rr %xmm16
; CHECK: %xmm16 = VPMOVZXWDZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMOVZXWDZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMOVZXWDZ128rm %rip, 1, _, %rax, _ %xmm16 = VPMOVZXWDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMOVZXWDZ128rr %xmm16 ; CHECK: %xmm16 = VPMOVZXWDZ128rr %xmm16
%xmm16 = VPMOVZXWDZ128rr %xmm16 %xmm16 = VPMOVZXWDZ128rr %xmm16
; CHECK: %xmm16 = VPMOVZXWQZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMOVZXWQZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMOVZXWQZ128rm %rip, 1, _, %rax, _ %xmm16 = VPMOVZXWQZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMOVZXWQZ128rr %xmm16 ; CHECK: %xmm16 = VPMOVZXWQZ128rr %xmm16
%xmm16 = VPMOVZXWQZ128rr %xmm16 %xmm16 = VPMOVZXWQZ128rr %xmm16
; CHECK: VMOVHPDZ128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVHPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVHPDZ128mr %rdi, 1, _, 0, _, %xmm16 VMOVHPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVHPDZ128rm %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VMOVHPDZ128rm %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VMOVHPDZ128rm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VMOVHPDZ128rm %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: VMOVHPSZ128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVHPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVHPSZ128mr %rdi, 1, _, 0, _, %xmm16 VMOVHPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVHPSZ128rm %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VMOVHPSZ128rm %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VMOVHPSZ128rm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VMOVHPSZ128rm %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: VMOVLPDZ128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVLPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVLPDZ128mr %rdi, 1, _, 0, _, %xmm16 VMOVLPDZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVLPDZ128rm %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VMOVLPDZ128rm %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VMOVLPDZ128rm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VMOVLPDZ128rm %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: VMOVLPSZ128mr %rdi, 1, _, 0, _, %xmm16 ; CHECK: VMOVLPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
VMOVLPSZ128mr %rdi, 1, _, 0, _, %xmm16 VMOVLPSZ128mr %rdi, 1, %noreg, 0, %noreg, %xmm16
; CHECK: %xmm16 = VMOVLPSZ128rm %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VMOVLPSZ128rm %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VMOVLPSZ128rm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VMOVLPSZ128rm %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VMAXCPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMAXCPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMAXCPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMAXCPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMAXCPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VMAXCPDZ128rr %xmm16, %xmm1
%xmm16 = VMAXCPDZ128rr %xmm16, %xmm1 %xmm16 = VMAXCPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VMAXCPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMAXCPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMAXCPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMAXCPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMAXCPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VMAXCPSZ128rr %xmm16, %xmm1
%xmm16 = VMAXCPSZ128rr %xmm16, %xmm1 %xmm16 = VMAXCPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VMAXPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMAXPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMAXPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMAXPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMAXPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VMAXPDZ128rr %xmm16, %xmm1
%xmm16 = VMAXPDZ128rr %xmm16, %xmm1 %xmm16 = VMAXPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VMAXPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMAXPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMAXPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMAXPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMAXPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VMAXPSZ128rr %xmm16, %xmm1
%xmm16 = VMAXPSZ128rr %xmm16, %xmm1 %xmm16 = VMAXPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VMINCPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMINCPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMINCPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMINCPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMINCPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VMINCPDZ128rr %xmm16, %xmm1
%xmm16 = VMINCPDZ128rr %xmm16, %xmm1 %xmm16 = VMINCPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VMINCPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMINCPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMINCPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMINCPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMINCPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VMINCPSZ128rr %xmm16, %xmm1
%xmm16 = VMINCPSZ128rr %xmm16, %xmm1 %xmm16 = VMINCPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VMINPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMINPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMINPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMINPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMINPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VMINPDZ128rr %xmm16, %xmm1
%xmm16 = VMINPDZ128rr %xmm16, %xmm1 %xmm16 = VMINPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VMINPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMINPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMINPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMINPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMINPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VMINPSZ128rr %xmm16, %xmm1
%xmm16 = VMINPSZ128rr %xmm16, %xmm1 %xmm16 = VMINPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VMULPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMULPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMULPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMULPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMULPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VMULPDZ128rr %xmm16, %xmm1
%xmm16 = VMULPDZ128rr %xmm16, %xmm1 %xmm16 = VMULPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VMULPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMULPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMULPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMULPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMULPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VMULPSZ128rr %xmm16, %xmm1
%xmm16 = VMULPSZ128rr %xmm16, %xmm1 %xmm16 = VMULPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VORPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VORPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VORPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VORPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VORPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VORPDZ128rr %xmm16, %xmm1
%xmm16 = VORPDZ128rr %xmm16, %xmm1 %xmm16 = VORPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VORPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VORPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VORPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VORPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VORPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VORPSZ128rr %xmm16, %xmm1
%xmm16 = VORPSZ128rr %xmm16, %xmm1 %xmm16 = VORPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPADDBZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPADDBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPADDBZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPADDBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPADDBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPADDBZ128rr %xmm16, %xmm1
%xmm16 = VPADDBZ128rr %xmm16, %xmm1 %xmm16 = VPADDBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPADDDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPADDDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPADDDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPADDDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPADDDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPADDDZ128rr %xmm16, %xmm1
%xmm16 = VPADDDZ128rr %xmm16, %xmm1 %xmm16 = VPADDDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPADDQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPADDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPADDQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPADDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPADDQZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPADDQZ128rr %xmm16, %xmm1
%xmm16 = VPADDQZ128rr %xmm16, %xmm1 %xmm16 = VPADDQZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPADDSBZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPADDSBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPADDSBZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPADDSBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPADDSBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPADDSBZ128rr %xmm16, %xmm1
%xmm16 = VPADDSBZ128rr %xmm16, %xmm1 %xmm16 = VPADDSBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPADDSWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPADDSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPADDSWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPADDSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPADDSWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPADDSWZ128rr %xmm16, %xmm1
%xmm16 = VPADDSWZ128rr %xmm16, %xmm1 %xmm16 = VPADDSWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPADDUSBZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPADDUSBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPADDUSBZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPADDUSBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPADDUSBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPADDUSBZ128rr %xmm16, %xmm1
%xmm16 = VPADDUSBZ128rr %xmm16, %xmm1 %xmm16 = VPADDUSBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPADDUSWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPADDUSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPADDUSWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPADDUSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPADDUSWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPADDUSWZ128rr %xmm16, %xmm1
%xmm16 = VPADDUSWZ128rr %xmm16, %xmm1 %xmm16 = VPADDUSWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPADDWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPADDWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPADDWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPADDWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPADDWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPADDWZ128rr %xmm16, %xmm1
%xmm16 = VPADDWZ128rr %xmm16, %xmm1 %xmm16 = VPADDWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPANDDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPANDDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPANDDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPANDDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPANDDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPANDDZ128rr %xmm16, %xmm1
%xmm16 = VPANDDZ128rr %xmm16, %xmm1 %xmm16 = VPANDDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPANDQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPANDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPANDQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPANDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPANDQZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPANDQZ128rr %xmm16, %xmm1
%xmm16 = VPANDQZ128rr %xmm16, %xmm1 %xmm16 = VPANDQZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPANDNDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPANDNDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPANDNDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPANDNDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPANDNDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPANDNDZ128rr %xmm16, %xmm1
%xmm16 = VPANDNDZ128rr %xmm16, %xmm1 %xmm16 = VPANDNDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPANDNQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPANDNQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPANDNQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPANDNQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPANDNQZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPANDNQZ128rr %xmm16, %xmm1
%xmm16 = VPANDNQZ128rr %xmm16, %xmm1 %xmm16 = VPANDNQZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPAVGBZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPAVGBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPAVGBZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPAVGBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPAVGBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPAVGBZ128rr %xmm16, %xmm1
%xmm16 = VPAVGBZ128rr %xmm16, %xmm1 %xmm16 = VPAVGBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPAVGWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPAVGWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPAVGWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPAVGWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPAVGWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPAVGWZ128rr %xmm16, %xmm1
%xmm16 = VPAVGWZ128rr %xmm16, %xmm1 %xmm16 = VPAVGWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMAXSBZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMAXSBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMAXSBZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMAXSBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMAXSBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMAXSBZ128rr %xmm16, %xmm1
%xmm16 = VPMAXSBZ128rr %xmm16, %xmm1 %xmm16 = VPMAXSBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMAXSDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMAXSDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMAXSDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMAXSDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMAXSDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMAXSDZ128rr %xmm16, %xmm1
%xmm16 = VPMAXSDZ128rr %xmm16, %xmm1 %xmm16 = VPMAXSDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMAXSWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMAXSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMAXSWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMAXSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMAXSWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMAXSWZ128rr %xmm16, %xmm1
%xmm16 = VPMAXSWZ128rr %xmm16, %xmm1 %xmm16 = VPMAXSWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMAXUBZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMAXUBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMAXUBZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMAXUBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMAXUBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMAXUBZ128rr %xmm16, %xmm1
%xmm16 = VPMAXUBZ128rr %xmm16, %xmm1 %xmm16 = VPMAXUBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMAXUDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMAXUDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMAXUDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMAXUDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMAXUDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMAXUDZ128rr %xmm16, %xmm1
%xmm16 = VPMAXUDZ128rr %xmm16, %xmm1 %xmm16 = VPMAXUDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMAXUWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMAXUWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMAXUWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMAXUWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMAXUWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMAXUWZ128rr %xmm16, %xmm1
%xmm16 = VPMAXUWZ128rr %xmm16, %xmm1 %xmm16 = VPMAXUWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMINSBZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMINSBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMINSBZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMINSBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMINSBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMINSBZ128rr %xmm16, %xmm1
%xmm16 = VPMINSBZ128rr %xmm16, %xmm1 %xmm16 = VPMINSBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMINSDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMINSDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMINSDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMINSDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMINSDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMINSDZ128rr %xmm16, %xmm1
%xmm16 = VPMINSDZ128rr %xmm16, %xmm1 %xmm16 = VPMINSDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMINSWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMINSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMINSWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMINSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMINSWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMINSWZ128rr %xmm16, %xmm1
%xmm16 = VPMINSWZ128rr %xmm16, %xmm1 %xmm16 = VPMINSWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMINUBZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMINUBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMINUBZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMINUBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMINUBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMINUBZ128rr %xmm16, %xmm1
%xmm16 = VPMINUBZ128rr %xmm16, %xmm1 %xmm16 = VPMINUBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMINUDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMINUDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMINUDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMINUDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMINUDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMINUDZ128rr %xmm16, %xmm1
%xmm16 = VPMINUDZ128rr %xmm16, %xmm1 %xmm16 = VPMINUDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMINUWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMINUWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMINUWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMINUWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMINUWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMINUWZ128rr %xmm16, %xmm1
%xmm16 = VPMINUWZ128rr %xmm16, %xmm1 %xmm16 = VPMINUWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMULDQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMULDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMULDQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMULDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMULDQZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMULDQZ128rr %xmm16, %xmm1
%xmm16 = VPMULDQZ128rr %xmm16, %xmm1 %xmm16 = VPMULDQZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMULHRSWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMULHRSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMULHRSWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMULHRSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMULHRSWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMULHRSWZ128rr %xmm16, %xmm1
%xmm16 = VPMULHRSWZ128rr %xmm16, %xmm1 %xmm16 = VPMULHRSWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMULHUWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMULHUWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMULHUWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMULHUWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMULHUWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMULHUWZ128rr %xmm16, %xmm1
%xmm16 = VPMULHUWZ128rr %xmm16, %xmm1 %xmm16 = VPMULHUWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMULHWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMULHWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMULHWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMULHWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMULHWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMULHWZ128rr %xmm16, %xmm1
%xmm16 = VPMULHWZ128rr %xmm16, %xmm1 %xmm16 = VPMULHWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMULLDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMULLDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMULLDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMULLDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMULLDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMULLDZ128rr %xmm16, %xmm1
%xmm16 = VPMULLDZ128rr %xmm16, %xmm1 %xmm16 = VPMULLDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMULLWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMULLWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMULLWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMULLWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMULLWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMULLWZ128rr %xmm16, %xmm1
%xmm16 = VPMULLWZ128rr %xmm16, %xmm1 %xmm16 = VPMULLWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMULUDQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMULUDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMULUDQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMULUDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMULUDQZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMULUDQZ128rr %xmm16, %xmm1
%xmm16 = VPMULUDQZ128rr %xmm16, %xmm1 %xmm16 = VPMULUDQZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPORDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPORDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPORDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPORDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPORDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPORDZ128rr %xmm16, %xmm1
%xmm16 = VPORDZ128rr %xmm16, %xmm1 %xmm16 = VPORDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPORQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPORQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPORQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPORQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPORQZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPORQZ128rr %xmm16, %xmm1
%xmm16 = VPORQZ128rr %xmm16, %xmm1 %xmm16 = VPORQZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPSUBBZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSUBBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSUBBZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSUBBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSUBBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPSUBBZ128rr %xmm16, %xmm1
%xmm16 = VPSUBBZ128rr %xmm16, %xmm1 %xmm16 = VPSUBBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPSUBDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSUBDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSUBDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSUBDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSUBDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPSUBDZ128rr %xmm16, %xmm1
%xmm16 = VPSUBDZ128rr %xmm16, %xmm1 %xmm16 = VPSUBDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPSUBQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSUBQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSUBQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSUBQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSUBQZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPSUBQZ128rr %xmm16, %xmm1
%xmm16 = VPSUBQZ128rr %xmm16, %xmm1 %xmm16 = VPSUBQZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPSUBSBZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSUBSBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSUBSBZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSUBSBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSUBSBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPSUBSBZ128rr %xmm16, %xmm1
%xmm16 = VPSUBSBZ128rr %xmm16, %xmm1 %xmm16 = VPSUBSBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPSUBSWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSUBSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSUBSWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSUBSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSUBSWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPSUBSWZ128rr %xmm16, %xmm1
%xmm16 = VPSUBSWZ128rr %xmm16, %xmm1 %xmm16 = VPSUBSWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPSUBUSBZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSUBUSBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSUBUSBZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSUBUSBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSUBUSBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPSUBUSBZ128rr %xmm16, %xmm1
%xmm16 = VPSUBUSBZ128rr %xmm16, %xmm1 %xmm16 = VPSUBUSBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPSUBUSWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSUBUSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSUBUSWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSUBUSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSUBUSWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPSUBUSWZ128rr %xmm16, %xmm1
%xmm16 = VPSUBUSWZ128rr %xmm16, %xmm1 %xmm16 = VPSUBUSWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPSUBWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSUBWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSUBWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSUBWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSUBWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPSUBWZ128rr %xmm16, %xmm1
%xmm16 = VPSUBWZ128rr %xmm16, %xmm1 %xmm16 = VPSUBWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VADDPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VADDPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VADDPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VADDPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VADDPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VADDPDZ128rr %xmm16, %xmm1
%xmm16 = VADDPDZ128rr %xmm16, %xmm1 %xmm16 = VADDPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VADDPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VADDPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VADDPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VADDPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VADDPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VADDPSZ128rr %xmm16, %xmm1
%xmm16 = VADDPSZ128rr %xmm16, %xmm1 %xmm16 = VADDPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VANDNPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VANDNPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VANDNPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VANDNPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VANDNPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VANDNPDZ128rr %xmm16, %xmm1
%xmm16 = VANDNPDZ128rr %xmm16, %xmm1 %xmm16 = VANDNPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VANDNPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VANDNPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VANDNPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VANDNPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VANDNPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VANDNPSZ128rr %xmm16, %xmm1
%xmm16 = VANDNPSZ128rr %xmm16, %xmm1 %xmm16 = VANDNPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VANDPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VANDPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VANDPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VANDPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VANDPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VANDPDZ128rr %xmm16, %xmm1
%xmm16 = VANDPDZ128rr %xmm16, %xmm1 %xmm16 = VANDPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VANDPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VANDPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VANDPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VANDPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VANDPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VANDPSZ128rr %xmm16, %xmm1
%xmm16 = VANDPSZ128rr %xmm16, %xmm1 %xmm16 = VANDPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VDIVPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VDIVPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VDIVPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VDIVPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VDIVPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VDIVPDZ128rr %xmm16, %xmm1
%xmm16 = VDIVPDZ128rr %xmm16, %xmm1 %xmm16 = VDIVPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VDIVPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VDIVPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VDIVPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VDIVPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VDIVPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VDIVPSZ128rr %xmm16, %xmm1
%xmm16 = VDIVPSZ128rr %xmm16, %xmm1 %xmm16 = VDIVPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPXORDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPXORDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPXORDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPXORDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPXORDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPXORDZ128rr %xmm16, %xmm1
%xmm16 = VPXORDZ128rr %xmm16, %xmm1 %xmm16 = VPXORDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPXORQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPXORQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPXORQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPXORQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPXORQZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPXORQZ128rr %xmm16, %xmm1
%xmm16 = VPXORQZ128rr %xmm16, %xmm1 %xmm16 = VPXORQZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VSUBPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VSUBPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VSUBPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VSUBPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VSUBPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VSUBPDZ128rr %xmm16, %xmm1
%xmm16 = VSUBPDZ128rr %xmm16, %xmm1 %xmm16 = VSUBPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VSUBPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VSUBPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VSUBPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VSUBPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VSUBPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VSUBPSZ128rr %xmm16, %xmm1
%xmm16 = VSUBPSZ128rr %xmm16, %xmm1 %xmm16 = VSUBPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VXORPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VXORPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VXORPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VXORPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VXORPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VXORPDZ128rr %xmm16, %xmm1
%xmm16 = VXORPDZ128rr %xmm16, %xmm1 %xmm16 = VXORPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VXORPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VXORPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VXORPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VXORPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VXORPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VXORPSZ128rr %xmm16, %xmm1
%xmm16 = VXORPSZ128rr %xmm16, %xmm1 %xmm16 = VXORPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMADDUBSWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMADDUBSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMADDUBSWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMADDUBSWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMADDUBSWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMADDUBSWZ128rr %xmm16, %xmm1
%xmm16 = VPMADDUBSWZ128rr %xmm16, %xmm1 %xmm16 = VPMADDUBSWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPMADDWDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPMADDWDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPMADDWDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPMADDWDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPMADDWDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPMADDWDZ128rr %xmm16, %xmm1
%xmm16 = VPMADDWDZ128rr %xmm16, %xmm1 %xmm16 = VPMADDWDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPACKSSDWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPACKSSDWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPACKSSDWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPACKSSDWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPACKSSDWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPACKSSDWZ128rr %xmm16, %xmm1
%xmm16 = VPACKSSDWZ128rr %xmm16, %xmm1 %xmm16 = VPACKSSDWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPACKSSWBZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPACKSSWBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPACKSSWBZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPACKSSWBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPACKSSWBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPACKSSWBZ128rr %xmm16, %xmm1
%xmm16 = VPACKSSWBZ128rr %xmm16, %xmm1 %xmm16 = VPACKSSWBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPACKUSDWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPACKUSDWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPACKUSDWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPACKUSDWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPACKUSDWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPACKUSDWZ128rr %xmm16, %xmm1
%xmm16 = VPACKUSDWZ128rr %xmm16, %xmm1 %xmm16 = VPACKUSDWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPACKUSWBZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPACKUSWBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPACKUSWBZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPACKUSWBZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPACKUSWBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPACKUSWBZ128rr %xmm16, %xmm1
%xmm16 = VPACKUSWBZ128rr %xmm16, %xmm1 %xmm16 = VPACKUSWBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPUNPCKHBWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPUNPCKHBWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPUNPCKHBWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPUNPCKHBWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPUNPCKHBWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPUNPCKHBWZ128rr %xmm16, %xmm1
%xmm16 = VPUNPCKHBWZ128rr %xmm16, %xmm1 %xmm16 = VPUNPCKHBWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPUNPCKHDQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPUNPCKHDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPUNPCKHDQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPUNPCKHDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPUNPCKHDQZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPUNPCKHDQZ128rr %xmm16, %xmm1
%xmm16 = VPUNPCKHDQZ128rr %xmm16, %xmm1 %xmm16 = VPUNPCKHDQZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPUNPCKHQDQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPUNPCKHQDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPUNPCKHQDQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPUNPCKHQDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPUNPCKHQDQZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPUNPCKHQDQZ128rr %xmm16, %xmm1
%xmm16 = VPUNPCKHQDQZ128rr %xmm16, %xmm1 %xmm16 = VPUNPCKHQDQZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPUNPCKHWDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPUNPCKHWDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPUNPCKHWDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPUNPCKHWDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPUNPCKHWDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPUNPCKHWDZ128rr %xmm16, %xmm1
%xmm16 = VPUNPCKHWDZ128rr %xmm16, %xmm1 %xmm16 = VPUNPCKHWDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPUNPCKLBWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPUNPCKLBWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPUNPCKLBWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPUNPCKLBWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPUNPCKLBWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPUNPCKLBWZ128rr %xmm16, %xmm1
%xmm16 = VPUNPCKLBWZ128rr %xmm16, %xmm1 %xmm16 = VPUNPCKLBWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPUNPCKLDQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPUNPCKLDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPUNPCKLDQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPUNPCKLDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPUNPCKLDQZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPUNPCKLDQZ128rr %xmm16, %xmm1
%xmm16 = VPUNPCKLDQZ128rr %xmm16, %xmm1 %xmm16 = VPUNPCKLDQZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPUNPCKLQDQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPUNPCKLQDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPUNPCKLQDQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPUNPCKLQDQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPUNPCKLQDQZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPUNPCKLQDQZ128rr %xmm16, %xmm1
%xmm16 = VPUNPCKLQDQZ128rr %xmm16, %xmm1 %xmm16 = VPUNPCKLQDQZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPUNPCKLWDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPUNPCKLWDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPUNPCKLWDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPUNPCKLWDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPUNPCKLWDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPUNPCKLWDZ128rr %xmm16, %xmm1
%xmm16 = VPUNPCKLWDZ128rr %xmm16, %xmm1 %xmm16 = VPUNPCKLWDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VUNPCKHPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VUNPCKHPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VUNPCKHPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VUNPCKHPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VUNPCKHPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VUNPCKHPDZ128rr %xmm16, %xmm1
%xmm16 = VUNPCKHPDZ128rr %xmm16, %xmm1 %xmm16 = VUNPCKHPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VUNPCKHPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VUNPCKHPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VUNPCKHPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VUNPCKHPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VUNPCKHPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VUNPCKHPSZ128rr %xmm16, %xmm1
%xmm16 = VUNPCKHPSZ128rr %xmm16, %xmm1 %xmm16 = VUNPCKHPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VUNPCKLPDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VUNPCKLPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VUNPCKLPDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VUNPCKLPDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VUNPCKLPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VUNPCKLPDZ128rr %xmm16, %xmm1
%xmm16 = VUNPCKLPDZ128rr %xmm16, %xmm1 %xmm16 = VUNPCKLPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VUNPCKLPSZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VUNPCKLPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VUNPCKLPSZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VUNPCKLPSZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VUNPCKLPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VUNPCKLPSZ128rr %xmm16, %xmm1
%xmm16 = VUNPCKLPSZ128rr %xmm16, %xmm1 %xmm16 = VUNPCKLPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VFMADD132PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD132PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD132PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD132PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD132PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD132PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD132PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD132PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD132PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD132PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD132PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD132PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD132PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD132PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD132PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD132PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD213PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD213PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD213PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD213PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD213PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD213PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD213PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD213PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD213PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD213PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD213PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD213PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD213PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD213PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD213PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD213PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD231PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD231PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD231PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD231PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD231PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD231PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD231PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD231PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD231PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD231PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD231PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD231PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD231PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD231PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD231PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD231PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADDSUB132PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADDSUB132PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADDSUB132PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADDSUB132PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADDSUB132PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADDSUB132PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMADDSUB132PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMADDSUB132PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADDSUB132PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADDSUB132PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADDSUB132PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADDSUB132PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADDSUB132PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADDSUB132PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMADDSUB132PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMADDSUB132PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADDSUB213PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADDSUB213PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADDSUB213PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADDSUB213PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADDSUB213PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADDSUB213PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMADDSUB213PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMADDSUB213PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADDSUB213PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADDSUB213PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADDSUB213PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADDSUB213PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADDSUB213PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADDSUB213PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMADDSUB213PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMADDSUB213PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADDSUB231PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADDSUB231PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADDSUB231PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADDSUB231PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADDSUB231PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADDSUB231PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMADDSUB231PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMADDSUB231PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADDSUB231PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADDSUB231PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADDSUB231PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADDSUB231PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADDSUB231PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADDSUB231PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMADDSUB231PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMADDSUB231PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB132PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB132PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB132PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB132PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB132PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB132PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB132PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB132PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB132PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB132PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB132PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB132PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB132PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB132PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB132PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB132PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB213PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB213PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB213PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB213PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB213PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB213PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB213PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB213PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB213PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB213PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB213PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB213PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB213PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB213PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB213PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB213PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB231PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB231PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB231PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB231PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB231PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB231PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB231PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB231PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB231PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB231PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB231PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB231PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB231PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB231PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB231PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB231PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUBADD132PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUBADD132PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUBADD132PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUBADD132PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUBADD132PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUBADD132PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUBADD132PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUBADD132PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUBADD132PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUBADD132PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUBADD132PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUBADD132PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUBADD132PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUBADD132PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUBADD132PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUBADD132PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUBADD213PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUBADD213PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUBADD213PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUBADD213PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUBADD213PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUBADD213PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUBADD213PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUBADD213PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUBADD213PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUBADD213PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUBADD213PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUBADD213PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUBADD213PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUBADD213PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUBADD213PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUBADD213PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUBADD231PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUBADD231PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUBADD231PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUBADD231PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUBADD231PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUBADD231PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUBADD231PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUBADD231PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUBADD231PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUBADD231PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUBADD231PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUBADD231PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUBADD231PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUBADD231PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUBADD231PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUBADD231PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD132PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD132PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD132PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD132PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD132PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD132PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD132PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD132PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD132PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD132PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD132PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD132PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD132PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD132PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD132PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD132PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD213PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD213PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD213PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD213PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD213PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD213PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD213PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD213PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD213PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD213PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD213PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD213PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD213PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD213PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD213PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD213PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD231PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD231PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD231PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD231PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD231PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD231PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD231PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD231PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD231PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD231PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD231PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD231PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD231PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD231PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD231PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD231PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB132PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB132PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB132PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB132PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB132PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB132PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB132PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB132PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB132PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB132PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB132PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB132PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB132PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB132PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB132PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB132PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB213PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB213PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB213PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB213PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB213PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB213PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB213PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB213PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB213PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB213PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB213PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB213PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB213PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB213PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB213PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB213PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB231PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB231PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB231PDZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB231PDZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB231PDZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB231PDZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB231PDZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB231PDZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB231PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB231PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB231PSZ128m %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB231PSZ128m %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB231PSZ128r %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB231PSZ128r %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB231PSZ128r %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB231PSZ128r %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VPSLLDZ128ri %xmm16, 7 ; CHECK: %xmm16 = VPSLLDZ128ri %xmm16, 7
%xmm16 = VPSLLDZ128ri %xmm16, 7 %xmm16 = VPSLLDZ128ri %xmm16, 7
; CHECK: %xmm16 = VPSLLDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSLLDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSLLDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSLLDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSLLDZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSLLDZ128rr %xmm16, 14
%xmm16 = VPSLLDZ128rr %xmm16, 14 %xmm16 = VPSLLDZ128rr %xmm16, 14
; CHECK: %xmm16 = VPSLLQZ128ri %xmm16, 7 ; CHECK: %xmm16 = VPSLLQZ128ri %xmm16, 7
%xmm16 = VPSLLQZ128ri %xmm16, 7 %xmm16 = VPSLLQZ128ri %xmm16, 7
; CHECK: %xmm16 = VPSLLQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSLLQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSLLQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSLLQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSLLQZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSLLQZ128rr %xmm16, 14
%xmm16 = VPSLLQZ128rr %xmm16, 14 %xmm16 = VPSLLQZ128rr %xmm16, 14
; CHECK: %xmm16 = VPSLLVDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSLLVDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSLLVDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSLLVDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSLLVDZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSLLVDZ128rr %xmm16, 14
%xmm16 = VPSLLVDZ128rr %xmm16, 14 %xmm16 = VPSLLVDZ128rr %xmm16, 14
; CHECK: %xmm16 = VPSLLVQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSLLVQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSLLVQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSLLVQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSLLVQZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSLLVQZ128rr %xmm16, 14
%xmm16 = VPSLLVQZ128rr %xmm16, 14 %xmm16 = VPSLLVQZ128rr %xmm16, 14
; CHECK: %xmm16 = VPSLLWZ128ri %xmm16, 7 ; CHECK: %xmm16 = VPSLLWZ128ri %xmm16, 7
%xmm16 = VPSLLWZ128ri %xmm16, 7 %xmm16 = VPSLLWZ128ri %xmm16, 7
; CHECK: %xmm16 = VPSLLWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSLLWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSLLWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSLLWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSLLWZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSLLWZ128rr %xmm16, 14
%xmm16 = VPSLLWZ128rr %xmm16, 14 %xmm16 = VPSLLWZ128rr %xmm16, 14
; CHECK: %xmm16 = VPSRADZ128ri %xmm16, 7 ; CHECK: %xmm16 = VPSRADZ128ri %xmm16, 7
%xmm16 = VPSRADZ128ri %xmm16, 7 %xmm16 = VPSRADZ128ri %xmm16, 7
; CHECK: %xmm16 = VPSRADZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSRADZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSRADZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSRADZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSRADZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSRADZ128rr %xmm16, 14
%xmm16 = VPSRADZ128rr %xmm16, 14 %xmm16 = VPSRADZ128rr %xmm16, 14
; CHECK: %xmm16 = VPSRAVDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSRAVDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSRAVDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSRAVDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSRAVDZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSRAVDZ128rr %xmm16, 14
%xmm16 = VPSRAVDZ128rr %xmm16, 14 %xmm16 = VPSRAVDZ128rr %xmm16, 14
; CHECK: %xmm16 = VPSRAWZ128ri %xmm16, 7 ; CHECK: %xmm16 = VPSRAWZ128ri %xmm16, 7
%xmm16 = VPSRAWZ128ri %xmm16, 7 %xmm16 = VPSRAWZ128ri %xmm16, 7
; CHECK: %xmm16 = VPSRAWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSRAWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSRAWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSRAWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSRAWZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSRAWZ128rr %xmm16, 14
%xmm16 = VPSRAWZ128rr %xmm16, 14 %xmm16 = VPSRAWZ128rr %xmm16, 14
; CHECK: %xmm16 = VPSRLDQZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSRLDQZ128rr %xmm16, 14
%xmm16 = VPSRLDQZ128rr %xmm16, 14 %xmm16 = VPSRLDQZ128rr %xmm16, 14
; CHECK: %xmm16 = VPSRLDZ128ri %xmm16, 7 ; CHECK: %xmm16 = VPSRLDZ128ri %xmm16, 7
%xmm16 = VPSRLDZ128ri %xmm16, 7 %xmm16 = VPSRLDZ128ri %xmm16, 7
; CHECK: %xmm16 = VPSRLDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSRLDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSRLDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSRLDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSRLDZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSRLDZ128rr %xmm16, 14
%xmm16 = VPSRLDZ128rr %xmm16, 14 %xmm16 = VPSRLDZ128rr %xmm16, 14
; CHECK: %xmm16 = VPSRLQZ128ri %xmm16, 7 ; CHECK: %xmm16 = VPSRLQZ128ri %xmm16, 7
%xmm16 = VPSRLQZ128ri %xmm16, 7 %xmm16 = VPSRLQZ128ri %xmm16, 7
; CHECK: %xmm16 = VPSRLQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSRLQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSRLQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSRLQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSRLQZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSRLQZ128rr %xmm16, 14
%xmm16 = VPSRLQZ128rr %xmm16, 14 %xmm16 = VPSRLQZ128rr %xmm16, 14
; CHECK: %xmm16 = VPSRLVDZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSRLVDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSRLVDZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSRLVDZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSRLVDZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSRLVDZ128rr %xmm16, 14
%xmm16 = VPSRLVDZ128rr %xmm16, 14 %xmm16 = VPSRLVDZ128rr %xmm16, 14
; CHECK: %xmm16 = VPSRLVQZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSRLVQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSRLVQZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSRLVQZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSRLVQZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSRLVQZ128rr %xmm16, 14
%xmm16 = VPSRLVQZ128rr %xmm16, 14 %xmm16 = VPSRLVQZ128rr %xmm16, 14
; CHECK: %xmm16 = VPSRLWZ128ri %xmm16, 7 ; CHECK: %xmm16 = VPSRLWZ128ri %xmm16, 7
%xmm16 = VPSRLWZ128ri %xmm16, 7 %xmm16 = VPSRLWZ128ri %xmm16, 7
; CHECK: %xmm16 = VPSRLWZ128rm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPSRLWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPSRLWZ128rm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VPSRLWZ128rm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPSRLWZ128rr %xmm16, 14 ; CHECK: %xmm16 = VPSRLWZ128rr %xmm16, 14
%xmm16 = VPSRLWZ128rr %xmm16, 14 %xmm16 = VPSRLWZ128rr %xmm16, 14
; CHECK: %xmm16 = VPERMILPDZ128mi %rdi, 1, _, 0, _, _ ; CHECK: %xmm16 = VPERMILPDZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
%xmm16 = VPERMILPDZ128mi %rdi, 1, _, 0, _, _ %xmm16 = VPERMILPDZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm16 = VPERMILPDZ128ri %xmm16, 9 ; CHECK: %xmm16 = VPERMILPDZ128ri %xmm16, 9
%xmm16 = VPERMILPDZ128ri %xmm16, 9 %xmm16 = VPERMILPDZ128ri %xmm16, 9
; CHECK: %xmm16 = VPERMILPDZ128rm %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VPERMILPDZ128rm %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VPERMILPDZ128rm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VPERMILPDZ128rm %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VPERMILPDZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPERMILPDZ128rr %xmm16, %xmm1
%xmm16 = VPERMILPDZ128rr %xmm16, %xmm1 %xmm16 = VPERMILPDZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPERMILPSZ128mi %rdi, 1, _, 0, _, _ ; CHECK: %xmm16 = VPERMILPSZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
%xmm16 = VPERMILPSZ128mi %rdi, 1, _, 0, _, _ %xmm16 = VPERMILPSZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm16 = VPERMILPSZ128ri %xmm16, 9 ; CHECK: %xmm16 = VPERMILPSZ128ri %xmm16, 9
%xmm16 = VPERMILPSZ128ri %xmm16, 9 %xmm16 = VPERMILPSZ128ri %xmm16, 9
; CHECK: %xmm16 = VPERMILPSZ128rm %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VPERMILPSZ128rm %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VPERMILPSZ128rm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VPERMILPSZ128rm %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VPERMILPSZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPERMILPSZ128rr %xmm16, %xmm1
%xmm16 = VPERMILPSZ128rr %xmm16, %xmm1 %xmm16 = VPERMILPSZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VCVTPH2PSZ128rm %rdi, %xmm16, 1, _, 0 ; CHECK: %xmm16 = VCVTPH2PSZ128rm %rdi, %xmm16, 1, %noreg, 0
%xmm16 = VCVTPH2PSZ128rm %rdi, %xmm16, 1, _, 0 %xmm16 = VCVTPH2PSZ128rm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %xmm16 = VCVTPH2PSZ128rr %xmm16 ; CHECK: %xmm16 = VCVTPH2PSZ128rr %xmm16
%xmm16 = VCVTPH2PSZ128rr %xmm16 %xmm16 = VCVTPH2PSZ128rr %xmm16
; CHECK: %xmm16 = VCVTDQ2PDZ128rm %rdi, %xmm16, 1, _, 0 ; CHECK: %xmm16 = VCVTDQ2PDZ128rm %rdi, %xmm16, 1, %noreg, 0
%xmm16 = VCVTDQ2PDZ128rm %rdi, %xmm16, 1, _, 0 %xmm16 = VCVTDQ2PDZ128rm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %xmm16 = VCVTDQ2PDZ128rr %xmm16 ; CHECK: %xmm16 = VCVTDQ2PDZ128rr %xmm16
%xmm16 = VCVTDQ2PDZ128rr %xmm16 %xmm16 = VCVTDQ2PDZ128rr %xmm16
; CHECK: %xmm16 = VCVTDQ2PSZ128rm %rdi, %xmm16, 1, _, 0 ; CHECK: %xmm16 = VCVTDQ2PSZ128rm %rdi, %xmm16, 1, %noreg, 0
%xmm16 = VCVTDQ2PSZ128rm %rdi, %xmm16, 1, _, 0 %xmm16 = VCVTDQ2PSZ128rm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %xmm16 = VCVTDQ2PSZ128rr %xmm16 ; CHECK: %xmm16 = VCVTDQ2PSZ128rr %xmm16
%xmm16 = VCVTDQ2PSZ128rr %xmm16 %xmm16 = VCVTDQ2PSZ128rr %xmm16
; CHECK: %xmm16 = VCVTPD2DQZ128rm %rdi, %xmm16, 1, _, 0 ; CHECK: %xmm16 = VCVTPD2DQZ128rm %rdi, %xmm16, 1, %noreg, 0
%xmm16 = VCVTPD2DQZ128rm %rdi, %xmm16, 1, _, 0 %xmm16 = VCVTPD2DQZ128rm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %xmm16 = VCVTPD2DQZ128rr %xmm16 ; CHECK: %xmm16 = VCVTPD2DQZ128rr %xmm16
%xmm16 = VCVTPD2DQZ128rr %xmm16 %xmm16 = VCVTPD2DQZ128rr %xmm16
; CHECK: %xmm16 = VCVTPD2PSZ128rm %rdi, %xmm16, 1, _, 0 ; CHECK: %xmm16 = VCVTPD2PSZ128rm %rdi, %xmm16, 1, %noreg, 0
%xmm16 = VCVTPD2PSZ128rm %rdi, %xmm16, 1, _, 0 %xmm16 = VCVTPD2PSZ128rm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %xmm16 = VCVTPD2PSZ128rr %xmm16 ; CHECK: %xmm16 = VCVTPD2PSZ128rr %xmm16
%xmm16 = VCVTPD2PSZ128rr %xmm16 %xmm16 = VCVTPD2PSZ128rr %xmm16
; CHECK: %xmm16 = VCVTPS2DQZ128rm %rdi, %xmm16, 1, _, 0 ; CHECK: %xmm16 = VCVTPS2DQZ128rm %rdi, %xmm16, 1, %noreg, 0
%xmm16 = VCVTPS2DQZ128rm %rdi, %xmm16, 1, _, 0 %xmm16 = VCVTPS2DQZ128rm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %xmm16 = VCVTPS2DQZ128rr %xmm16 ; CHECK: %xmm16 = VCVTPS2DQZ128rr %xmm16
%xmm16 = VCVTPS2DQZ128rr %xmm16 %xmm16 = VCVTPS2DQZ128rr %xmm16
; CHECK: %xmm16 = VCVTPS2PDZ128rm %rdi, %xmm16, 1, _, 0 ; CHECK: %xmm16 = VCVTPS2PDZ128rm %rdi, %xmm16, 1, %noreg, 0
%xmm16 = VCVTPS2PDZ128rm %rdi, %xmm16, 1, _, 0 %xmm16 = VCVTPS2PDZ128rm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %xmm16 = VCVTPS2PDZ128rr %xmm16 ; CHECK: %xmm16 = VCVTPS2PDZ128rr %xmm16
%xmm16 = VCVTPS2PDZ128rr %xmm16 %xmm16 = VCVTPS2PDZ128rr %xmm16
; CHECK: %xmm16 = VCVTTPD2DQZ128rm %rdi, %xmm16, 1, _, 0 ; CHECK: %xmm16 = VCVTTPD2DQZ128rm %rdi, %xmm16, 1, %noreg, 0
%xmm16 = VCVTTPD2DQZ128rm %rdi, %xmm16, 1, _, 0 %xmm16 = VCVTTPD2DQZ128rm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %xmm16 = VCVTTPD2DQZ128rr %xmm16 ; CHECK: %xmm16 = VCVTTPD2DQZ128rr %xmm16
%xmm16 = VCVTTPD2DQZ128rr %xmm16 %xmm16 = VCVTTPD2DQZ128rr %xmm16
; CHECK: %xmm16 = VCVTTPS2DQZ128rm %rdi, %xmm16, 1, _, 0 ; CHECK: %xmm16 = VCVTTPS2DQZ128rm %rdi, %xmm16, 1, %noreg, 0
%xmm16 = VCVTTPS2DQZ128rm %rdi, %xmm16, 1, _, 0 %xmm16 = VCVTTPS2DQZ128rm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %xmm16 = VCVTTPS2DQZ128rr %xmm16 ; CHECK: %xmm16 = VCVTTPS2DQZ128rr %xmm16
%xmm16 = VCVTTPS2DQZ128rr %xmm16 %xmm16 = VCVTTPS2DQZ128rr %xmm16
; CHECK: %xmm16 = VSQRTPDZ128m %rdi, _, _, _, _ ; CHECK: %xmm16 = VSQRTPDZ128m %rdi, %noreg, %noreg, %noreg, %noreg
%xmm16 = VSQRTPDZ128m %rdi, _, _, _, _ %xmm16 = VSQRTPDZ128m %rdi, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VSQRTPDZ128r %xmm16 ; CHECK: %xmm16 = VSQRTPDZ128r %xmm16
%xmm16 = VSQRTPDZ128r %xmm16 %xmm16 = VSQRTPDZ128r %xmm16
; CHECK: %xmm16 = VSQRTPSZ128m %rdi, _, _, _, _ ; CHECK: %xmm16 = VSQRTPSZ128m %rdi, %noreg, %noreg, %noreg, %noreg
%xmm16 = VSQRTPSZ128m %rdi, _, _, _, _ %xmm16 = VSQRTPSZ128m %rdi, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VSQRTPSZ128r %xmm16 ; CHECK: %xmm16 = VSQRTPSZ128r %xmm16
%xmm16 = VSQRTPSZ128r %xmm16 %xmm16 = VSQRTPSZ128r %xmm16
; CHECK: %xmm16 = VMOVDDUPZ128rm %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VMOVDDUPZ128rm %rdi, 1, %noreg, 0, %noreg
%xmm16 = VMOVDDUPZ128rm %rdi, 1, _, 0, _ %xmm16 = VMOVDDUPZ128rm %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VMOVDDUPZ128rr %xmm16 ; CHECK: %xmm16 = VMOVDDUPZ128rr %xmm16
%xmm16 = VMOVDDUPZ128rr %xmm16 %xmm16 = VMOVDDUPZ128rr %xmm16
; CHECK: %xmm16 = VMOVSHDUPZ128rm %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VMOVSHDUPZ128rm %rdi, 1, %noreg, 0, %noreg
%xmm16 = VMOVSHDUPZ128rm %rdi, 1, _, 0, _ %xmm16 = VMOVSHDUPZ128rm %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VMOVSHDUPZ128rr %xmm16 ; CHECK: %xmm16 = VMOVSHDUPZ128rr %xmm16
%xmm16 = VMOVSHDUPZ128rr %xmm16 %xmm16 = VMOVSHDUPZ128rr %xmm16
; CHECK: %xmm16 = VMOVSLDUPZ128rm %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VMOVSLDUPZ128rm %rdi, 1, %noreg, 0, %noreg
%xmm16 = VMOVSLDUPZ128rm %rdi, 1, _, 0, _ %xmm16 = VMOVSLDUPZ128rm %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VMOVSLDUPZ128rr %xmm16 ; CHECK: %xmm16 = VMOVSLDUPZ128rr %xmm16
%xmm16 = VMOVSLDUPZ128rr %xmm16 %xmm16 = VMOVSLDUPZ128rr %xmm16
; CHECK: %xmm16 = VPSHUFBZ128rm %xmm16, _, _, _, _, _ ; CHECK: %xmm16 = VPSHUFBZ128rm %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm16 = VPSHUFBZ128rm %xmm16, _, _, _, _, _ %xmm16 = VPSHUFBZ128rm %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VPSHUFBZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPSHUFBZ128rr %xmm16, %xmm1
%xmm16 = VPSHUFBZ128rr %xmm16, %xmm1 %xmm16 = VPSHUFBZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VPSHUFDZ128mi %rdi, 1, _, 0, _, _ ; CHECK: %xmm16 = VPSHUFDZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
%xmm16 = VPSHUFDZ128mi %rdi, 1, _, 0, _, _ %xmm16 = VPSHUFDZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm16 = VPSHUFDZ128ri %xmm16, -24 ; CHECK: %xmm16 = VPSHUFDZ128ri %xmm16, -24
%xmm16 = VPSHUFDZ128ri %xmm16, -24 %xmm16 = VPSHUFDZ128ri %xmm16, -24
; CHECK: %xmm16 = VPSHUFHWZ128mi %rdi, 1, _, 0, _, _ ; CHECK: %xmm16 = VPSHUFHWZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
%xmm16 = VPSHUFHWZ128mi %rdi, 1, _, 0, _, _ %xmm16 = VPSHUFHWZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm16 = VPSHUFHWZ128ri %xmm16, -24 ; CHECK: %xmm16 = VPSHUFHWZ128ri %xmm16, -24
%xmm16 = VPSHUFHWZ128ri %xmm16, -24 %xmm16 = VPSHUFHWZ128ri %xmm16, -24
; CHECK: %xmm16 = VPSHUFLWZ128mi %rdi, 1, _, 0, _, _ ; CHECK: %xmm16 = VPSHUFLWZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
%xmm16 = VPSHUFLWZ128mi %rdi, 1, _, 0, _, _ %xmm16 = VPSHUFLWZ128mi %rdi, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm16 = VPSHUFLWZ128ri %xmm16, -24 ; CHECK: %xmm16 = VPSHUFLWZ128ri %xmm16, -24
%xmm16 = VPSHUFLWZ128ri %xmm16, -24 %xmm16 = VPSHUFLWZ128ri %xmm16, -24
; CHECK: %xmm16 = VPSLLDQZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPSLLDQZ128rr %xmm16, %xmm1
%xmm16 = VPSLLDQZ128rr %xmm16, %xmm1 %xmm16 = VPSLLDQZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VSHUFPDZ128rmi %xmm16, _, _, _, _, _, _ ; CHECK: %xmm16 = VSHUFPDZ128rmi %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm16 = VSHUFPDZ128rmi %xmm16, _, _, _, _, _, _ %xmm16 = VSHUFPDZ128rmi %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VSHUFPDZ128rri %xmm16, _, _ ; CHECK: %xmm16 = VSHUFPDZ128rri %xmm16, %noreg, %noreg
%xmm16 = VSHUFPDZ128rri %xmm16, _, _ %xmm16 = VSHUFPDZ128rri %xmm16, %noreg, %noreg
; CHECK: %xmm16 = VSHUFPSZ128rmi %xmm16, _, _, _, _, _, _ ; CHECK: %xmm16 = VSHUFPSZ128rmi %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm16 = VSHUFPSZ128rmi %xmm16, _, _, _, _, _, _ %xmm16 = VSHUFPSZ128rmi %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VSHUFPSZ128rri %xmm16, _, _ ; CHECK: %xmm16 = VSHUFPSZ128rri %xmm16, %noreg, %noreg
%xmm16 = VSHUFPSZ128rri %xmm16, _, _ %xmm16 = VSHUFPSZ128rri %xmm16, %noreg, %noreg
; CHECK: %xmm16 = VPSADBWZ128rm %xmm16, 1, _, %rax, _, _ ; CHECK: %xmm16 = VPSADBWZ128rm %xmm16, 1, %noreg, %rax, %noreg, %noreg
%xmm16 = VPSADBWZ128rm %xmm16, 1, _, %rax, _, _ %xmm16 = VPSADBWZ128rm %xmm16, 1, %noreg, %rax, %noreg, %noreg
; CHECK: %xmm16 = VPSADBWZ128rr %xmm16, %xmm1 ; CHECK: %xmm16 = VPSADBWZ128rr %xmm16, %xmm1
%xmm16 = VPSADBWZ128rr %xmm16, %xmm1 %xmm16 = VPSADBWZ128rr %xmm16, %xmm1
; CHECK: %xmm16 = VBROADCASTSSZ128m %rip, _, _, _, _ ; CHECK: %xmm16 = VBROADCASTSSZ128m %rip, %noreg, %noreg, %noreg, %noreg
%xmm16 = VBROADCASTSSZ128m %rip, _, _, _, _ %xmm16 = VBROADCASTSSZ128m %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VBROADCASTSSZ128r %xmm16 ; CHECK: %xmm16 = VBROADCASTSSZ128r %xmm16
%xmm16 = VBROADCASTSSZ128r %xmm16 %xmm16 = VBROADCASTSSZ128r %xmm16
; CHECK: %xmm16 = VPBROADCASTBZ128m %rip, _, _, _, _ ; CHECK: %xmm16 = VPBROADCASTBZ128m %rip, %noreg, %noreg, %noreg, %noreg
%xmm16 = VPBROADCASTBZ128m %rip, _, _, _, _ %xmm16 = VPBROADCASTBZ128m %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VPBROADCASTBZ128r %xmm16 ; CHECK: %xmm16 = VPBROADCASTBZ128r %xmm16
%xmm16 = VPBROADCASTBZ128r %xmm16 %xmm16 = VPBROADCASTBZ128r %xmm16
; CHECK: %xmm16 = VPBROADCASTDZ128m %rip, _, _, _, _ ; CHECK: %xmm16 = VPBROADCASTDZ128m %rip, %noreg, %noreg, %noreg, %noreg
%xmm16 = VPBROADCASTDZ128m %rip, _, _, _, _ %xmm16 = VPBROADCASTDZ128m %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VPBROADCASTDZ128r %xmm16 ; CHECK: %xmm16 = VPBROADCASTDZ128r %xmm16
%xmm16 = VPBROADCASTDZ128r %xmm16 %xmm16 = VPBROADCASTDZ128r %xmm16
; CHECK: %xmm16 = VPBROADCASTQZ128m %rip, _, _, _, _ ; CHECK: %xmm16 = VPBROADCASTQZ128m %rip, %noreg, %noreg, %noreg, %noreg
%xmm16 = VPBROADCASTQZ128m %rip, _, _, _, _ %xmm16 = VPBROADCASTQZ128m %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VPBROADCASTQZ128r %xmm16 ; CHECK: %xmm16 = VPBROADCASTQZ128r %xmm16
%xmm16 = VPBROADCASTQZ128r %xmm16 %xmm16 = VPBROADCASTQZ128r %xmm16
; CHECK: %xmm16 = VPBROADCASTWZ128m %rip, _, _, _, _ ; CHECK: %xmm16 = VPBROADCASTWZ128m %rip, %noreg, %noreg, %noreg, %noreg
%xmm16 = VPBROADCASTWZ128m %rip, _, _, _, _ %xmm16 = VPBROADCASTWZ128m %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VPBROADCASTWZ128r %xmm16 ; CHECK: %xmm16 = VPBROADCASTWZ128r %xmm16
%xmm16 = VPBROADCASTWZ128r %xmm16 %xmm16 = VPBROADCASTWZ128r %xmm16
; CHECK: %xmm16 = VBROADCASTI32X2Z128m %rip, _, _, _, _ ; CHECK: %xmm16 = VBROADCASTI32X2Z128m %rip, %noreg, %noreg, %noreg, %noreg
%xmm16 = VBROADCASTI32X2Z128m %rip, _, _, _, _ %xmm16 = VBROADCASTI32X2Z128m %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VBROADCASTI32X2Z128r %xmm0 ; CHECK: %xmm16 = VBROADCASTI32X2Z128r %xmm0
%xmm16 = VBROADCASTI32X2Z128r %xmm0 %xmm16 = VBROADCASTI32X2Z128r %xmm0
; CHECK: %xmm16 = VCVTPS2PHZ128rr %xmm16, 2 ; CHECK: %xmm16 = VCVTPS2PHZ128rr %xmm16, 2
%xmm16 = VCVTPS2PHZ128rr %xmm16, 2 %xmm16 = VCVTPS2PHZ128rr %xmm16, 2
; CHECK: VCVTPS2PHZ128mr %rdi, %xmm16, 1, _, 0, _, _ ; CHECK: VCVTPS2PHZ128mr %rdi, %xmm16, 1, %noreg, 0, %noreg, %noreg
VCVTPS2PHZ128mr %rdi, %xmm16, 1, _, 0, _, _ VCVTPS2PHZ128mr %rdi, %xmm16, 1, %noreg, 0, %noreg, %noreg
; CHECK: %xmm16 = VPABSBZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPABSBZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPABSBZ128rm %rip, 1, _, %rax, _ %xmm16 = VPABSBZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPABSBZ128rr %xmm16 ; CHECK: %xmm16 = VPABSBZ128rr %xmm16
%xmm16 = VPABSBZ128rr %xmm16 %xmm16 = VPABSBZ128rr %xmm16
; CHECK: %xmm16 = VPABSDZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPABSDZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPABSDZ128rm %rip, 1, _, %rax, _ %xmm16 = VPABSDZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPABSDZ128rr %xmm16 ; CHECK: %xmm16 = VPABSDZ128rr %xmm16
%xmm16 = VPABSDZ128rr %xmm16 %xmm16 = VPABSDZ128rr %xmm16
; CHECK: %xmm16 = VPABSWZ128rm %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VPABSWZ128rm %rip, 1, %noreg, %rax, %noreg
%xmm16 = VPABSWZ128rm %rip, 1, _, %rax, _ %xmm16 = VPABSWZ128rm %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VPABSWZ128rr %xmm16 ; CHECK: %xmm16 = VPABSWZ128rr %xmm16
%xmm16 = VPABSWZ128rr %xmm16 %xmm16 = VPABSWZ128rr %xmm16
; CHECK: %xmm16 = VPALIGNRZ128rmi %xmm16, _, _, _, _, _, _ ; CHECK: %xmm16 = VPALIGNRZ128rmi %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm16 = VPALIGNRZ128rmi %xmm16, _, _, _, _, _, _ %xmm16 = VPALIGNRZ128rmi %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VPALIGNRZ128rri %xmm16, %xmm1, 15 ; CHECK: %xmm16 = VPALIGNRZ128rri %xmm16, %xmm1, 15
%xmm16 = VPALIGNRZ128rri %xmm16, %xmm1, 15 %xmm16 = VPALIGNRZ128rri %xmm16, %xmm1, 15
; CHECK: VEXTRACTPSZmr %rdi, 1, _, 0, _, %xmm16, _ ; CHECK: VEXTRACTPSZmr %rdi, 1, %noreg, 0, %noreg, %xmm16, %noreg
VEXTRACTPSZmr %rdi, 1, _, 0, _, %xmm16, _ VEXTRACTPSZmr %rdi, 1, %noreg, 0, %noreg, %xmm16, %noreg
; CHECK: %eax = VEXTRACTPSZrr %xmm16, _ ; CHECK: %eax = VEXTRACTPSZrr %xmm16, %noreg
%eax = VEXTRACTPSZrr %xmm16, _ %eax = VEXTRACTPSZrr %xmm16, %noreg
; CHECK: %xmm16 = VINSERTPSZrm %xmm16, %rdi, _, _, _, _, _ ; CHECK: %xmm16 = VINSERTPSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm16 = VINSERTPSZrm %xmm16, %rdi, _, _, _, _, _ %xmm16 = VINSERTPSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VINSERTPSZrr %xmm16, %xmm16, _ ; CHECK: %xmm16 = VINSERTPSZrr %xmm16, %xmm16, %noreg
%xmm16 = VINSERTPSZrr %xmm16, %xmm16, _ %xmm16 = VINSERTPSZrr %xmm16, %xmm16, %noreg
RET 0, %zmm0, %zmm1 RET 0, %zmm0, %zmm1
... ...
--- ---
# CHECK-LABEL: name: evex_scalar_to_evex_test # CHECK-LABEL: name: evex_scalar_to_evex_test
# CHECK: bb.0: # CHECK: bb.0:
name: evex_scalar_to_evex_test name: evex_scalar_to_evex_test
body: | body: |
bb.0: bb.0:
; CHECK: %xmm16 = VADDSDZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VADDSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VADDSDZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VADDSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VADDSDZrm_Int %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VADDSDZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VADDSDZrm_Int %xmm16, %rip, 1, _, %rax, _ %xmm16 = VADDSDZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VADDSDZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VADDSDZrr %xmm16, %xmm1
%xmm16 = VADDSDZrr %xmm16, %xmm1 %xmm16 = VADDSDZrr %xmm16, %xmm1
; CHECK: %xmm16 = VADDSDZrr_Int %xmm16, %xmm1 ; CHECK: %xmm16 = VADDSDZrr_Int %xmm16, %xmm1
%xmm16 = VADDSDZrr_Int %xmm16, %xmm1 %xmm16 = VADDSDZrr_Int %xmm16, %xmm1
; CHECK: %xmm16 = VADDSSZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VADDSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VADDSSZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VADDSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VADDSSZrm_Int %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VADDSSZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VADDSSZrm_Int %xmm16, %rip, 1, _, %rax, _ %xmm16 = VADDSSZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VADDSSZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VADDSSZrr %xmm16, %xmm1
%xmm16 = VADDSSZrr %xmm16, %xmm1 %xmm16 = VADDSSZrr %xmm16, %xmm1
; CHECK: %xmm16 = VADDSSZrr_Int %xmm16, %xmm1 ; CHECK: %xmm16 = VADDSSZrr_Int %xmm16, %xmm1
%xmm16 = VADDSSZrr_Int %xmm16, %xmm1 %xmm16 = VADDSSZrr_Int %xmm16, %xmm1
; CHECK: %xmm16 = VDIVSDZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VDIVSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VDIVSDZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VDIVSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VDIVSDZrm_Int %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VDIVSDZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VDIVSDZrm_Int %xmm16, %rip, 1, _, %rax, _ %xmm16 = VDIVSDZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VDIVSDZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VDIVSDZrr %xmm16, %xmm1
%xmm16 = VDIVSDZrr %xmm16, %xmm1 %xmm16 = VDIVSDZrr %xmm16, %xmm1
; CHECK: %xmm16 = VDIVSDZrr_Int %xmm16, %xmm1 ; CHECK: %xmm16 = VDIVSDZrr_Int %xmm16, %xmm1
%xmm16 = VDIVSDZrr_Int %xmm16, %xmm1 %xmm16 = VDIVSDZrr_Int %xmm16, %xmm1
; CHECK: %xmm16 = VDIVSSZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VDIVSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VDIVSSZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VDIVSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VDIVSSZrm_Int %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VDIVSSZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VDIVSSZrm_Int %xmm16, %rip, 1, _, %rax, _ %xmm16 = VDIVSSZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VDIVSSZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VDIVSSZrr %xmm16, %xmm1
%xmm16 = VDIVSSZrr %xmm16, %xmm1 %xmm16 = VDIVSSZrr %xmm16, %xmm1
; CHECK: %xmm16 = VDIVSSZrr_Int %xmm16, %xmm1 ; CHECK: %xmm16 = VDIVSSZrr_Int %xmm16, %xmm1
%xmm16 = VDIVSSZrr_Int %xmm16, %xmm1 %xmm16 = VDIVSSZrr_Int %xmm16, %xmm1
; CHECK: %xmm16 = VMAXCSDZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMAXCSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMAXCSDZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMAXCSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMAXCSDZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VMAXCSDZrr %xmm16, %xmm1
%xmm16 = VMAXCSDZrr %xmm16, %xmm1 %xmm16 = VMAXCSDZrr %xmm16, %xmm1
; CHECK: %xmm16 = VMAXCSSZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMAXCSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMAXCSSZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMAXCSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMAXCSSZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VMAXCSSZrr %xmm16, %xmm1
%xmm16 = VMAXCSSZrr %xmm16, %xmm1 %xmm16 = VMAXCSSZrr %xmm16, %xmm1
; CHECK: %xmm16 = VMAXSDZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMAXSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMAXSDZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMAXSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMAXSDZrm_Int %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMAXSDZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMAXSDZrm_Int %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMAXSDZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMAXSDZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VMAXSDZrr %xmm16, %xmm1
%xmm16 = VMAXSDZrr %xmm16, %xmm1 %xmm16 = VMAXSDZrr %xmm16, %xmm1
; CHECK: %xmm16 = VMAXSDZrr_Int %xmm16, %xmm1 ; CHECK: %xmm16 = VMAXSDZrr_Int %xmm16, %xmm1
%xmm16 = VMAXSDZrr_Int %xmm16, %xmm1 %xmm16 = VMAXSDZrr_Int %xmm16, %xmm1
; CHECK: %xmm16 = VMAXSSZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMAXSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMAXSSZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMAXSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMAXSSZrm_Int %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMAXSSZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMAXSSZrm_Int %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMAXSSZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMAXSSZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VMAXSSZrr %xmm16, %xmm1
%xmm16 = VMAXSSZrr %xmm16, %xmm1 %xmm16 = VMAXSSZrr %xmm16, %xmm1
; CHECK: %xmm16 = VMAXSSZrr_Int %xmm16, %xmm1 ; CHECK: %xmm16 = VMAXSSZrr_Int %xmm16, %xmm1
%xmm16 = VMAXSSZrr_Int %xmm16, %xmm1 %xmm16 = VMAXSSZrr_Int %xmm16, %xmm1
; CHECK: %xmm16 = VMINCSDZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMINCSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMINCSDZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMINCSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMINCSDZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VMINCSDZrr %xmm16, %xmm1
%xmm16 = VMINCSDZrr %xmm16, %xmm1 %xmm16 = VMINCSDZrr %xmm16, %xmm1
; CHECK: %xmm16 = VMINCSSZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMINCSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMINCSSZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMINCSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMINCSSZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VMINCSSZrr %xmm16, %xmm1
%xmm16 = VMINCSSZrr %xmm16, %xmm1 %xmm16 = VMINCSSZrr %xmm16, %xmm1
; CHECK: %xmm16 = VMINSDZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMINSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMINSDZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMINSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMINSDZrm_Int %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMINSDZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMINSDZrm_Int %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMINSDZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMINSDZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VMINSDZrr %xmm16, %xmm1
%xmm16 = VMINSDZrr %xmm16, %xmm1 %xmm16 = VMINSDZrr %xmm16, %xmm1
; CHECK: %xmm16 = VMINSDZrr_Int %xmm16, %xmm1 ; CHECK: %xmm16 = VMINSDZrr_Int %xmm16, %xmm1
%xmm16 = VMINSDZrr_Int %xmm16, %xmm1 %xmm16 = VMINSDZrr_Int %xmm16, %xmm1
; CHECK: %xmm16 = VMINSSZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMINSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMINSSZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMINSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMINSSZrm_Int %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMINSSZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMINSSZrm_Int %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMINSSZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMINSSZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VMINSSZrr %xmm16, %xmm1
%xmm16 = VMINSSZrr %xmm16, %xmm1 %xmm16 = VMINSSZrr %xmm16, %xmm1
; CHECK: %xmm16 = VMINSSZrr_Int %xmm16, %xmm1 ; CHECK: %xmm16 = VMINSSZrr_Int %xmm16, %xmm1
%xmm16 = VMINSSZrr_Int %xmm16, %xmm1 %xmm16 = VMINSSZrr_Int %xmm16, %xmm1
; CHECK: %xmm16 = VMULSDZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMULSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMULSDZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMULSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMULSDZrm_Int %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMULSDZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMULSDZrm_Int %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMULSDZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMULSDZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VMULSDZrr %xmm16, %xmm1
%xmm16 = VMULSDZrr %xmm16, %xmm1 %xmm16 = VMULSDZrr %xmm16, %xmm1
; CHECK: %xmm16 = VMULSDZrr_Int %xmm16, %xmm1 ; CHECK: %xmm16 = VMULSDZrr_Int %xmm16, %xmm1
%xmm16 = VMULSDZrr_Int %xmm16, %xmm1 %xmm16 = VMULSDZrr_Int %xmm16, %xmm1
; CHECK: %xmm16 = VMULSSZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMULSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMULSSZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMULSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMULSSZrm_Int %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VMULSSZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VMULSSZrm_Int %xmm16, %rip, 1, _, %rax, _ %xmm16 = VMULSSZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VMULSSZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VMULSSZrr %xmm16, %xmm1
%xmm16 = VMULSSZrr %xmm16, %xmm1 %xmm16 = VMULSSZrr %xmm16, %xmm1
; CHECK: %xmm16 = VMULSSZrr_Int %xmm16, %xmm1 ; CHECK: %xmm16 = VMULSSZrr_Int %xmm16, %xmm1
%xmm16 = VMULSSZrr_Int %xmm16, %xmm1 %xmm16 = VMULSSZrr_Int %xmm16, %xmm1
; CHECK: %xmm16 = VSUBSDZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VSUBSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VSUBSDZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VSUBSDZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VSUBSDZrm_Int %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VSUBSDZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VSUBSDZrm_Int %xmm16, %rip, 1, _, %rax, _ %xmm16 = VSUBSDZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VSUBSDZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VSUBSDZrr %xmm16, %xmm1
%xmm16 = VSUBSDZrr %xmm16, %xmm1 %xmm16 = VSUBSDZrr %xmm16, %xmm1
; CHECK: %xmm16 = VSUBSDZrr_Int %xmm16, %xmm1 ; CHECK: %xmm16 = VSUBSDZrr_Int %xmm16, %xmm1
%xmm16 = VSUBSDZrr_Int %xmm16, %xmm1 %xmm16 = VSUBSDZrr_Int %xmm16, %xmm1
; CHECK: %xmm16 = VSUBSSZrm %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VSUBSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VSUBSSZrm %xmm16, %rip, 1, _, %rax, _ %xmm16 = VSUBSSZrm %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VSUBSSZrm_Int %xmm16, %rip, 1, _, %rax, _ ; CHECK: %xmm16 = VSUBSSZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
%xmm16 = VSUBSSZrm_Int %xmm16, %rip, 1, _, %rax, _ %xmm16 = VSUBSSZrm_Int %xmm16, %rip, 1, %noreg, %rax, %noreg
; CHECK: %xmm16 = VSUBSSZrr %xmm16, %xmm1 ; CHECK: %xmm16 = VSUBSSZrr %xmm16, %xmm1
%xmm16 = VSUBSSZrr %xmm16, %xmm1 %xmm16 = VSUBSSZrr %xmm16, %xmm1
; CHECK: %xmm16 = VSUBSSZrr_Int %xmm16, %xmm1 ; CHECK: %xmm16 = VSUBSSZrr_Int %xmm16, %xmm1
%xmm16 = VSUBSSZrr_Int %xmm16, %xmm1 %xmm16 = VSUBSSZrr_Int %xmm16, %xmm1
; CHECK: %xmm16 = VFMADD132SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD132SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD132SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD132SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD132SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD132SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD132SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD132SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD132SDZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD132SDZr %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD132SDZr %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD132SDZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD132SDZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD132SDZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD132SDZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD132SDZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD132SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD132SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD132SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD132SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD132SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD132SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD132SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD132SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD132SSZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD132SSZr %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD132SSZr %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD132SSZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD132SSZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD132SSZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD132SSZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD132SSZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD213SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD213SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD213SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD213SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD213SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD213SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD213SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD213SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD213SDZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD213SDZr %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD213SDZr %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD213SDZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD213SDZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD213SDZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD213SDZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD213SDZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD213SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD213SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD213SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD213SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD213SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD213SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD213SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD213SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD213SSZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD213SSZr %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD213SSZr %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD213SSZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD213SSZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD213SSZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD213SSZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD213SSZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD231SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD231SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD231SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD231SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD231SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD231SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD231SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD231SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD231SDZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD231SDZr %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD231SDZr %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD231SDZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD231SDZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD231SDZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD231SDZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD231SDZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD231SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD231SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD231SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD231SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD231SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMADD231SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMADD231SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMADD231SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMADD231SSZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD231SSZr %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD231SSZr %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD231SSZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMADD231SSZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMADD231SSZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFMADD231SSZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFMADD231SSZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB132SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB132SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB132SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB132SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB132SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB132SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB132SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB132SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB132SDZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB132SDZr %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB132SDZr %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB132SDZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB132SDZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB132SDZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB132SDZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB132SDZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB132SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB132SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB132SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB132SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB132SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB132SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB132SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB132SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB132SSZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB132SSZr %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB132SSZr %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB132SSZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB132SSZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB132SSZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB132SSZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB132SSZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB213SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB213SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB213SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB213SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB213SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB213SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB213SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB213SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB213SDZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB213SDZr %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB213SDZr %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB213SDZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB213SDZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB213SDZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB213SDZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB213SDZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB213SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB213SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB213SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB213SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB213SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB213SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB213SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB213SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB213SSZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB213SSZr %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB213SSZr %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB213SSZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB213SSZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB213SSZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB213SSZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB213SSZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB231SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB231SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB231SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB231SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB231SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB231SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB231SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB231SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB231SDZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB231SDZr %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB231SDZr %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB231SDZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB231SDZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB231SDZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB231SDZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB231SDZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB231SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB231SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB231SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB231SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB231SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFMSUB231SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFMSUB231SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFMSUB231SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFMSUB231SSZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB231SSZr %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB231SSZr %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB231SSZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFMSUB231SSZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFMSUB231SSZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFMSUB231SSZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFMSUB231SSZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD132SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD132SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD132SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD132SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD132SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD132SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD132SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD132SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD132SDZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD132SDZr %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD132SDZr %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD132SDZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD132SDZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD132SDZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD132SDZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD132SDZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD132SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD132SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD132SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD132SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD132SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD132SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD132SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD132SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD132SSZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD132SSZr %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD132SSZr %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD132SSZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD132SSZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD132SSZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD132SSZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD132SSZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD213SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD213SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD213SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD213SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD213SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD213SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD213SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD213SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD213SDZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD213SDZr %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD213SDZr %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD213SDZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD213SDZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD213SDZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD213SDZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD213SDZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD213SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD213SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD213SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD213SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD213SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD213SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD213SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD213SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD213SSZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD213SSZr %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD213SSZr %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD213SSZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD213SSZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD213SSZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD213SSZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD213SSZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD231SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD231SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD231SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD231SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD231SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD231SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD231SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD231SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD231SDZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD231SDZr %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD231SDZr %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD231SDZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD231SDZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD231SDZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD231SDZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD231SDZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD231SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD231SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD231SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD231SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD231SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMADD231SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMADD231SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMADD231SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMADD231SSZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD231SSZr %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD231SSZr %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD231SSZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMADD231SSZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMADD231SSZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFNMADD231SSZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFNMADD231SSZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB132SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB132SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB132SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB132SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB132SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB132SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB132SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB132SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB132SDZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB132SDZr %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB132SDZr %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB132SDZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB132SDZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB132SDZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB132SDZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB132SDZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB132SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB132SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB132SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB132SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB132SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB132SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB132SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB132SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB132SSZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB132SSZr %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB132SSZr %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB132SSZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB132SSZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB132SSZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB132SSZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB132SSZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB213SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB213SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB213SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB213SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB213SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB213SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB213SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB213SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB213SDZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB213SDZr %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB213SDZr %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB213SDZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB213SDZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB213SDZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB213SDZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB213SDZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB213SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB213SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB213SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB213SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB213SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB213SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB213SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB213SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB213SSZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB213SSZr %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB213SSZr %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB213SSZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB213SSZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB213SSZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB213SSZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB213SSZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB231SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB231SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB231SDZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB231SDZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB231SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB231SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB231SDZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB231SDZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB231SDZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB231SDZr %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB231SDZr %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB231SDZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB231SDZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB231SDZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB231SDZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB231SDZr_Int %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB231SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB231SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB231SSZm %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB231SSZm %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB231SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ ; CHECK: %xmm16 = VFNMSUB231SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
%xmm16 = VFNMSUB231SSZm_Int %xmm16, %xmm16, %rsi, 1, _, 0, _ %xmm16 = VFNMSUB231SSZm_Int %xmm16, %xmm16, %rsi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VFNMSUB231SSZr %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB231SSZr %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB231SSZr %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB231SSZr %xmm16, %xmm1, %xmm2
; CHECK: %xmm16 = VFNMSUB231SSZr_Int %xmm16, %xmm1, %xmm2 ; CHECK: %xmm16 = VFNMSUB231SSZr_Int %xmm16, %xmm1, %xmm2
%xmm16 = VFNMSUB231SSZr_Int %xmm16, %xmm1, %xmm2 %xmm16 = VFNMSUB231SSZr_Int %xmm16, %xmm1, %xmm2
; CHECK: VPEXTRBZmr %rdi, 1, _, 0, _, %xmm16, 3 ; CHECK: VPEXTRBZmr %rdi, 1, %noreg, 0, %noreg, %xmm16, 3
VPEXTRBZmr %rdi, 1, _, 0, _, %xmm16, 3 VPEXTRBZmr %rdi, 1, %noreg, 0, %noreg, %xmm16, 3
; CHECK: %eax = VPEXTRBZrr %xmm16, 1 ; CHECK: %eax = VPEXTRBZrr %xmm16, 1
%eax = VPEXTRBZrr %xmm16, 1 %eax = VPEXTRBZrr %xmm16, 1
; CHECK: VPEXTRDZmr %rdi, 1, _, 0, _, %xmm16, 3 ; CHECK: VPEXTRDZmr %rdi, 1, %noreg, 0, %noreg, %xmm16, 3
VPEXTRDZmr %rdi, 1, _, 0, _, %xmm16, 3 VPEXTRDZmr %rdi, 1, %noreg, 0, %noreg, %xmm16, 3
; CHECK: %eax = VPEXTRDZrr %xmm16, 1 ; CHECK: %eax = VPEXTRDZrr %xmm16, 1
%eax = VPEXTRDZrr %xmm16, 1 %eax = VPEXTRDZrr %xmm16, 1
; CHECK: VPEXTRQZmr %rdi, 1, _, 0, _, %xmm16, 3 ; CHECK: VPEXTRQZmr %rdi, 1, %noreg, 0, %noreg, %xmm16, 3
VPEXTRQZmr %rdi, 1, _, 0, _, %xmm16, 3 VPEXTRQZmr %rdi, 1, %noreg, 0, %noreg, %xmm16, 3
; CHECK: %rax = VPEXTRQZrr %xmm16, 1 ; CHECK: %rax = VPEXTRQZrr %xmm16, 1
%rax = VPEXTRQZrr %xmm16, 1 %rax = VPEXTRQZrr %xmm16, 1
; CHECK: VPEXTRWZmr %rdi, 1, _, 0, _, %xmm16, 3 ; CHECK: VPEXTRWZmr %rdi, 1, %noreg, 0, %noreg, %xmm16, 3
VPEXTRWZmr %rdi, 1, _, 0, _, %xmm16, 3 VPEXTRWZmr %rdi, 1, %noreg, 0, %noreg, %xmm16, 3
; CHECK: %eax = VPEXTRWZrr %xmm16, 1 ; CHECK: %eax = VPEXTRWZrr %xmm16, 1
%eax = VPEXTRWZrr %xmm16, 1 %eax = VPEXTRWZrr %xmm16, 1
; CHECK: %eax = VPEXTRWZrr_REV %xmm16, 1 ; CHECK: %eax = VPEXTRWZrr_REV %xmm16, 1
%eax = VPEXTRWZrr_REV %xmm16, 1 %eax = VPEXTRWZrr_REV %xmm16, 1
; CHECK: %xmm16 = VPINSRBZrm %xmm16, %rsi, 1, _, 0, _, 3 ; CHECK: %xmm16 = VPINSRBZrm %xmm16, %rsi, 1, %noreg, 0, %noreg, 3
%xmm16 = VPINSRBZrm %xmm16, %rsi, 1, _, 0, _, 3 %xmm16 = VPINSRBZrm %xmm16, %rsi, 1, %noreg, 0, %noreg, 3
; CHECK: %xmm16 = VPINSRBZrr %xmm16, %edi, 5 ; CHECK: %xmm16 = VPINSRBZrr %xmm16, %edi, 5
%xmm16 = VPINSRBZrr %xmm16, %edi, 5 %xmm16 = VPINSRBZrr %xmm16, %edi, 5
; CHECK: %xmm16 = VPINSRDZrm %xmm16, %rsi, 1, _, 0, _, 3 ; CHECK: %xmm16 = VPINSRDZrm %xmm16, %rsi, 1, %noreg, 0, %noreg, 3
%xmm16 = VPINSRDZrm %xmm16, %rsi, 1, _, 0, _, 3 %xmm16 = VPINSRDZrm %xmm16, %rsi, 1, %noreg, 0, %noreg, 3
; CHECK: %xmm16 = VPINSRDZrr %xmm16, %edi, 5 ; CHECK: %xmm16 = VPINSRDZrr %xmm16, %edi, 5
%xmm16 = VPINSRDZrr %xmm16, %edi, 5 %xmm16 = VPINSRDZrr %xmm16, %edi, 5
; CHECK: %xmm16 = VPINSRQZrm %xmm16, %rsi, 1, _, 0, _, 3 ; CHECK: %xmm16 = VPINSRQZrm %xmm16, %rsi, 1, %noreg, 0, %noreg, 3
%xmm16 = VPINSRQZrm %xmm16, %rsi, 1, _, 0, _, 3 %xmm16 = VPINSRQZrm %xmm16, %rsi, 1, %noreg, 0, %noreg, 3
; CHECK: %xmm16 = VPINSRQZrr %xmm16, %rdi, 5 ; CHECK: %xmm16 = VPINSRQZrr %xmm16, %rdi, 5
%xmm16 = VPINSRQZrr %xmm16, %rdi, 5 %xmm16 = VPINSRQZrr %xmm16, %rdi, 5
; CHECK: %xmm16 = VPINSRWZrm %xmm16, %rsi, 1, _, 0, _, 3 ; CHECK: %xmm16 = VPINSRWZrm %xmm16, %rsi, 1, %noreg, 0, %noreg, 3
%xmm16 = VPINSRWZrm %xmm16, %rsi, 1, _, 0, _, 3 %xmm16 = VPINSRWZrm %xmm16, %rsi, 1, %noreg, 0, %noreg, 3
; CHECK: %xmm16 = VPINSRWZrr %xmm16, %edi, 5 ; CHECK: %xmm16 = VPINSRWZrr %xmm16, %edi, 5
%xmm16 = VPINSRWZrr %xmm16, %edi, 5 %xmm16 = VPINSRWZrr %xmm16, %edi, 5
; CHECK: %xmm16 = VSQRTSDZm %xmm16, _, _, _, _, _ ; CHECK: %xmm16 = VSQRTSDZm %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm16 = VSQRTSDZm %xmm16, _, _, _, _, _ %xmm16 = VSQRTSDZm %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VSQRTSDZm_Int %xmm16, _, _, _, _, _ ; CHECK: %xmm16 = VSQRTSDZm_Int %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm16 = VSQRTSDZm_Int %xmm16, _, _, _, _, _ %xmm16 = VSQRTSDZm_Int %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VSQRTSDZr %xmm16, _ ; CHECK: %xmm16 = VSQRTSDZr %xmm16, %noreg
%xmm16 = VSQRTSDZr %xmm16, _ %xmm16 = VSQRTSDZr %xmm16, %noreg
; CHECK: %xmm16 = VSQRTSDZr_Int %xmm16, _ ; CHECK: %xmm16 = VSQRTSDZr_Int %xmm16, %noreg
%xmm16 = VSQRTSDZr_Int %xmm16, _ %xmm16 = VSQRTSDZr_Int %xmm16, %noreg
; CHECK: %xmm16 = VSQRTSSZm %xmm16, _, _, _, _, _ ; CHECK: %xmm16 = VSQRTSSZm %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm16 = VSQRTSSZm %xmm16, _, _, _, _, _ %xmm16 = VSQRTSSZm %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VSQRTSSZm_Int %xmm16, _, _, _, _, _ ; CHECK: %xmm16 = VSQRTSSZm_Int %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg
%xmm16 = VSQRTSSZm_Int %xmm16, _, _, _, _, _ %xmm16 = VSQRTSSZm_Int %xmm16, %noreg, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VSQRTSSZr %xmm16, _ ; CHECK: %xmm16 = VSQRTSSZr %xmm16, %noreg
%xmm16 = VSQRTSSZr %xmm16, _ %xmm16 = VSQRTSSZr %xmm16, %noreg
; CHECK: %xmm16 = VSQRTSSZr_Int %xmm16, _ ; CHECK: %xmm16 = VSQRTSSZr_Int %xmm16, %noreg
%xmm16 = VSQRTSSZr_Int %xmm16, _ %xmm16 = VSQRTSSZr_Int %xmm16, %noreg
; CHECK: %rdi = VCVTSD2SI64Zrm %rdi, %xmm16, 1, _, 0 ; CHECK: %rdi = VCVTSD2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
%rdi = VCVTSD2SI64Zrm %rdi, %xmm16, 1, _, 0 %rdi = VCVTSD2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %rdi = VCVTSD2SI64Zrr %xmm16 ; CHECK: %rdi = VCVTSD2SI64Zrr %xmm16
%rdi = VCVTSD2SI64Zrr %xmm16 %rdi = VCVTSD2SI64Zrr %xmm16
; CHECK: %edi = VCVTSD2SIZrm %rdi, %xmm16, 1, _, 0 ; CHECK: %edi = VCVTSD2SIZrm %rdi, %xmm16, 1, %noreg, 0
%edi = VCVTSD2SIZrm %rdi, %xmm16, 1, _, 0 %edi = VCVTSD2SIZrm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %edi = VCVTSD2SIZrr %xmm16 ; CHECK: %edi = VCVTSD2SIZrr %xmm16
%edi = VCVTSD2SIZrr %xmm16 %edi = VCVTSD2SIZrr %xmm16
; CHECK: %xmm16 = VCVTSD2SSZrm %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSD2SSZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VCVTSD2SSZrm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSD2SSZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VCVTSD2SSZrm_Int %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSD2SSZrm_Int %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VCVTSD2SSZrm_Int %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSD2SSZrm_Int %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VCVTSD2SSZrr %xmm16, _ ; CHECK: %xmm16 = VCVTSD2SSZrr %xmm16, %noreg
%xmm16 = VCVTSD2SSZrr %xmm16, _ %xmm16 = VCVTSD2SSZrr %xmm16, %noreg
; CHECK: %xmm16 = VCVTSD2SSZrr_Int %xmm16, _ ; CHECK: %xmm16 = VCVTSD2SSZrr_Int %xmm16, %noreg
%xmm16 = VCVTSD2SSZrr_Int %xmm16, _ %xmm16 = VCVTSD2SSZrr_Int %xmm16, %noreg
; CHECK: %xmm16 = VCVTSI2SDZrm %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSI2SDZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VCVTSI2SDZrm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSI2SDZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VCVTSI2SDZrm_Int %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSI2SDZrm_Int %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VCVTSI2SDZrm_Int %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSI2SDZrm_Int %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VCVTSI2SDZrr %xmm16, _ ; CHECK: %xmm16 = VCVTSI2SDZrr %xmm16, %noreg
%xmm16 = VCVTSI2SDZrr %xmm16, _ %xmm16 = VCVTSI2SDZrr %xmm16, %noreg
; CHECK: %xmm16 = VCVTSI2SDZrr_Int %xmm16, _ ; CHECK: %xmm16 = VCVTSI2SDZrr_Int %xmm16, %noreg
%xmm16 = VCVTSI2SDZrr_Int %xmm16, _ %xmm16 = VCVTSI2SDZrr_Int %xmm16, %noreg
; CHECK: %xmm16 = VCVTSI2SSZrm %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSI2SSZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VCVTSI2SSZrm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSI2SSZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VCVTSI2SSZrm_Int %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSI2SSZrm_Int %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VCVTSI2SSZrm_Int %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSI2SSZrm_Int %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VCVTSI2SSZrr %xmm16, _ ; CHECK: %xmm16 = VCVTSI2SSZrr %xmm16, %noreg
%xmm16 = VCVTSI2SSZrr %xmm16, _ %xmm16 = VCVTSI2SSZrr %xmm16, %noreg
; CHECK: %xmm16 = VCVTSI2SSZrr_Int %xmm16, _ ; CHECK: %xmm16 = VCVTSI2SSZrr_Int %xmm16, %noreg
%xmm16 = VCVTSI2SSZrr_Int %xmm16, _ %xmm16 = VCVTSI2SSZrr_Int %xmm16, %noreg
; CHECK: %xmm16 = VCVTSI642SDZrm %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSI642SDZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VCVTSI642SDZrm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSI642SDZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VCVTSI642SDZrm_Int %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSI642SDZrm_Int %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VCVTSI642SDZrm_Int %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSI642SDZrm_Int %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VCVTSI642SDZrr %xmm16, _ ; CHECK: %xmm16 = VCVTSI642SDZrr %xmm16, %noreg
%xmm16 = VCVTSI642SDZrr %xmm16, _ %xmm16 = VCVTSI642SDZrr %xmm16, %noreg
; CHECK: %xmm16 = VCVTSI642SDZrr_Int %xmm16, _ ; CHECK: %xmm16 = VCVTSI642SDZrr_Int %xmm16, %noreg
%xmm16 = VCVTSI642SDZrr_Int %xmm16, _ %xmm16 = VCVTSI642SDZrr_Int %xmm16, %noreg
; CHECK: %xmm16 = VCVTSI642SSZrm %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSI642SSZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VCVTSI642SSZrm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSI642SSZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VCVTSI642SSZrm_Int %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSI642SSZrm_Int %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VCVTSI642SSZrm_Int %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSI642SSZrm_Int %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VCVTSI642SSZrr %xmm16, _ ; CHECK: %xmm16 = VCVTSI642SSZrr %xmm16, %noreg
%xmm16 = VCVTSI642SSZrr %xmm16, _ %xmm16 = VCVTSI642SSZrr %xmm16, %noreg
; CHECK: %xmm16 = VCVTSI642SSZrr_Int %xmm16, _ ; CHECK: %xmm16 = VCVTSI642SSZrr_Int %xmm16, %noreg
%xmm16 = VCVTSI642SSZrr_Int %xmm16, _ %xmm16 = VCVTSI642SSZrr_Int %xmm16, %noreg
; CHECK: %xmm16 = VCVTSS2SDZrm %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSS2SDZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VCVTSS2SDZrm %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSS2SDZrm %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VCVTSS2SDZrm_Int %xmm16, %rdi, 1, _, 0, _ ; CHECK: %xmm16 = VCVTSS2SDZrm_Int %xmm16, %rdi, 1, %noreg, 0, %noreg
%xmm16 = VCVTSS2SDZrm_Int %xmm16, %rdi, 1, _, 0, _ %xmm16 = VCVTSS2SDZrm_Int %xmm16, %rdi, 1, %noreg, 0, %noreg
; CHECK: %xmm16 = VCVTSS2SDZrr %xmm16, _ ; CHECK: %xmm16 = VCVTSS2SDZrr %xmm16, %noreg
%xmm16 = VCVTSS2SDZrr %xmm16, _ %xmm16 = VCVTSS2SDZrr %xmm16, %noreg
; CHECK: %xmm16 = VCVTSS2SDZrr_Int %xmm16, _ ; CHECK: %xmm16 = VCVTSS2SDZrr_Int %xmm16, %noreg
%xmm16 = VCVTSS2SDZrr_Int %xmm16, _ %xmm16 = VCVTSS2SDZrr_Int %xmm16, %noreg
; CHECK: %rdi = VCVTSS2SI64Zrm %rdi, %xmm16, 1, _, 0 ; CHECK: %rdi = VCVTSS2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
%rdi = VCVTSS2SI64Zrm %rdi, %xmm16, 1, _, 0 %rdi = VCVTSS2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %rdi = VCVTSS2SI64Zrr %xmm16 ; CHECK: %rdi = VCVTSS2SI64Zrr %xmm16
%rdi = VCVTSS2SI64Zrr %xmm16 %rdi = VCVTSS2SI64Zrr %xmm16
; CHECK: %edi = VCVTSS2SIZrm %rdi, %xmm16, 1, _, 0 ; CHECK: %edi = VCVTSS2SIZrm %rdi, %xmm16, 1, %noreg, 0
%edi = VCVTSS2SIZrm %rdi, %xmm16, 1, _, 0 %edi = VCVTSS2SIZrm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %edi = VCVTSS2SIZrr %xmm16 ; CHECK: %edi = VCVTSS2SIZrr %xmm16
%edi = VCVTSS2SIZrr %xmm16 %edi = VCVTSS2SIZrr %xmm16
; CHECK: %rdi = VCVTTSD2SI64Zrm %rdi, %xmm16, 1, _, 0 ; CHECK: %rdi = VCVTTSD2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
%rdi = VCVTTSD2SI64Zrm %rdi, %xmm16, 1, _, 0 %rdi = VCVTTSD2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %rdi = VCVTTSD2SI64Zrm_Int %rdi, %xmm16, 1, _, 0 ; CHECK: %rdi = VCVTTSD2SI64Zrm_Int %rdi, %xmm16, 1, %noreg, 0
%rdi = VCVTTSD2SI64Zrm_Int %rdi, %xmm16, 1, _, 0 %rdi = VCVTTSD2SI64Zrm_Int %rdi, %xmm16, 1, %noreg, 0
; CHECK: %rdi = VCVTTSD2SI64Zrr %xmm16 ; CHECK: %rdi = VCVTTSD2SI64Zrr %xmm16
%rdi = VCVTTSD2SI64Zrr %xmm16 %rdi = VCVTTSD2SI64Zrr %xmm16
; CHECK: %rdi = VCVTTSD2SI64Zrr_Int %xmm16 ; CHECK: %rdi = VCVTTSD2SI64Zrr_Int %xmm16
%rdi = VCVTTSD2SI64Zrr_Int %xmm16 %rdi = VCVTTSD2SI64Zrr_Int %xmm16
; CHECK: %edi = VCVTTSD2SIZrm %rdi, %xmm16, 1, _, 0 ; CHECK: %edi = VCVTTSD2SIZrm %rdi, %xmm16, 1, %noreg, 0
%edi = VCVTTSD2SIZrm %rdi, %xmm16, 1, _, 0 %edi = VCVTTSD2SIZrm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %edi = VCVTTSD2SIZrm_Int %rdi, %xmm16, 1, _, 0 ; CHECK: %edi = VCVTTSD2SIZrm_Int %rdi, %xmm16, 1, %noreg, 0
%edi = VCVTTSD2SIZrm_Int %rdi, %xmm16, 1, _, 0 %edi = VCVTTSD2SIZrm_Int %rdi, %xmm16, 1, %noreg, 0
; CHECK: %edi = VCVTTSD2SIZrr %xmm16 ; CHECK: %edi = VCVTTSD2SIZrr %xmm16
%edi = VCVTTSD2SIZrr %xmm16 %edi = VCVTTSD2SIZrr %xmm16
; CHECK: %edi = VCVTTSD2SIZrr_Int %xmm16 ; CHECK: %edi = VCVTTSD2SIZrr_Int %xmm16
%edi = VCVTTSD2SIZrr_Int %xmm16 %edi = VCVTTSD2SIZrr_Int %xmm16
; CHECK: %rdi = VCVTTSS2SI64Zrm %rdi, %xmm16, 1, _, 0 ; CHECK: %rdi = VCVTTSS2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
%rdi = VCVTTSS2SI64Zrm %rdi, %xmm16, 1, _, 0 %rdi = VCVTTSS2SI64Zrm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %rdi = VCVTTSS2SI64Zrm_Int %rdi, %xmm16, 1, _, 0 ; CHECK: %rdi = VCVTTSS2SI64Zrm_Int %rdi, %xmm16, 1, %noreg, 0
%rdi = VCVTTSS2SI64Zrm_Int %rdi, %xmm16, 1, _, 0 %rdi = VCVTTSS2SI64Zrm_Int %rdi, %xmm16, 1, %noreg, 0
; CHECK: %rdi = VCVTTSS2SI64Zrr %xmm16 ; CHECK: %rdi = VCVTTSS2SI64Zrr %xmm16
%rdi = VCVTTSS2SI64Zrr %xmm16 %rdi = VCVTTSS2SI64Zrr %xmm16
; CHECK: %rdi = VCVTTSS2SI64Zrr_Int %xmm16 ; CHECK: %rdi = VCVTTSS2SI64Zrr_Int %xmm16
%rdi = VCVTTSS2SI64Zrr_Int %xmm16 %rdi = VCVTTSS2SI64Zrr_Int %xmm16
; CHECK: %edi = VCVTTSS2SIZrm %rdi, %xmm16, 1, _, 0 ; CHECK: %edi = VCVTTSS2SIZrm %rdi, %xmm16, 1, %noreg, 0
%edi = VCVTTSS2SIZrm %rdi, %xmm16, 1, _, 0 %edi = VCVTTSS2SIZrm %rdi, %xmm16, 1, %noreg, 0
; CHECK: %edi = VCVTTSS2SIZrm_Int %rdi, %xmm16, 1, _, 0 ; CHECK: %edi = VCVTTSS2SIZrm_Int %rdi, %xmm16, 1, %noreg, 0
%edi = VCVTTSS2SIZrm_Int %rdi, %xmm16, 1, _, 0 %edi = VCVTTSS2SIZrm_Int %rdi, %xmm16, 1, %noreg, 0
; CHECK: %edi = VCVTTSS2SIZrr %xmm16 ; CHECK: %edi = VCVTTSS2SIZrr %xmm16
%edi = VCVTTSS2SIZrr %xmm16 %edi = VCVTTSS2SIZrr %xmm16
; CHECK: %edi = VCVTTSS2SIZrr_Int %xmm16 ; CHECK: %edi = VCVTTSS2SIZrr_Int %xmm16
%edi = VCVTTSS2SIZrr_Int %xmm16 %edi = VCVTTSS2SIZrr_Int %xmm16
; CHECK: %xmm16 = VMOV64toSDZrr %rdi ; CHECK: %xmm16 = VMOV64toSDZrr %rdi
%xmm16 = VMOV64toSDZrr %rdi %xmm16 = VMOV64toSDZrr %rdi
; CHECK: %xmm16 = VMOVDI2SSZrm %rip, _, _, _, _ ; CHECK: %xmm16 = VMOVDI2SSZrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm16 = VMOVDI2SSZrm %rip, _, _, _, _ %xmm16 = VMOVDI2SSZrm %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VMOVDI2SSZrr %eax ; CHECK: %xmm16 = VMOVDI2SSZrr %eax
%xmm16 = VMOVDI2SSZrr %eax %xmm16 = VMOVDI2SSZrr %eax
; CHECK: VMOVSDZmr %rdi, %xmm16, _, _, _, _ ; CHECK: VMOVSDZmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
VMOVSDZmr %rdi, %xmm16, _, _, _, _ VMOVSDZmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VMOVSDZrm %rip, _, _, _, _ ; CHECK: %xmm16 = VMOVSDZrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm16 = VMOVSDZrm %rip, _, _, _, _ %xmm16 = VMOVSDZrm %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VMOVSDZrr %xmm16, _ ; CHECK: %xmm16 = VMOVSDZrr %xmm16, %noreg
%xmm16 = VMOVSDZrr %xmm16, _ %xmm16 = VMOVSDZrr %xmm16, %noreg
; CHECK: %xmm16 = VMOVSDZrr_REV %xmm16, _ ; CHECK: %xmm16 = VMOVSDZrr_REV %xmm16, %noreg
%xmm16 = VMOVSDZrr_REV %xmm16, _ %xmm16 = VMOVSDZrr_REV %xmm16, %noreg
; CHECK: %rax = VMOVSDto64Zrr %xmm16 ; CHECK: %rax = VMOVSDto64Zrr %xmm16
%rax = VMOVSDto64Zrr %xmm16 %rax = VMOVSDto64Zrr %xmm16
; CHECK: VMOVSDto64Zmr %rdi, %xmm16, _, _, _, _ ; CHECK: VMOVSDto64Zmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
VMOVSDto64Zmr %rdi, %xmm16, _, _, _, _ VMOVSDto64Zmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
; CHECK: VMOVSSZmr %rdi, %xmm16, _, _, _, _ ; CHECK: VMOVSSZmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
VMOVSSZmr %rdi, %xmm16, _, _, _, _ VMOVSSZmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VMOVSSZrm %rip, _, _, _, _ ; CHECK: %xmm16 = VMOVSSZrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm16 = VMOVSSZrm %rip, _, _, _, _ %xmm16 = VMOVSSZrm %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VMOVSSZrr %xmm16, _ ; CHECK: %xmm16 = VMOVSSZrr %xmm16, %noreg
%xmm16 = VMOVSSZrr %xmm16, _ %xmm16 = VMOVSSZrr %xmm16, %noreg
; CHECK: %xmm16 = VMOVSSZrr_REV %xmm16, _ ; CHECK: %xmm16 = VMOVSSZrr_REV %xmm16, %noreg
%xmm16 = VMOVSSZrr_REV %xmm16, _ %xmm16 = VMOVSSZrr_REV %xmm16, %noreg
; CHECK: VMOVSS2DIZmr %rdi, %xmm16, _, _, _, _ ; CHECK: VMOVSS2DIZmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
VMOVSS2DIZmr %rdi, %xmm16, _, _, _, _ VMOVSS2DIZmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
; CHECK: %eax = VMOVSS2DIZrr %xmm16 ; CHECK: %eax = VMOVSS2DIZrr %xmm16
%eax = VMOVSS2DIZrr %xmm16 %eax = VMOVSS2DIZrr %xmm16
; CHECK: %xmm16 = VMOV64toPQIZrr %rdi ; CHECK: %xmm16 = VMOV64toPQIZrr %rdi
%xmm16 = VMOV64toPQIZrr %rdi %xmm16 = VMOV64toPQIZrr %rdi
; CHECK: %xmm16 = VMOV64toPQIZrm %rdi, _, _, _, _ ; CHECK: %xmm16 = VMOV64toPQIZrm %rdi, %noreg, %noreg, %noreg, %noreg
%xmm16 = VMOV64toPQIZrm %rdi, _, _, _, _ %xmm16 = VMOV64toPQIZrm %rdi, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VMOV64toSDZrr %rdi ; CHECK: %xmm16 = VMOV64toSDZrr %rdi
%xmm16 = VMOV64toSDZrr %rdi %xmm16 = VMOV64toSDZrr %rdi
; CHECK: %xmm16 = VMOVDI2PDIZrm %rip, _, _, _, _ ; CHECK: %xmm16 = VMOVDI2PDIZrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm16 = VMOVDI2PDIZrm %rip, _, _, _, _ %xmm16 = VMOVDI2PDIZrm %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VMOVDI2PDIZrr %edi ; CHECK: %xmm16 = VMOVDI2PDIZrr %edi
%xmm16 = VMOVDI2PDIZrr %edi %xmm16 = VMOVDI2PDIZrr %edi
; CHECK: %xmm16 = VMOVLHPSZrr %xmm16, _ ; CHECK: %xmm16 = VMOVLHPSZrr %xmm16, %noreg
%xmm16 = VMOVLHPSZrr %xmm16, _ %xmm16 = VMOVLHPSZrr %xmm16, %noreg
; CHECK: %xmm16 = VMOVHLPSZrr %xmm16, _ ; CHECK: %xmm16 = VMOVHLPSZrr %xmm16, %noreg
%xmm16 = VMOVHLPSZrr %xmm16, _ %xmm16 = VMOVHLPSZrr %xmm16, %noreg
; CHECK: VMOVPDI2DIZmr %rdi, %xmm16, _, _, _, _ ; CHECK: VMOVPDI2DIZmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
VMOVPDI2DIZmr %rdi, %xmm16, _, _, _, _ VMOVPDI2DIZmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
; CHECK: %edi = VMOVPDI2DIZrr %xmm16 ; CHECK: %edi = VMOVPDI2DIZrr %xmm16
%edi = VMOVPDI2DIZrr %xmm16 %edi = VMOVPDI2DIZrr %xmm16
; CHECK: %xmm16 = VMOVPQI2QIZrr %xmm16 ; CHECK: %xmm16 = VMOVPQI2QIZrr %xmm16
%xmm16 = VMOVPQI2QIZrr %xmm16 %xmm16 = VMOVPQI2QIZrr %xmm16
; CHECK: VMOVPQI2QIZmr %rdi, %xmm16, _, _, _, _ ; CHECK: VMOVPQI2QIZmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
VMOVPQI2QIZmr %rdi, %xmm16, _, _, _, _ VMOVPQI2QIZmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
; CHECK: %rdi = VMOVPQIto64Zrr %xmm16 ; CHECK: %rdi = VMOVPQIto64Zrr %xmm16
%rdi = VMOVPQIto64Zrr %xmm16 %rdi = VMOVPQIto64Zrr %xmm16
; CHECK: VMOVPQIto64Zmr %rdi, %xmm16, _, _, _, _ ; CHECK: VMOVPQIto64Zmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
VMOVPQIto64Zmr %rdi, %xmm16, _, _, _, _ VMOVPQIto64Zmr %rdi, %xmm16, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VMOVQI2PQIZrm %rip, _, _, _, _ ; CHECK: %xmm16 = VMOVQI2PQIZrm %rip, %noreg, %noreg, %noreg, %noreg
%xmm16 = VMOVQI2PQIZrm %rip, _, _, _, _ %xmm16 = VMOVQI2PQIZrm %rip, %noreg, %noreg, %noreg, %noreg
; CHECK: %xmm16 = VMOVZPQILo2PQIZrr %xmm16 ; CHECK: %xmm16 = VMOVZPQILo2PQIZrr %xmm16
%xmm16 = VMOVZPQILo2PQIZrr %xmm16 %xmm16 = VMOVZPQILo2PQIZrr %xmm16
; CHECK: Int_VCOMISDZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: Int_VCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
Int_VCOMISDZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags Int_VCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: Int_VCOMISDZrr %xmm16, %xmm1, implicit-def %eflags ; CHECK: Int_VCOMISDZrr %xmm16, %xmm1, implicit-def %eflags
Int_VCOMISDZrr %xmm16, %xmm1, implicit-def %eflags Int_VCOMISDZrr %xmm16, %xmm1, implicit-def %eflags
; CHECK: Int_VCOMISSZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: Int_VCOMISSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
Int_VCOMISSZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags Int_VCOMISSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: Int_VCOMISSZrr %xmm16, %xmm1, implicit-def %eflags ; CHECK: Int_VCOMISSZrr %xmm16, %xmm1, implicit-def %eflags
Int_VCOMISSZrr %xmm16, %xmm1, implicit-def %eflags Int_VCOMISSZrr %xmm16, %xmm1, implicit-def %eflags
; CHECK: Int_VUCOMISDZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: Int_VUCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
Int_VUCOMISDZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags Int_VUCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: Int_VUCOMISDZrr %xmm16, %xmm1, implicit-def %eflags ; CHECK: Int_VUCOMISDZrr %xmm16, %xmm1, implicit-def %eflags
Int_VUCOMISDZrr %xmm16, %xmm1, implicit-def %eflags Int_VUCOMISDZrr %xmm16, %xmm1, implicit-def %eflags
; CHECK: Int_VUCOMISSZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: Int_VUCOMISSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
Int_VUCOMISSZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags Int_VUCOMISSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: Int_VUCOMISSZrr %xmm16, %xmm1, implicit-def %eflags ; CHECK: Int_VUCOMISSZrr %xmm16, %xmm1, implicit-def %eflags
Int_VUCOMISSZrr %xmm16, %xmm1, implicit-def %eflags Int_VUCOMISSZrr %xmm16, %xmm1, implicit-def %eflags
; CHECK: VCOMISDZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: VCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
VCOMISDZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags VCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: VCOMISDZrr %xmm16, %xmm1, implicit-def %eflags ; CHECK: VCOMISDZrr %xmm16, %xmm1, implicit-def %eflags
VCOMISDZrr %xmm16, %xmm1, implicit-def %eflags VCOMISDZrr %xmm16, %xmm1, implicit-def %eflags
; CHECK: VCOMISSZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: VCOMISSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
VCOMISSZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags VCOMISSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: VCOMISSZrr %xmm16, %xmm1, implicit-def %eflags ; CHECK: VCOMISSZrr %xmm16, %xmm1, implicit-def %eflags
VCOMISSZrr %xmm16, %xmm1, implicit-def %eflags VCOMISSZrr %xmm16, %xmm1, implicit-def %eflags
; CHECK: VUCOMISDZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: VUCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
VUCOMISDZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags VUCOMISDZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: VUCOMISDZrr %xmm16, %xmm1, implicit-def %eflags ; CHECK: VUCOMISDZrr %xmm16, %xmm1, implicit-def %eflags
VUCOMISDZrr %xmm16, %xmm1, implicit-def %eflags VUCOMISDZrr %xmm16, %xmm1, implicit-def %eflags
; CHECK: VUCOMISSZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags ; CHECK: VUCOMISSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
VUCOMISSZrm %xmm16, %rdi, _, _, _, _, implicit-def %eflags VUCOMISSZrm %xmm16, %rdi, %noreg, %noreg, %noreg, %noreg, implicit-def %eflags
; CHECK: VUCOMISSZrr %xmm16, %xmm1, implicit-def %eflags ; CHECK: VUCOMISSZrr %xmm16, %xmm1, implicit-def %eflags
VUCOMISSZrr %xmm16, %xmm1, implicit-def %eflags VUCOMISSZrr %xmm16, %xmm1, implicit-def %eflags
RET 0, %zmm0, %zmm1 RET 0, %zmm0, %zmm1
... ...

llvm/trunk/test/CodeGen/X86/expand-vr64-gr64-copy.mir

Show All 17 Lines
--- ---
name: test_pswapdsi name: test_pswapdsi
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %xmm0 liveins: %xmm0
%xmm0 = PSHUFDri killed %xmm0, -24 %xmm0 = PSHUFDri killed %xmm0, -24
MOVPQI2QImr %rsp, 1, _, -8, _, killed %xmm0 MOVPQI2QImr %rsp, 1, %noreg, -8, %noreg, killed %xmm0
%mm0 = PSWAPDrm %rsp, 1, _, -8, _ %mm0 = PSWAPDrm %rsp, 1, %noreg, -8, %noreg
; CHECK: %rax = MMX_MOVD64from64rr %mm0 ; CHECK: %rax = MMX_MOVD64from64rr %mm0
; CHECK-NEXT: %mm0 = MMX_MOVD64to64rr %rax ; CHECK-NEXT: %mm0 = MMX_MOVD64to64rr %rax
%rax = COPY %mm0 %rax = COPY %mm0
%mm0 = COPY %rax %mm0 = COPY %rax
MMX_MOVQ64mr %rsp, 1, _, -16, _, killed %mm0 MMX_MOVQ64mr %rsp, 1, %noreg, -16, %noreg, killed %mm0
%xmm0 = MOVQI2PQIrm %rsp, 1, _, -16, _ %xmm0 = MOVQI2PQIrm %rsp, 1, %noreg, -16, %noreg
%xmm0 = PSHUFDri killed %xmm0, -44 %xmm0 = PSHUFDri killed %xmm0, -44
RETQ %xmm0 RETQ %xmm0
... ...

llvm/trunk/test/CodeGen/X86/fcmove.ll

; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s ; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-unknown" target triple = "x86_64-unknown-unknown"
; Test that we can generate an fcmove, and also that it passes verification. ; Test that we can generate an fcmove, and also that it passes verification.
; CHECK-LABEL: cmove_f ; CHECK-LABEL: cmove_f
; CHECK: fcmove %st({{[0-7]}}), %st(0) ; CHECK: fcmove %st({{[0-7]}}), %st(0)
define x86_fp80 @cmove_f(x86_fp80 %a, x86_fp80 %b, i32 %c) { define x86_fp80 @cmove_f(x86_fp80 %a, x86_fp80 %b, i32 %c) {
%test = icmp eq i32 %c, 0 %test = icmp eq i32 %c, 0
%add = fadd x86_fp80 %a, %b %add = fadd x86_fp80 %a, %b
%ret = select i1 %test, x86_fp80 %add, x86_fp80 %b %ret = select i1 %test, x86_fp80 %add, x86_fp80 %b
ret x86_fp80 %ret ret x86_fp80 %ret
} }
No newline at end of file

llvm/trunk/test/CodeGen/X86/fixup-bw-inst.mir

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
# #
# For that to happen, the liveness information after the MOV16rm # For that to happen, the liveness information after the MOV16rm
# instruction should be used, not before it because %rax is live # instruction should be used, not before it because %rax is live
# before the MOV and is killed by it. # before the MOV and is killed by it.
body: | body: |
bb.0: bb.0:
liveins: %rax liveins: %rax
%ax = MOV16rm killed %rax, 1, _, 0, _ %ax = MOV16rm killed %rax, 1, %noreg, 0, %noreg
; CHECK: %eax = MOVZX32rm16 killed %rax ; CHECK: %eax = MOVZX32rm16 killed %rax
RETQ %ax RETQ %ax
... ...
--- ---
# CHECK-LABEL: name: test2 # CHECK-LABEL: name: test2
name: test2 name: test2
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines bb.0.entry:
liveins: %rdi liveins: %rdi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.1, implicit %eflags JE_1 %bb.1, implicit %eflags
bb.2.if.then: bb.2.if.then:
liveins: %rdi liveins: %rdi
%ax = MOV16rm killed %rdi, 1, _, 0, _, implicit-def %eax :: (load 2 from %ir.p) %ax = MOV16rm killed %rdi, 1, %noreg, 0, %noreg, implicit-def %eax :: (load 2 from %ir.p)
; CHECK: %eax = MOVZX32rm16 killed %rdi, 1, _, 0, _, implicit-def %eax :: (load 2 from %ir.p) ; CHECK: %eax = MOVZX32rm16 killed %rdi, 1, %noreg, 0, %noreg, implicit-def %eax :: (load 2 from %ir.p)
%ax = KILL %ax, implicit killed %eax %ax = KILL %ax, implicit killed %eax
RETQ %ax RETQ %ax
bb.1: bb.1:
%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
%ax = KILL %ax, implicit killed %eax %ax = KILL %ax, implicit killed %eax
RETQ %ax RETQ %ax
... ...

llvm/trunk/test/CodeGen/X86/i486-fence-loop.ll

Show All 17 Lineswhile.body:
%0 = load volatile i32, i32* %addr, align 4 %0 = load volatile i32, i32* %addr, align 4
fence seq_cst fence seq_cst
%1 = load volatile i32, i32* %addr, align 4 %1 = load volatile i32, i32* %addr, align 4
%cmp = icmp sgt i32 %1, %0 %cmp = icmp sgt i32 %1, %0
br i1 %cmp, label %while.body, label %if.then br i1 %cmp, label %while.body, label %if.then
if.then: if.then:
ret void ret void
} }
No newline at end of file

llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir

Show First 20 Lines • Show All 385 Lines • ▼ Show 20 Lines
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_0 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_0
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%esi' } - { reg: '%esi' }
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: %eax = MOV32ri 2200000 # CHECK: %eax = MOV32ri 2200000
# CHECK-NEXT: %eax = FAULTING_OP 1, %bb.3.is_null, {{[0-9]+}}, %eax, %rdi, 1, _, 0, _, implicit-def %eflags :: (load 4 from %ir.x) # CHECK-NEXT: %eax = FAULTING_OP 1, %bb.3.is_null, {{[0-9]+}}, %eax, %rdi, 1, %noreg, 0, %noreg, implicit-def %eflags :: (load 4 from %ir.x)
# CHECK-NEXT: JMP_1 %bb.1.not_null # CHECK-NEXT: JMP_1 %bb.1.not_null
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %esi, %rdi liveins: %esi, %rdi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.3.is_null, implicit %eflags JE_1 %bb.3.is_null, implicit %eflags
bb.1.not_null: bb.1.not_null:
liveins: %esi, %rdi liveins: %esi, %rdi
%eax = MOV32ri 2200000 %eax = MOV32ri 2200000
%eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x) %eax = AND32rm killed %eax, killed %rdi, 1, %noreg, 0, %noreg, implicit-def dead %eflags :: (load 4 from %ir.x)
CMP32rr killed %eax, killed %esi, implicit-def %eflags CMP32rr killed %eax, killed %esi, implicit-def %eflags
JE_1 %bb.4.ret_100, implicit %eflags JE_1 %bb.4.ret_100, implicit %eflags
bb.2.ret_200: bb.2.ret_200:
%eax = MOV32ri 200 %eax = MOV32ri 200
RETQ %eax RETQ %eax
bb.3.is_null: bb.3.is_null:
Show All 9 Lines
name: imp_null_check_with_bitwise_op_1 name: imp_null_check_with_bitwise_op_1
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%esi' } - { reg: '%esi' }
- { reg: '%rdx' } - { reg: '%rdx' }
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: %eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr) # CHECK: %eax = MOV32rm killed %rdx, 1, %noreg, 0, %noreg :: (volatile load 4 from %ir.ptr)
# CHECK-NEXT: TEST64rr %rdi, %rdi, implicit-def %eflags # CHECK-NEXT: TEST64rr %rdi, %rdi, implicit-def %eflags
# CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags # CHECK-NEXT: JE_1 %bb.3.is_null, implicit %eflags
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %esi, %rdi, %rdx liveins: %esi, %rdi, %rdx
%eax = MOV32rm killed %rdx, 1, _, 0, _ :: (volatile load 4 from %ir.ptr) %eax = MOV32rm killed %rdx, 1, %noreg, 0, %noreg :: (volatile load 4 from %ir.ptr)
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.3.is_null, implicit %eflags JE_1 %bb.3.is_null, implicit %eflags
bb.1.not_null: bb.1.not_null:
liveins: %esi, %rdi liveins: %esi, %rdi
%eax = MOV32ri 2200000 %eax = MOV32ri 2200000
%eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x) %eax = AND32rm killed %eax, killed %rdi, 1, %noreg, 0, %noreg, implicit-def dead %eflags :: (load 4 from %ir.x)
CMP32rr killed %eax, killed %esi, implicit-def %eflags CMP32rr killed %eax, killed %esi, implicit-def %eflags
JE_1 %bb.4.ret_100, implicit %eflags JE_1 %bb.4.ret_100, implicit %eflags
bb.2.ret_200: bb.2.ret_200:
%eax = MOV32ri 200 %eax = MOV32ri 200
bb.3.is_null: bb.3.is_null:
Show All 25 Lines bb.0.entry:
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.3.is_null, implicit %eflags JE_1 %bb.3.is_null, implicit %eflags
bb.1.not_null: bb.1.not_null:
liveins: %esi, %rdi liveins: %esi, %rdi
%eax = MOV32ri 2200000 %eax = MOV32ri 2200000
%eax = ADD32ri killed %eax, 100, implicit-def dead %eflags %eax = ADD32ri killed %eax, 100, implicit-def dead %eflags
%eax = AND32rm killed %eax, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x) %eax = AND32rm killed %eax, killed %rdi, 1, %noreg, 0, %noreg, implicit-def dead %eflags :: (load 4 from %ir.x)
CMP32rr killed %eax, killed %esi, implicit-def %eflags CMP32rr killed %eax, killed %esi, implicit-def %eflags
JE_1 %bb.4.ret_100, implicit %eflags JE_1 %bb.4.ret_100, implicit %eflags
bb.2.ret_200: bb.2.ret_200:
%eax = MOV32ri 200 %eax = MOV32ri 200
RETQ %eax RETQ %eax
bb.3.is_null: bb.3.is_null:
Show All 23 Lines bb.0.entry:
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.3.is_null, implicit %eflags JE_1 %bb.3.is_null, implicit %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rsi, %rdi liveins: %rsi, %rdi
%rdi = MOV64ri 5000 %rdi = MOV64ri 5000
%rdi = AND64rm killed %rdi, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x) %rdi = AND64rm killed %rdi, killed %rdi, 1, %noreg, 0, %noreg, implicit-def dead %eflags :: (load 4 from %ir.x)
CMP64rr killed %rdi, killed %rsi, implicit-def %eflags CMP64rr killed %rdi, killed %rsi, implicit-def %eflags
JE_1 %bb.4.ret_100, implicit %eflags JE_1 %bb.4.ret_100, implicit %eflags
bb.2.ret_200: bb.2.ret_200:
%eax = MOV32ri 200 %eax = MOV32ri 200
RETQ %eax RETQ %eax
bb.3.is_null: bb.3.is_null:
Show All 10 Lines
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_4 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_4
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%rsi' } - { reg: '%rsi' }
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: %rbx = MOV64rr %rdx # CHECK: %rbx = MOV64rr %rdx
# CHECK-NEXT: %rbx = FAULTING_OP 1, %bb.3.is_null, {{[0-9]+}}, %rbx, %rdi, 1, _, 0, _, implicit-def %eflags :: (load 4 from %ir.x) # CHECK-NEXT: %rbx = FAULTING_OP 1, %bb.3.is_null, {{[0-9]+}}, %rbx, %rdi, 1, %noreg, 0, %noreg, implicit-def %eflags :: (load 4 from %ir.x)
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rsi, %rdi, %rdx liveins: %rsi, %rdi, %rdx
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.3.is_null, implicit %eflags JE_1 %bb.3.is_null, implicit %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rsi, %rdi, %rdx liveins: %rsi, %rdi, %rdx
%rbx = MOV64rr %rdx %rbx = MOV64rr %rdx
%rbx = AND64rm killed %rbx, killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.x) %rbx = AND64rm killed %rbx, killed %rdi, 1, %noreg, 0, %noreg, implicit-def dead %eflags :: (load 4 from %ir.x)
%rdx = MOV64ri 0 %rdx = MOV64ri 0
CMP64rr killed %rbx, killed %rsi, implicit-def %eflags CMP64rr killed %rbx, killed %rsi, implicit-def %eflags
JE_1 %bb.4.ret_100, implicit %eflags JE_1 %bb.4.ret_100, implicit %eflags
bb.2.ret_200: bb.2.ret_200:
%eax = MOV32ri 200 %eax = MOV32ri 200
RETQ %eax RETQ %eax
Show All 31 Lines bb.0.entry:
%rbx = MOV64rr %rdi %rbx = MOV64rr %rdi
TEST64rr %rbx, %rbx, implicit-def %eflags TEST64rr %rbx, %rbx, implicit-def %eflags
JE_1 %bb.2.leave, implicit killed %eflags JE_1 %bb.2.leave, implicit killed %eflags
bb.1.stay: bb.1.stay:
liveins: %rbx liveins: %rbx
CALL64pcrel32 @f, csr_64, implicit %rsp, implicit-def %rsp CALL64pcrel32 @f, csr_64, implicit %rsp, implicit-def %rsp
%eax = MOV32rm killed %rbx, 1, _, 0, _ :: (load 4 from %ir.ptr) %eax = MOV32rm killed %rbx, 1, %noreg, 0, %noreg :: (load 4 from %ir.ptr)
%rbx = POP64r implicit-def %rsp, implicit %rsp %rbx = POP64r implicit-def %rsp, implicit %rsp
RETQ %eax RETQ %eax
bb.2.leave: bb.2.leave:
%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
%rbx = POP64r implicit-def %rsp, implicit %rsp %rbx = POP64r implicit-def %rsp, implicit %rsp
RETQ %eax RETQ %eax
Show All 19 Lines bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
%rcx = MOV64rm killed %rsi, 1, _, 0, _ :: (load 8 from %ir.ptr2) %rcx = MOV64rm killed %rsi, 1, %noreg, 0, %noreg :: (load 8 from %ir.ptr2)
%esi = MOV32ri 3076 %esi = MOV32ri 3076
%eax = BEXTR32rm killed %rdi, 1, _, 0, _, killed %esi, implicit-def dead %eflags :: (load 4 from %ir.ptr) %eax = BEXTR32rm killed %rdi, 1, %noreg, 0, %noreg, killed %esi, implicit-def dead %eflags :: (load 4 from %ir.ptr)
%eax = ADD32rm killed %eax, killed %rcx, 1, _, 0, _, implicit-def dead %eflags :: (load 4 from %ir.val) %eax = ADD32rm killed %eax, killed %rcx, 1, %noreg, 0, %noreg, implicit-def dead %eflags :: (load 4 from %ir.val)
RETQ %eax RETQ %eax
bb.2.is_null: bb.2.is_null:
%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
RETQ %eax RETQ %eax
... ...
--- ---
name: use_alternate_load_op name: use_alternate_load_op
# CHECK-LABEL: name: use_alternate_load_op # CHECK-LABEL: name: use_alternate_load_op
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: %rax = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, _, 0, _ # CHECK: %rax = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, %noreg, 0, %noreg
# CHECK-NEXT: JMP_1 %bb.1.not_null # CHECK-NEXT: JMP_1 %bb.1.not_null
# CHECK: bb.1.not_null # CHECK: bb.1.not_null
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%rsi' } - { reg: '%rsi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
%rcx = MOV64rm killed %rsi, 1, _, 0, _ %rcx = MOV64rm killed %rsi, 1, %noreg, 0, %noreg
%rcx = AND64rm killed %rcx, %rdi, 1, _, 0, _, implicit-def dead %eflags %rcx = AND64rm killed %rcx, %rdi, 1, %noreg, 0, %noreg, implicit-def dead %eflags
%rax = MOV64rm killed %rdi, 1, _, 0, _ %rax = MOV64rm killed %rdi, 1, %noreg, 0, %noreg
RETQ %eax RETQ %eax
bb.2.is_null: bb.2.is_null:
%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
RETQ %eax RETQ %eax
... ...
--- ---
name: imp_null_check_gep_load_with_use_dep name: imp_null_check_gep_load_with_use_dep
# CHECK-LABEL: name: imp_null_check_gep_load_with_use_dep # CHECK-LABEL: name: imp_null_check_gep_load_with_use_dep
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: %eax = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, _, 0, _, implicit-def %rax :: (load 4 from %ir.x) # CHECK: %eax = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, %noreg, 0, %noreg, implicit-def %rax :: (load 4 from %ir.x)
# CHECK-NEXT: JMP_1 %bb.1.not_null # CHECK-NEXT: JMP_1 %bb.1.not_null
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%rsi' } - { reg: '%rsi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rsi, %rdi liveins: %rsi, %rdi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.1.is_null, implicit %eflags JE_1 %bb.1.is_null, implicit %eflags
bb.2.not_null: bb.2.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
%rsi = ADD64rr %rsi, %rdi, implicit-def dead %eflags %rsi = ADD64rr %rsi, %rdi, implicit-def dead %eflags
%eax = MOV32rm killed %rdi, 1, _, 0, _, implicit-def %rax :: (load 4 from %ir.x) %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg, implicit-def %rax :: (load 4 from %ir.x)
%eax = LEA64_32r killed %rax, 1, killed %rsi, 4, _ %eax = LEA64_32r killed %rax, 1, killed %rsi, 4, %noreg
RETQ %eax RETQ %eax
bb.1.is_null: bb.1.is_null:
%eax = MOV32ri 42 %eax = MOV32ri 42
RETQ %eax RETQ %eax
... ...
--- ---
name: imp_null_check_load_with_base_sep name: imp_null_check_load_with_base_sep
# CHECK-LABEL: name: imp_null_check_load_with_base_sep # CHECK-LABEL: name: imp_null_check_load_with_base_sep
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: %rsi = ADD64rr %rsi, %rdi, implicit-def dead %eflags # CHECK: %rsi = ADD64rr %rsi, %rdi, implicit-def dead %eflags
# CHECK-NEXT: %esi = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, %esi, %rdi, 1, _, 0, _, implicit-def %eflags # CHECK-NEXT: %esi = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, %esi, %rdi, 1, %noreg, 0, %noreg, implicit-def %eflags
# CHECK-NEXT: JMP_1 %bb.1.not_null # CHECK-NEXT: JMP_1 %bb.1.not_null
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%rsi' } - { reg: '%rsi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rsi, %rdi liveins: %rsi, %rdi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.1.is_null, implicit %eflags JE_1 %bb.1.is_null, implicit %eflags
bb.2.not_null: bb.2.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
%rsi = ADD64rr %rsi, %rdi, implicit-def dead %eflags %rsi = ADD64rr %rsi, %rdi, implicit-def dead %eflags
%esi = AND32rm killed %esi, %rdi, 1, _, 0, _, implicit-def dead %eflags %esi = AND32rm killed %esi, %rdi, 1, %noreg, 0, %noreg, implicit-def dead %eflags
%eax = MOV32rr %esi %eax = MOV32rr %esi
RETQ %eax RETQ %eax
bb.1.is_null: bb.1.is_null:
%eax = MOV32ri 42 %eax = MOV32ri 42
RETQ %eax RETQ %eax
... ...
--- ---
name: inc_store name: inc_store
# CHECK-LABEL: name: inc_store # CHECK-LABEL: name: inc_store
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: _ = FAULTING_OP 3, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, _, 0, _, %rsi # CHECK: %noreg = FAULTING_OP 3, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, %noreg, 0, %noreg, %rsi
# CHECK-NEXT: JMP_1 %bb.1.not_null # CHECK-NEXT: JMP_1 %bb.1.not_null
# CHECK: bb.1.not_null # CHECK: bb.1.not_null
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%rsi' } - { reg: '%rsi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
MOV64mr killed %rdi, 1, _, 0, _, killed %rsi MOV64mr killed %rdi, 1, %noreg, 0, %noreg, killed %rsi
RETQ RETQ
bb.2.is_null: bb.2.is_null:
RETQ RETQ
... ...
--- ---
name: inc_store_plus_offset name: inc_store_plus_offset
# CHECK-LABEL: inc_store_plus_offset # CHECK-LABEL: inc_store_plus_offset
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: _ = FAULTING_OP 3, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, _, 16, _, %rsi # CHECK: %noreg = FAULTING_OP 3, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, %noreg, 16, %noreg, %rsi
# CHECK-NEXT: JMP_1 %bb.1.not_null # CHECK-NEXT: JMP_1 %bb.1.not_null
# CHECK: bb.1.not_null # CHECK: bb.1.not_null
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%rsi' } - { reg: '%rsi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
MOV64mr killed %rdi, 1, _, 16, _, killed %rsi MOV64mr killed %rdi, 1, %noreg, 16, %noreg, killed %rsi
RETQ RETQ
bb.2.is_null: bb.2.is_null:
RETQ RETQ
... ...
--- ---
name: inc_store_with_dep name: inc_store_with_dep
# CHECK-LABEL: inc_store_with_dep # CHECK-LABEL: inc_store_with_dep
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: %esi = ADD32rr killed %esi, killed %esi, implicit-def dead %eflags # CHECK: %esi = ADD32rr killed %esi, killed %esi, implicit-def dead %eflags
# CHECK-NEXT: _ = FAULTING_OP 3, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, _, 16, _, %esi # CHECK-NEXT: %noreg = FAULTING_OP 3, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, %noreg, 16, %noreg, %esi
# CHECK-NEXT: JMP_1 %bb.1.not_null # CHECK-NEXT: JMP_1 %bb.1.not_null
# CHECK: bb.1.not_null # CHECK: bb.1.not_null
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%rsi' } - { reg: '%rsi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
%esi = ADD32rr killed %esi, killed %esi, implicit-def dead %eflags %esi = ADD32rr killed %esi, killed %esi, implicit-def dead %eflags
MOV32mr killed %rdi, 1, _, 16, _, killed %esi MOV32mr killed %rdi, 1, %noreg, 16, %noreg, killed %esi
RETQ RETQ
bb.2.is_null: bb.2.is_null:
RETQ RETQ
... ...
--- ---
name: inc_store_with_dep_in_null name: inc_store_with_dep_in_null
Show All 14 Lines bb.0.entry:
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
%esi = ADD32rr %esi, %esi, implicit-def dead %eflags %esi = ADD32rr %esi, %esi, implicit-def dead %eflags
MOV32mr killed %rdi, 1, _, 0, _, %esi MOV32mr killed %rdi, 1, %noreg, 0, %noreg, %esi
%eax = MOV32rr killed %esi %eax = MOV32rr killed %esi
RETQ %eax RETQ %eax
bb.2.is_null: bb.2.is_null:
liveins: %rsi liveins: %rsi
%eax = MOV32rr killed %esi %eax = MOV32rr killed %esi
RETQ %eax RETQ %eax
Show All 17 Lines bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
MOV32mr killed %rdi, 1, _, 0, _, killed %esi :: (volatile store 4 into %ir.ptr) MOV32mr killed %rdi, 1, %noreg, 0, %noreg, killed %esi :: (volatile store 4 into %ir.ptr)
RETQ RETQ
bb.2.is_null: bb.2.is_null:
RETQ RETQ
... ...
--- ---
name: inc_store_with_two_dep name: inc_store_with_two_dep
Show All 15 Lines bb.0.entry:
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
%esi = ADD32rr killed %esi, killed %esi, implicit-def dead %eflags %esi = ADD32rr killed %esi, killed %esi, implicit-def dead %eflags
%esi = ADD32ri killed %esi, 15, implicit-def dead %eflags %esi = ADD32ri killed %esi, 15, implicit-def dead %eflags
MOV32mr killed %rdi, 1, _, 16, _, killed %esi MOV32mr killed %rdi, 1, %noreg, 16, %noreg, killed %esi
RETQ RETQ
bb.2.is_null: bb.2.is_null:
RETQ RETQ
... ...
--- ---
name: inc_store_with_redefined_base name: inc_store_with_redefined_base
Show All 14 Lines bb.0.entry:
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
%rdi = ADD64rr killed %rdi, killed %rdi, implicit-def dead %eflags %rdi = ADD64rr killed %rdi, killed %rdi, implicit-def dead %eflags
MOV32mr killed %rdi, 1, _, 16, _, killed %esi MOV32mr killed %rdi, 1, %noreg, 16, %noreg, killed %esi
RETQ RETQ
bb.2.is_null: bb.2.is_null:
RETQ RETQ
... ...
--- ---
name: inc_store_with_reused_base name: inc_store_with_reused_base
# CHECK-LABEL: inc_store_with_reused_base # CHECK-LABEL: inc_store_with_reused_base
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: _ = FAULTING_OP 3, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, _, 16, _, %esi # CHECK: %noreg = FAULTING_OP 3, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, %noreg, 16, %noreg, %esi
# CHECK-NEXT: JMP_1 %bb.1.not_null # CHECK-NEXT: JMP_1 %bb.1.not_null
# CHECK: bb.1.not_null # CHECK: bb.1.not_null
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%rsi' } - { reg: '%rsi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
%rax = MOV64rr %rdi %rax = MOV64rr %rdi
MOV32mr killed %rdi, 1, _, 16, _, killed %esi MOV32mr killed %rdi, 1, %noreg, 16, %noreg, killed %esi
RETQ %eax RETQ %eax
bb.2.is_null: bb.2.is_null:
%rax = XOR64rr undef %rax, undef %rax, implicit-def dead %eflags %rax = XOR64rr undef %rax, undef %rax, implicit-def dead %eflags
RETQ %eax RETQ %eax
... ...
--- ---
Show All 22 Lines bb.0.entry:
%rbx = MOV64rr killed %rdi %rbx = MOV64rr killed %rdi
TEST64rr %rbx, %rbx, implicit-def %eflags TEST64rr %rbx, %rbx, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rbx liveins: %rbx
CALL64pcrel32 @f, csr_64, implicit %rsp, implicit-def %rsp CALL64pcrel32 @f, csr_64, implicit %rsp, implicit-def %rsp
MOV32mi %rbx, 1, _, 0, _, 20 MOV32mi %rbx, 1, %noreg, 0, %noreg, 20
%rax = MOV64rr killed %rbx %rax = MOV64rr killed %rbx
%rbx = POP64r implicit-def %rsp, implicit %rsp %rbx = POP64r implicit-def %rsp, implicit %rsp
RETQ %eax RETQ %eax
bb.2.is_null: bb.2.is_null:
%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
%rbx = POP64r implicit-def %rsp, implicit %rsp %rbx = POP64r implicit-def %rsp, implicit %rsp
RETQ %eax RETQ %eax
Show All 19 Lines bb.0.entry:
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
%eax = MOV32rr %esi %eax = MOV32rr %esi
%esi = ADD32ri killed %esi, 15, implicit-def dead %eflags %esi = ADD32ri killed %esi, 15, implicit-def dead %eflags
MOV32mr killed %rdi, 1, _, 0, _, killed %esi MOV32mr killed %rdi, 1, %noreg, 0, %noreg, killed %esi
RETQ %eax RETQ %eax
bb.2.is_null: bb.2.is_null:
%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
RETQ %eax RETQ %eax
... ...
--- ---
Show All 14 Lines bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
MOV32mi killed %rsi, 1, _, 0, _, 2 MOV32mi killed %rsi, 1, %noreg, 0, %noreg, 2
%eax = MOV32rm killed %rdi, 1, _, 0, _ %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg
RETQ %eax RETQ %eax
bb.2.is_null: bb.2.is_null:
%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
RETQ %eax RETQ %eax
... ...
--- ---
Show All 14 Lines bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
%eax = MOV32rm killed %rsi, 1, _, 0, _ %eax = MOV32rm killed %rsi, 1, %noreg, 0, %noreg
MOV32mi killed %rdi, 1, _, 0, _, 2 MOV32mi killed %rdi, 1, %noreg, 0, %noreg, 2
RETQ %eax RETQ %eax
bb.2.is_null: bb.2.is_null:
%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
RETQ %eax RETQ %eax
... ...
--- ---
Show All 14 Lines bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
MOV32mi killed %rsi, 1, _, 0, _, 3 MOV32mi killed %rsi, 1, %noreg, 0, %noreg, 3
MOV32mi killed %rdi, 1, _, 0, _, 2 MOV32mi killed %rdi, 1, %noreg, 0, %noreg, 2
RETQ RETQ
bb.2.is_null: bb.2.is_null:
RETQ RETQ
... ...
--- ---
name: inc_store_with_load_and_store name: inc_store_with_load_and_store
# CHECK-LABEL: inc_store_with_load_and_store # CHECK-LABEL: inc_store_with_load_and_store
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: _ = FAULTING_OP 2, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, _, 0, _, %esi, implicit-def %eflags # CHECK: %noreg = FAULTING_OP 2, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, %noreg, 0, %noreg, %esi, implicit-def %eflags
# CHECK-NEXT: JMP_1 %bb.1.not_null # CHECK-NEXT: JMP_1 %bb.1.not_null
# CHECK: bb.1.not_null # CHECK: bb.1.not_null
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%rsi' } - { reg: '%rsi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
%esi = ADD32rr %esi, %esi, implicit-def dead %eflags %esi = ADD32rr %esi, %esi, implicit-def dead %eflags
ADD32mr killed %rdi, 1, _, 0, _, killed %esi, implicit-def dead %eflags ADD32mr killed %rdi, 1, %noreg, 0, %noreg, killed %esi, implicit-def dead %eflags
RETQ RETQ
bb.2.is_null: bb.2.is_null:
RETQ RETQ
... ...
--- ---
name: inc_store_and_load_no_alias name: inc_store_and_load_no_alias
# CHECK-LABEL: inc_store_and_load_no_alias # CHECK-LABEL: inc_store_and_load_no_alias
# CHECK: bb.0.entry: # CHECK: bb.0.entry:
# CHECK: %eax = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr) # CHECK: %eax = FAULTING_OP 1, %bb.2.is_null, {{[0-9]+}}, %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.ptr)
# CHECK-NEXT: JMP_1 %bb.1.not_null # CHECK-NEXT: JMP_1 %bb.1.not_null
# CHECK: bb.1.not_null # CHECK: bb.1.not_null
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
liveins: liveins:
- { reg: '%rdi' } - { reg: '%rdi' }
- { reg: '%rsi' } - { reg: '%rsi' }
body: | body: |
bb.0.entry: bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
MOV32mi killed %rsi, 1, _, 0, _, 3 :: (store 4 into %ir.ptr2) MOV32mi killed %rsi, 1, %noreg, 0, %noreg, 3 :: (store 4 into %ir.ptr2)
%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr) %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.ptr)
RETQ %eax RETQ %eax
bb.2.is_null: bb.2.is_null:
%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
RETQ %eax RETQ %eax
... ...
--- ---
Show All 14 Lines bb.0.entry:
liveins: %rdi, %rsi liveins: %rdi, %rsi
TEST64rr %rdi, %rdi, implicit-def %eflags TEST64rr %rdi, %rdi, implicit-def %eflags
JE_1 %bb.2.is_null, implicit killed %eflags JE_1 %bb.2.is_null, implicit killed %eflags
bb.1.not_null: bb.1.not_null:
liveins: %rdi, %rsi liveins: %rdi, %rsi
MOV32mi killed %rsi, 1, _, 0, _, 3 :: (store 4 into %ir.ptr2) MOV32mi killed %rsi, 1, %noreg, 0, %noreg, 3 :: (store 4 into %ir.ptr2)
%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.ptr) %eax = MOV32rm killed %rdi, 1, %noreg, 0, %noreg :: (load 4 from %ir.ptr)
RETQ %eax RETQ %eax
bb.2.is_null: bb.2.is_null:
%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
RETQ %eax RETQ %eax
... ...
--- ---
Show All 37 Lines

llvm/trunk/test/CodeGen/X86/implicit-use-spill.mir

# RUN: llc -run-pass=greedy -mtriple=x86_64-apple-macosx -o - %s | FileCheck %s # RUN: llc -run-pass=greedy -mtriple=x86_64-apple-macosx -o - %s | FileCheck %s
# Make sure we don't assert when we try to reload a value that is just implicitly used. # Make sure we don't assert when we try to reload a value that is just implicitly used.
--- ---
# CHECK: name: foo # CHECK: name: foo
# This test forces a spill of %0. # This test forces a spill of %0.
name: foo name: foo
registers: registers:
- { id: 0, class: gr64 } - { id: 0, class: gr64 }
body: | body: |
bb.0: bb.0:
; CHECK: NOOP implicit-def [[VAL:%[0-9]+]] ; CHECK: NOOP implicit-def [[VAL:%[0-9]+]]
; VAL should be spilled before csr_noregs, i.e., before we clobber all the registers ; VAL should be spilled before csr_noregs, i.e., before we clobber all the registers
; CHECK-NEXT: MOV64mr [[SLOT:%stack.[0-9]+]], 1, _, 0, _, [[VAL]] ; CHECK-NEXT: MOV64mr [[SLOT:%stack.[0-9]+]], 1, %noreg, 0, %noreg, [[VAL]]
; CHECK-NEXT: NOOP csr_noregs ; CHECK-NEXT: NOOP csr_noregs
; We need to reload before the (implicit) use. ; We need to reload before the (implicit) use.
; CHECK-NEXT: [[RELOADED_VAL:%[0-9]+]]:gr64 = MOV64rm [[SLOT]], 1, _, 0, _ ; CHECK-NEXT: [[RELOADED_VAL:%[0-9]+]]:gr64 = MOV64rm [[SLOT]], 1, %noreg, 0, %noreg
; CHECK-NEXT: NOOP implicit [[RELOADED_VAL]] ; CHECK-NEXT: NOOP implicit [[RELOADED_VAL]]
NOOP implicit-def %0 NOOP implicit-def %0
NOOP csr_noregs NOOP csr_noregs
NOOP implicit %0 NOOP implicit %0
... ...

llvm/trunk/test/CodeGen/X86/ipra-inline-asm.ll

; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s ; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.12.0" target triple = "x86_64-apple-macosx10.12.0"
; Verify that bar does not clobber anything ; Verify that bar does not clobber anything
; CHECK-NOT: bar Clobbered Registers:{{.+}} ; CHECK-NOT: bar Clobbered Registers:{{.+}}
; CHECK: bar Clobbered Registers: ; CHECK: bar Clobbered Registers:
define void @bar() #0 { define void @bar() #0 {
ret void ret void
} }
; Verifies that inline assembly is correctly handled by giving a list of clobbered registers ; Verifies that inline assembly is correctly handled by giving a list of clobbered registers
; CHECK: foo Clobbered Registers: AH AL AX CH CL CX DI DIL EAX ECX EDI RAX RCX RDI ; CHECK: foo Clobbered Registers: %ah %al %ax %ch %cl %cx %di %dil %eax %ecx %edi %rax %rcx %rdi
define void @foo() #0 { define void @foo() #0 {
call void asm sideeffect "", "~{eax},~{ecx},~{edi}"() #0 call void asm sideeffect "", "~{eax},~{ecx},~{edi}"() #0
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/trunk/test/CodeGen/X86/ipra-reg-alias.ll

; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s ; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s
target triple = "x86_64--" target triple = "x86_64--"
define i8 @main(i8 %X) { define i8 @main(i8 %X) {
%inc = add i8 %X, 1 %inc = add i8 %X, 1
%inc2 = mul i8 %inc, 5 %inc2 = mul i8 %inc, 5
; Here only CL is clobbred so CH should not be clobbred, but CX, ECX and RCX ; Here only CL is clobbred so CH should not be clobbred, but CX, ECX and RCX
; should be clobbered. ; should be clobbered.
; CHECK: main Clobbered Registers: AH AL AX CL CX EAX ECX EFLAGS RAX RCX ; CHECK: main Clobbered Registers: %ah %al %ax %cl %cx %eax %ecx %eflags %rax %rcx
ret i8 %inc2 ret i8 %inc2
} }

llvm/trunk/test/CodeGen/X86/ipra-reg-usage.ll

; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s ; RUN: llc -enable-ipra -print-regusage -o /dev/null 2>&1 < %s | FileCheck %s
target triple = "x86_64-unknown-unknown" target triple = "x86_64-unknown-unknown"
declare void @bar1() declare void @bar1()
define preserve_allcc void @foo()#0 { define preserve_allcc void @foo()#0 {
; CHECK: foo Clobbered Registers: CS DS EFLAGS EIP EIZ ES FPSW FS GS IP RIP RIZ SS SSP BND0 BND1 BND2 BND3 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 K0 K1 K2 K3 K4 K5 K6 K7 MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 R11 ST0 ST1 ST2 ST3 ST4 ST5 ST6 ST7 XMM16 XMM17 XMM18 XMM19 XMM20 XMM21 XMM22 XMM23 XMM24 XMM25 XMM26 XMM27 XMM28 XMM29 XMM30 XMM31 YMM0 YMM1 YMM2 YMM3 YMM4 YMM5 YMM6 YMM7 YMM8 YMM9 YMM10 YMM11 YMM12 YMM13 YMM14 YMM15 YMM16 YMM17 YMM18 YMM19 YMM20 YMM21 YMM22 YMM23 YMM24 YMM25 YMM26 YMM27 YMM28 YMM29 YMM30 YMM31 ZMM0 ZMM1 ZMM2 ZMM3 ZMM4 ZMM5 ZMM6 ZMM7 ZMM8 ZMM9 ZMM10 ZMM11 ZMM12 ZMM13 ZMM14 ZMM15 ZMM16 ZMM17 ZMM18 ZMM19 ZMM20 ZMM21 ZMM22 ZMM23 ZMM24 ZMM25 ZMM26 ZMM27 ZMM28 ZMM29 ZMM30 ZMM31 R11B R11D R11W ; CHECK: foo Clobbered Registers: %cs %ds %eflags %eip %eiz %es %fpsw %fs %gs %ip %rip %riz %ss %ssp %bnd0 %bnd1 %bnd2 %bnd3 %cr0 %cr1 %cr2 %cr3 %cr4 %cr5 %cr6 %cr7 %cr8 %cr9 %cr10 %cr11 %cr12 %cr13 %cr14 %cr15 %dr0 %dr1 %dr2 %dr3 %dr4 %dr5 %dr6 %dr7 %dr8 %dr9 %dr10 %dr11 %dr12 %dr13 %dr14 %dr15 %fp0 %fp1 %fp2 %fp3 %fp4 %fp5 %fp6 %fp7 %k0 %k1 %k2 %k3 %k4 %k5 %k6 %k7 %mm0 %mm1 %mm2 %mm3 %mm4 %mm5 %mm6 %mm7 %r11 %st0 %st1 %st2 %st3 %st4 %st5 %st6 %st7 %xmm16 %xmm17 %xmm18 %xmm19 %xmm20 %xmm21 %xmm22 %xmm23 %xmm24 %xmm25 %xmm26 %xmm27 %xmm28 %xmm29 %xmm30 %xmm31 %ymm0 %ymm1 %ymm2 %ymm3 %ymm4 %ymm5 %ymm6 %ymm7 %ymm8 %ymm9 %ymm10 %ymm11 %ymm12 %ymm13 %ymm14 %ymm15 %ymm16 %ymm17 %ymm18 %ymm19 %ymm20 %ymm21 %ymm22 %ymm23 %ymm24 %ymm25 %ymm26 %ymm27 %ymm28 %ymm29 %ymm30 %ymm31 %zmm0 %zmm1 %zmm2 %zmm3 %zmm4 %zmm5 %zmm6 %zmm7 %zmm8 %zmm9 %zmm10 %zmm11 %zmm12 %zmm13 %zmm14 %zmm15 %zmm16 %zmm17 %zmm18 %zmm19 %zmm20 %zmm21 %zmm22 %zmm23 %zmm24 %zmm25 %zmm26 %zmm27 %zmm28 %zmm29 %zmm30 %zmm31 %r11b %r11d %r11w
call void @bar1() call void @bar1()
call void @bar2() call void @bar2()
ret void ret void
} }
declare void @bar2() declare void @bar2()
attributes #0 = {nounwind} attributes #0 = {nounwind}

llvm/trunk/test/CodeGen/X86/lea-opt-with-debug.mir

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 LinesframeInfo:
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
; CHECK: %3:gr64_nosp = LEA64r %2, 2, %2, 0, _, debug-location !13 ; CHECK: %3:gr64_nosp = LEA64r %2, 2, %2, 0, %noreg, debug-location !13
; CHECK-NEXT: %4:gr64 = LEA64r %1, 4, %3, 0, _, debug-location !13 ; CHECK-NEXT: %4:gr64 = LEA64r %1, 4, %3, 0, %noreg, debug-location !13
; CHECK-NOT: %0:gr64 = LEA64r %1, 4, %3, 8, _, debug-location !14 ; CHECK-NOT: %0:gr64 = LEA64r %1, 4, %3, 8, %noreg, debug-location !14
; CHECK: DBG_VALUE debug-use %4, debug-use _, !11, !DIExpression(DW_OP_plus_uconst, 8, DW_OP_stack_value), debug-location !15 ; CHECK: DBG_VALUE debug-use %4, debug-use %noreg, !11, !DIExpression(DW_OP_plus_uconst, 8, DW_OP_stack_value), debug-location !15
%1 = MOV64rm %rip, 1, _, @c, _, debug-location !13 :: (dereferenceable load 8 from @c) %1 = MOV64rm %rip, 1, %noreg, @c, %noreg, debug-location !13 :: (dereferenceable load 8 from @c)
%2 = MOVSX64rm32 %rip, 1, _, @a, _, debug-location !13 :: (dereferenceable load 4 from @a) %2 = MOVSX64rm32 %rip, 1, %noreg, @a, %noreg, debug-location !13 :: (dereferenceable load 4 from @a)
%3 = LEA64r %2, 2, %2, 0, _, debug-location !13 %3 = LEA64r %2, 2, %2, 0, %noreg, debug-location !13
%4 = LEA64r %1, 4, %3, 0, _, debug-location !13 %4 = LEA64r %1, 4, %3, 0, %noreg, debug-location !13
%5 = COPY %4.sub_32bit, debug-location !13 %5 = COPY %4.sub_32bit, debug-location !13
MOV32mr %rip, 1, _, @d, _, killed %5, debug-location !13 :: (store 4 into @d) MOV32mr %rip, 1, %noreg, @d, %noreg, killed %5, debug-location !13 :: (store 4 into @d)
%0 = LEA64r %1, 4, %3, 8, _, debug-location !14 %0 = LEA64r %1, 4, %3, 8, %noreg, debug-location !14
DBG_VALUE debug-use %0, debug-use _, !11, !DIExpression(), debug-location !15 DBG_VALUE debug-use %0, debug-use %noreg, !11, !DIExpression(), debug-location !15
; CHECK-LABEL: bb.1 (%ir-block.8): ; CHECK-LABEL: bb.1 (%ir-block.8):
; CHECK: %6:gr32 = MOV32rm %4, 1, _, 8, _, debug-location !17 :: (load 4 from %ir.7) ; CHECK: %6:gr32 = MOV32rm %4, 1, %noreg, 8, %noreg, debug-location !17 :: (load 4 from %ir.7)
bb.1 (%ir-block.8): bb.1 (%ir-block.8):
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
%6 = MOV32rm %0, 1, _, 0, _, debug-location !17 :: (load 4 from %ir.7) %6 = MOV32rm %0, 1, %noreg, 0, %noreg, debug-location !17 :: (load 4 from %ir.7)
MOV32mr %rip, 1, _, @d, _, killed %6, debug-location !17 :: (store 4 into @d) MOV32mr %rip, 1, %noreg, @d, %noreg, killed %6, debug-location !17 :: (store 4 into @d)
JMP_1 %bb.1, debug-location !18 JMP_1 %bb.1, debug-location !18
... ...

llvm/trunk/test/CodeGen/X86/leaFixup32.mir

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %eax, %ebp liveins: %eax, %ebp
; CHECK: %eax = ADD32rr %eax, killed %ebp ; CHECK: %eax = ADD32rr %eax, killed %ebp
; CHECK: %eax = ADD32ri8 %eax, -5 ; CHECK: %eax = ADD32ri8 %eax, -5
%eax = LEA32r killed %eax, 1, killed %ebp, -5, _ %eax = LEA32r killed %eax, 1, killed %ebp, -5, %noreg
RETQ %eax RETQ %eax
... ...
--- ---
name: test2add_ebp_32 name: test2add_ebp_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 18 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %eax, %ebp liveins: %eax, %ebp
; CHECK: %ebp = ADD32rr %ebp, killed %eax ; CHECK: %ebp = ADD32rr %ebp, killed %eax
; CHECK: %ebp = ADD32ri8 %ebp, -5 ; CHECK: %ebp = ADD32ri8 %ebp, -5
%ebp = LEA32r killed %ebp, 1, killed %eax, -5, _ %ebp = LEA32r killed %ebp, 1, killed %eax, -5, %noreg
RETQ %ebp RETQ %ebp
... ...
--- ---
name: test1add_ebp_32 name: test1add_ebp_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 17 LinesframeInfo:
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %eax, %ebp liveins: %eax, %ebp
; CHECK: %ebp = ADD32rr %ebp, killed %eax ; CHECK: %ebp = ADD32rr %ebp, killed %eax
%ebp = LEA32r killed %ebp, 1, killed %eax, 0, _ %ebp = LEA32r killed %ebp, 1, killed %eax, 0, %noreg
RETQ %ebp RETQ %ebp
... ...
--- ---
name: testleaadd_32 name: testleaadd_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 19 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %eax, %ebp, %esi liveins: %eax, %ebp, %esi
; CHECK: %ebx = LEA32r killed %eax, 1, killed %ebp, 0 ; CHECK: %ebx = LEA32r killed %eax, 1, killed %ebp, 0
; CHECK: %ebx = ADD32ri8 %ebx, -5 ; CHECK: %ebx = ADD32ri8 %ebx, -5
%ebx = LEA32r killed %eax, 1, killed %ebp, -5, _ %ebx = LEA32r killed %eax, 1, killed %ebp, -5, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: testleaadd_ebp_32 name: testleaadd_ebp_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 16 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %eax, %ebp liveins: %eax, %ebp
; CHECK: %ebx = LEA32r killed %eax, 1, killed %ebp, 0, _ ; CHECK: %ebx = LEA32r killed %eax, 1, killed %ebp, 0, %noreg
; CHECK: %ebx = ADD32ri8 %ebx, -5 ; CHECK: %ebx = ADD32ri8 %ebx, -5
%ebx = LEA32r killed %ebp, 1, killed %eax, -5, _ %ebx = LEA32r killed %ebp, 1, killed %eax, -5, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: test1lea_ebp_32 name: test1lea_ebp_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 16 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %eax, %ebp liveins: %eax, %ebp
; CHECK: %ebx = LEA32r killed %eax, 1, killed %ebp, 0, _ ; CHECK: %ebx = LEA32r killed %eax, 1, killed %ebp, 0, %noreg
%ebx = LEA32r killed %ebp, 1, killed %eax, 0, _ %ebx = LEA32r killed %ebp, 1, killed %eax, 0, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: test2addi32_32 name: test2addi32_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 18 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %eax, %ebp liveins: %eax, %ebp
; CHECK: %eax = ADD32rr %eax, killed %ebp ; CHECK: %eax = ADD32rr %eax, killed %ebp
; CHECK: %eax = ADD32ri %eax, 129 ; CHECK: %eax = ADD32ri %eax, 129
%eax = LEA32r killed %eax, 1, killed %ebp, 129, _ %eax = LEA32r killed %eax, 1, killed %ebp, 129, %noreg
RETQ %eax RETQ %eax
... ...
--- ---
name: test1mov1add_ebp_32 name: test1mov1add_ebp_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 19 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %eax, %ebp, %ebx liveins: %eax, %ebp, %ebx
; CHECK: %ebx = MOV32rr %ebp ; CHECK: %ebx = MOV32rr %ebp
; CHECK: %ebx = ADD32rr %ebx, %ebp ; CHECK: %ebx = ADD32rr %ebx, %ebp
%ebx = LEA32r %ebp, 1, %ebp, 0, _ %ebx = LEA32r %ebp, 1, %ebp, 0, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: testleaadd_ebp_index_32 name: testleaadd_ebp_index_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %eax, %ebp, %ebx liveins: %eax, %ebp, %ebx
; CHECK: %ebx = LEA32r _, 1, %ebp, 5, _ ; CHECK: %ebx = LEA32r %noreg, 1, %ebp, 5, %noreg
; CHECK: %ebx = ADD32rr %ebx, %ebp ; CHECK: %ebx = ADD32rr %ebx, %ebp
%ebx = LEA32r %ebp, 1, %ebp, 5, _ %ebx = LEA32r %ebp, 1, %ebp, 5, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: testleaadd_ebp_index2_32 name: testleaadd_ebp_index2_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %eax, %ebp, %ebx liveins: %eax, %ebp, %ebx
; CHECK: %ebx = LEA32r _, 4, %ebp, 5, _ ; CHECK: %ebx = LEA32r %noreg, 4, %ebp, 5, %noreg
; CHECK: %ebx = ADD32rr %ebx, %ebp ; CHECK: %ebx = ADD32rr %ebx, %ebp
%ebx = LEA32r %ebp, 4, %ebp, 5, _ %ebx = LEA32r %ebp, 4, %ebp, 5, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: test_skip_opt_32 name: test_skip_opt_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %eax, %ebp, %ebx liveins: %eax, %ebp, %ebx
; CHECK: %ebp = LEA32r killed %ebp, 4, killed %ebp, 0, _ ; CHECK: %ebp = LEA32r killed %ebp, 4, killed %ebp, 0, %noreg
%ebp = LEA32r killed %ebp, 4, killed %ebp, 0, _ %ebp = LEA32r killed %ebp, 4, killed %ebp, 0, %noreg
RETQ %ebp RETQ %ebp
... ...
--- ---
name: test_skip_eflags_32 name: test_skip_eflags_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %eax, %ebp, %ebx liveins: %eax, %ebp, %ebx
; CHECK: %ebx = LEA32r killed %eax, 4, killed %eax, 5, _ ; CHECK: %ebx = LEA32r killed %eax, 4, killed %eax, 5, %noreg
; CHECK: %ebp = LEA32r killed %ebx, 4, killed %ebx, 0, _ ; CHECK: %ebp = LEA32r killed %ebx, 4, killed %ebx, 0, %noreg
; CHECK: %ebp = ADD32ri8 %ebp, 5 ; CHECK: %ebp = ADD32ri8 %ebp, 5
CMP32rr %eax, killed %ebx, implicit-def %eflags CMP32rr %eax, killed %ebx, implicit-def %eflags
%ebx = LEA32r killed %eax, 4, killed %eax, 5, _ %ebx = LEA32r killed %eax, 4, killed %eax, 5, %noreg
JE_1 %bb.1, implicit %eflags JE_1 %bb.1, implicit %eflags
RETQ %ebx RETQ %ebx
bb.1: bb.1:
liveins: %eax, %ebp, %ebx liveins: %eax, %ebp, %ebx
%ebp = LEA32r killed %ebx, 4, killed %ebx, 5, _ %ebp = LEA32r killed %ebx, 4, killed %ebx, 5, %noreg
RETQ %ebp RETQ %ebp
... ...

llvm/trunk/test/CodeGen/X86/leaFixup64.mir

Show First 20 Lines • Show All 174 Lines • ▼ Show 20 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %eax = LEA64_32r killed %rax, 1, killed %rbp, 0 ; CHECK: %eax = LEA64_32r killed %rax, 1, killed %rbp, 0
; CHECK: %eax = ADD32ri8 %eax, -5 ; CHECK: %eax = ADD32ri8 %eax, -5
%eax = LEA64_32r killed %rax, 1, killed %rbp, -5, _ %eax = LEA64_32r killed %rax, 1, killed %rbp, -5, %noreg
RETQ %eax RETQ %eax
... ...
--- ---
name: testleaadd_rbp_64_32_1 name: testleaadd_rbp_64_32_1
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 18 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %ebp = LEA64_32r killed %rax, 1, killed %rbp, 0 ; CHECK: %ebp = LEA64_32r killed %rax, 1, killed %rbp, 0
; CHECK: %ebp = ADD32ri8 %ebp, -5 ; CHECK: %ebp = ADD32ri8 %ebp, -5
%ebp = LEA64_32r killed %rbp, 1, killed %rax, -5, _ %ebp = LEA64_32r killed %rbp, 1, killed %rax, -5, %noreg
RETQ %ebp RETQ %ebp
... ...
--- ---
name: test1lea_rbp_64_32_1 name: test1lea_rbp_64_32_1
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 17 LinesframeInfo:
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %ebp = LEA64_32r killed %rax, 1, killed %rbp, 0 ; CHECK: %ebp = LEA64_32r killed %rax, 1, killed %rbp, 0
%ebp = LEA64_32r killed %rbp, 1, killed %rax, 0, _ %ebp = LEA64_32r killed %rbp, 1, killed %rax, 0, %noreg
RETQ %ebp RETQ %ebp
... ...
--- ---
name: test2add_64 name: test2add_64
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 18 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %rax = ADD64rr %rax, killed %rbp ; CHECK: %rax = ADD64rr %rax, killed %rbp
; CHECK: %rax = ADD64ri8 %rax, -5 ; CHECK: %rax = ADD64ri8 %rax, -5
%rax = LEA64r killed %rax, 1, killed %rbp, -5, _ %rax = LEA64r killed %rax, 1, killed %rbp, -5, %noreg
RETQ %eax RETQ %eax
... ...
--- ---
name: test2add_rbp_64 name: test2add_rbp_64
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 18 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %rbp = ADD64rr %rbp, killed %rax ; CHECK: %rbp = ADD64rr %rbp, killed %rax
; CHECK: %rbp = ADD64ri8 %rbp, -5 ; CHECK: %rbp = ADD64ri8 %rbp, -5
%rbp = LEA64r killed %rbp, 1, killed %rax, -5, _ %rbp = LEA64r killed %rbp, 1, killed %rax, -5, %noreg
RETQ %ebp RETQ %ebp
... ...
--- ---
name: test1add_rbp_64 name: test1add_rbp_64
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 17 LinesframeInfo:
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %rbp = ADD64rr %rbp, killed %rax ; CHECK: %rbp = ADD64rr %rbp, killed %rax
%rbp = LEA64r killed %rbp, 1, killed %rax, 0, _ %rbp = LEA64r killed %rbp, 1, killed %rax, 0, %noreg
RETQ %ebp RETQ %ebp
... ...
--- ---
name: testleaadd_64_32 name: testleaadd_64_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 16 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %ebx = LEA64_32r killed %rax, 1, killed %rbp, 0, _ ; CHECK: %ebx = LEA64_32r killed %rax, 1, killed %rbp, 0, %noreg
; CHECK: %ebx = ADD32ri8 %ebx, -5 ; CHECK: %ebx = ADD32ri8 %ebx, -5
%ebx = LEA64_32r killed %rax, 1, killed %rbp, -5, _ %ebx = LEA64_32r killed %rax, 1, killed %rbp, -5, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: testleaadd_rbp_64_32 name: testleaadd_rbp_64_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 16 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %ebx = LEA64_32r killed %rax, 1, killed %rbp, 0, _ ; CHECK: %ebx = LEA64_32r killed %rax, 1, killed %rbp, 0, %noreg
; CHECK: %ebx = ADD32ri8 %ebx, -5 ; CHECK: %ebx = ADD32ri8 %ebx, -5
%ebx = LEA64_32r killed %rbp, 1, killed %rax, -5, _ %ebx = LEA64_32r killed %rbp, 1, killed %rax, -5, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: test1lea_rbp_64_32 name: test1lea_rbp_64_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 16 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %ebx = LEA64_32r killed %rax, 1, killed %rbp, 0, _ ; CHECK: %ebx = LEA64_32r killed %rax, 1, killed %rbp, 0, %noreg
%ebx = LEA64_32r killed %rbp, 1, killed %rax, 0, _ %ebx = LEA64_32r killed %rbp, 1, killed %rax, 0, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: testleaadd_64 name: testleaadd_64
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 16 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %rbx = LEA64r killed %rax, 1, killed %rbp, 0, _ ; CHECK: %rbx = LEA64r killed %rax, 1, killed %rbp, 0, %noreg
; CHECK: %rbx = ADD64ri8 %rbx, -5 ; CHECK: %rbx = ADD64ri8 %rbx, -5
%rbx = LEA64r killed %rax, 1, killed %rbp, -5, _ %rbx = LEA64r killed %rax, 1, killed %rbp, -5, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: testleaadd_rbp_64 name: testleaadd_rbp_64
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 16 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %rbx = LEA64r killed %rax, 1, killed %rbp, 0, _ ; CHECK: %rbx = LEA64r killed %rax, 1, killed %rbp, 0, %noreg
; CHECK: %rbx = ADD64ri8 %rbx, -5 ; CHECK: %rbx = ADD64ri8 %rbx, -5
%rbx = LEA64r killed %rbp, 1, killed %rax, -5, _ %rbx = LEA64r killed %rbp, 1, killed %rax, -5, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: test1lea_rbp_64 name: test1lea_rbp_64
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 16 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %rbx = LEA64r killed %rax, 1, killed %rbp, 0, _ ; CHECK: %rbx = LEA64r killed %rax, 1, killed %rbp, 0, %noreg
%rbx = LEA64r killed %rbp, 1, killed %rax, 0, _ %rbx = LEA64r killed %rbp, 1, killed %rax, 0, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: test8 name: test8
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rdi, %rbp liveins: %rdi, %rbp
; CHECK: %r12 = LEA64r _, 2, killed %r13, 5, _ ; CHECK: %r12 = LEA64r %noreg, 2, killed %r13, 5, %noreg
; CHECK: %r12 = ADD64rr %r12, killed %rbp ; CHECK: %r12 = ADD64rr %r12, killed %rbp
%rbp = KILL %rbp, implicit-def %rbp %rbp = KILL %rbp, implicit-def %rbp
%r13 = KILL %rdi, implicit-def %r13 %r13 = KILL %rdi, implicit-def %r13
%r12 = LEA64r killed %rbp, 2, killed %r13, 5, _ %r12 = LEA64r killed %rbp, 2, killed %r13, 5, %noreg
RETQ %r12 RETQ %r12
... ...
--- ---
name: testleaaddi32_64_32 name: testleaaddi32_64_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 18 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %eax = LEA64_32r killed %rax, 1, killed %rbp, 0 ; CHECK: %eax = LEA64_32r killed %rax, 1, killed %rbp, 0
; CHECK: %eax = ADD32ri %eax, 129 ; CHECK: %eax = ADD32ri %eax, 129
%eax = LEA64_32r killed %rax, 1, killed %rbp, 129, _ %eax = LEA64_32r killed %rax, 1, killed %rbp, 129, %noreg
RETQ %eax RETQ %eax
... ...
--- ---
name: test1mov1add_rbp_64_32 name: test1mov1add_rbp_64_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp, %rbx liveins: %rax, %rbp, %rbx
; CHECK: %ebx = LEA64_32r killed %rbp, 1, killed %rbp, 0, _ ; CHECK: %ebx = LEA64_32r killed %rbp, 1, killed %rbp, 0, %noreg
%ebx = LEA64_32r killed %rbp, 1, killed %rbp, 0, _ %ebx = LEA64_32r killed %rbp, 1, killed %rbp, 0, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: testleaadd_rbp_index_64_32 name: testleaadd_rbp_index_64_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp, %rbx liveins: %rax, %rbp, %rbx
; CHECK: %ebx = LEA64_32r killed %rbp, 1, killed %rbp, 5, _ ; CHECK: %ebx = LEA64_32r killed %rbp, 1, killed %rbp, 5, %noreg
%ebx = LEA64_32r killed %rbp, 1, killed %rbp, 5, _ %ebx = LEA64_32r killed %rbp, 1, killed %rbp, 5, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: testleaadd_rbp_index2_64_32 name: testleaadd_rbp_index2_64_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %eax, %ebp, %ebx liveins: %eax, %ebp, %ebx
; CHECK: %ebx = LEA64_32r killed %rbp, 4, killed %rbp, 5, _ ; CHECK: %ebx = LEA64_32r killed %rbp, 4, killed %rbp, 5, %noreg
%ebx = LEA64_32r killed %rbp, 4, killed %rbp, 5, _ %ebx = LEA64_32r killed %rbp, 4, killed %rbp, 5, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: test2addi32_64 name: test2addi32_64
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 18 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp liveins: %rax, %rbp
; CHECK: %rax = ADD64rr %rax, killed %rbp ; CHECK: %rax = ADD64rr %rax, killed %rbp
; CHECK: %rax = ADD64ri32 %rax, 129 ; CHECK: %rax = ADD64ri32 %rax, 129
%rax = LEA64r killed %rax, 1, killed %rbp, 129, _ %rax = LEA64r killed %rax, 1, killed %rbp, 129, %noreg
RETQ %eax RETQ %eax
... ...
--- ---
name: test1mov1add_rbp_64 name: test1mov1add_rbp_64
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 18 LinesframeInfo:
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp, %rbx liveins: %rax, %rbp, %rbx
; CHECK: %rbx = MOV64rr %rbp ; CHECK: %rbx = MOV64rr %rbp
; CHECK: %rbx = ADD64rr %rbx, %rbp ; CHECK: %rbx = ADD64rr %rbx, %rbp
%rbx = LEA64r %rbp, 1, %rbp, 0, _ %rbx = LEA64r %rbp, 1, %rbp, 0, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: testleaadd_rbp_index_64 name: testleaadd_rbp_index_64
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp, %rbx liveins: %rax, %rbp, %rbx
; CHECK: %rbx = LEA64r _, 1, %rbp, 5, _ ; CHECK: %rbx = LEA64r %noreg, 1, %rbp, 5, %noreg
; CHECK: %rbx = ADD64rr %rbx, %rbp ; CHECK: %rbx = ADD64rr %rbx, %rbp
%rbx = LEA64r %rbp, 1, %rbp, 5, _ %rbx = LEA64r %rbp, 1, %rbp, 5, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: testleaadd_rbp_index2_64 name: testleaadd_rbp_index2_64
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp, %rbx liveins: %rax, %rbp, %rbx
; CHECK: %rbx = LEA64r _, 4, %rbp, 5, _ ; CHECK: %rbx = LEA64r %noreg, 4, %rbp, 5, %noreg
; CHECK: %rbx = ADD64rr %rbx, %rbp ; CHECK: %rbx = ADD64rr %rbx, %rbp
%rbx = LEA64r %rbp, 4, %rbp, 5, _ %rbx = LEA64r %rbp, 4, %rbp, 5, %noreg
RETQ %ebx RETQ %ebx
... ...
--- ---
name: test_skip_opt_64 name: test_skip_opt_64
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp, %rbx liveins: %rax, %rbp, %rbx
; CHECK: %rbp = LEA64r killed %rbp, 4, killed %rbp, 0, _ ; CHECK: %rbp = LEA64r killed %rbp, 4, killed %rbp, 0, %noreg
%rbp = LEA64r killed %rbp, 4, killed %rbp, 0, _ %rbp = LEA64r killed %rbp, 4, killed %rbp, 0, %noreg
RETQ %ebp RETQ %ebp
... ...
--- ---
name: test_skip_eflags_64 name: test_skip_eflags_64
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp, %rbx liveins: %rax, %rbp, %rbx
; CHECK: %rbx = LEA64r killed %rax, 4, killed %rax, 5, _ ; CHECK: %rbx = LEA64r killed %rax, 4, killed %rax, 5, %noreg
; CHECK: %rbp = LEA64r killed %rbx, 4, killed %rbx, 0, _ ; CHECK: %rbp = LEA64r killed %rbx, 4, killed %rbx, 0, %noreg
; CHECK: %rbp = ADD64ri8 %rbp, 5 ; CHECK: %rbp = ADD64ri8 %rbp, 5
CMP64rr %rax, killed %rbx, implicit-def %eflags CMP64rr %rax, killed %rbx, implicit-def %eflags
%rbx = LEA64r killed %rax, 4, killed %rax, 5, _ %rbx = LEA64r killed %rax, 4, killed %rax, 5, %noreg
JE_1 %bb.1, implicit %eflags JE_1 %bb.1, implicit %eflags
RETQ %ebx RETQ %ebx
bb.1: bb.1:
liveins: %rax, %rbp, %rbx liveins: %rax, %rbp, %rbx
%rbp = LEA64r killed %rbx, 4, killed %rbx, 5, _ %rbp = LEA64r killed %rbx, 4, killed %rbx, 5, %noreg
RETQ %ebp RETQ %ebp
... ...
--- ---
name: test_skip_opt_64_32 name: test_skip_opt_64_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp, %rbx liveins: %rax, %rbp, %rbx
; CHECK: %ebp = LEA64_32r killed %rbp, 4, killed %rbp, 0, _ ; CHECK: %ebp = LEA64_32r killed %rbp, 4, killed %rbp, 0, %noreg
%ebp = LEA64_32r killed %rbp, 4, killed %rbp, 0, _ %ebp = LEA64_32r killed %rbp, 4, killed %rbp, 0, %noreg
RETQ %ebp RETQ %ebp
... ...
--- ---
name: test_skip_eflags_64_32 name: test_skip_eflags_64_32
alignment: 4 alignment: 4
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
Show All 15 LinesframeInfo:
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0 (%ir-block.0): bb.0 (%ir-block.0):
liveins: %rax, %rbp, %rbx liveins: %rax, %rbp, %rbx
; CHECK: %ebx = LEA64_32r killed %rax, 4, killed %rax, 5, _ ; CHECK: %ebx = LEA64_32r killed %rax, 4, killed %rax, 5, %noreg
; CHECK: %ebp = LEA64_32r killed %rbx, 4, killed %rbx, 0, _ ; CHECK: %ebp = LEA64_32r killed %rbx, 4, killed %rbx, 0, %noreg
; CHECK: %ebp = ADD32ri8 %ebp, 5 ; CHECK: %ebp = ADD32ri8 %ebp, 5
CMP64rr %rax, killed %rbx, implicit-def %eflags CMP64rr %rax, killed %rbx, implicit-def %eflags
%ebx = LEA64_32r killed %rax, 4, killed %rax, 5, _ %ebx = LEA64_32r killed %rax, 4, killed %rax, 5, %noreg
JE_1 %bb.1, implicit %eflags JE_1 %bb.1, implicit %eflags
RETQ %ebx RETQ %ebx
bb.1: bb.1:
liveins: %rax, %rbp, %rbx liveins: %rax, %rbp, %rbx
%ebp = LEA64_32r killed %rbx, 4, killed %rbx, 5, _ %ebp = LEA64_32r killed %rbx, 4, killed %rbx, 5, %noreg
RETQ %ebp RETQ %ebp
... ...

llvm/trunk/test/CodeGen/X86/movtopush.mir

Show All 35 Lines
# CHECK: ADJCALLSTACKDOWN32 16, 0, 16, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp # CHECK: ADJCALLSTACKDOWN32 16, 0, 16, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp
# CHECK-NEXT: PUSH32i8 4, implicit-def %esp, implicit %esp # CHECK-NEXT: PUSH32i8 4, implicit-def %esp, implicit %esp
# CHECK-NEXT: PUSH32i8 3, implicit-def %esp, implicit %esp # CHECK-NEXT: PUSH32i8 3, implicit-def %esp, implicit %esp
# CHECK-NEXT: PUSH32i8 2, implicit-def %esp, implicit %esp # CHECK-NEXT: PUSH32i8 2, implicit-def %esp, implicit %esp
# CHECK-NEXT: PUSH32i8 1, implicit-def %esp, implicit %esp # CHECK-NEXT: PUSH32i8 1, implicit-def %esp, implicit %esp
# CHECK-NEXT: CALLpcrel32 @good, csr_32, implicit %esp, implicit %ssp, implicit-def %esp, implicit-def %ssp # CHECK-NEXT: CALLpcrel32 @good, csr_32, implicit %esp, implicit %ssp, implicit-def %esp, implicit-def %ssp
# CHECK-NEXT: ADJCALLSTACKUP32 16, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp # CHECK-NEXT: ADJCALLSTACKUP32 16, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp
# CHECK-NEXT: ADJCALLSTACKDOWN32 20, 0, 20, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp # CHECK-NEXT: ADJCALLSTACKDOWN32 20, 0, 20, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp
# CHECK-NEXT: %1:gr32 = MOV32rm %stack.2.s, 1, _, 0, _ :: (load 4 from %stack.2.s, align 8) # CHECK-NEXT: %1:gr32 = MOV32rm %stack.2.s, 1, %noreg, 0, %noreg :: (load 4 from %stack.2.s, align 8)
# CHECK-NEXT: %2:gr32 = MOV32rm %stack.2.s, 1, _, 4, _ :: (load 4 from %stack.2.s + 4) # CHECK-NEXT: %2:gr32 = MOV32rm %stack.2.s, 1, %noreg, 4, %noreg :: (load 4 from %stack.2.s + 4)
# CHECK-NEXT: %4:gr32 = LEA32r %stack.0.p, 1, _, 0, _ # CHECK-NEXT: %4:gr32 = LEA32r %stack.0.p, 1, %noreg, 0, %noreg
# CHECK-NEXT: %5:gr32 = LEA32r %stack.1.q, 1, _, 0, _ # CHECK-NEXT: %5:gr32 = LEA32r %stack.1.q, 1, %noreg, 0, %noreg
# CHECK-NEXT: PUSH32r %4, implicit-def %esp, implicit %esp # CHECK-NEXT: PUSH32r %4, implicit-def %esp, implicit %esp
# CHECK-NEXT: PUSH32r %5, implicit-def %esp, implicit %esp # CHECK-NEXT: PUSH32r %5, implicit-def %esp, implicit %esp
# CHECK-NEXT: PUSH32i8 6, implicit-def %esp, implicit %esp # CHECK-NEXT: PUSH32i8 6, implicit-def %esp, implicit %esp
# CHECK-NEXT: PUSH32r %2, implicit-def %esp, implicit %esp # CHECK-NEXT: PUSH32r %2, implicit-def %esp, implicit %esp
# CHECK-NEXT: PUSH32r %1, implicit-def %esp, implicit %esp # CHECK-NEXT: PUSH32r %1, implicit-def %esp, implicit %esp
# CHECK-NEXT: CALLpcrel32 @struct, csr_32, implicit %esp, implicit %ssp, implicit-def %esp, implicit-def %ssp # CHECK-NEXT: CALLpcrel32 @struct, csr_32, implicit %esp, implicit %ssp, implicit-def %esp, implicit-def %ssp
# CHECK-NEXT: ADJCALLSTACKUP32 20, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp # CHECK-NEXT: ADJCALLSTACKUP32 20, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp
# CHECK-NEXT: RET 0 # CHECK-NEXT: RET 0
Show All 40 Linesstack:
- { id: 2, name: s, type: default, offset: 0, size: 8, alignment: 8, - { id: 2, name: s, type: default, offset: 0, size: 8, alignment: 8,
stack-id: 0, callee-saved-register: '', callee-saved-restored: true, stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
di-variable: '', di-expression: '', di-location: '' } di-variable: '', di-expression: '', di-location: '' }
constants: constants:
body: | body: |
bb.0.entry: bb.0.entry:
ADJCALLSTACKDOWN32 16, 0, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp ADJCALLSTACKDOWN32 16, 0, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp
%0 = COPY %esp %0 = COPY %esp
MOV32mi %0, 1, _, 12, _, 4 :: (store 4 into stack + 12) MOV32mi %0, 1, %noreg, 12, %noreg, 4 :: (store 4 into stack + 12)
MOV32mi %0, 1, _, 8, _, 3 :: (store 4 into stack + 8) MOV32mi %0, 1, %noreg, 8, %noreg, 3 :: (store 4 into stack + 8)
MOV32mi %0, 1, _, 4, _, 2 :: (store 4 into stack + 4) MOV32mi %0, 1, %noreg, 4, %noreg, 2 :: (store 4 into stack + 4)
MOV32mi %0, 1, _, 0, _, 1 :: (store 4 into stack) MOV32mi %0, 1, %noreg, 0, %noreg, 1 :: (store 4 into stack)
CALLpcrel32 @good, csr_32, implicit %esp, implicit %ssp, implicit-def %esp, implicit-def %ssp CALLpcrel32 @good, csr_32, implicit %esp, implicit %ssp, implicit-def %esp, implicit-def %ssp
ADJCALLSTACKUP32 16, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp ADJCALLSTACKUP32 16, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp
ADJCALLSTACKDOWN32 20, 0, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp ADJCALLSTACKDOWN32 20, 0, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp
%1 = MOV32rm %stack.2.s, 1, _, 0, _ :: (load 4 from %stack.2.s, align 8) %1 = MOV32rm %stack.2.s, 1, %noreg, 0, %noreg :: (load 4 from %stack.2.s, align 8)
%2 = MOV32rm %stack.2.s, 1, _, 4, _ :: (load 4 from %stack.2.s + 4) %2 = MOV32rm %stack.2.s, 1, %noreg, 4, %noreg :: (load 4 from %stack.2.s + 4)
%3 = COPY %esp %3 = COPY %esp
MOV32mr %3, 1, _, 4, _, killed %2 :: (store 4) MOV32mr %3, 1, %noreg, 4, %noreg, killed %2 :: (store 4)
MOV32mr %3, 1, _, 0, _, killed %1 :: (store 4) MOV32mr %3, 1, %noreg, 0, %noreg, killed %1 :: (store 4)
%4 = LEA32r %stack.0.p, 1, _, 0, _ %4 = LEA32r %stack.0.p, 1, %noreg, 0, %noreg
MOV32mr %3, 1, _, 16, _, killed %4 :: (store 4 into stack + 16) MOV32mr %3, 1, %noreg, 16, %noreg, killed %4 :: (store 4 into stack + 16)
%5 = LEA32r %stack.1.q, 1, _, 0, _ %5 = LEA32r %stack.1.q, 1, %noreg, 0, %noreg
MOV32mr %3, 1, _, 12, _, killed %5 :: (store 4 into stack + 12) MOV32mr %3, 1, %noreg, 12, %noreg, killed %5 :: (store 4 into stack + 12)
MOV32mi %3, 1, _, 8, _, 6 :: (store 4 into stack + 8) MOV32mi %3, 1, %noreg, 8, %noreg, 6 :: (store 4 into stack + 8)
CALLpcrel32 @struct, csr_32, implicit %esp, implicit %ssp, implicit-def %esp, implicit-def %ssp, CALLpcrel32 @struct, csr_32, implicit %esp, implicit %ssp, implicit-def %esp, implicit-def %ssp,
ADJCALLSTACKUP32 20, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp ADJCALLSTACKUP32 20, 0, implicit-def dead %esp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %esp, implicit %ssp
RET 0 RET 0
... ...

llvm/trunk/test/CodeGen/X86/non-value-mem-operand.mir

Show First 20 Lines • Show All 169 Lines • ▼ Show 20 Lines bb.2:
%xmm0 = XORPSrr undef %xmm0, undef %xmm0 %xmm0 = XORPSrr undef %xmm0, undef %xmm0
%ebx = IMPLICIT_DEF implicit-def %rbx %ebx = IMPLICIT_DEF implicit-def %rbx
JMP_1 %bb.12.bb51 JMP_1 %bb.12.bb51
bb.3.bb3: bb.3.bb3:
successors: %bb.4.bb7(0x80000000) successors: %bb.4.bb7(0x80000000)
liveins: %rax liveins: %rax
MOV64mr %rsp, 1, _, 32, _, %rax :: (store 8 into %stack.5) MOV64mr %rsp, 1, %noreg, 32, %noreg, %rax :: (store 8 into %stack.5)
%r12 = MOV64rr killed %rax %r12 = MOV64rr killed %rax
%r12 = ADD64ri8 killed %r12, 16, implicit-def dead %eflags %r12 = ADD64ri8 killed %r12, 16, implicit-def dead %eflags
%xmm0 = XORPSrr undef %xmm0, undef %xmm0 %xmm0 = XORPSrr undef %xmm0, undef %xmm0
%esi = XOR32rr undef %esi, undef %esi, implicit-def dead %eflags %esi = XOR32rr undef %esi, undef %esi, implicit-def dead %eflags
%rax = MOV64ri %const.0 %rax = MOV64ri %const.0
%xmm1 = MOVSDrm killed %rax, 1, _, 0, _ :: (load 8 from constant-pool) %xmm1 = MOVSDrm killed %rax, 1, %noreg, 0, %noreg :: (load 8 from constant-pool)
MOVSDmr %rsp, 1, _, 40, _, killed %xmm1 :: (store 8 into %stack.4) MOVSDmr %rsp, 1, %noreg, 40, %noreg, killed %xmm1 :: (store 8 into %stack.4)
%eax = IMPLICIT_DEF %eax = IMPLICIT_DEF
%ecx = XOR32rr undef %ecx, undef %ecx, implicit-def dead %eflags %ecx = XOR32rr undef %ecx, undef %ecx, implicit-def dead %eflags
bb.4.bb7: bb.4.bb7:
successors: %bb.6.bb26(0x40000000), %bb.5.bb15(0x40000000) successors: %bb.6.bb26(0x40000000), %bb.5.bb15(0x40000000)
liveins: %eax, %ecx, %esi, %r12, %xmm0 liveins: %eax, %ecx, %esi, %r12, %xmm0
%ebp = MOV32rr killed %ecx %ebp = MOV32rr killed %ecx
%ebx = MOV32rr killed %eax, implicit-def %rbx %ebx = MOV32rr killed %eax, implicit-def %rbx
%r14d = MOV32rr %ebx, implicit-def %r14 %r14d = MOV32rr %ebx, implicit-def %r14
TEST8rr %sil, %sil, implicit-def %eflags TEST8rr %sil, %sil, implicit-def %eflags
JNE_1 %bb.6.bb26, implicit %eflags JNE_1 %bb.6.bb26, implicit %eflags
bb.5.bb15: bb.5.bb15:
successors: %bb.6.bb26(0x80000000) successors: %bb.6.bb26(0x80000000)
liveins: %ebp, %rbx, %r14, %xmm0 liveins: %ebp, %rbx, %r14, %xmm0
MOV32mr %rsp, 1, _, 24, _, %ebx :: (store 4 into %stack.0, align 8) MOV32mr %rsp, 1, %noreg, 24, %noreg, %ebx :: (store 4 into %stack.0, align 8)
MOV32mr %rsp, 1, _, 16, _, %ebp :: (store 4 into %stack.1, align 8) MOV32mr %rsp, 1, %noreg, 16, %noreg, %ebp :: (store 4 into %stack.1, align 8)
MOVSDmr %rsp, 1, _, 8, _, killed %xmm0 :: (store 8 into %stack.2) MOVSDmr %rsp, 1, %noreg, 8, %noreg, killed %xmm0 :: (store 8 into %stack.2)
%rax = MOV64rm %rsp, 1, _, 32, _ :: (load 8 from %stack.5) %rax = MOV64rm %rsp, 1, %noreg, 32, %noreg :: (load 8 from %stack.5)
MOV64mr %rsp, 1, _, 48, _, killed %rax :: (store 8 into %stack.3) MOV64mr %rsp, 1, %noreg, 48, %noreg, killed %rax :: (store 8 into %stack.3)
%rax = MOV64ri @wibble %rax = MOV64ri @wibble
STATEPOINT 2882400000, 0, 0, killed %rax, 2, 0, 2, 0, 2, 30, 2, 1, 2, 0, 2, 99, 2, 0, 2, 12, 2, 0, 2, 10, 1, 8, %rsp, 24, 2, 10, 2, 0, 2, 10, 1, 8, %rsp, 16, 2, 10, 2, 4278124286, 2, 6, 2, 4278124286, 2, 7, 1, 8, %rsp, 8, 2, 99, 2, 0, 2, 7, 2, 4278124286, 2, 99, 2, 0, 2, 13, 1, 8, %rsp, 48, 2, 7, 2, 4278124286, 2, 99, 2, 0, csr_64, implicit-def %rsp :: (volatile load 8 from %stack.0), (volatile load 8 from %stack.1), (volatile load 8 from %stack.2), (volatile load 8 from %stack.3) STATEPOINT 2882400000, 0, 0, killed %rax, 2, 0, 2, 0, 2, 30, 2, 1, 2, 0, 2, 99, 2, 0, 2, 12, 2, 0, 2, 10, 1, 8, %rsp, 24, 2, 10, 2, 0, 2, 10, 1, 8, %rsp, 16, 2, 10, 2, 4278124286, 2, 6, 2, 4278124286, 2, 7, 1, 8, %rsp, 8, 2, 99, 2, 0, 2, 7, 2, 4278124286, 2, 99, 2, 0, 2, 13, 1, 8, %rsp, 48, 2, 7, 2, 4278124286, 2, 99, 2, 0, csr_64, implicit-def %rsp :: (volatile load 8 from %stack.0), (volatile load 8 from %stack.1), (volatile load 8 from %stack.2), (volatile load 8 from %stack.3)
%esi = XOR32rr undef %esi, undef %esi, implicit-def dead %eflags %esi = XOR32rr undef %esi, undef %esi, implicit-def dead %eflags
%r12 = IMPLICIT_DEF %r12 = IMPLICIT_DEF
bb.6.bb26: bb.6.bb26:
successors: %bb.8.bb37(0x40000000), %bb.7.bb35(0x40000000) successors: %bb.8.bb37(0x40000000), %bb.7.bb35(0x40000000)
liveins: %ebp, %esi, %rbx, %r12, %r14 liveins: %ebp, %esi, %rbx, %r12, %r14
%rax = MOV64ri @global.1 %rax = MOV64ri @global.1
%rax = MOV64rm killed %rax, 1, _, 0, _ :: (dereferenceable load 8 from @global.1) %rax = MOV64rm killed %rax, 1, %noreg, 0, %noreg :: (dereferenceable load 8 from @global.1)
TEST64rr %rax, %rax, implicit-def %eflags TEST64rr %rax, %rax, implicit-def %eflags
%rax = CMOVE64rr undef %rax, killed %rax, implicit killed %eflags %rax = CMOVE64rr undef %rax, killed %rax, implicit killed %eflags
%ecx = MOV32rm undef %rax, 1, _, 0, _ :: (load 4 from `i32* undef`) %ecx = MOV32rm undef %rax, 1, %noreg, 0, %noreg :: (load 4 from `i32* undef`)
%rdx = MOV64rm %r12, 8, %r14, 0, _ :: (load 8 from %ir.tmp3) %rdx = MOV64rm %r12, 8, %r14, 0, %noreg :: (load 8 from %ir.tmp3)
%r15 = LEA64r %rdx, 1, _, 1, _ %r15 = LEA64r %rdx, 1, %noreg, 1, _
MOV64mr %r12, 8, %r14, 0, _, %r15 :: (store 8 into %ir.tmp3) MOV64mr %r12, 8, %r14, 0, %noreg, %r15 :: (store 8 into %ir.tmp3)
%ecx = SUB32rr killed %ecx, %edx, implicit-def dead %eflags, implicit killed %rdx %ecx = SUB32rr killed %ecx, %edx, implicit-def dead %eflags, implicit killed %rdx
MOV32mr undef %rax, 1, _, 0, _, killed %ecx :: (store 4 into `i32* undef`) MOV32mr undef %rax, 1, %noreg, 0, %noreg, killed %ecx :: (store 4 into `i32* undef`)
%r13 = MOV64rm killed %rax, 1, _, 768, _ :: (load 8 from %ir.tmp33) %r13 = MOV64rm killed %rax, 1, %noreg, 768, %noreg :: (load 8 from %ir.tmp33)
TEST8rr %sil, %sil, implicit-def %eflags TEST8rr %sil, %sil, implicit-def %eflags
%rax = IMPLICIT_DEF %rax = IMPLICIT_DEF
JNE_1 %bb.8.bb37, implicit %eflags JNE_1 %bb.8.bb37, implicit %eflags
bb.7.bb35: bb.7.bb35:
successors: %bb.8.bb37(0x80000000) successors: %bb.8.bb37(0x80000000)
liveins: %ebp, %rbx, %r12, %r13, %r14, %r15 liveins: %ebp, %rbx, %r12, %r13, %r14, %r15
%rsi = MOV64ri @global %rsi = MOV64ri @global
%rax = MOV64ri @ham %rax = MOV64ri @ham
CALL64r killed %rax, csr_64, implicit %rsp, implicit undef %rdi, implicit %rsi, implicit-def %rsp, implicit-def %rax CALL64r killed %rax, csr_64, implicit %rsp, implicit undef %rdi, implicit %rsi, implicit-def %rsp, implicit-def %rax
%esi = XOR32rr undef %esi, undef %esi, implicit-def dead %eflags %esi = XOR32rr undef %esi, undef %esi, implicit-def dead %eflags
bb.8.bb37: bb.8.bb37:
successors: %bb.9.bb37(0x40000000), %bb.10.bb37(0x40000000) successors: %bb.9.bb37(0x40000000), %bb.10.bb37(0x40000000)
liveins: %ebp, %esi, %rax, %rbx, %r12, %r13, %r14, %r15 liveins: %ebp, %esi, %rax, %rbx, %r12, %r13, %r14, %r15
%rcx = MOV64rm killed %rax, 1, _, 760, _ :: (load 8 from %ir.tmp40) %rcx = MOV64rm killed %rax, 1, %noreg, 760, %noreg :: (load 8 from %ir.tmp40)
CMP64rr %r13, %rcx, implicit-def %eflags CMP64rr %r13, %rcx, implicit-def %eflags
JL_1 %bb.10.bb37, implicit %eflags JL_1 %bb.10.bb37, implicit %eflags
bb.9.bb37: bb.9.bb37:
successors: %bb.10.bb37(0x80000000) successors: %bb.10.bb37(0x80000000)
liveins: %ebp, %esi, %rbx, %r12, %r13, %r14, %r15 liveins: %ebp, %esi, %rbx, %r12, %r13, %r14, %r15
%cl = MOV8rr %r13b, implicit killed %r13, implicit-def %rcx %cl = MOV8rr %r13b, implicit killed %r13, implicit-def %rcx
bb.10.bb37: bb.10.bb37:
successors: %bb.11.bb51.loopexit(0x00000800), %bb.4.bb7(0x7ffff800) successors: %bb.11.bb51.loopexit(0x00000800), %bb.4.bb7(0x7ffff800)
liveins: %ebp, %esi, %rbx, %rcx, %r12, %r14, %r15 liveins: %ebp, %esi, %rbx, %rcx, %r12, %r14, %r15
%cl = KILL %cl, implicit killed %rcx %cl = KILL %cl, implicit killed %rcx
%r15 = SAR64rCL killed %r15, implicit-def dead %eflags, implicit %cl %r15 = SAR64rCL killed %r15, implicit-def dead %eflags, implicit %cl
MOV64mr %r12, 8, killed %r14, 0, _, killed %r15 :: (store 8 into %ir.tmp7) MOV64mr %r12, 8, killed %r14, 0, %noreg, killed %r15 :: (store 8 into %ir.tmp7)
MOV64mi32 undef %rax, 1, _, 0, _, 0 :: (store 8 into `i64* undef`) MOV64mi32 undef %rax, 1, %noreg, 0, %noreg, 0 :: (store 8 into `i64* undef`)
%eax = LEA64_32r %rbx, 1, _, 1, _ %eax = LEA64_32r %rbx, 1, %noreg, 1, _
%ecx = MOV32ri 6 %ecx = MOV32ri 6
CMP32ri %eax, 15141, implicit-def %eflags CMP32ri %eax, 15141, implicit-def %eflags
%xmm0 = MOVSDrm %rsp, 1, _, 40, _ :: (load 8 from %stack.4) %xmm0 = MOVSDrm %rsp, 1, %noreg, 40, %noreg :: (load 8 from %stack.4)
JL_1 %bb.4.bb7, implicit %eflags JL_1 %bb.4.bb7, implicit %eflags
bb.11.bb51.loopexit: bb.11.bb51.loopexit:
successors: %bb.12.bb51(0x80000000) successors: %bb.12.bb51(0x80000000)
liveins: %ebp, %rbx liveins: %ebp, %rbx
%ebp = INC32r killed %ebp, implicit-def dead %eflags %ebp = INC32r killed %ebp, implicit-def dead %eflags
%ebx = INC32r %ebx, implicit-def dead %eflags, implicit killed %rbx, implicit-def %rbx %ebx = INC32r %ebx, implicit-def dead %eflags, implicit killed %rbx, implicit-def %rbx
%rax = MOV64ri %const.0 %rax = MOV64ri %const.0
%xmm0 = MOVSDrm killed %rax, 1, _, 0, _ :: (load 8 from constant-pool) %xmm0 = MOVSDrm killed %rax, 1, %noreg, 0, %noreg :: (load 8 from constant-pool)
bb.12.bb51: bb.12.bb51:
liveins: %ebp, %rbx, %xmm0 liveins: %ebp, %rbx, %xmm0
MOV32mr %rsp, 1, _, 24, _, %ebx, implicit killed %rbx :: (store 4 into %stack.0, align 8) MOV32mr %rsp, 1, %noreg, 24, %noreg, %ebx, implicit killed %rbx :: (store 4 into %stack.0, align 8)
MOV32mr %rsp, 1, _, 16, _, killed %ebp :: (store 4 into %stack.1, align 8) MOV32mr %rsp, 1, %noreg, 16, %noreg, killed %ebp :: (store 4 into %stack.1, align 8)
MOVSDmr %rsp, 1, _, 8, _, killed %xmm0 :: (store 8 into %stack.2) MOVSDmr %rsp, 1, %noreg, 8, %noreg, killed %xmm0 :: (store 8 into %stack.2)
%rax = MOV64ri @wobble %rax = MOV64ri @wobble
%edi = MOV32ri -121 %edi = MOV32ri -121
STATEPOINT 2882400000, 0, 1, killed %rax, %edi, 2, 0, 2, 0, 2, 38, 2, 1, 2, 0, 2, 270, 2, 4, 2, 12, 2, 0, 2, 11, 2, 4278124286, 2, 99, 2, 0, 2, 10, 1, 8, %rsp, 24, 2, 6, 2, 4278124286, 2, 99, 2, 0, 2, 99, 2, 0, 2, 10, 1, 8, %rsp, 16, 2, 10, 2, 4278124286, 2, 99, 2, 0, 2, 7, 1, 8, %rsp, 8, 2, 99, 2, 0, 2, 7, 2, 4278124286, 2, 99, 2, 0, 2, 13, 2, 4278124286, 2, 99, 2, 0, 2, 99, 2, 0, csr_64, implicit-def %rsp :: (volatile load 8 from %stack.0), (volatile load 8 from %stack.1), (volatile load 8 from %stack.2) STATEPOINT 2882400000, 0, 1, killed %rax, %edi, 2, 0, 2, 0, 2, 38, 2, 1, 2, 0, 2, 270, 2, 4, 2, 12, 2, 0, 2, 11, 2, 4278124286, 2, 99, 2, 0, 2, 10, 1, 8, %rsp, 24, 2, 6, 2, 4278124286, 2, 99, 2, 0, 2, 99, 2, 0, 2, 10, 1, 8, %rsp, 16, 2, 10, 2, 4278124286, 2, 99, 2, 0, 2, 7, 1, 8, %rsp, 8, 2, 99, 2, 0, 2, 7, 2, 4278124286, 2, 99, 2, 0, 2, 13, 2, 4278124286, 2, 99, 2, 0, 2, 99, 2, 0, csr_64, implicit-def %rsp :: (volatile load 8 from %stack.0), (volatile load 8 from %stack.1), (volatile load 8 from %stack.2)
bb.13.bb59: bb.13.bb59:
%rax = MOV64ri @wobble %rax = MOV64ri @wobble
%edi = MOV32ri 8 %edi = MOV32ri 8
STATEPOINT 2882400000, 0, 1, killed %rax, %edi, 2, 0, 2, 0, 2, 38, 2, 1, 2, 0, 2, 123, 2, 4, 2, 12, 2, 0, 2, 13, 2, 0, 2, 99, 2, 4278124286, 2, 13, 2, 0, 2, 10, 2, 4278124286, 2, 99, 2, 4278124286, 2, 99, 2, 4278124286, 2, 99, 2, 4278124286, 2, 99, 2, 0, 2, 99, 2, 4278124286, 2, 99, 2, 4278124286, 2, 99, 2, 0, 2, 99, 2, 4278124286, 2, 99, 2, 0, 2, 13, 2, 0, 2, 99, 2, 4278124286, 2, 99, 2, 0, csr_64, implicit-def %rsp STATEPOINT 2882400000, 0, 1, killed %rax, %edi, 2, 0, 2, 0, 2, 38, 2, 1, 2, 0, 2, 123, 2, 4, 2, 12, 2, 0, 2, 13, 2, 0, 2, 99, 2, 4278124286, 2, 13, 2, 0, 2, 10, 2, 4278124286, 2, 99, 2, 4278124286, 2, 99, 2, 4278124286, 2, 99, 2, 4278124286, 2, 99, 2, 0, 2, 99, 2, 4278124286, 2, 99, 2, 4278124286, 2, 99, 2, 0, 2, 99, 2, 4278124286, 2, 99, 2, 0, 2, 13, 2, 0, 2, 99, 2, 4278124286, 2, 99, 2, 0, csr_64, implicit-def %rsp
... ...

llvm/trunk/test/CodeGen/X86/peephole-recurrence.mir

Show First 20 Lines • Show All 209 Lines • ▼ Show 20 Linesbody: |
bb.5.bb7: bb.5.bb7:
successors: %bb.1.bb1(0x7c000000), %bb.6.bb8(0x04000000) successors: %bb.1.bb1(0x7c000000), %bb.6.bb8(0x04000000)
%2 = PHI %7, %bb.3.bb4, %10, %bb.4.bb6 %2 = PHI %7, %bb.3.bb4, %10, %bb.4.bb6
%11 = ADD32rr %1, %0, implicit-def dead %eflags %11 = ADD32rr %1, %0, implicit-def dead %eflags
; CHECK: %11:gr32 = ADD32rr ; CHECK: %11:gr32 = ADD32rr
; CHECK-SAME: %1, ; CHECK-SAME: %1,
; CHECK-SAME: %0, ; CHECK-SAME: %0,
MOV32mr %5, 1, _, 0, _, %0 :: (store 4 into %ir.p) MOV32mr %5, 1, %noreg, 0, %noreg, %0 :: (store 4 into %ir.p)
%3 = ADD32rr %2, killed %11, implicit-def dead %eflags %3 = ADD32rr %2, killed %11, implicit-def dead %eflags
; CHECK: %3:gr32 = ADD32rr ; CHECK: %3:gr32 = ADD32rr
; CHECK-SAME: %2, ; CHECK-SAME: %2,
; CHECK-SAME: %11, ; CHECK-SAME: %11,
%12 = SUB32ri8 %3, 10, implicit-def %eflags %12 = SUB32ri8 %3, 10, implicit-def %eflags
JL_1 %bb.1.bb1, implicit %eflags JL_1 %bb.1.bb1, implicit %eflags
JMP_1 %bb.6.bb8 JMP_1 %bb.6.bb8
bb.6.bb8: bb.6.bb8:
%13 = MOV32r0 implicit-def dead %eflags %13 = MOV32r0 implicit-def dead %eflags
%eax = COPY %13 %eax = COPY %13
RET 0, %eax RET 0, %eax
... ...

llvm/trunk/test/CodeGen/X86/post-ra-sched-with-debug.mir

Show First 20 Lines • Show All 244 Lines • ▼ Show 20 LinesfixedStack:
- { id: 2, type: spill-slot, offset: -16, size: 8, alignment: 16 } - { id: 2, type: spill-slot, offset: -16, size: 8, alignment: 16 }
stack: stack:
- { id: 0, offset: -36, size: 4, alignment: 4 } - { id: 0, offset: -36, size: 4, alignment: 4 }
body: | body: |
bb.0: bb.0:
successors: %bb.3, %bb.2 successors: %bb.3, %bb.2
liveins: %esi, %rdi, %r14, %rbx, %rbp liveins: %esi, %rdi, %r14, %rbx, %rbp
; CHECK: [[REGISTER:%r[a-z0-9]+]] = LEA64r {{%r[a-z0-9]+}}, 1, _, -20, _ ; CHECK: [[REGISTER:%r[a-z0-9]+]] = LEA64r {{%r[a-z0-9]+}}, 1, %noreg, -20, %noreg
; CHECK-NEXT: DBG_VALUE debug-use [[REGISTER]], debug-use _, ![[J_VAR]], !DIExpression(), debug-location ![[J_LOC]] ; CHECK-NEXT: DBG_VALUE debug-use [[REGISTER]], debug-use %noreg, ![[J_VAR]], !DIExpression(), debug-location ![[J_LOC]]
; CHECK-NEXT: DBG_VALUE debug-use [[REGISTER]], debug-use _, ![[I_VAR]], !DIExpression(), debug-location ![[I_LOC]] ; CHECK-NEXT: DBG_VALUE debug-use [[REGISTER]], debug-use %noreg, ![[I_VAR]], !DIExpression(), debug-location ![[I_LOC]]
frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION def_cfa_offset 16
CFI_INSTRUCTION offset %rbp, -16 CFI_INSTRUCTION offset %rbp, -16
%rbp = frame-setup MOV64rr %rsp %rbp = frame-setup MOV64rr %rsp
CFI_INSTRUCTION def_cfa_register %rbp CFI_INSTRUCTION def_cfa_register %rbp
frame-setup PUSH64r killed %r14, implicit-def %rsp, implicit %rsp frame-setup PUSH64r killed %r14, implicit-def %rsp, implicit %rsp
frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
%rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags
CFI_INSTRUCTION offset %rbx, -32 CFI_INSTRUCTION offset %rbx, -32
CFI_INSTRUCTION offset %r14, -24 CFI_INSTRUCTION offset %r14, -24
%r14d = MOV32rr %esi %r14d = MOV32rr %esi
%rbx = MOV64rr %rdi %rbx = MOV64rr %rdi
CALL64pcrel32 @_ZN1lC2Ei, csr_64, implicit %rsp, implicit %rdi, implicit %esi, implicit-def %rsp CALL64pcrel32 @_ZN1lC2Ei, csr_64, implicit %rsp, implicit %rdi, implicit %esi, implicit-def %rsp
%rdi = LEA64r %rbx, 1, _, 8, _ %rdi = LEA64r %rbx, 1, %noreg, 8, %noreg
DBG_VALUE debug-use %rdi, debug-use _, !20, !17, debug-location !27 DBG_VALUE debug-use %rdi, debug-use %noreg, !20, !17, debug-location !27
DBG_VALUE debug-use %rdi, debug-use _, !10, !17, debug-location !18 DBG_VALUE debug-use %rdi, debug-use %noreg, !10, !17, debug-location !18
%rax = MOV64rm %rbx, 1, _, 16, _ :: (load 8) %rax = MOV64rm %rbx, 1, %noreg, 16, %noreg :: (load 8)
MOV64mr %rbx, 1, _, 8, _, killed %rax :: (store 8) MOV64mr %rbx, 1, %noreg, 8, %noreg, killed %rax :: (store 8)
MOV64mr %rbx, 1, _, 24, _, %rdi :: (store 8) MOV64mr %rbx, 1, %noreg, 24, %noreg, %rdi :: (store 8)
%eax = MOV32ri -1 %eax = MOV32ri -1
%cl = MOV8rr %r14b, implicit killed %r14d %cl = MOV8rr %r14b, implicit killed %r14d
%eax = SHL32rCL killed %eax, implicit-def dead %eflags, implicit %cl %eax = SHL32rCL killed %eax, implicit-def dead %eflags, implicit %cl
MOV32mr %rbx, 1, _, 32, _, %eax :: (store 4, align 8) MOV32mr %rbx, 1, %noreg, 32, %noreg, %eax :: (store 4, align 8)
MOV32mi %rbp, 1, _, -20, _, 0 :: (store 4) MOV32mi %rbp, 1, %noreg, -20, %noreg, 0 :: (store 4)
%rcx = MOV64rm %rbx, 1, _, 8, _ :: (load 8) %rcx = MOV64rm %rbx, 1, %noreg, 8, %noreg :: (load 8)
MOV64mr %rip, 1, _, @n, _, %rcx :: (store 8) MOV64mr %rip, 1, %noreg, @n, %noreg, %rcx :: (store 8)
%edx = XOR32rr undef %edx, undef %edx, implicit-def dead %eflags, implicit-def %rdx %edx = XOR32rr undef %edx, undef %edx, implicit-def dead %eflags, implicit-def %rdx
TEST64rr %rcx, %rcx, implicit-def %eflags TEST64rr %rcx, %rcx, implicit-def %eflags
%esi = MOV32ri @o, implicit-def %rsi %esi = MOV32ri @o, implicit-def %rsi
%rsi = CMOVNE64rr killed %rsi, %rdx, implicit killed %eflags %rsi = CMOVNE64rr killed %rsi, %rdx, implicit killed %eflags
%rsi = OR64rr killed %rsi, killed %rcx, implicit-def %eflags %rsi = OR64rr killed %rsi, killed %rcx, implicit-def %eflags
%rcx = LEA64r %rbp, 1, _, -20, _ %rcx = LEA64r %rbp, 1, %noreg, -20, %noreg
DBG_VALUE debug-use %rcx, debug-use _, !46, !17, debug-location !48 DBG_VALUE debug-use %rcx, debug-use %noreg, !46, !17, debug-location !48
DBG_VALUE debug-use %rcx, debug-use _, !39, !17, debug-location !44 DBG_VALUE debug-use %rcx, debug-use %noreg, !39, !17, debug-location !44
DBG_VALUE %rbp, -20, !29, !17, debug-location !36 DBG_VALUE %rbp, -20, !29, !17, debug-location !36
%rcx = CMOVNE64rr killed %rcx, killed %rdx, implicit killed %eflags %rcx = CMOVNE64rr killed %rcx, killed %rdx, implicit killed %eflags
%rcx = OR64rr killed %rcx, killed %rsi, implicit-def dead %eflags %rcx = OR64rr killed %rcx, killed %rsi, implicit-def dead %eflags
%rdx = MOVSX64rm32 %rbx, 1, _, 0, _ :: (load 4, align 8) %rdx = MOVSX64rm32 %rbx, 1, %noreg, 0, %noreg :: (load 4, align 8)
TEST32mr killed %rcx, 4, killed %rdx, 0, _, killed %eax, implicit-def %eflags :: (load 4) TEST32mr killed %rcx, 4, killed %rdx, 0, %noreg, killed %eax, implicit-def %eflags :: (load 4)
JNE_1 %bb.2, implicit %eflags JNE_1 %bb.2, implicit %eflags
JMP_1 %bb.3 JMP_1 %bb.3
bb.1: bb.1:
successors: %bb.2 successors: %bb.2
liveins: %rbx, %rbp liveins: %rbx, %rbp
%rdi = MOV64rm %rbx, 1, _, 24, _ :: (load 8) %rdi = MOV64rm %rbx, 1, %noreg, 24, %noreg :: (load 8)
bb.2: bb.2:
successors: %bb.1, %bb.3 successors: %bb.1, %bb.3
liveins: %rbx, %rbp, %rsp, %rdi liveins: %rbx, %rbp, %rsp, %rdi
CALL64pcrel32 @_ZN1p2aaEv, csr_64, implicit %rsp, implicit %rdi, implicit-def %rsp, implicit-def %eax CALL64pcrel32 @_ZN1p2aaEv, csr_64, implicit %rsp, implicit %rdi, implicit-def %rsp, implicit-def %eax
%eax = KILL %eax, implicit-def %rax %eax = KILL %eax, implicit-def %rax
%ecx = LEA64_32r %rax, 1, _, -1, _, implicit-def %rcx %ecx = LEA64_32r %rax, 1, %noreg, -1, %noreg, implicit-def %rcx
%ecx = SHR32ri %ecx, 31, implicit-def dead %eflags, implicit killed %rcx, implicit-def %rcx %ecx = SHR32ri %ecx, 31, implicit-def dead %eflags, implicit killed %rcx, implicit-def %rcx
%eax = LEA64_32r killed %rax, 1, killed %rcx, -1, _ %eax = LEA64_32r killed %rax, 1, killed %rcx, -1, %noreg
%eax = SAR32r1 killed %eax, implicit-def dead %eflags %eax = SAR32r1 killed %eax, implicit-def dead %eflags
CMP32mr %rbx, 1, _, 0, _, killed %eax, implicit-def %eflags :: (load 4, align 8), (load 4, align 8) CMP32mr %rbx, 1, %noreg, 0, %noreg, killed %eax, implicit-def %eflags :: (load 4, align 8), (load 4, align 8)
JG_1 %bb.1, implicit killed %eflags JG_1 %bb.1, implicit killed %eflags
bb.3: bb.3:
liveins: %rbp liveins: %rbp
%rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags
%rbx = POP64r implicit-def %rsp, implicit %rsp %rbx = POP64r implicit-def %rsp, implicit %rsp
%r14 = POP64r implicit-def %rsp, implicit %rsp %r14 = POP64r implicit-def %rsp, implicit %rsp
%rbp = POP64r implicit-def %rsp, implicit %rsp %rbp = POP64r implicit-def %rsp, implicit %rsp
RETQ RETQ
... ...

llvm/trunk/test/CodeGen/X86/pr27681.mir

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Linesbody: |
bb.1: bb.1:
liveins: %eax, %ebp, %ebx, %ecx, %edi, %edx liveins: %eax, %ebp, %ebx, %ecx, %edi, %edx
%ebp = SHR32rCL killed %ebp, implicit-def dead %eflags, implicit %cl %ebp = SHR32rCL killed %ebp, implicit-def dead %eflags, implicit %cl
%ebp = XOR32rr killed %ebp, killed %ebx, implicit-def dead %eflags %ebp = XOR32rr killed %ebp, killed %ebx, implicit-def dead %eflags
TEST32rr %edx, %edx, implicit-def %eflags TEST32rr %edx, %edx, implicit-def %eflags
%cl = SETNEr implicit %eflags %cl = SETNEr implicit %eflags
; This %bl def is antidependent on the above use of %ebx ; This %bl def is antidependent on the above use of %ebx
%bl = MOV8rm %esp, 1, _, 3, _ ; :: (load 1 from %stack.0) %bl = MOV8rm %esp, 1, %noreg, 3, _ ; :: (load 1 from %stack.0)
%cl = OR8rr killed %cl, %bl, implicit-def dead %eflags %cl = OR8rr killed %cl, %bl, implicit-def dead %eflags
%esi = MOVZX32rr8 killed %cl %esi = MOVZX32rr8 killed %cl
%esi = ADD32rr killed %esi, killed %edi, implicit-def dead %eflags %esi = ADD32rr killed %esi, killed %edi, implicit-def dead %eflags
%ecx = MOV32rm %esp, 1, _, 24, _ ; :: (load 4 from %stack.2) %ecx = MOV32rm %esp, 1, %noreg, 24, _ ; :: (load 4 from %stack.2)
%edx = SAR32rCL killed %edx, implicit-def dead %eflags, implicit %cl %edx = SAR32rCL killed %edx, implicit-def dead %eflags, implicit %cl
TEST32rr killed %edx, %edx, implicit-def %eflags TEST32rr killed %edx, %edx, implicit-def %eflags
%cl = SETNEr implicit %eflags %cl = SETNEr implicit %eflags
; Verify that removal of the %bl antidependence does not use %ch ; Verify that removal of the %bl antidependence does not use %ch
; as a replacement register. ; as a replacement register.
; CHECK: %cl = AND8rr killed %cl, killed %b ; CHECK: %cl = AND8rr killed %cl, killed %b
%cl = AND8rr killed %cl, killed %bl, implicit-def dead %eflags %cl = AND8rr killed %cl, killed %bl, implicit-def dead %eflags
CMP32ri8 %ebp, -1, implicit-def %eflags CMP32ri8 %ebp, -1, implicit-def %eflags
%edx = MOV32ri 0 %edx = MOV32ri 0
JE_1 %bb.3, implicit %eflags JE_1 %bb.3, implicit %eflags
bb.2: bb.2:
liveins: %cl, %eax, %ebp, %esi liveins: %cl, %eax, %ebp, %esi
OR32mr %esp, 1, _, 8, _, killed %eax, implicit-def %eflags ; :: (store 4 into %stack.1) OR32mr %esp, 1, %noreg, 8, %noreg, killed %eax, implicit-def %eflags ; :: (store 4 into %stack.1)
%dl = SETNEr implicit %eflags, implicit-def %edx %dl = SETNEr implicit %eflags, implicit-def %edx
bb.3: bb.3:
liveins: %cl, %ebp, %edx, %esi liveins: %cl, %ebp, %edx, %esi
%eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
%esp = ADD32ri8 %esp, 36, implicit-def dead %eflags %esp = ADD32ri8 %esp, 36, implicit-def dead %eflags
%esi = POP32r implicit-def %esp, implicit %esp %esi = POP32r implicit-def %esp, implicit %esp
%edi = POP32r implicit-def %esp, implicit %esp %edi = POP32r implicit-def %esp, implicit %esp
%ebx = POP32r implicit-def %esp, implicit %esp %ebx = POP32r implicit-def %esp, implicit %esp
%ebp = POP32r implicit-def %esp, implicit %esp %ebp = POP32r implicit-def %esp, implicit %esp
RET 0, %eax RET 0, %eax
... ...

llvm/trunk/test/CodeGen/X86/pre-coalesce.mir

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 LinesframeInfo:
adjustsStack: false adjustsStack: false
hasCalls: false hasCalls: false
maxCallFrameSize: 0 maxCallFrameSize: 0
hasOpaqueSPAdjustment: false hasOpaqueSPAdjustment: false
hasVAStart: false hasVAStart: false
hasMustTailInVarArgFunc: false hasMustTailInVarArgFunc: false
body: | body: |
bb.0.entry: bb.0.entry:
%0 = MOV64rm %rip, 1, _, @b, _ :: (dereferenceable load 8 from @b) %0 = MOV64rm %rip, 1, %noreg, @b, %noreg :: (dereferenceable load 8 from @b)
%12 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.t0) %12 = MOV8rm %0, 1, %noreg, 0, %noreg :: (load 1 from %ir.t0)
TEST8rr %12, %12, implicit-def %eflags TEST8rr %12, %12, implicit-def %eflags
%11 = MOV32rm %rip, 1, _, @a, _ :: (dereferenceable load 4 from @a) %11 = MOV32rm %rip, 1, %noreg, @a, %noreg :: (dereferenceable load 4 from @a)
JNE_1 %bb.1.while.body.preheader, implicit killed %eflags JNE_1 %bb.1.while.body.preheader, implicit killed %eflags
bb.4: bb.4:
%10 = COPY %11 %10 = COPY %11
JMP_1 %bb.3.while.end JMP_1 %bb.3.while.end
bb.1.while.body.preheader: bb.1.while.body.preheader:
bb.2.while.body: bb.2.while.body:
%8 = MOVSX32rr8 %12 %8 = MOVSX32rr8 %12
%10 = COPY %11 %10 = COPY %11
%10 = SHL32ri %10, 5, implicit-def dead %eflags %10 = SHL32ri %10, 5, implicit-def dead %eflags
%10 = ADD32rr %10, %11, implicit-def dead %eflags %10 = ADD32rr %10, %11, implicit-def dead %eflags
%10 = ADD32rr %10, %8, implicit-def dead %eflags %10 = ADD32rr %10, %8, implicit-def dead %eflags
MOV32mr %rip, 1, _, @a, _, %10 :: (store 4 into @a) MOV32mr %rip, 1, %noreg, @a, %noreg, %10 :: (store 4 into @a)
%12 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.t0) %12 = MOV8rm %0, 1, %noreg, 0, %noreg :: (load 1 from %ir.t0)
TEST8rr %12, %12, implicit-def %eflags TEST8rr %12, %12, implicit-def %eflags
%11 = COPY %10 %11 = COPY %10
JNE_1 %bb.2.while.body, implicit killed %eflags JNE_1 %bb.2.while.body, implicit killed %eflags
JMP_1 %bb.3.while.end JMP_1 %bb.3.while.end
bb.3.while.end: bb.3.while.end:
%eax = COPY %10 %eax = COPY %10
RET 0, killed %eax RET 0, killed %eax
... ...

llvm/trunk/test/CodeGen/X86/system-intrinsics-xgetbv.ll

Show All 12 Lines
; CHECK64: shlq $32, %rdx ; CHECK64: shlq $32, %rdx
; CHECK64: orq %rdx, %rax ; CHECK64: orq %rdx, %rax
; CHECK64: ret ; CHECK64: ret
%1 = call i64 @llvm.x86.xgetbv(i32 %in) %1 = call i64 @llvm.x86.xgetbv(i32 %in)
ret i64 %1; ret i64 %1;
} }
declare i64 @llvm.x86.xgetbv(i32) declare i64 @llvm.x86.xgetbv(i32)
No newline at end of file

llvm/trunk/test/CodeGen/X86/tail-merge-after-mbp.mir

# RUN: llc -mtriple=x86_64-linux -run-pass=block-placement -o - %s | FileCheck %s # RUN: llc -mtriple=x86_64-linux -run-pass=block-placement -o - %s | FileCheck %s
--- ---
# check loop bb.7 is not merged with bb.10, bb.13 # check loop bb.7 is not merged with bb.10, bb.13
# check loop bb.9 is not merged with bb.12 # check loop bb.9 is not merged with bb.12
# CHECK: bb.2: # CHECK: bb.2:
# CHECK-NEXT: successors: %bb.3(0x30000000), %bb.4(0x50000000) # CHECK-NEXT: successors: %bb.3(0x30000000), %bb.4(0x50000000)
# CHECK: %rax = MOV64rm %r14, 1, _, 0, _ # CHECK: %rax = MOV64rm %r14, 1, %noreg, 0, %noreg
# CHECK-NEXT: TEST64rr %rax, %rax # CHECK-NEXT: TEST64rr %rax, %rax
# CHECK-NEXT: JE_1 %bb.3 # CHECK-NEXT: JE_1 %bb.3
# CHECK: bb.4: # CHECK: bb.4:
# CHECK-NEXT: successors: %bb.5(0x30000000), %bb.10(0x50000000) # CHECK-NEXT: successors: %bb.5(0x30000000), %bb.10(0x50000000)
# CHECK: CMP64mi8 killed %rax, 1, _, 8, _, 0 # CHECK: CMP64mi8 killed %rax, 1, %noreg, 8, %noreg, 0
# CHECK-NEXT: JNE_1 %bb.10 # CHECK-NEXT: JNE_1 %bb.10
# CHECK: bb.5: # CHECK: bb.5:
# CHECK-NEXT: successors: %bb.6(0x30000000), %bb.7(0x50000000) # CHECK-NEXT: successors: %bb.6(0x30000000), %bb.7(0x50000000)
# CHECK: %rax = MOV64rm %r14, 1, _, 0, _ # CHECK: %rax = MOV64rm %r14, 1, %noreg, 0, %noreg
# CHECK-NEXT: TEST64rr %rax, %rax # CHECK-NEXT: TEST64rr %rax, %rax
# CHECK-NEXT: JE_1 %bb.6 # CHECK-NEXT: JE_1 %bb.6
# CHECK: bb.7 # CHECK: bb.7
# CHECK-NEXT: successors: %bb.8(0x71555555), %bb.10(0x0eaaaaab) # CHECK-NEXT: successors: %bb.8(0x71555555), %bb.10(0x0eaaaaab)
# CHECK: CMP64mi8 killed %rax, 1, _, 8, _, 0 # CHECK: CMP64mi8 killed %rax, 1, %noreg, 8, %noreg, 0
# CHECK-NEXT: JNE_1 %bb.10 # CHECK-NEXT: JNE_1 %bb.10
# CHECK: bb.8: # CHECK: bb.8:
# CHECK-NEXT: successors: %bb.9(0x04000000), %bb.7(0x7c000000) # CHECK-NEXT: successors: %bb.9(0x04000000), %bb.7(0x7c000000)
# CHECK: %rax = MOV64rm %r14, 1, _, 0, _ # CHECK: %rax = MOV64rm %r14, 1, %noreg, 0, %noreg
# CHECK-NEXT: TEST64rr %rax, %rax # CHECK-NEXT: TEST64rr %rax, %rax
# CHECK-NEXT: JNE_1 %bb.7 # CHECK-NEXT: JNE_1 %bb.7
name: foo name: foo
body: | body: |
bb.0: bb.0:
successors: %bb.1(0x40000000), %bb.7(0x40000000) successors: %bb.1(0x40000000), %bb.7(0x40000000)
TEST8ri %dl, 1, implicit-def %eflags, implicit killed %edx TEST8ri %dl, 1, implicit-def %eflags, implicit killed %edx
JE_1 %bb.7, implicit %eflags JE_1 %bb.7, implicit %eflags
bb.1: bb.1:
successors: %bb.16(0x80000000) successors: %bb.16(0x80000000)
%ebp = XOR32rr undef %ebp, undef %ebp, implicit-def dead %eflags %ebp = XOR32rr undef %ebp, undef %ebp, implicit-def dead %eflags
JMP_1 %bb.16 JMP_1 %bb.16
bb.7: bb.7:
successors: %bb.8(0x30000000), %bb.9(0x50000000) successors: %bb.8(0x30000000), %bb.9(0x50000000)
%rax = MOV64rm %r14, 1, _, 0, _ :: (load 8) %rax = MOV64rm %r14, 1, %noreg, 0, %noreg :: (load 8)
TEST64rr %rax, %rax, implicit-def %eflags TEST64rr %rax, %rax, implicit-def %eflags
JNE_1 %bb.9, implicit killed %eflags JNE_1 %bb.9, implicit killed %eflags
bb.8: bb.8:
successors: %bb.16(0x80000000) successors: %bb.16(0x80000000)
%ebp = XOR32rr undef %ebp, undef %ebp, implicit-def dead %eflags %ebp = XOR32rr undef %ebp, undef %ebp, implicit-def dead %eflags
JMP_1 %bb.16 JMP_1 %bb.16
bb.9: bb.9:
successors: %bb.10(0x30000000), %bb.15(0x50000000) successors: %bb.10(0x30000000), %bb.15(0x50000000)
CMP64mi8 killed %rax, 1, _, 8, _, 0, implicit-def %eflags :: (load 8) CMP64mi8 killed %rax, 1, %noreg, 8, %noreg, 0, implicit-def %eflags :: (load 8)
JNE_1 %bb.15, implicit %eflags JNE_1 %bb.15, implicit %eflags
bb.10: bb.10:
successors: %bb.11(0x30000000), %bb.12(0x50000000) successors: %bb.11(0x30000000), %bb.12(0x50000000)
%rax = MOV64rm %r14, 1, _, 0, _ :: (load 8) %rax = MOV64rm %r14, 1, %noreg, 0, %noreg :: (load 8)
TEST64rr %rax, %rax, implicit-def %eflags TEST64rr %rax, %rax, implicit-def %eflags
JNE_1 %bb.12, implicit %eflags JNE_1 %bb.12, implicit %eflags
bb.11: bb.11:
successors: %bb.16(0x80000000) successors: %bb.16(0x80000000)
%ebp = XOR32rr undef %ebp, undef %ebp, implicit-def dead %eflags %ebp = XOR32rr undef %ebp, undef %ebp, implicit-def dead %eflags
JMP_1 %bb.16 JMP_1 %bb.16
bb.12: bb.12:
successors: %bb.13(0x71555555), %bb.15(0x0eaaaaab) successors: %bb.13(0x71555555), %bb.15(0x0eaaaaab)
CMP64mi8 killed %rax, 1, _, 8, _, 0, implicit-def %eflags :: (load 8), (load 8) CMP64mi8 killed %rax, 1, %noreg, 8, %noreg, 0, implicit-def %eflags :: (load 8), (load 8)
JNE_1 %bb.15, implicit %eflags JNE_1 %bb.15, implicit %eflags
bb.13: bb.13:
successors: %bb.14(0x04000000), %bb.12(0x7c000000) successors: %bb.14(0x04000000), %bb.12(0x7c000000)
%rax = MOV64rm %r14, 1, _, 0, _ :: (load 8) %rax = MOV64rm %r14, 1, %noreg, 0, %noreg :: (load 8)
TEST64rr %rax, %rax, implicit-def %eflags TEST64rr %rax, %rax, implicit-def %eflags
JNE_1 %bb.12, implicit %eflags JNE_1 %bb.12, implicit %eflags
bb.14: bb.14:
successors: %bb.16(0x80000000) successors: %bb.16(0x80000000)
%ebp = XOR32rr undef %ebp, undef %ebp, implicit-def dead %eflags %ebp = XOR32rr undef %ebp, undef %ebp, implicit-def dead %eflags
JMP_1 %bb.16 JMP_1 %bb.16
Show All 12 Lines
llvm/trunk/test/CodeGen/X86/domain-reassignment.mir