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[X86][SSE]: Adding full coverage of MC encoding tests for the SSE isa sets.<NFC>
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Authored by tianqing on Nov 23 2017, 4:00 AM.

Details

Summary

NFC.
Adding MC regressions tests to cover all the SSE ISA sets as follows:
SSE, SSE2, SSE3, SSE4, SSE42, SSEMXCSR, SSE_PREFETCH, SSSE3

This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
See revision: https://reviews.llvm.org/D39952

Diff Detail

Repository
rL LLVM

Event Timeline

gadi.haber created this revision.Nov 23 2017, 4:00 AM
craig.topper added inline comments.Dec 12 2017, 10:26 AM
test/MC/X86/SSE4-64.s
301

movntsd/movntss is an AMD SSE4A instruction. Can you move it any other instructions to SSE4A-64.s/SSE4A-32.s Probably should split SSE4.1 and SSE4.2 as well.

tianqing commandeered this revision.Jan 9 2019, 6:05 PM
tianqing added a reviewer: gadi.haber.
tianqing updated this revision to Diff 183021.Jan 22 2019, 7:14 PM

Removed SSE4a tests. Split SSE4.1 and SSE4.2 tests.

Why were the SSE4a tests removed? They should be split out, but I don't see any reason to remove them unless we already have equivalent coverage for them.

Why were the SSE4a tests removed? They should be split out, but I don't see any reason to remove them unless we already have equivalent coverage for them.

I saw there is a x86_64-sse4a.s which has the 64-bit part already covered. Should I just ignore it and split out SSE4a-32/64.s, or just add the 32-bit tests with some name like x86-sse4a.s?

I think just ignore what’s there already. We definitely need a 32 bit test. We can look for redundant tests once we get everything in.

Please add the SSE4A test files back - once those are in we can look at stripping out the older (partial) coverage tests

Also, please can you PCLMUL full coverage tests as well - AFAICT we have AVX variants tests but not non-VEX

tianqing updated this revision to Diff 183260.Jan 24 2019, 12:04 AM

Added SSE4a tests.

Also, please can you PCLMUL full coverage tests as well - AFAICT we have AVX variants tests but not non-VEX

Of course. But I'd prefer to do it in a separate patch, and after we are finished with the AVX tests.

Shouldn't the MMX pextrw/pinsrw ops be under SSE1 not MMX?

Shouldn't the MMX pextrw/pinsrw ops be under SSE1 not MMX?

Same could also be said for PADDQ and PSUBQ which are in the MMX file but are SSE2. Despite the Intel SDM mistakenly listing PADDQ as MMX.

Weirdly pextrw is missing from MMX-32.s but its in MMX-64.s

The reg-reg variant of pinsrw is missing from the MMX tests as well.

tianqing updated this revision to Diff 183786.Jan 27 2019, 6:24 PM

Fix tests for pinsrw/pextrw/paddq.

tianqing updated this revision to Diff 183787.Jan 27 2019, 6:30 PM

Fixed whitespace.

I think psubq needs moving to SSE2 as well

tianqing updated this revision to Diff 183996.Jan 28 2019, 5:11 PM

Moved psubq tests from MMX to SSE2

craig.topper added inline comments.Jan 28 2019, 5:23 PM
test/MC/X86/SSE42-64.s
34

crc32q?

tianqing updated this revision to Diff 184007.Jan 28 2019, 6:55 PM

Added crc32 tests.

psubq needs removing from MMX-64.s as well

tianqing updated this revision to Diff 184466.Jan 31 2019, 12:52 AM

Removed psubq from MMX-64.s.

I don't know what's wrong with me but I'm sorry for so many negligences ...

Not your fault, we don't have a canonical list of the instructions and their CPUID bits to generate this kind of thing from (at least not one that people can agree on), so everybody ends up redoing this from scratch - I went through the same thing with the llvm-mca resource tests.

@craig.topper Any more comments?

This revision is now accepted and ready to land.Feb 1 2019, 10:30 AM
This revision was automatically updated to reflect the committed changes.
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