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| Differential D40387
[X86][SSE]: Adding full coverage of MC encoding tests for the SSE isa sets.<NFC> ClosedPublic Authored by tianqing on Nov 23 2017, 4:00 AM.
Details Summary NFC. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
Diff Detail
Event Timeline
Comment Actions Why were the SSE4a tests removed? They should be split out, but I don't see any reason to remove them unless we already have equivalent coverage for them. Comment Actions
I saw there is a x86_64-sse4a.s which has the 64-bit part already covered. Should I just ignore it and split out SSE4a-32/64.s, or just add the 32-bit tests with some name like x86-sse4a.s? Comment Actions I think just ignore what’s there already. We definitely need a 32 bit test. We can look for redundant tests once we get everything in. Comment Actions Please add the SSE4A test files back - once those are in we can look at stripping out the older (partial) coverage tests Comment Actions Also, please can you PCLMUL full coverage tests as well - AFAICT we have AVX variants tests but not non-VEX Comment Actions
Of course. But I'd prefer to do it in a separate patch, and after we are finished with the AVX tests. Comment Actions
Same could also be said for PADDQ and PSUBQ which are in the MMX file but are SSE2. Despite the Intel SDM mistakenly listing PADDQ as MMX. Weirdly pextrw is missing from MMX-32.s but its in MMX-64.s
Comment Actions Removed psubq from MMX-64.s. I don't know what's wrong with me but I'm sorry for so many negligences ... Comment Actions Not your fault, we don't have a canonical list of the instructions and their CPUID bits to generate this kind of thing from (at least not one that people can agree on), so everybody ends up redoing this from scratch - I went through the same thing with the llvm-mca resource tests. This revision is now accepted and ready to land.Feb 1 2019, 10:30 AM Closed by commit rL352955: [X86][SSE]: Adding full coverage of MC encoding tests for the SSE isa sets.<NFC> (authored by ctopper). · Explain WhyFeb 1 2019, 10:21 PM This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 184898 llvm/trunk/test/MC/X86/MMX-32.s
llvm/trunk/test/MC/X86/MMX-64.s
llvm/trunk/test/MC/X86/SSE-32.s
llvm/trunk/test/MC/X86/SSE-64.s
llvm/trunk/test/MC/X86/SSE2-32.s
llvm/trunk/test/MC/X86/SSE2-64.s
llvm/trunk/test/MC/X86/SSE3-32.s
llvm/trunk/test/MC/X86/SSE3-64.s
llvm/trunk/test/MC/X86/SSE41-32.s
llvm/trunk/test/MC/X86/SSE41-64.s
llvm/trunk/test/MC/X86/SSE42-32.s
llvm/trunk/test/MC/X86/SSE42-64.s
llvm/trunk/test/MC/X86/SSE4a-32.s
llvm/trunk/test/MC/X86/SSE4a-64.s
llvm/trunk/test/MC/X86/SSEMXCSR-32.s
llvm/trunk/test/MC/X86/SSEMXCSR-64.s
llvm/trunk/test/MC/X86/SSE_PREFETCH-32.s
llvm/trunk/test/MC/X86/SSE_PREFETCH-64.s
llvm/trunk/test/MC/X86/SSSE3-32.s
llvm/trunk/test/MC/X86/SSSE3-64.s
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