[ARM] 't' asm constraint should accept i32

[kongyi]

Summary

't' constraint normally only accepts f32 operands, but for VCVT the operands can be i32. LLVM is overly restrictive and rejects asm like:

float foo() {
  float result;
  __asm__ __volatile__(
    "vcvt.f32.s32 %[result], %[arg1]\n"
    : [result]"=t"(result)
    : [arg1]"t"(0x01020304) );
  return result;
}

Relax the value type for 't' constraint to either f32 or i32.

[srhines]

Thanks for addressing this.

test/CodeGen/ARM/inlineasm.ll

13 ↗

(On Diff #123202)

constraint

[efriedma]

test/CodeGen/ARM/inlineasm.ll

14 ↗

(On Diff #123202)

Pleas add some CHECK lines to this test so it's obvious the generated assembly is correct.

[rengolin]

Is the T constraint only used for movs?

[kongyi]

In D40137#927870, @rengolin wrote:

Is the T constraint only used for movs?

t VFP floating-point registers s0-s31. Used for 32 bit values.
https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html#Machine-Constraints

[efriedma]

test/CodeGen/ARM/inlineasm.ll

13 ↗

(On Diff #123202)

Spelling is still wrong.

[efriedma]

LGTM

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

case 'x':
       if (VT == MVT::f32)
         return RCPair(0U, &ARM::SPR_8RegClass);
       if (VT.getSizeInBits() == 64)
         return RCPair(0U, &ARM::DPR_8RegClass);
       if (VT.getSizeInBits() == 128)
         return RCPair(0U, &ARM::QPR_8RegClass);
       break;
     case 't':
-      if (VT == MVT::f32)
+      if (VT == MVT::f32 || VT == MVT::i32)
         return RCPair(0U, &ARM::SPRRegClass);
       break;
     }
   }
   if (StringRef("{cc}").equals_lower(Constraint))
     return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
 
   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);

llvm/trunk/test/CodeGen/ARM/inlineasm.ll

-; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o /dev/null
+; RUN: llc -mtriple=armv8-eabi -mattr=+neon %s -o - | FileCheck %s
 
 define i32 @test1(i32 %tmp54) {
   %tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 )    ; <i32> [#uses=1]
   ret i32 %tmp56
 }
 
 define void @test2() {
   tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )
   ret void
 }
+
+define float @t-constraint-int(i32 %i) {
+  ; CHECK-LABEL: t-constraint-int
+  ; CHECK: vcvt.f32.s32 {{s[0-9]+}}, {{s[0-9]+}}
+  %ret = call float asm "vcvt.f32.s32 $0, $1\0A", "=t,t"(i32 %i)
+  ret float %ret
+}