Add -print-schedule scheduling comments to inline asm

[avt77]

Summary

Currently we don't generate the scheduler comments for instructions inside inline asm. The patch fixes that and address PR35162.

[andreadb]

Overall, the patch looks good to me.
I made some minor comments below.

include/llvm/MC/MCParser/MCAsmParser.h

131

Comments should end with a period. I noticed the same mistake in AsmPrinter.h.

135

Unrelated to your code review. However, this comment should be associated to field 'HadError' at line 130. I think this should be fixed.

169

I suggest to rename enablePrintSchedInfo() to shouldPrintSchedInfo().

lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp

198

Add a /* unused */ for the bool param.

1046–1047

I suggest to change EnableSchedInfo to just PrintSchedInfo (or PrintSchedInfoEnabled).

1050–1052

Same.

lib/Target/X86/AsmParser/X86AsmInstrumentation.h

45–46

I suggest to change EnableSchedInfo to just PrintSchedInfo (or PrintSchedInfoEnabled).

58–59

Same.

lib/Target/X86/AsmParser/X86AsmParser.cpp

2704

I suggest to rename enablePrintSchedInfo() to shouldPrintSchedInfo().

[avt77]

All andreadb's comments were fixed.

[andreadb]

LGTM.

include/llvm/MC/MCParser/MCAsmParser.h

private:
   MCTargetAsmParser *TargetParser = nullptr;
 
   unsigned ShowParsedOperands : 1;
 
 protected: // Can only create subclasses.
   MCAsmParser();
 
   bool HadError = false;
+  /// Enable print [latency:throughput] in output file
+  bool EnablePrintSchedInfo = false;
 
   SmallVector<MCPendingError, 1> PendingErrors;
   /// Flag tracking whether any errors have been encountered.
 
 public:
   MCAsmParser(const MCAsmParser &) = delete;
   MCAsmParser &operator=(const MCAsmParser &) = delete;
   virtual ~MCAsmParser();
 
   virtual void addDirectiveHandler(StringRef Directive,
                                    ExtensionDirectiveHandler Handler) = 0;
public:
   void setTargetParser(MCTargetAsmParser &P);
 
   virtual unsigned getAssemblerDialect() { return 0;}
   virtual void setAssemblerDialect(unsigned i) { }
 
   bool getShowParsedOperands() const { return ShowParsedOperands; }
   void setShowParsedOperands(bool Value) { ShowParsedOperands = Value; }
 
+  void setEnablePrintSchedInfo(bool Value) { EnablePrintSchedInfo = Value; }
+  bool enablePrintSchedInfo() { return EnablePrintSchedInfo; }
+
   /// \brief Run the parser on the input source buffer.
   virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false) = 0;
 
   virtual void setParsingInlineAsm(bool V) = 0;
   virtual bool isParsingInlineAsm() = 0;
 
   /// \brief Parse MS-style inline assembly.
   virtual bool parseMSInlineAsm(

lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

void AsmPrinter::EmitInlineAsm(StringRef Str, const MCSubtargetInfo &STI,
   std::unique_ptr<MCInstrInfo> MII(TM.getTarget().createMCInstrInfo());
   std::unique_ptr<MCTargetAsmParser> TAP(TM.getTarget().createMCAsmParser(
       STI, *Parser, *MII, MCOptions));
   if (!TAP)
     report_fatal_error("Inline asm not supported by this streamer because"
                        " we don't have an asm parser for this target\n");
   Parser->setAssemblerDialect(Dialect);
   Parser->setTargetParser(*TAP.get());
+  Parser->setEnablePrintSchedInfo(EnablePrintSchedInfo);
   if (Dialect == InlineAsm::AD_Intel)
     // We need this flag to be able to parse numbers like "0bH"
     Parser->setParsingInlineAsm(true);
   if (MF) {
     const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
     TAP->SetFrameRegister(TRI->getFrameRegister(*MF));
   }
 

lib/Target/X86/AsmParser/X86AsmInstrumentation.h

public:
   void SetInitialFrameRegister(unsigned RegNo) {
     InitialFrameReg = RegNo;
   }
 
   // Tries to instrument and emit instruction.
   virtual void InstrumentAndEmitInstruction(
       const MCInst &Inst,
       SmallVectorImpl<std::unique_ptr<MCParsedAsmOperand>> &Operands,
-      MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
+      MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out,
+      bool EnableSchedInfo);
 
 protected:
   friend X86AsmInstrumentation *
   CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
                               const MCContext &Ctx,
                               const MCSubtargetInfo *&STI);
 
   X86AsmInstrumentation(const MCSubtargetInfo *&STI);
 
   unsigned GetFrameRegGeneric(const MCContext &Ctx, MCStreamer &Out);
 
-  void EmitInstruction(MCStreamer &Out, const MCInst &Inst);
+  void EmitInstruction(MCStreamer &Out, const MCInst &Inst,
+                       bool EnableSchedInfo = false);
 
   const MCSubtargetInfo *&STI;
 
   unsigned InitialFrameReg = 0;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_X86_ASMPARSER_X86ASMINSTRUMENTATION_H

lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp

public:
   };
 
   X86AddressSanitizer(const MCSubtargetInfo *&STI)
       : X86AsmInstrumentation(STI), RepPrefix(false), OrigSPOffset(0) {}
 
   ~X86AddressSanitizer() override = default;
 
   // X86AsmInstrumentation implementation:
-  void InstrumentAndEmitInstruction(const MCInst &Inst,
-                                    OperandVector &Operands,
-                                    MCContext &Ctx,
-                                    const MCInstrInfo &MII,
-                                    MCStreamer &Out) override {
+  void InstrumentAndEmitInstruction(const MCInst &Inst, OperandVector &Operands,
+                                    MCContext &Ctx, const MCInstrInfo &MII,
+                                    MCStreamer &Out, bool) override {
     InstrumentMOVS(Inst, Operands, Ctx, MII, Out);
     if (RepPrefix)
       EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
 
     InstrumentMOV(Inst, Operands, Ctx, MII, Out);
 
     RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX);
     if (!RepPrefix)

 
 X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo *&STI)
     : STI(STI) {}
 
 X86AsmInstrumentation::~X86AsmInstrumentation() = default;
 
 void X86AsmInstrumentation::InstrumentAndEmitInstruction(
     const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
-    const MCInstrInfo &MII, MCStreamer &Out) {
-  EmitInstruction(Out, Inst);
+    const MCInstrInfo &MII, MCStreamer &Out, bool EnableSchedInfo) {
+  EmitInstruction(Out, Inst, EnableSchedInfo);
 }
 
-void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
-                                            const MCInst &Inst) {
-  Out.EmitInstruction(Inst, *STI);
+void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out, const MCInst &Inst,
+                                            bool EnableSchedInfo) {
+  Out.EmitInstruction(Inst, *STI, EnableSchedInfo);
 }
 
 unsigned X86AsmInstrumentation::GetFrameRegGeneric(const MCContext &Ctx,
                                                    MCStreamer &Out) {
   if (!Out.getNumFrameInfos()) // No active dwarf frame
     return X86::NoRegister;
   const MCDwarfFrameInfo &Frame = Out.getDwarfFrameInfos().back();
   if (Frame.End) // Active dwarf frame is closed

lib/Target/X86/AsmParser/X86AsmParser.cpp

bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
 
   return false;
 }
 
 static const char *getSubtargetFeatureName(uint64_t Val);
 
 void X86AsmParser::EmitInstruction(MCInst &Inst, OperandVector &Operands,
                                    MCStreamer &Out) {
-  Instrumentation->InstrumentAndEmitInstruction(Inst, Operands, getContext(),
-                                                MII, Out);
+  Instrumentation->InstrumentAndEmitInstruction(
+      Inst, Operands, getContext(), MII, Out,
+      getParser().enablePrintSchedInfo());
 }
 
 bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                            OperandVector &Operands,
                                            MCStreamer &Out, uint64_t &ErrorInfo,
                                            bool MatchingInlineAsm) {
   if (isParsingIntelSyntax())
     return MatchAndEmitIntelInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,

test/CodeGen/X86/inline-schedule.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 | FileCheck %s --check-prefix=BTVER2
+
+define i64 @test_bsr64(i64 %a0, i64 *%a1) nounwind {
+; BTVER2-LABEL: test_bsr64:
+; BTVER2:       # BB#0:
+; BTVER2-NEXT:    #APP
+; BTVER2-NEXT:    bsrq (%rsi), %rax # sched: [4:1.00]
+; BTVER2-NEXT:    #NO_APP
+; BTVER2-NEXT:    #APP
+; BTVER2-NEXT:    bsrq %rdi, %rcx # sched: [1:0.50]
+; BTVER2-NEXT:    #NO_APP
+; BTVER2-NEXT:    orq %rcx, %rax # sched: [1:0.50]
+; BTVER2-NEXT:    retq # sched: [4:1.00]
+  %1 = tail call i64 asm "bsr $1, $0", "=r,r"(i64 %a0) nounwind
+  %2 = tail call i64 asm "bsr $1, $0", "=r,*m"(i64 *%a1) nounwind
+  %3 = or i64 %1, %2
+  ret i64 %3
+}
+
+define i64 @test_bswap64(i64 %a0) nounwind {
+; BTVER2-LABEL: test_bswap64:
+; BTVER2:       # BB#0:
+; BTVER2-NEXT:    bswapq %rdi # sched: [1:0.50]
+; BTVER2-NEXT:    movq %rdi, %rax # sched: [1:0.17]
+; BTVER2-NEXT:    retq # sched: [4:1.00]
+  %1 = tail call i64 asm "bswap $0", "=r,0"(i64 %a0) nounwind
+  ret i64 %1
+}
+