[AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*

[dp]

Summary

See bug 35148: https://bugs.llvm.org//show_bug.cgi?id=35148

[arsenm]

lib/Target/AMDGPU/SIInstrFormats.td

118–119 ↗

(On Diff #121125)

If you're going to introduce this field, it should probably be consistently used. I think I did something else when changing the default printed value in the InstPrinter.

[dp]

lib/Target/AMDGPU/SIInstrFormats.td

118–119 ↗

(On Diff #121125)

This field was introduced for InstPrinter to distinguish between packed and non-packed instructions. Is there another simple way doing it? I do not see any.

Or do you suggest correcting AsmParser to use this new field instead of VOP3P_NotPacked?

[dp]

Corrected and simplified as suggested by Matt

[arsenm]

LGTM

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

public:
   AMDGPUOperand::Ptr defaultOffsetS13() const;
 
   OperandMatchResultTy parseOModOperand(OperandVector &Operands);
 
   void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
                OptionalImmIndexMap &OptionalIdx);
   void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
   void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
-  void cvtVOP3PImpl(MCInst &Inst, const OperandVector &Operands,
-                    bool IsPacked);
   void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
-  void cvtVOP3P_NotPacked(MCInst &Inst, const OperandVector &Operands);
 
   void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
 
   void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
                bool IsAtomic = false);
   void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
 
   OperandMatchResultTy parseDPPCtrl(OperandVector &Operands);
void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
   }
 }
 
 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
   OptionalImmIndexMap OptionalIdx;
   cvtVOP3(Inst, Operands, OptionalIdx);
 }
 
-void AMDGPUAsmParser::cvtVOP3PImpl(MCInst &Inst,
-                                   const OperandVector &Operands,
-                                   bool IsPacked) {
+void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst,
+                               const OperandVector &Operands) {
   OptionalImmIndexMap OptIdx;
-  int Opc = Inst.getOpcode();
+  const int Opc = Inst.getOpcode();
+  const MCInstrDesc &Desc = MII.get(Opc);
+
+  const bool IsPacked = (Desc.TSFlags & SIInstrFlags::IsPacked) != 0;
 
   cvtVOP3(Inst, Operands, OptIdx);
 
   if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) {
     assert(!IsPacked);
     Inst.addOperand(Inst.getOperand(0));
   }
 
   // FIXME: This is messy. Parse the modifiers as if it was a normal VOP3
   // instruction, and then figure out where to actually put the modifiers
 
   addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);
 
   int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);
   if (OpSelHiIdx != -1) {
-    // TODO: Should we change the printing to match?
     int DefaultVal = IsPacked ? -1 : 0;
     addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,
                           DefaultVal);
   }
 
   int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo);
   if (NegLoIdx != -1) {
     assert(IsPacked);
if ((NegHi & (1 << J)) != 0)
       ModVal |= SISrcMods::NEG_HI;
 
     int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
 
     Inst.getOperand(ModIdx).setImm(Inst.getOperand(ModIdx).getImm() | ModVal);
   }
 }
 
-void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
-  cvtVOP3PImpl(Inst, Operands, true);
-}
-
-void AMDGPUAsmParser::cvtVOP3P_NotPacked(MCInst &Inst,
-                                         const OperandVector &Operands) {
-  cvtVOP3PImpl(Inst, Operands, false);
-}
-
 //===----------------------------------------------------------------------===//
 // dpp
 //===----------------------------------------------------------------------===//
 
 bool AMDGPUOperand::isDPPCtrl() const {
   bool result = isImm() && getImmTy() == ImmTyDppCtrl && isUInt<9>(getImm());
   if (result) {
     int64_t Imm = getImm();

llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp

else if (Tgt >= 32 && Tgt <= 63)
     O << " param" << Tgt - 32;
   else {
     // Reserved values 10, 11
     O << " invalid_target_" << Tgt;
   }
 }
 
 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
-                               bool HasDstSel) {
-  int DefaultValue = (Mod == SISrcMods::OP_SEL_1);
+                               bool IsPacked, bool HasDstSel) {
+  int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
 
   for (int I = 0; I < NumOps; ++I) {
     if (!!(Ops[I] & Mod) != DefaultValue)
       return false;
   }
 
   if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
     return false;
for (int OpName : { AMDGPU::OpName::src0_modifiers,
     Ops[NumOps++] = MI->getOperand(Idx).getImm();
   }
 
   const bool HasDstSel =
     NumOps > 0 &&
     Mod == SISrcMods::OP_SEL_0 &&
     MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
 
-  if (allOpsDefaultValue(Ops, NumOps, Mod, HasDstSel))
+  const bool IsPacked =
+    MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
+
+  if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
     return;
 
   O << Name;
   for (int I = 0; I < NumOps; ++I) {
     if (I != 0)
       O << ',';
 
     O << !!(Ops[I] & Mod);

llvm/trunk/lib/Target/AMDGPU/SIDefines.h

// TODO: Should this be spilt into VOP3 a and b?
   // Is an integer clamp
   IntClamp = UINT64_C(1) << 46,
 
   // Clamps lo component of register.
   ClampLo = UINT64_C(1) << 47,
 
   // Clamps hi component of register.
   // ClampLo and ClampHi set for packed clamp.
-  ClampHi = UINT64_C(1) << 48
+  ClampHi = UINT64_C(1) << 48,
+
+  // Is a packed VOP3P instruction.
+  IsPacked = UINT64_C(1) << 49
 };
 
 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
 // The result is true if any of these tests are true.
 enum ClassFlags {
   S_NAN = 1 << 0,        // Signaling NaN
   Q_NAN = 1 << 1,        // Quiet NaN
   N_INFINITY = 1 << 2,   // Negative infinity

llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td

class InstSI <dag outs, dag ins, string asm = "",
   // This field indicates that the clamp applies to the low component
   // of a packed output register.
   field bit ClampLo = 0;
 
   // This field indicates that the clamp applies to the high component
   // of a packed output register.
   field bit ClampHi = 0;
 
+  // This bit indicates that this is a packed VOP3P instruction
+  field bit IsPacked = 0;
+
   // These need to be kept in sync with the enum in SIInstrFlags.
   let TSFlags{0} = SALU;
   let TSFlags{1} = VALU;
 
   let TSFlags{2} = SOP1;
   let TSFlags{3} = SOP2;
   let TSFlags{4} = SOPC;
   let TSFlags{5} = SOPK;
class InstSI <dag outs, dag ins, string asm = "",
   let TSFlags{43} = maybeAtomic;
   let TSFlags{44} = F16_ZFILL;
 
   let TSFlags{45} = FPClamp;
   let TSFlags{46} = IntClamp;
   let TSFlags{47} = ClampLo;
   let TSFlags{48} = ClampHi;
 
+  let TSFlags{49} = IsPacked;
+
   let SchedRW = [Write32Bit];
 
   field bits<1> DisableSIDecoder = 0;
   field bits<1> DisableVIDecoder = 0;
   field bits<1> DisableDecoder = 0;
 
   let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
   let AsmVariantName = AMDGPUAsmVariants.Default;

llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td

class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
   VOP <opName>,
   SIMCInstr<opName#"_e64", SIEncodingFamily.NONE>,
   MnemonicAlias<opName#"_e64", opName> {
 
   let isPseudo = 1;
   let isCodeGenOnly = 1;
   let UseNamedOperandTable = 1;
   let VOP3_OPSEL = isVop3OpSel;
+  let IsPacked = P.IsPacked;
 
   string Mnemonic = opName;
   string AsmOperands = !if(isVop3OpSel,
                            P.AsmVOP3OpSel,
                            !if(!and(isVOP3P, P.IsPacked), P.AsmVOP3P, P.Asm64));
 
   let Size = 8;
   let mayLoad = 0;
class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
   let IntClamp = P.HasIntClamp;
   let ClampLo = P.HasClampLo;
   let ClampHi = P.HasClampHi;
 
   let Uses = [EXEC];
 
   let AsmVariantName = AMDGPUAsmVariants.VOP3;
   let AsmMatchConverter =
-    !if(!and(P.IsPacked, isVOP3P),
+    !if(isVOP3P,
         "cvtVOP3P",
-        !if(isVOP3P, "cvtVOP3P_NotPacked",
-          !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
-              "cvtVOP3",
-              "")));
+            ""));
 
   VOPProfile Pfl = P;
 }
 
 class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> :
   VOP3_Pseudo<opName, P, pattern, 1, 1> {
   let VOP3P = 1;
 }

llvm/trunk/test/CodeGen/AMDGPU/mad-mix-hi.ll

define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext(half %src0, half %src1, half %src2) #0 {
   %cvt.result = fptrunc float %result to half
   %bc = bitcast half %cvt.result to i16
   %ext = sext i16 %bc to i32
   %shr = shl i32 %ext, 16
   ret i32 %shr
 }
 
 ; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
-; GFX9: v_mad_mix_f32 v0, v0, v1, v2 clamp{{$}}
+; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
 ; GFX9: v_cvt_f16_f32_e32 v0, v0
 define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %src0, half %src1, half %src2) #0 {
   %src0.ext = fpext half %src0 to float
   %src1.ext = fpext half %src1 to float
   %src2.ext = fpext half %src2 to float
   %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
   %max = call float @llvm.maxnum.f32(float %result, float 0.0)
   %clamp = call float @llvm.minnum.f32(float %max, float 1.0)
   %cvt.result = fptrunc float %clamp to half
   %vec.result = insertelement <2 x half> undef, half %cvt.result, i32 1
   ret <2 x half> %vec.result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:
 ; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 clamp{{$}}
+; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
 ; GFX9-NEXT: s_setpc_b64
 define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt(half %src0, half %src1, half %src2) #0 {
   %src0.ext = fpext half %src0 to float
   %src1.ext = fpext half %src1 to float
   %src2.ext = fpext half %src2 to float
   %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
   %cvt.result = fptrunc float %result to half
   %max = call half @llvm.maxnum.f16(half %cvt.result, half 0.0)
   %clamp = call half @llvm.minnum.f16(half %max, half 1.0)
   %vec.result = insertelement <2 x half> undef, half %clamp, i32 1
   ret <2 x half> %vec.result
 }
 
 
 ; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:
 ; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2{{$}}
+; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]{{$}}
 ; GFX9-NEXT: global_store_short v{{\[[0-9]+:[0-9]+\]}}, v3
-; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 clamp{{$}}
+; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
 ; GFX9-NEXT: s_waitcnt vmcnt(0)
 ; GFX9-NEXT: s_setpc_b64
 define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use(half %src0, half %src1, half %src2) #0 {
   %src0.ext = fpext half %src0 to float
   %src1.ext = fpext half %src1 to float
   %src2.ext = fpext half %src2 to float
   %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
   %cvt.result = fptrunc float %result to half

llvm/trunk/test/CodeGen/AMDGPU/mad-mix-lo.ll

 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,VI %s
 ; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s
 
 ; GCN-LABEL: mixlo_simple:
 ; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[0,0,0]{{$}}
+; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2{{$}}
 ; GFX9-NEXT: s_setpc_b64
 
 ; CIVI: v_mac_f32_e32
 ; CIVI: v_cvt_f16_f32_e32
 define half @mixlo_simple(float %src0, float %src1, float %src2) #0 {
   %result = call float @llvm.fmuladd.f32(float %src0, float %src1, float %src2)
   %cvt.result = fptrunc float %result to half
   ret half %cvt.result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mixlo_f16_f16lo_f16lo_f16lo:
-; GFX9: v_mad_mixlo_f16 v0, v0, v1, v2{{$}}
+; GFX9: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]{{$}}
 ; CI: v_mac_f32
 ; CIVI: v_cvt_f16_f32
 define half @v_mad_mixlo_f16_f16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
   %src0.ext = fpext half %src0 to float
   %src1.ext = fpext half %src1 to float
   %src2.ext = fpext half %src2 to float
   %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
   %cvt.result = fptrunc float %result to half
define half @v_mad_mixlo_f16_f16lo_f16lo_f32_clamp_pre_cvt(half %src0, half %src1, float %src2) #0 {
   %cvt.result = fptrunc float %clamp to half
   ret half %cvt.result
 }
 
 ; FIXME: Should abe able to avoid extra register because first
 ; operation only clobbers relevant lane.
 ; GCN-LABEL: {{^}}v_mad_mix_v2f32:
 ; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2{{$}}
-; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1]{{$}}
+; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]{{$}}
+; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]{{$}}
 ; GFX9-NEXT: v_mov_b32_e32 v0, v3
 ; GFX9-NEXT: s_setpc_b64
 define <2 x half> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
   %src0.ext = fpext <2 x half> %src0 to <2 x float>
   %src1.ext = fpext <2 x half> %src1 to <2 x float>
   %src2.ext = fpext <2 x half> %src2 to <2 x float>
   %result = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.ext)
   %cvt.result = fptrunc <2 x float> %result to <2 x half>
   ret <2 x half> %cvt.result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_v3f32:
 ; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v3, v6
-; GFX9-NEXT: v_mad_mixlo_f16 v1, v1, v4, v7
-; GFX9-NEXT: v_mad_mixlo_f16 v2, v2, v5, v8
+; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v3, v6 op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mixlo_f16 v1, v1, v4, v7 op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mixlo_f16 v2, v2, v5, v8 op_sel_hi:[1,1,1]
 ; GFX9-NEXT: s_setpc_b64
 define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half> %src2) #0 {
   %src0.ext = fpext <3 x half> %src0 to <3 x float>
   %src1.ext = fpext <3 x half> %src1 to <3 x float>
   %src2.ext = fpext <3 x half> %src2 to <3 x float>
   %result = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %src0.ext, <3 x float> %src1.ext, <3 x float> %src2.ext)
   %cvt.result = fptrunc <3 x float> %result to <3 x half>
   ret <3 x half> %cvt.result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_v4f32:
 ; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4
-; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1]
-; GFX9-NEXT: v_mad_mixlo_f16 v2, v1, v3, v5
-; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1]
+; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mixlo_f16 v2, v1, v3, v5 op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
 ; GFX9-NEXT: v_mov_b32_e32 v0, v6
 ; GFX9-NEXT: v_mov_b32_e32 v1, v2
 ; GFX9-NEXT: s_setpc_b64
 define <4 x half> @v_mad_mix_v4f32(<4 x half> %src0, <4 x half> %src1, <4 x half> %src2) #0 {
   %src0.ext = fpext <4 x half> %src0 to <4 x float>
   %src1.ext = fpext <4 x half> %src1 to <4 x float>
   %src2.ext = fpext <4 x half> %src2 to <4 x float>
   %result = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %src0.ext, <4 x float> %src1.ext, <4 x float> %src2.ext)
   %cvt.result = fptrunc <4 x float> %result to <4 x half>
   ret <4 x half> %cvt.result
 }
 
 ; FIXME: Fold clamp
 ; GCN-LABEL: {{^}}v_mad_mix_v2f32_clamp_postcvt:
-; GFX9: v_mad_mixlo_f16 v3, v0, v1, v2 clamp{{$}}
-; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] clamp{{$}}
+; GFX9: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
+; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp{{$}}
 ; GFX9-NEXT: v_mov_b32_e32 v0, v3
 ; GFX9-NEXT: s_setpc_b64
 define <2 x half> @v_mad_mix_v2f32_clamp_postcvt(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
   %src0.ext = fpext <2 x half> %src0 to <2 x float>
   %src1.ext = fpext <2 x half> %src1 to <2 x float>
   %src2.ext = fpext <2 x half> %src2 to <2 x float>
   %result = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.ext)
   %cvt.result = fptrunc <2 x float> %result to <2 x half>
   %max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %cvt.result, <2 x half> zeroinitializer)
   %clamp = call <2 x half> @llvm.minnum.v2f16(<2 x half> %max, <2 x half> <half 1.0, half 1.0>)
   ret <2 x half> %clamp
 }
 
 ; FIXME: Should be packed into 2 registers per argument?
 ; GCN-LABEL: {{^}}v_mad_mix_v3f32_clamp_postcvt:
 ; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v2, v2, v5, v8 clamp
-; GFX9-NEXT: v_mad_mixhi_f16 v2, v0, v0, v0 op_sel_hi:[0,0,0] clamp
-; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v3, v6 clamp
-; GFX9-NEXT: v_mad_mixhi_f16 v0, v1, v4, v7 clamp
+; GFX9-NEXT: v_mad_mixlo_f16 v2, v2, v5, v8 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixhi_f16 v2, v0, v0, v0 clamp
+; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v3, v6 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixhi_f16 v0, v1, v4, v7 op_sel_hi:[1,1,1] clamp
 ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0
 ; GFX9-NEXT: s_setpc_b64
 define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %src1, <3 x half> %src2) #0 {
   %src0.ext = fpext <3 x half> %src0 to <3 x float>
   %src1.ext = fpext <3 x half> %src1 to <3 x float>
   %src2.ext = fpext <3 x half> %src2 to <3 x float>
   %result = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %src0.ext, <3 x float> %src1.ext, <3 x float> %src2.ext)
   %cvt.result = fptrunc <3 x float> %result to <3 x half>
   %max = call <3 x half> @llvm.maxnum.v3f16(<3 x half> %cvt.result, <3 x half> zeroinitializer)
   %clamp = call <3 x half> @llvm.minnum.v3f16(<3 x half> %max, <3 x half> <half 1.0, half 1.0, half 1.0>)
   ret <3 x half> %clamp
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_v4f32_clamp_postcvt:
 ; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 clamp
-; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] clamp
-; GFX9-NEXT: v_mad_mixlo_f16 v2, v1, v3, v5 clamp
-; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixlo_f16 v2, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
 ; GFX9-DAG: v_mov_b32_e32 v0, v6
 ; GFX9-DAG: v_mov_b32_e32 v1, v2
 ; GFX9: s_setpc_b64
 define <4 x half> @v_mad_mix_v4f32_clamp_postcvt(<4 x half> %src0, <4 x half> %src1, <4 x half> %src2) #0 {
   %src0.ext = fpext <4 x half> %src0 to <4 x float>
   %src1.ext = fpext <4 x half> %src1 to <4 x float>
   %src2.ext = fpext <4 x half> %src2 to <4 x float>
   %result = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %src0.ext, <4 x float> %src1.ext, <4 x float> %src2.ext)
   %cvt.result = fptrunc <4 x float> %result to <4 x half>
   %max = call <4 x half> @llvm.maxnum.v4f16(<4 x half> %cvt.result, <4 x half> zeroinitializer)
   %clamp = call <4 x half> @llvm.minnum.v4f16(<4 x half> %max, <4 x half> <half 1.0, half 1.0, half 1.0, half 1.0>)
   ret <4 x half> %clamp
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_v2f32_clamp_postcvt_lo:
 ; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 clamp
-; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1]
+; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
 ; GFX9-NEXT: v_mov_b32_e32 v0, v3
 ; GFX9-NEXT: s_setpc_b64
 define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_lo(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
   %src0.ext = fpext <2 x half> %src0 to <2 x float>
   %src1.ext = fpext <2 x half> %src1 to <2 x float>
   %src2.ext = fpext <2 x half> %src2 to <2 x float>
   %result = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.ext)
   %cvt.result = fptrunc <2 x float> %result to <2 x half>
   %cvt.lo = extractelement <2 x half> %cvt.result, i32 0
   %max.lo = call half @llvm.maxnum.f16(half %cvt.lo, half 0.0)
   %clamp.lo = call half @llvm.minnum.f16(half %max.lo, half 1.0)
   %insert = insertelement <2 x half> %cvt.result, half %clamp.lo, i32 0
   ret <2 x half> %insert
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_v2f32_clamp_postcvt_hi:
 ; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2
-; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
 ; GFX9-NEXT: v_mov_b32_e32 v0, v3
 ; GFX9-NEXT: s_setpc_b64
 define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_hi(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
   %src0.ext = fpext <2 x half> %src0 to <2 x float>
   %src1.ext = fpext <2 x half> %src1 to <2 x float>
   %src2.ext = fpext <2 x half> %src2 to <2 x float>
   %result = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.ext)
   %cvt.result = fptrunc <2 x float> %result to <2 x half>
   %cvt.hi = extractelement <2 x half> %cvt.result, i32 1
   %max.hi = call half @llvm.maxnum.f16(half %cvt.hi, half 0.0)
   %clamp.hi = call half @llvm.minnum.f16(half %max.hi, half 1.0)
   %insert = insertelement <2 x half> %cvt.result, half %clamp.hi, i32 1
   ret <2 x half> %insert
 }
 
 ; FIXME: Should be able to use mixlo/mixhi
 ; GCN-LABEL: {{^}}v_mad_mix_v2f32_clamp_precvt:
-; GFX9: v_mad_mix_f32 v3, v0, v1, v2 clamp
-; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] clamp
+; GFX9: v_mad_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
 ; GFX9: v_cvt_f16_f32_e32 v1, v3
 ; GFX9: v_cvt_f16_f32_e32 v0, v0
 ; GFX9: v_and_b32_e32 v1, 0xffff, v1
 ; GFX9: v_lshl_or_b32 v0, v0, 16, v1
 ; GFX9: s_setpc_b64
 define <2 x half> @v_mad_mix_v2f32_clamp_precvt(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
   %src0.ext = fpext <2 x half> %src0 to <2 x float>
   %src1.ext = fpext <2 x half> %src1 to <2 x float>
   %src2.ext = fpext <2 x half> %src2 to <2 x float>
   %result = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.ext)
   %max = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %result, <2 x float> zeroinitializer)
   %clamp = call <2 x float> @llvm.minnum.v2f32(<2 x float> %max, <2 x float> <float 1.0, float 1.0>)
   %cvt.result = fptrunc <2 x float> %clamp to <2 x half>
   ret <2 x half> %cvt.result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_v3f32_clamp_precvt:
-; GFX9: v_mad_mix_f32 v0, v0, v3, v6 clamp
-; GFX9: v_mad_mix_f32 v1, v1, v4, v7 clamp
-; GFX9: v_mad_mix_f32 v2, v2, v5, v8 clamp
+; GFX9: v_mad_mix_f32 v0, v0, v3, v6 op_sel_hi:[1,1,1] clamp
+; GFX9: v_mad_mix_f32 v1, v1, v4, v7 op_sel_hi:[1,1,1] clamp
+; GFX9: v_mad_mix_f32 v2, v2, v5, v8 op_sel_hi:[1,1,1] clamp
 ; GFX9: v_cvt_f16_f32
 ; GFX9: v_cvt_f16_f32
 ; GFX9: v_cvt_f16_f32
 define <3 x half> @v_mad_mix_v3f32_clamp_precvt(<3 x half> %src0, <3 x half> %src1, <3 x half> %src2) #0 {
   %src0.ext = fpext <3 x half> %src0 to <3 x float>
   %src1.ext = fpext <3 x half> %src1 to <3 x float>
   %src2.ext = fpext <3 x half> %src2 to <3 x float>
   %result = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %src0.ext, <3 x float> %src1.ext, <3 x float> %src2.ext)
   %max = call <3 x float> @llvm.maxnum.v3f32(<3 x float> %result, <3 x float> zeroinitializer)
   %clamp = call <3 x float> @llvm.minnum.v3f32(<3 x float> %max, <3 x float> <float 1.0, float 1.0, float 1.0>)
   %cvt.result = fptrunc <3 x float> %clamp to <3 x half>
   ret <3 x half> %cvt.result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_v4f32_clamp_precvt:
-; GFX9: v_mad_mix_f32 v6, v0, v2, v4 op_sel:[1,1,1] clamp
-; GFX9: v_mad_mix_f32 v0, v0, v2, v4 clamp
-; GFX9: v_mad_mix_f32 v2, v1, v3, v5 op_sel:[1,1,1] clamp
-; GFX9: v_mad_mix_f32 v1, v1, v3, v5 clamp
+; GFX9: v_mad_mix_f32 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GFX9: v_mad_mix_f32 v0, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GFX9: v_mad_mix_f32 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GFX9: v_mad_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
 ; GFX9: v_cvt_f16_f32
 ; GFX9: v_cvt_f16_f32
 ; GFX9: v_cvt_f16_f32
 ; GFX9: v_cvt_f16_f32
 define <4 x half> @v_mad_mix_v4f32_clamp_precvt(<4 x half> %src0, <4 x half> %src1, <4 x half> %src2) #0 {
   %src0.ext = fpext <4 x half> %src0 to <4 x float>
   %src1.ext = fpext <4 x half> %src1 to <4 x float>
   %src2.ext = fpext <4 x half> %src2 to <4 x float>

llvm/trunk/test/CodeGen/AMDGPU/mad-mix.ll

 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,VI %s
 ; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s
 
 ; GCN-LABEL: {{^}}v_mad_mix_f32_f16lo_f16lo_f16lo:
-; GFX9: v_mad_mix_f32 v0, v0, v1, v2 ; encoding: [0x00,0x40,0xa0,0xd3,0x00,0x03,0x0a,0x1c]
+; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] ; encoding: [0x00,0x40,0xa0,0xd3,0x00,0x03,0x0a,0x1c]
 ; VI: v_mac_f32
 ; CI: v_mad_f32
 define float @v_mad_mix_f32_f16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
   %src0.ext = fpext half %src0 to float
   %src1.ext = fpext half %src1 to float
   %src2.ext = fpext half %src2 to float
   %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
   ret float %result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_f32_f16hi_f16hi_f16hi_int:
-; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] ; encoding
+; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] ; encoding
 ; CIVI: v_mac_f32
 define float @v_mad_mix_f32_f16hi_f16hi_f16hi_int(i32 %src0, i32 %src1, i32 %src2) #0 {
   %src0.hi = lshr i32 %src0, 16
   %src1.hi = lshr i32 %src1, 16
   %src2.hi = lshr i32 %src2, 16
   %src0.i16 = trunc i32 %src0.hi to i16
   %src1.i16 = trunc i32 %src1.hi to i16
   %src2.i16 = trunc i32 %src2.hi to i16
   %src0.fp16 = bitcast i16 %src0.i16 to half
   %src1.fp16 = bitcast i16 %src1.i16 to half
   %src2.fp16 = bitcast i16 %src2.i16 to half
   %src0.ext = fpext half %src0.fp16 to float
   %src1.ext = fpext half %src1.fp16 to float
   %src2.ext = fpext half %src2.fp16 to float
   %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
   ret float %result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_f32_f16hi_f16hi_f16hi_elt:
-; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] ; encoding
+; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] ; encoding
 ; VI: v_mac_f32
 ; CI: v_mad_f32
 define float @v_mad_mix_f32_f16hi_f16hi_f16hi_elt(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
   %src0.hi = extractelement <2 x half> %src0, i32 1
   %src1.hi = extractelement <2 x half> %src1, i32 1
   %src2.hi = extractelement <2 x half> %src2, i32 1
   %src0.ext = fpext half %src0.hi to float
   %src1.ext = fpext half %src1.hi to float
   %src2.ext = fpext half %src2.hi to float
   %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
   ret float %result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_v2f32:
 ; GFX9: v_mov_b32_e32 v3, v1
-; GFX9-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[1,1,1]
-; GFX9-NEXT: v_mad_mix_f32 v0, v0, v3, v2
+; GFX9-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mix_f32 v0, v0, v3, v2 op_sel_hi:[1,1,1]
 
 ; CIVI: v_mac_f32
 define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
   %src0.ext = fpext <2 x half> %src0 to <2 x float>
   %src1.ext = fpext <2 x half> %src1 to <2 x float>
   %src2.ext = fpext <2 x half> %src2 to <2 x float>
   %result = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.ext)
   ret <2 x float> %result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_v2f32_shuffle:
 ; GCN: s_waitcnt
 ; GFX9-NEXT: v_mov_b32_e32 v3, v1
-; GFX9-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[0,1,1]
-; GFX9-NEXT: v_mad_mix_f32 v0, v0, v3, v2 op_sel:[1,0,1]
+; GFX9-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mix_f32 v0, v0, v3, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1]
 ; GFX9-NEXT: s_setpc_b64
 
 ; CIVI: v_mac_f32
 define <2 x float> @v_mad_mix_v2f32_shuffle(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
   %src0.shuf = shufflevector <2 x half> %src0, <2 x half> undef, <2 x i32> <i32 1, i32 0>
   %src1.shuf = shufflevector <2 x half> %src1, <2 x half> undef, <2 x i32> <i32 0, i32 1>
   %src2.shuf = shufflevector <2 x half> %src2, <2 x half> undef, <2 x i32> <i32 1, i32 1>
   %src0.ext = fpext <2 x half> %src0.shuf to <2 x float>
   %src1.ext = fpext <2 x half> %src1.shuf to <2 x float>
   %src2.ext = fpext <2 x half> %src2.shuf to <2 x float>
   %result = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> %src2.ext)
   ret <2 x float> %result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_f32_negf16lo_f16lo_f16lo:
 ; GFX9: s_waitcnt
-; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 ; encoding
+; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1] ; encoding
 ; GFX9-NEXT: s_setpc_b64
 
 ; CIVI: v_mad_f32
 define float @v_mad_mix_f32_negf16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
   %src0.ext = fpext half %src0 to float
   %src1.ext = fpext half %src1 to float
   %src2.ext = fpext half %src2 to float
   %src0.ext.neg = fsub float -0.0, %src0.ext
   %result = tail call float @llvm.fmuladd.f32(float %src0.ext.neg, float %src1.ext, float %src2.ext)
   ret float %result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_f32_absf16lo_f16lo_f16lo:
-; GFX9: v_mad_mix_f32 v0, |v0|, v1, v2
+; GFX9: v_mad_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
 
 ; CIVI: v_mad_f32
 define float @v_mad_mix_f32_absf16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
   %src0.ext = fpext half %src0 to float
   %src1.ext = fpext half %src1 to float
   %src2.ext = fpext half %src2 to float
   %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext)
   %result = tail call float @llvm.fmuladd.f32(float %src0.ext.abs, float %src1.ext, float %src2.ext)
   ret float %result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_f32_negabsf16lo_f16lo_f16lo:
 ; GFX9: s_waitcnt
-; GFX9-NEXT: v_mad_mix_f32 v0, -|v0|, v1, v2
+; GFX9-NEXT: v_mad_mix_f32 v0, -|v0|, v1, v2 op_sel_hi:[1,1,1]
 ; GFX9-NEXT: s_setpc_b64
 
 ; CIVI: v_mad_f32
 define float @v_mad_mix_f32_negabsf16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
   %src0.ext = fpext half %src0 to float
   %src1.ext = fpext half %src1 to float
   %src2.ext = fpext half %src2 to float
   %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext)
define <2 x float> @v_mad_mix_v2f32_f32imminv2pi(<2 x half> %src0, <2 x half> %src1) #0 {
   %src0.ext = fpext <2 x half> %src0 to <2 x float>
   %src1.ext = fpext <2 x half> %src1 to <2 x float>
   %src2 = fpext <2 x half> <half 0xH3118, half 0xH3118> to <2 x float>
   %result = tail call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %src0.ext, <2 x float> %src1.ext, <2 x float> <float 0x3FC45F3060000000, float 0x3FC45F3060000000>)
   ret <2 x float> %result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_clamp_f32_f16hi_f16hi_f16hi_elt:
-; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] clamp ; encoding
+; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp ; encoding
 ; VI: v_mac_f32_e64 v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]}} clamp{{$}}
 ; CI: v_mad_f32 v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]}} clamp{{$}}
 define float @v_mad_mix_clamp_f32_f16hi_f16hi_f16hi_elt(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
   %src0.hi = extractelement <2 x half> %src0, i32 1
   %src1.hi = extractelement <2 x half> %src1, i32 1
   %src2.hi = extractelement <2 x half> %src2, i32 1
   %src0.ext = fpext half %src0.hi to float
   %src1.ext = fpext half %src1.hi to float
define float @v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd(half %src0, half %src1, float %src2) #1 {
   %src1.ext = fpext half %src1 to float
   %mul = fmul float %src0.ext, %src1.ext
   %result = fadd float %mul, %src2
   ret float %result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd:
 ; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 ; encoding
+; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] ; encoding
 ; GFX9-NEXT: s_setpc_b64
 define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd(half %src0, half %src1, half %src2) #0 {
   %src0.ext = fpext half %src0 to float
   %src1.ext = fpext half %src1 to float
   %src2.ext = fpext half %src2 to float
   %mul = fmul float %src0.ext, %src1.ext
   %result = fadd float %mul, %src2.ext
   ret float %result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_f32_f16lo_f16lo_f32_flush_fmulfadd:
 ; GCN: s_waitcnt
 ; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0] ; encoding
 ; GFX9-NEXT: s_setpc_b64
 define float @v_mad_mix_f32_f16lo_f16lo_f32_flush_fmulfadd(half %src0, half %src1, float %src2) #0 {
   %src0.ext = fpext half %src0 to float
   %src1.ext = fpext half %src1 to float
   %mul = fmul float %src0.ext, %src1.ext
   %result = fadd float %mul, %src2
   ret float %result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
 ; GFX9: s_waitcnt
-; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 ; encoding
+; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1] ; encoding
 ; GFX9-NEXT: s_setpc_b64
 
 ; CIVI: v_mad_f32
 define float @v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
   %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
   %src0 = extractelement <2 x half> %src0.arg.bc, i32 0
   %src0.neg = fsub half -0.0, %src0
   %src0.ext = fpext half %src0.neg to float
define float @v_mad_mix_f32_precvtnegf16hi_abs_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
   %src1.ext = fpext half %src1 to float
   %src2.ext = fpext half %src2 to float
   %result = tail call float @llvm.fmuladd.f32(float %src0.ext.abs, float %src1.ext, float %src2.ext)
   ret float %result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo:
 ; GFX9: s_waitcnt
-; GFX9-NEXT: v_mad_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0]
+; GFX9-NEXT: v_mad_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
 ; GFX9-NEXT: s_setpc_b64
 define float @v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
   %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
   %src0 = extractelement <2 x half> %src0.arg.bc, i32 1
   %src0.abs = call half @llvm.fabs.f16(half %src0)
   %src0.ext = fpext half %src0.abs to float
   %src1.ext = fpext half %src1 to float
   %src2.ext = fpext half %src2 to float
   %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
   ret float %result
 }
 
 ; GCN-LABEL: {{^}}v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
 ; GFX9: s_waitcnt
-; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0]
+; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
 ; GFX9-NEXT: s_setpc_b64
 define float @v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
   %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
   %fneg = fsub <2 x half> <half -0.0, half -0.0>, %src0.arg.bc
   %src0 = extractelement <2 x half> %fneg, i32 1
   %src0.ext = fpext half %src0 to float
   %src1.ext = fpext half %src1 to float
   %src2.ext = fpext half %src2 to float
   %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
   ret float %result
 }
 
 ; FIXME: Should be able to fold
 ; GCN-LABEL: {{^}}v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
 ; GFX9: s_waitcnt
 ; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
-; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,0,0]
+; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
 ; GFX9-NEXT: s_setpc_b64
 define float @v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
   %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
   %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc)
   %src0 = extractelement <2 x half> %fabs, i32 1
   %src0.ext = fpext half %src0 to float
   %src1.ext = fpext half %src1 to float
   %src2.ext = fpext half %src2 to float
   %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
   ret float %result
 }
 
 ; FIXME: Should be able to fold
 ; GCN-LABEL: {{^}}v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
 ; GFX9: s_waitcnt
 ; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
-; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0]
+; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
 ; GFX9-NEXT: s_setpc_b64
 define float @v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
   %src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
   %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc)
   %fneg.fabs = fsub <2 x half> <half -0.0, half -0.0>, %fabs
   %src0 = extractelement <2 x half> %fneg.fabs, i32 1
   %src0.ext = fpext half %src0 to float
   %src1.ext = fpext half %src1 to float

llvm/trunk/test/MC/AMDGPU/vop3p.s

 
 v_pk_min_f16 v0, v1, v2
 // GFX9: v_pk_min_f16 v0, v1, v2 ; encoding: [0x00,0x00,0x91,0xd3,0x01,0x05,0x02,0x18]
 
 v_pk_max_f16 v0, v1, v2
 // GFX9: v_pk_max_f16 v0, v1, v2 ; encoding: [0x00,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]
 
 v_mad_mix_f32 v0, v1, v2, v3
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 
 v_mad_mixlo_f16 v0, v1, v2, v3
-// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
 
 v_mad_mixhi_f16 v0, v1, v2, v3
-// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
 
 //
 // Regular source modifiers on non-packed instructions
 //
 
 v_mad_mix_f32 v0, abs(v1), v2, v3
-// GFX9: v_mad_mix_f32 v0, |v1|, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, |v1|, v2, v3 ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 
 v_mad_mix_f32 v0, v1, abs(v2), v3
-// GFX9: v_mad_mix_f32 v0, v1, |v2|, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, |v2|, v3 ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 
 v_mad_mix_f32 v0, v1, v2, abs(v3)
-// GFX9: v_mad_mix_f32 v0, v1, v2, |v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, |v3| ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 
 v_mad_mix_f32 v0, -v1, v2, v3
-// GFX9: v_mad_mix_f32 v0, -v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24]
+// GFX9: v_mad_mix_f32 v0, -v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24]
 
 v_mad_mix_f32 v0, v1, -v2, v3
-// GFX9: v_mad_mix_f32 v0, v1, -v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44]
+// GFX9: v_mad_mix_f32 v0, v1, -v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44]
 
 v_mad_mix_f32 v0, v1, v2, -v3
-// GFX9: v_mad_mix_f32 v0, v1, v2, -v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84]
+// GFX9: v_mad_mix_f32 v0, v1, v2, -v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84]
 
 v_mad_mix_f32 v0, -abs(v1), v2, v3
-// GFX9: v_mad_mix_f32 v0, -|v1|, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x24]
+// GFX9: v_mad_mix_f32 v0, -|v1|, v2, v3 ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x24]
 
 v_mad_mix_f32 v0, v1, -abs(v2), v3
-// GFX9: v_mad_mix_f32 v0, v1, -|v2|, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x44]
+// GFX9: v_mad_mix_f32 v0, v1, -|v2|, v3 ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x44]
 
 v_mad_mix_f32 v0, v1, v2, -abs(v3)
-// GFX9: v_mad_mix_f32 v0, v1, v2, -|v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x84]
+// GFX9: v_mad_mix_f32 v0, v1, v2, -|v3| ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x84]
 
 v_mad_mixlo_f16 v0, abs(v1), -v2, abs(v3)
-// GFX9: v_mad_mixlo_f16 v0, |v1|, -v2, |v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x05,0xa1,0xd3,0x01,0x05,0x0e,0x44]
+// GFX9: v_mad_mixlo_f16 v0, |v1|, -v2, |v3| ; encoding: [0x00,0x05,0xa1,0xd3,0x01,0x05,0x0e,0x44]
 
 v_mad_mixhi_f16 v0, -v1, abs(v2), -abs(v3)
-// GFX9: v_mad_mixhi_f16 v0, -v1, |v2|, -|v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x06,0xa2,0xd3,0x01,0x05,0x0e,0xa4]
+// GFX9: v_mad_mixhi_f16 v0, -v1, |v2|, -|v3| ; encoding: [0x00,0x06,0xa2,0xd3,0x01,0x05,0x0e,0xa4]
 
 v_mad_mixlo_f16 v0, v1, v2, v3 clamp
-// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] clamp ; encoding: [0x00,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]
 
 v_mad_mixhi_f16 v0, v1, v2, v3 clamp
-// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] clamp ; encoding: [0x00,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04]
 
 //
 // op_sel with non-packed instructions
 //
 
 v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,0]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 
 v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x00,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 
 v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x00,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 
 v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1] op_sel_hi:[0,0,0] ; encoding: [0x00,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1] ; encoding: [0x00,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 
 v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1] op_sel_hi:[0,0,0] ; encoding: [0x00,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1] ; encoding: [0x00,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 
 v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 
 v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,0,0]
 // GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c]
 
 v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,1,0]
 // GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x14]
 
 v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,1]
 // GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,1] ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 
 v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,1,1]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3    ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,1,1] ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
 
 v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[1,0,1] clamp
 // GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[1,0,1] clamp ; encoding: [0x00,0xc0,0xa1,0xd3,0x01,0x05,0x0e,0x0c]
 
 v_mad_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[1,0,1] clamp
 // GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[1,0,1] clamp ; encoding: [0x00,0xc0,0xa2,0xd3,0x01,0x05,0x0e,0x0c]

llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt

 # GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x04,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x40,0x04,0xd2,0x01,0x05,0x0e,0x04
 
 # GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x04,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x78,0x04,0xd2,0x01,0x05,0x0e,0x04
 
 # GFX9: v_mad_u16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x04,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x80,0x04,0xd2,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v255, v1, v2, v3    ; encoding: [0xff,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0xff,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v255, v2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0xff,0x05,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0xff,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, s1, v2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, s101, v2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x65,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x65,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, flat_scratch_lo, v2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x66,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x66,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, flat_scratch_hi, v2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x67,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x67,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, vcc_lo, v2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x6a,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x6a,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, vcc_hi, v2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x6b,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x6b,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, m0, v2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x7c,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x7c,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, exec_lo, v2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x7e,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x7e,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, exec_hi, v2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x7f,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x7f,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v255, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0f,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xff,0x0f,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, s2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, s101, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xcb,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xcb,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, flat_scratch_lo, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xcd,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xcd,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, flat_scratch_hi, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xcf,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xcf,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, vcc_lo, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xd5,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xd5,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, vcc_hi, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xd7,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xd7,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, m0, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xf9,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xf9,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, exec_lo, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xfd,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xfd,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, exec_hi, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xff,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v255    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x07]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x07
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, s3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x00]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x00
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, s101    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x96,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x96,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, flat_scratch_lo    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x9a,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x9a,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, flat_scratch_hi    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x9e,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x9e,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, vcc_lo    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xaa,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0xaa,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, vcc_hi    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xae,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0xae,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, m0    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xf2,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0xf2,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, exec_lo    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfa,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0xfa,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, exec_hi    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,0,0]    ; encoding: [0x05,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,1,0]    ; encoding: [0x05,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,0,1]    ; encoding: [0x05,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,1,1]    ; encoding: [0x05,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,0,0]    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,1,0]    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x14]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x14
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,0,1]    ; encoding: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,1,1]    ; encoding: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c
+
+# GFX9: v_mad_mix_f32 v5, -v1, v2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24
+
+# GFX9: v_mad_mix_f32 v5, v1, -v2, v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, -v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84
+
+# GFX9: v_mad_mix_f32 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0xe4
+
+# GFX9: v_mad_mix_f32 v5, |v1|, v2, v3    ; encoding: [0x05,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, |v2|, v3    ; encoding: [0x05,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, |v3|    ; encoding: [0x05,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v255, v1, v2, v3    ; encoding: [0xff,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0xff,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v255, v2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0xff,0x05,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0xff,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, s1, v2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, s101, v2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x65,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x65,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, flat_scratch_lo, v2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x66,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x66,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, flat_scratch_hi, v2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x67,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x67,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, vcc_lo, v2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x6a,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x6a,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, vcc_hi, v2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x6b,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x6b,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, m0, v2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x7c,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x7c,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, exec_lo, v2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x7e,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x7e,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, exec_hi, v2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x7f,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x7f,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v255, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xff,0x0f,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xff,0x0f,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, s2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, s101, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xcb,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xcb,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, flat_scratch_lo, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xcd,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xcd,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, flat_scratch_hi, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xcf,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xcf,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, vcc_lo, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xd5,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xd5,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, vcc_hi, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xd7,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xd7,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, m0, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xf9,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xf9,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, exec_lo, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xfd,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xfd,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, exec_hi, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xff,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xff,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v255    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x07]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x07
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, s3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x00]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x00
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, s101    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x96,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x96,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, flat_scratch_lo    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x9a,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x9a,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, flat_scratch_hi    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x9e,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x9e,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, vcc_lo    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xaa,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0xaa,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, vcc_hi    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xae,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0xae,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, m0    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xf2,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0xf2,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, exec_lo    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfa,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0xfa,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, exec_hi    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[1,0,0]    ; encoding: [0x05,0x08,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x08,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,1,0]    ; encoding: [0x05,0x10,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x10,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,0,1]    ; encoding: [0x05,0x20,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x20,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[1,1,1]    ; encoding: [0x05,0x38,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x38,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0]    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x0c]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x0c
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0]    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x14]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x14
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1]    ; encoding: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[1,1,1]    ; encoding: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c
+
+# GFX9: v_mad_mixhi_f16 v5, -v1, v2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x24]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x24
+
+# GFX9: v_mad_mixhi_f16 v5, v1, -v2, v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x44]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x44
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, -v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x84]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x84
+
+# GFX9: v_mad_mixhi_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0xe4
+
+# GFX9: v_mad_mixhi_f16 v5, |v1|, v2, v3    ; encoding: [0x05,0x01,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x01,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, |v2|, v3    ; encoding: [0x05,0x02,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x02,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, |v3|    ; encoding: [0x05,0x04,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x04,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v255, v1, v2, v3    ; encoding: [0xff,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0xff,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v255, v2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0xff,0x05,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0xff,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, s1, v2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, s101, v2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x65,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x65,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, flat_scratch_lo, v2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x66,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x66,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, flat_scratch_hi, v2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x67,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x67,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, vcc_lo, v2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x6a,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x6a,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, vcc_hi, v2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x6b,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x6b,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, m0, v2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x7c,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x7c,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, exec_lo, v2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x7e,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x7e,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, exec_hi, v2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x7f,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x7f,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v255, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xff,0x0f,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xff,0x0f,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, s2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, s101, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xcb,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xcb,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, flat_scratch_lo, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xcd,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xcd,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, flat_scratch_hi, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xcf,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xcf,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, vcc_lo, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xd5,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xd5,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, vcc_hi, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xd7,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xd7,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, m0, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xf9,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xf9,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, exec_lo, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xfd,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xfd,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, exec_hi, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xff,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xff,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v255    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x07]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x07
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, s3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x00]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x00
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, s101    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x96,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x96,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, flat_scratch_lo    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x9a,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x9a,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, flat_scratch_hi    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x9e,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x9e,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, vcc_lo    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xaa,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0xaa,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, vcc_hi    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xae,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0xae,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, m0    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xf2,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0xf2,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, exec_lo    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfa,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0xfa,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, exec_hi    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[1,0,0]    ; encoding: [0x05,0x08,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x08,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,1,0]    ; encoding: [0x05,0x10,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x10,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,0,1]    ; encoding: [0x05,0x20,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x20,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[1,1,1]    ; encoding: [0x05,0x38,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x38,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0]    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x0c]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x0c
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0]    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x14]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x14
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1]    ; encoding: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[1,1,1]    ; encoding: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c
+
+# GFX9: v_mad_mixlo_f16 v5, -v1, v2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x24]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x24
+
+# GFX9: v_mad_mixlo_f16 v5, v1, -v2, v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x44]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x44
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, -v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x84]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x84
+
+# GFX9: v_mad_mixlo_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0xe4
+
+# GFX9: v_mad_mixlo_f16 v5, |v1|, v2, v3    ; encoding: [0x05,0x01,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x01,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, |v2|, v3    ; encoding: [0x05,0x02,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x02,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, |v3|    ; encoding: [0x05,0x04,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x04,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04