AMDGPU/SI: Implement d16 support for buffer intrinsics

[cfang]

Summary

This patch implements buffer_load_format and tbuffer_load_format intrinsics that support half data types.

While types that are not legal currently ( v4f16, for example), we are using ReplaceNodeResults to change the
type and cast it back after customer lowering.

[arsenm]

lib/Target/AMDGPU/SIISelLowering.cpp

204

This also applies to VI, but it doesn't really matter if it is legal or not. you can still set it to custom

3230

Should put this into a new function

3232–3234

This should not be an assert, but should also probably handle v3f16

3258–3261

This should be moved into getTgtMemIntrinsic so the MMO already exists

3277–3280

Ditto

3284

Return on different line

3286

Typo yo, pu

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.d16.ll

1 ↗

(On Diff #118982)

GCN as check prefix. Also should have a VI check line? Is this the one where the output register layout can differ on some gfx8 variant?

test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll

15–16

Should check operands

[cfang]

lib/Target/AMDGPU/SIISelLowering.cpp

3258–3261

I could not understand your intention here. Can you be more specific how to move this to "bool SITargetLowering::getTgtMemIntrinsic"?
And how to get MMO? Thanks.

[arsenm]

lib/Target/AMDGPU/SIISelLowering.cpp

3258–3261

If you implement getTgtMemIntrinsic it will add the same MMO to the intrinsic. You then just need to forward it to the new node. This is still suboptimal since we should really be using the buffer PseudoSourceValue instead of a null MachinePointerInfo

[cfang]

Update based on Matt's review comments.

[cfang]

lib/Target/AMDGPU/SIISelLowering.cpp

204

OK

3232–3234

v3f16 as TODO.

3258–3261

Implemented getTgtMemIntrinsic, and made appropriate changes. Thanks.

3286

Thanks.

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.d16.ll

1 ↗

(On Diff #118982)

I am not sure. But the ISA for the instructions are exactly the same for both VI and gfx9. So I didn't add VI check.

[cfang]

Implement getTgtMemIntrinsic for buffer_load/tbuffer_load intrinsics.
Update based on Matt's review comments.

[cfang]

1. Define a new feature, HasPackedD16VMem for gfx8.1 and beyond to guard the generation of VMem instructions with D16 bit set.
2. Put buffer_store intrinsics implementation in the same patch as buffer_loads;

[arsenm]

lib/Target/AMDGPU/AMDGPU.td

289

I think we should invert this, to HasUnpackedD16Mem. It's only the one weird target, the packed layout is the expected one and for every other subtarget.

lib/Target/AMDGPU/BUFInstructions.td

675

Comment belongs somewhere else. We usually have the true opcode name as all caps, and modifiers like this as lowercase. In this case we should maybe call it _gfx81 instead.

lib/Target/AMDGPU/SIISelLowering.cpp

549

Since you really want to get the i16 equivalent vector, you can use changeTypeToInteger on the f16 type.

589

I think you can assume the ABI type alignment for these (at least for the scalar type) not that it probably matters

3268

s/ChangeResultType/lowerIntrinsicWChain/

3274

switch over IID

3345

I'm pretty sure there should be no f32 or FP_ROUND here. This is returning the half format result just expanded into multiple 32-bit registers. They are still half, you need to truncate the int type and bitcast to f16.

4548–4549

Same thing as with stores

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll

1

These should have a common GCN check prefix to avoid the duplicated -LABEL lines

5

Spaces after ;

test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll

34

The waitcnts aren't interesting to check. it would be more useful to extract and store the components to see what instructions are required.

[cfang]

lib/Target/AMDGPU/SIISelLowering.cpp

549

For v2f16, I want something that uses 2 registers, so v2i16 doesn't work for me.
What should be the type that specifies the two registers that hold the two half values? Here I am using v2f32.

3345

Do you mean the returned type is not v2f32? so what is the type that returned? v2f16? I just could not understand how to represent the two half values in two registers!

I hope you can be more specific on what to do here.

[cfang]

lib/Target/AMDGPU/AMDGPU.td

289

OK. Use HasUnpackedD16VMem.

lib/Target/AMDGPU/BUFInstructions.td

675

Done. Use _gfx80 because only gfx80 has the feature "HasUnpackedD16VMem".

lib/Target/AMDGPU/SIISelLowering.cpp

549

Right. So Remove this function definition.

589

Not sure how to get the ABI type alignment here since we are using nullptr as ptrval.

3268

Changed func name to lowerIntrinsicWChain.

3274

OK switch.

3345

For v2f16, changed the intrinsic load type to v2i32 if the target has unpacked vmem instructions. After the load,
we truncate the data to v2i16, and then bitcast it back to v2f16. v4f16 case is done similarly.

4548–4549

For store of v2f16, we first bitcast the data to v2i16, and then zero_extend it to v2i32 to store. v4f16 case is done similarly.

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll

5

Thanks.

[cfang]

Update based on Matt's comments.

[b-sumner]

Pardon my ignorance, but why isn't include/llvm/IR/IntrinsicsAMDGPU.td being updated?

[nhaehnle]

In D38906#922226, @b-sumner wrote:

Pardon my ignorance, but why isn't include/llvm/IR/IntrinsicsAMDGPU.td being updated?

The intrinsics use overloading based on the type, so no new intrinsics need to be defined.

lib/Target/AMDGPU/BUFInstructions.td

1464–1475

Are the pattens with SItbuffer_load and 16-bit types ever used? I believe the f16 maybe, but isn't the v2f16 getting replaced by ReplaceNodeResults?

[nhaehnle]

I should add that apart from the one comment I had, the change looks good to me. It would be great if we could avoid those added custom SD nodes somehow, though...

[cfang]

lib/Target/AMDGPU/BUFInstructions.td

1464–1475

ReplaceNodeResults will only replace illegal vector types (v2f16 on gfx8 and v4f16 on gfx8+).
So the pattens with SItbuffer_load and v2f16 are used for gfx9+ (and f16 are used for gfx8+).

[cfang]

1. Merge the patch with LLVM trunk.
2. Update LIT tests to avoid specific registers.

[cfang]

Merge with the latest LLVM trunk.

We need to keep the ball rolling! Please advice what else to do in order to move ahead. Thanks.

[arsenm]

lib/Target/AMDGPU/SIISelLowering.cpp

556–561

You don't need this, you can just do VT.getScalarType()

3333

I'm confused because all of the intrinsic logic isn't contained here, and this also just always uses the d16 version which is wrong

3412

The only use of this is the negated condition, so just don't negate it

4390–4393

This is an unrelated change

4711

This is redundant with the other type check, you really want isVector() and to just assert on v3f16

4720

Missing space before //

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

2

Use -enable-var-scope

test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll

2

-enable-var-scope

test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll

2

-enable-var-scope

[cfang]

lib/Target/AMDGPU/SIISelLowering.cpp

3333

SDValue Res = lowerIntrinsicWChain(Op, EquivLoadVT, DAG)

This is just a help function to replace the result type of "Op" with " EquivLoadVT". maybe we should use a different name to avoid confusion.

What about: ReplaceResultType ? Thanks.

4390–4393

Why do you think this is unrelated? I have to handle Intrinsic::amdgcn_buffer_load_format in getTgtMemIntrinsic.
After return "true" there, I think it is better to make appropriate change here also.

4711

Do you think we need to assert for v3f16? The code in this block has no reason not to handle v3f16. So the assert of v3f16, if any, should be somewhere else. Also MVY::v3f16 is not recognized in LC.

[cfang]

Update based on Matt's recent comments. Thanks.

[cfang]

ping

[arsenm]

Can you add some assembler tests for this, particularly the 3x components ones

lib/Target/AMDGPU/BUFInstructions.td

925

You an use VReg_96

1873

You should be able to define the 3x encoded ones

1881

You should be able to define the 3x encoded ones

lib/Target/AMDGPU/SIISelLowering.cpp

581–601

This part should be superseded by D41470

3398

This should be in a separate function

4747

Dead code. You need to check the number of elements since there is no v3f16 yet

[arsenm]

lib/Target/AMDGPU/SIISelLowering.cpp

581–601

Also it's unrelated because this could be done separately for the existing intrinsics, as is done in D41470

3333

The point of this is to move all of the intrinsic lowering logic to one function. The type change wrapper may be a useful function used by the function called from the switch. Part of the point is to reduce the amount of code nested in switches

[cfang]

Update based on Reviewer's comments:

1. define encoding subtarget "GFX80" to encode unpacked d16 buffer/tbuffer instructions;
2. add MC test cases;
3. define two functions: SITargetLowering::lowerIntrinsicWChain and SITargetLowering::handleVDataToStore.

[arsenm]

lib/Target/AMDGPU/SIISelLowering.cpp

3552–3553

This is still structured strangely. Most of the code inside this function should be in a helper, and lowerIntrinsicWChain should have the switch over the intrinsic

3565

This is not the correct chain, this is the input chain, not the output result chain

3572–3573

No return after else

3606

Remove = SDValue()

lib/Target/AMDGPU/SIISelLowering.h

63 ↗

(On Diff #128660)

Typo brirf, but autobrief is on so you can just remove it

64 ↗

(On Diff #128660)

Use reference for chain out argument, or just pass in the SmallVectorImpl& directly

lib/Target/AMDGPU/SIInstrInfo.td

1899

You should add a note explaining why this is here and that it should probably be removed at some point

[cfang]

lib/Target/AMDGPU/SIISelLowering.cpp

3565

I though "Res" is the output here, except that it has to be type-converted to the final result.

So how to get the "output result chain" you mentioned? Thanks.

[cfang]

Update based on Matt's latest comments.

Please advice how to get the chain if you still don't agree what I got is actually the result chain. Thanks.

[cfang]

Get the output "Chain" of the intrinsic correctly. Thanks.

[arsenm]

lib/Target/AMDGPU/SIISelLowering.cpp

3508–3509

We already have LowerINTRINSIC_W_CHAIN, so this name could be confusing

3564

Move this into a helper function called in each switch rather than putting code after the switch. Not every intrinsic with an illegal type will necessarily be this situation

3569

No return after else

[cfang]

lib/Target/AMDGPU/SIISelLowering.cpp

3508–3509

This is actually the name you suggested before.

Do you think lowerIntrinsicWChainWithIllegalReturnType is OK? Or any ither name suggestion? Thanks.

3564

OK, will do as you suggested. Thanks.

3569

What do you mean here "no return after else"? Do you mean there should not be a return statement, or a return statement is missing?
Thanks.

[cfang]

Rename a function and add a new helper function based on Matt's comments.

[arsenm]

lib/Target/AMDGPU/SIISelLowering.cpp

4915

You don't need a pointer out argument here. You can just have handleVDataToStore return SDValue() if it doesn't need to do anything. If it actaully does something you know it is d16

[cfang]

Redesign the function to handle Vdata to store so that is will be called only when vdata is of type d16.

lib/Target/AMDGPU/SIISelLowering.cpp

4915

I redesigned this function. It will called called only when VData is the type of "D16".

What do you think?

[arsenm]

LGTM

lib/Target/AMDGPU/AMDGPU.td

   "true",
   "Support DPP (Data Parallel Primitives) extension"
 >;
 
 def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
   "HasIntClamp",
   "true",
   "Support clamp for integer destination"
 >;
 
+def FeaturePackedD16VMem : SubtargetFeature<"packed-d16-vmem",
+  "HasPackedD16VMem",
+  "true",
+  "Has packed d16 vmem instructions"
+>;
+
 //===------------------------------------------------------------===//
 // Subtarget Features (options and debugging)
 //===------------------------------------------------------------===//
 
 // Some instructions do not support denormals despite this flag. Using
 // fp32 denormals also causes instructions to run at the double
 // precision rate for the device.
 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
   "FP32Denormals",
   "true",

 
 def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
   [FeatureFP64, FeatureLocalMemorySize65536,
    FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
    FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
    FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
    FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
    FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
    FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
-   FeatureAddNoCarryInsts
+   FeatureAddNoCarryInsts, FeaturePackedD16VMem
   ]
 >;
 
 class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
                                   list<SubtargetFeature> Implies>
                                  : SubtargetFeature <
   "isaver"#Major#"."#Minor#"."#Stepping,
   "IsaVersion",
   "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
   "Instruction set version number",

   [FeatureVolcanicIslands,
    FeatureLDSBankCount32]>;
 
 def FeatureISAVersion8_0_4 : SubtargetFeatureISAVersion <8,0,4,
   [FeatureVolcanicIslands,
    FeatureLDSBankCount32]>;
 
 def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
   [FeatureVolcanicIslands,
    FeatureLDSBankCount16,
-   FeatureXNACK]>;
+   FeatureXNACK,
+   FeaturePackedD16VMem]>;
 
 def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
   [FeatureGFX9,
    FeatureMadMixInsts,
    FeatureLDSBankCount32
    ]>;
 
 def FeatureISAVersion9_0_1 : SubtargetFeatureISAVersion <9,0,1,
   [FeatureGFX9,
    FeatureMadMixInsts,

 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
   AssemblerPredicate<"FeatureFlatAddressSpace">;
 
 def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
   AssemblerPredicate<"FeatureFlatGlobalInsts">;
 def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
   AssemblerPredicate<"FeatureFlatScratchInsts">;
 def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
   AssemblerPredicate<"FeatureGFX9Insts">;
 
+def HasPackedD16VMem : Predicate<"Subtarget->hasPackedD16VMem()">,
+  AssemblerPredicate<"FeaturePackedD16VMem">;
+
+def NotHasPackedD16VMem : Predicate<"!Subtarget->hasPackedD16VMem()">,
+  AssemblerPredicate<"!FeaturePackedD16VMem">;
+
 def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
   AssemblerPredicate<"FeatureGFX9Insts">;
 
 def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
   AssemblerPredicate<"FeatureAddNoCarryInsts">;
 
 def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
   AssemblerPredicate<"!FeatureAddNoCarryInsts">;
 
 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,

lib/Target/AMDGPU/AMDGPUISelLowering.h

   INTERP_P1,
   INTERP_P2,
   PC_ADD_REL_OFFSET,
   KILL,
   DUMMY_CHAIN,
   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
   STORE_MSKOR,
   LOAD_CONSTANT,
   TBUFFER_STORE_FORMAT,
   TBUFFER_STORE_FORMAT_X3,
+  TBUFFER_STORE_FORMAT_D16,
   TBUFFER_LOAD_FORMAT,
+  TBUFFER_LOAD_FORMAT_D16,
   ATOMIC_CMP_SWAP,
   ATOMIC_INC,
   ATOMIC_DEC,
   BUFFER_LOAD,
   BUFFER_LOAD_FORMAT,
+  BUFFER_LOAD_FORMAT_D16,
+  BUFFER_STORE_FORMAT,
+  BUFFER_STORE_FORMAT_D16,
   LAST_AMDGPU_ISD_NUMBER
 };
 
 
 } // End namespace AMDGPUISD
 
 } // End namespace llvm
 
 #endif

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

   NODE_NAME_CASE(INIT_EXEC_FROM_INPUT)
   NODE_NAME_CASE(SENDMSG)
   NODE_NAME_CASE(SENDMSGHALT)
   NODE_NAME_CASE(INTERP_MOV)
   NODE_NAME_CASE(INTERP_P1)
   NODE_NAME_CASE(INTERP_P2)
   NODE_NAME_CASE(STORE_MSKOR)
   NODE_NAME_CASE(LOAD_CONSTANT)
   NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
   NODE_NAME_CASE(TBUFFER_STORE_FORMAT_X3)
+  NODE_NAME_CASE(TBUFFER_STORE_FORMAT_D16)
   NODE_NAME_CASE(TBUFFER_LOAD_FORMAT)
+  NODE_NAME_CASE(TBUFFER_LOAD_FORMAT_D16)
   NODE_NAME_CASE(ATOMIC_CMP_SWAP)
   NODE_NAME_CASE(ATOMIC_INC)
   NODE_NAME_CASE(ATOMIC_DEC)
   NODE_NAME_CASE(BUFFER_LOAD)
   NODE_NAME_CASE(BUFFER_LOAD_FORMAT)
+  NODE_NAME_CASE(BUFFER_LOAD_FORMAT_D16)
+  NODE_NAME_CASE(BUFFER_STORE_FORMAT)
+  NODE_NAME_CASE(BUFFER_STORE_FORMAT_D16)
   case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
   }
   return nullptr;
 }
 
 SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,
                                               SelectionDAG &DAG, int Enabled,
                                               int &RefinementSteps,
                                               bool &UseOneConstNR,
                                               bool Reciprocal) const {

lib/Target/AMDGPU/AMDGPUSubtarget.h

   bool HasSDWA;
   bool HasSDWAOmod;
   bool HasSDWAScalar;
   bool HasSDWASdst;
   bool HasSDWAMac;
   bool HasSDWAOutModsVOPC;
   bool HasDPP;
   bool FlatAddressSpace;
   bool FlatInstOffsets;
   bool FlatGlobalInsts;
+  bool HasPackedD16VMem;
   bool FlatScratchInsts;
   bool AddNoCarryInsts;
   bool R600ALUInst;
   bool CaymanISA;
   bool CFALUBug;
   bool HasVertexCache;
   short TexVTXClauseSize;
   bool ScalarizeGlobal;
 
   // Dummy feature to use for assembler in tablegen.

   }
 
   bool hasFlatScratchInsts() const {
     return FlatScratchInsts;
   }
 
   bool hasD16LoadStore() const {
     return getGeneration() >= GFX9;
   }
 
+ bool hasPackedD16VMem() const {
+    return HasPackedD16VMem;
+  }
+
   bool hasAddNoCarry() const {
     return AddNoCarryInsts;
   }
 
   bool isMesaKernel(const MachineFunction &MF) const {
     return isMesa3DOS() && !AMDGPU::isShader(MF.getFunction()->getCallingConv());
   }
 
   // Covers VS/PS/CS graphics shaders
   bool isMesaGfxShader(const MachineFunction &MF) const {

lib/Target/AMDGPU/AMDGPUSubtarget.cpp

     HasSDWA(false),
     HasSDWAOmod(false),
     HasSDWAScalar(false),
     HasSDWASdst(false),
     HasSDWAMac(false),
     HasSDWAOutModsVOPC(false),
     HasDPP(false),
     FlatAddressSpace(false),
     FlatInstOffsets(false),
     FlatGlobalInsts(false),
+    HasPackedD16VMem(false),
     FlatScratchInsts(false),
     AddNoCarryInsts(false),
 
     R600ALUInst(false),
     CaymanISA(false),
     CFALUBug(false),
     HasVertexCache(false),
     TexVTXClauseSize(0),
     ScalarizeGlobal(false),
 

lib/Target/AMDGPU/BUFInstructions.td

 >;
 defm BUFFER_STORE_FORMAT_XY : MUBUF_Pseudo_Stores <
   "buffer_store_format_xy", VReg_64
 >;
 defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Pseudo_Stores <
   "buffer_store_format_xyz", VReg_96
 >;
 defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Pseudo_Stores <
   "buffer_store_format_xyzw", VReg_128
 >;
+
+let SubtargetPredicate = NotHasPackedD16VMem in { // NP means data not packed.
+defm BUFFER_LOAD_FORMAT_D16_X_NP : MUBUF_Pseudo_Loads <
+  "buffer_load_format_d16_x", VGPR_32
+>;
+defm BUFFER_LOAD_FORMAT_D16_XY_NP : MUBUF_Pseudo_Loads <
+  "buffer_load_format_d16_xy", VReg_64
+>;
+defm BUFFER_LOAD_FORMAT_D16_XYZ_NP : MUBUF_Pseudo_Loads <
+  "buffer_load_format_d16_xyz", VReg_96
+>;
+defm BUFFER_LOAD_FORMAT_D16_XYZW_NP : MUBUF_Pseudo_Loads <
+  "buffer_load_format_d16_xyzw", VReg_128
+>;
+defm BUFFER_STORE_FORMAT_D16_X_NP : MUBUF_Pseudo_Stores <
+  "buffer_store_format_d16_x", VGPR_32
+>;
+defm BUFFER_STORE_FORMAT_D16_XY_NP : MUBUF_Pseudo_Stores <
+  "buffer_store_format_d16_xy", VReg_64
+>;
+defm BUFFER_STORE_FORMAT_D16_XYZ_NP : MUBUF_Pseudo_Stores <
+  "buffer_store_format_d15_xyz", VReg_96
+>;
+defm BUFFER_STORE_FORMAT_D16_XYZW_NP : MUBUF_Pseudo_Stores <
+  "buffer_store_format_d16_xyzw", VReg_128
+>;
+} // End NotHasPackedD16VMem.
+
+let SubtargetPredicate = HasPackedD16VMem in {
+defm BUFFER_LOAD_FORMAT_D16_X : MUBUF_Pseudo_Loads <
+  "buffer_load_format_d16_x", VGPR_32
+>;
+defm BUFFER_LOAD_FORMAT_D16_XY : MUBUF_Pseudo_Loads <
+  "buffer_load_format_d16_xy", VGPR_32
+>;
+defm BUFFER_LOAD_FORMAT_D16_XYZ : MUBUF_Pseudo_Loads <
+  "buffer_load_format_d16_xyz", VReg_64
+>;
+defm BUFFER_LOAD_FORMAT_D16_XYZW : MUBUF_Pseudo_Loads <
+  "buffer_load_format_d16_xyzw", VReg_64
+>;
+defm BUFFER_STORE_FORMAT_D16_X : MUBUF_Pseudo_Stores <
+  "buffer_store_format_d16_x", VGPR_32
+>;
+defm BUFFER_STORE_FORMAT_D16_XY : MUBUF_Pseudo_Stores <
+  "buffer_store_format_d16_xy", VGPR_32
+>;
+defm BUFFER_STORE_FORMAT_D16_XYZ : MUBUF_Pseudo_Stores <
+  "buffer_store_format_d15_xyz", VReg_64
+>;
+defm BUFFER_STORE_FORMAT_D16_XYZW : MUBUF_Pseudo_Stores <
+  "buffer_store_format_d16_xyzw", VReg_64
+>;
+} // End HasPackedD16VMem.
+
 defm BUFFER_LOAD_UBYTE : MUBUF_Pseudo_Loads <
   "buffer_load_ubyte", VGPR_32, i32, mubuf_az_extloadi8
 >;
 defm BUFFER_LOAD_SBYTE : MUBUF_Pseudo_Loads <
   "buffer_load_sbyte", VGPR_32, i32, mubuf_sextloadi8
 >;
 defm BUFFER_LOAD_USHORT : MUBUF_Pseudo_Loads <
   "buffer_load_ushort", VGPR_32, i32, mubuf_az_extloadi16
 >;
 defm BUFFER_LOAD_SSHORT : MUBUF_Pseudo_Loads <

 
 defm TBUFFER_LOAD_FORMAT_X     : MTBUF_Pseudo_Loads  <"tbuffer_load_format_x",     VGPR_32>;
 defm TBUFFER_LOAD_FORMAT_XY    : MTBUF_Pseudo_Loads  <"tbuffer_load_format_xy",    VReg_64>;
 defm TBUFFER_LOAD_FORMAT_XYZ   : MTBUF_Pseudo_Loads  <"tbuffer_load_format_xyz",   VReg_128>;
 defm TBUFFER_LOAD_FORMAT_XYZW  : MTBUF_Pseudo_Loads  <"tbuffer_load_format_xyzw",  VReg_128>;
 defm TBUFFER_STORE_FORMAT_X    : MTBUF_Pseudo_Stores <"tbuffer_store_format_x",    VGPR_32>;
 defm TBUFFER_STORE_FORMAT_XY   : MTBUF_Pseudo_Stores <"tbuffer_store_format_xy",   VReg_64>;
 defm TBUFFER_STORE_FORMAT_XYZ  : MTBUF_Pseudo_Stores <"tbuffer_store_format_xyz",  VReg_128>;
 defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Pseudo_Stores <"tbuffer_store_format_xyzw", VReg_128>;
 
+let SubtargetPredicate = NotHasPackedD16VMem in { // NP means data not packed.
+defm TBUFFER_LOAD_FORMAT_D16_X_NP     : MTBUF_Pseudo_Loads  <"tbuffer_load_format_d16_x",     VGPR_32>;
+defm TBUFFER_LOAD_FORMAT_D16_XY_NP    : MTBUF_Pseudo_Loads  <"tbuffer_load_format_d16_xy",    VReg_64>;
+defm TBUFFER_LOAD_FORMAT_D16_XYZ_NP   : MTBUF_Pseudo_Loads  <"tbuffer_load_format_d16_xyz",   VReg_128>;
+defm TBUFFER_LOAD_FORMAT_D16_XYZW_NP  : MTBUF_Pseudo_Loads  <"tbuffer_load_format_d16_xyzw",  VReg_128>;
+defm TBUFFER_STORE_FORMAT_D16_X_NP    : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_x",    VGPR_32>;
+defm TBUFFER_STORE_FORMAT_D16_XY_NP   : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xy",   VReg_64>;
+defm TBUFFER_STORE_FORMAT_D16_XYZ_NP  : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xyz",  VReg_128>;
+defm TBUFFER_STORE_FORMAT_D16_XYZW_NP : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xyzw", VReg_128>;
+} // End NotHasPackedD16VMem.
+
+let SubtargetPredicate = HasPackedD16VMem in {
+defm TBUFFER_LOAD_FORMAT_D16_X     : MTBUF_Pseudo_Loads  <"tbuffer_load_format_d16_x",     VGPR_32>;
+defm TBUFFER_LOAD_FORMAT_D16_XY    : MTBUF_Pseudo_Loads  <"tbuffer_load_format_d16_xy",    VGPR_32>;
+defm TBUFFER_LOAD_FORMAT_D16_XYZ   : MTBUF_Pseudo_Loads  <"tbuffer_load_format_d16_xyz",   VReg_64>;
+defm TBUFFER_LOAD_FORMAT_D16_XYZW  : MTBUF_Pseudo_Loads  <"tbuffer_load_format_d16_xyzw",  VReg_64>;
+defm TBUFFER_STORE_FORMAT_D16_X    : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_x",    VGPR_32>;
+defm TBUFFER_STORE_FORMAT_D16_XY   : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xy",   VGPR_32>;
+defm TBUFFER_STORE_FORMAT_D16_XYZ  : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xyz",  VReg_64>;
+defm TBUFFER_STORE_FORMAT_D16_XYZW : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xyzw", VReg_64>;
+} // End HasPackedD16VMem.
+
+
 let SubtargetPredicate = isCIVI in {
 
 //===----------------------------------------------------------------------===//
 // Instruction definitions for CI and newer.
 //===----------------------------------------------------------------------===//
 // Remaining instructions:
 // BUFFER_LOAD_DWORDX3
 // BUFFER_STORE_DWORDX3
 
 def BUFFER_WBINVL1_VOL : MUBUF_Invalidate <"buffer_wbinvl1_vol",

     (!cast<MUBUF_Pseudo>(opcode # _BOTHEN)
       (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
       $rsrc, $soffset, (as_i16imm $offset),
       (as_i1imm $glc), (as_i1imm $slc), 0)
   >;
 }
 
 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, f32, "BUFFER_LOAD_FORMAT_X">;
 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v2f32, "BUFFER_LOAD_FORMAT_XY">;
 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v4f32, "BUFFER_LOAD_FORMAT_XYZW">;
+
+let SubtargetPredicate = NotHasPackedD16VMem in { // NP means data not packed.
+defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, f16, "BUFFER_LOAD_FORMAT_D16_X_NP">;
+defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, v2f32, "BUFFER_LOAD_FORMAT_D16_XY_NP">;
+defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, v4f32, "BUFFER_LOAD_FORMAT_D16_XYZW_NP">;
+} // End NotHasPackedD16VMem.
+
+let SubtargetPredicate = HasPackedD16VMem in {
+defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, f16, "BUFFER_LOAD_FORMAT_D16_X">;
+defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v2f16, "BUFFER_LOAD_FORMAT_D16_XY">;
+defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, i32, "BUFFER_LOAD_FORMAT_D16_XY">;
+defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format_d16, v2i32, "BUFFER_LOAD_FORMAT_D16_XYZW">;
+} // End HasPackedD16VMem.
+
 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, f32, "BUFFER_LOAD_DWORD">;
 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v2f32, "BUFFER_LOAD_DWORDX2">;
 defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v4f32, "BUFFER_LOAD_DWORDX4">;
 
 multiclass MUBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt,
                                    string opcode> {
   def : GCNPat<
     (name vt:$vdata, v4i32:$rsrc, 0,
           (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
           imm:$glc, imm:$slc),

           (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
           imm:$glc, imm:$slc),
     (!cast<MUBUF_Pseudo>(opcode # _BOTHEN_exact)
       $vdata,
       (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
       $rsrc, $soffset, (as_i16imm $offset),
       (as_i1imm $glc), (as_i1imm $slc), 0)
   >;
 }
 
-defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, f32, "BUFFER_STORE_FORMAT_X">;
-defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, v2f32, "BUFFER_STORE_FORMAT_XY">;
-defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store_format, v4f32, "BUFFER_STORE_FORMAT_XYZW">;
+defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, f32, "BUFFER_STORE_FORMAT_X">;
+defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v2f32, "BUFFER_STORE_FORMAT_XY">;
+defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v4f32, "BUFFER_STORE_FORMAT_XYZW">;
+
+let SubtargetPredicate = NotHasPackedD16VMem in { // NP means data not packed.
+defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, f16, "BUFFER_STORE_FORMAT_D16_X_NP">;
+defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, v2f32, "BUFFER_STORE_FORMAT_D16_XY_NP">;
+defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, v4f32, "BUFFER_STORE_FORMAT_D16_XYZW_NP">;
+} // End NotHasPackedD16VMem.
+
+let SubtargetPredicate = HasPackedD16VMem in {
+defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, f16, "BUFFER_STORE_FORMAT_D16_X">;
+defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, v2f16, "BUFFER_STORE_FORMAT_D16_XY">;
+defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, i32, "BUFFER_STORE_FORMAT_D16_XY">;
+defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format_d16, v2i32, "BUFFER_STORE_FORMAT_D16_XYZW">;
+} // End HasPackedD16VMem.
+
 defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, f32, "BUFFER_STORE_DWORD">;
 defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, v2f32, "BUFFER_STORE_DWORDX2">;
 defm : MUBUF_StoreIntrinsicPat<int_amdgcn_buffer_store, v4f32, "BUFFER_STORE_DWORDX4">;
 
 //===----------------------------------------------------------------------===//
 // buffer_atomic patterns
 //===----------------------------------------------------------------------===//
 
 multiclass BufferAtomicPatterns<SDPatternOperator name, string opcode> {
   def : GCNPat<

   >;
 }
 
 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, i32,   "TBUFFER_LOAD_FORMAT_X">;
 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v2i32, "TBUFFER_LOAD_FORMAT_XY">;
 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v4i32, "TBUFFER_LOAD_FORMAT_XYZW">;
 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, f32,   "TBUFFER_LOAD_FORMAT_X">;
 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v2f32, "TBUFFER_LOAD_FORMAT_XY">;
 defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v4f32, "TBUFFER_LOAD_FORMAT_XYZW">;
 
+let SubtargetPredicate = NotHasPackedD16VMem in { // NP means data not packed.
+defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, f16,   "TBUFFER_LOAD_FORMAT_D16_X_NP">;
+defm : MTBUF_LoadIntrinsicPat<SItbuffer_load_d16, v2f32, "TBUFFER_LOAD_FORMAT_D16_XY_NP">;
+defm : MTBUF_LoadIntrinsicPat<SItbuffer_load_d16, v4f32, "TBUFFER_LOAD_FORMAT_D16_XYZW_NP">;
+} // End NotHasPackedD16VMem.
+
+let SubtargetPredicate = HasPackedD16VMem in {
+defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, f16,   "TBUFFER_LOAD_FORMAT_D16_X">;
+defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v2f16, "TBUFFER_LOAD_FORMAT_D16_XY">;
+defm : MTBUF_LoadIntrinsicPat<SItbuffer_load_d16, i32, "TBUFFER_LOAD_FORMAT_D16_XY">;
+defm : MTBUF_LoadIntrinsicPat<SItbuffer_load_d16, v2i32, "TBUFFER_LOAD_FORMAT_D16_XYZW">;
+} // End HasPackedD16VMem.
+
 multiclass MTBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt,
                                    string opcode> {
   def : GCNPat<
     (name vt:$vdata, v4i32:$rsrc, 0, 0, i32:$soffset, imm:$offset,
           imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc),
     (!cast<MTBUF_Pseudo>(opcode # _OFFSET_exact) $vdata, $rsrc, $soffset,
                                 (as_i16imm $offset), (as_i8imm $dfmt),
                                 (as_i8imm $nfmt), (as_i1imm $glc),
                                 (as_i1imm $slc), 0)
   >;

 
 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, i32,   "TBUFFER_STORE_FORMAT_X">;
 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v2i32, "TBUFFER_STORE_FORMAT_XY">;
 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_x3, v4i32, "TBUFFER_STORE_FORMAT_XYZ">;
 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v4i32, "TBUFFER_STORE_FORMAT_XYZW">;
 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, f32,   "TBUFFER_STORE_FORMAT_X">;
 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v2f32, "TBUFFER_STORE_FORMAT_XY">;
 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_x3, v4f32, "TBUFFER_STORE_FORMAT_XYZ">;
 defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v4f32, "TBUFFER_STORE_FORMAT_XYZW">;
 
+let SubtargetPredicate = NotHasPackedD16VMem in { // NP means data not packed.
+defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, f16,   "TBUFFER_STORE_FORMAT_D16_X_NP">;
+defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, v2f32, "TBUFFER_STORE_FORMAT_D16_XY_NP">;
+defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, v4f32, "TBUFFER_STORE_FORMAT_D16_XYZW_NP">;
+} // End NotHasPackedD16VMem.
+
+let SubtargetPredicate = HasPackedD16VMem in {
+defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, f16,   "TBUFFER_STORE_FORMAT_D16_X">;
+defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, v2f16, "TBUFFER_STORE_FORMAT_D16_XY">;
+defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, i32, "TBUFFER_STORE_FORMAT_D16_XY">;
+defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_d16, v2i32, "TBUFFER_STORE_FORMAT_D16_XYZW">;
+} // End HasPackedD16VMem.
+
+
 //===----------------------------------------------------------------------===//
 // Target instructions, move to the appropriate target TD file
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // SI
 //===----------------------------------------------------------------------===//
 
 class MUBUF_Real_si <bits<7> op, MUBUF_Pseudo ps> :
   MUBUF_Real<op, ps>,

 }
 
 defm BUFFER_LOAD_FORMAT_X       : MUBUF_Real_AllAddr_vi <0x00>;
 defm BUFFER_LOAD_FORMAT_XY      : MUBUF_Real_AllAddr_vi <0x01>;
 defm BUFFER_LOAD_FORMAT_XYZ     : MUBUF_Real_AllAddr_vi <0x02>;
 defm BUFFER_LOAD_FORMAT_XYZW    : MUBUF_Real_AllAddr_vi <0x03>;
 defm BUFFER_STORE_FORMAT_X      : MUBUF_Real_AllAddr_vi <0x04>;
 defm BUFFER_STORE_FORMAT_XY     : MUBUF_Real_AllAddr_vi <0x05>;
 defm BUFFER_STORE_FORMAT_XYZ    : MUBUF_Real_AllAddr_vi <0x06>;
 defm BUFFER_STORE_FORMAT_XYZW   : MUBUF_Real_AllAddr_vi <0x07>;
+defm BUFFER_LOAD_FORMAT_D16_X       : MUBUF_Real_AllAddr_vi <0x08>;
+defm BUFFER_LOAD_FORMAT_D16_XY      : MUBUF_Real_AllAddr_vi <0x09>;
+defm BUFFER_LOAD_FORMAT_D16_XYZ     : MUBUF_Real_AllAddr_vi <0x0a>;
+defm BUFFER_LOAD_FORMAT_D16_XYZW    : MUBUF_Real_AllAddr_vi <0x0b>;
+defm BUFFER_STORE_FORMAT_D16_X      : MUBUF_Real_AllAddr_vi <0x0c>;
+defm BUFFER_STORE_FORMAT_D16_XY     : MUBUF_Real_AllAddr_vi <0x0d>;
+defm BUFFER_STORE_FORMAT_D16_XYZ    : MUBUF_Real_AllAddr_vi <0x0e>;
+defm BUFFER_STORE_FORMAT_D16_XYZW   : MUBUF_Real_AllAddr_vi <0x0f>;
 defm BUFFER_LOAD_UBYTE          : MUBUF_Real_AllAddr_vi <0x10>;
 defm BUFFER_LOAD_SBYTE          : MUBUF_Real_AllAddr_vi <0x11>;
 defm BUFFER_LOAD_USHORT         : MUBUF_Real_AllAddr_vi <0x12>;
 defm BUFFER_LOAD_SSHORT         : MUBUF_Real_AllAddr_vi <0x13>;
 defm BUFFER_LOAD_DWORD          : MUBUF_Real_AllAddr_vi <0x14>;
 defm BUFFER_LOAD_DWORDX2        : MUBUF_Real_AllAddr_vi <0x15>;
 defm BUFFER_LOAD_DWORDX3        : MUBUF_Real_AllAddr_vi <0x16>;
 defm BUFFER_LOAD_DWORDX4        : MUBUF_Real_AllAddr_vi <0x17>;
 defm BUFFER_STORE_BYTE          : MUBUF_Real_AllAddr_vi <0x18>;
 defm BUFFER_STORE_BYTE_D16_HI   : MUBUF_Real_AllAddr_vi <0x19>;

   let Inst{63-56} = !if(ps.has_soffset, soffset, ?);
 }
 
 multiclass MTBUF_Real_AllAddr_vi<bits<4> op> {
   def _OFFSET_vi : MTBUF_Real_vi <op, !cast<MTBUF_Pseudo>(NAME#"_OFFSET")>;
   def _OFFEN_vi  : MTBUF_Real_vi <op, !cast<MTBUF_Pseudo>(NAME#"_OFFEN")>;
   def _IDXEN_vi  : MTBUF_Real_vi <op, !cast<MTBUF_Pseudo>(NAME#"_IDXEN")>;
   def _BOTHEN_vi : MTBUF_Real_vi <op, !cast<MTBUF_Pseudo>(NAME#"_BOTHEN")>;
 }
 
-defm TBUFFER_LOAD_FORMAT_X     : MTBUF_Real_AllAddr_vi <0>;
-defm TBUFFER_LOAD_FORMAT_XY    : MTBUF_Real_AllAddr_vi <1>;
-//defm TBUFFER_LOAD_FORMAT_XYZ   : MTBUF_Real_AllAddr_vi <2>;
-defm TBUFFER_LOAD_FORMAT_XYZW  : MTBUF_Real_AllAddr_vi <3>;
-defm TBUFFER_STORE_FORMAT_X    : MTBUF_Real_AllAddr_vi <4>;
-defm TBUFFER_STORE_FORMAT_XY   : MTBUF_Real_AllAddr_vi <5>;
-defm TBUFFER_STORE_FORMAT_XYZ  : MTBUF_Real_AllAddr_vi <6>;
-defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Real_AllAddr_vi <7>;
+defm TBUFFER_LOAD_FORMAT_X     : MTBUF_Real_AllAddr_vi <0x00>;
+defm TBUFFER_LOAD_FORMAT_XY    : MTBUF_Real_AllAddr_vi <0x01>;
+//defm TBUFFER_LOAD_FORMAT_XYZ   : MTBUF_Real_AllAddr_vi <0x02>;
+defm TBUFFER_LOAD_FORMAT_XYZW  : MTBUF_Real_AllAddr_vi <0x03>;
+defm TBUFFER_STORE_FORMAT_X    : MTBUF_Real_AllAddr_vi <0x04>;
+defm TBUFFER_STORE_FORMAT_XY   : MTBUF_Real_AllAddr_vi <0x05>;
+defm TBUFFER_STORE_FORMAT_XYZ  : MTBUF_Real_AllAddr_vi <0x06>;
+defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Real_AllAddr_vi <0x07>;
+defm TBUFFER_LOAD_FORMAT_D16_X     : MTBUF_Real_AllAddr_vi <0x08>;
+defm TBUFFER_LOAD_FORMAT_D16_XY    : MTBUF_Real_AllAddr_vi <0x09>;
+//defm TBUFFER_LOAD_FORMAT_D16_XYZ   : MTBUF_Real_AllAddr_vi <0x0a>;
+defm TBUFFER_LOAD_FORMAT_D16_XYZW  : MTBUF_Real_AllAddr_vi <0x0b>;
+defm TBUFFER_STORE_FORMAT_D16_X    : MTBUF_Real_AllAddr_vi <0x0c>;
+defm TBUFFER_STORE_FORMAT_D16_XY   : MTBUF_Real_AllAddr_vi <0x0d>;
+defm TBUFFER_STORE_FORMAT_D16_XYZ  : MTBUF_Real_AllAddr_vi <0x0e>;
+defm TBUFFER_STORE_FORMAT_D16_XYZW : MTBUF_Real_AllAddr_vi <0x0f>;

lib/Target/AMDGPU/SIISelLowering.cpp

   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
 
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f16, Custom);
 
+  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2f16, Custom);
+  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4f16, Custom);
   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
 
   setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
   setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom);
   setOperationAction(ISD::INTRINSIC_VOID, MVT::v2f16, Custom);
+  setOperationAction(ISD::INTRINSIC_VOID, MVT::v4f16, Custom);
 
   setOperationAction(ISD::BRCOND, MVT::Other, Custom);
   setOperationAction(ISD::BR_CC, MVT::i1, Expand);
   setOperationAction(ISD::BR_CC, MVT::i32, Expand);
   setOperationAction(ISD::BR_CC, MVT::i64, Expand);
   setOperationAction(ISD::BR_CC, MVT::f32, Expand);
   setOperationAction(ISD::BR_CC, MVT::f64, Expand);
 
   setOperationAction(ISD::UADDO, MVT::i32, Legal);
   setOperationAction(ISD::USUBO, MVT::i32, Legal);

 }
 
 const SISubtarget *SITargetLowering::getSubtarget() const {
   return static_cast<const SISubtarget *>(Subtarget);
 }
 
 //===----------------------------------------------------------------------===//
 // TargetLowering queries
 //===----------------------------------------------------------------------===//
 
+static bool isHalfVT (EVT VT) {
+  return (VT == MVT::f16   ||
+          VT == MVT::v2f16 ||
+          //VT == MVT::v3f16 ||
+          VT == MVT::v4f16);
+}
+
+static EVT getExtVT (EVT VT) {
+  if (VT == MVT::v2f16)
+    return MVT::v2f32;
+  // else if (VT == MVT::v3f16)
+  //   return MVT::v3f32;
+  else if (VT == MVT::v4f16)
+    return MVT::v4f32;
+  else
+    llvm_unreachable("Handle new hylf type");
+}
+
 bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
   // SI has some legal vector types, but no legal vector operations. Say no
   // shuffles are legal in order to prefer scalarizing some vector operations.
   return false;
 }
 
 bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
                                           const CallInst &CI,
                                           unsigned IntrID) const {
   switch (IntrID) {

     Info.memVT = MVT::getVT(CI.getType());
     Info.ptrVal = CI.getOperand(0);
     Info.align = 0;
 
     const ConstantInt *Vol = dyn_cast<ConstantInt>(CI.getOperand(4));
     Info.vol = !Vol || !Vol->isZero();
     Info.readMem = true;
     Info.writeMem = true;
     return true;
   }
+  case Intrinsic::amdgcn_buffer_load:
+  case Intrinsic::amdgcn_buffer_load_format:
+  case Intrinsic::amdgcn_tbuffer_load: {
+    Info.opc = ISD::INTRINSIC_W_CHAIN;
+    Info.memVT = MVT::getVT(CI.getType());
+    Info.ptrVal = nullptr;
+    Info.align = 0;
+
+    Info.vol = false;
+    Info.readMem = true;
+    Info.writeMem = false;
+    return true;
+  }
+  case Intrinsic::amdgcn_buffer_store_format:
+  case Intrinsic::amdgcn_tbuffer_store: {
+    Info.opc = ISD::INTRINSIC_VOID;
+    Info.memVT = MVT::getVT(CI.getOperand(0)->getType());
+    Info.ptrVal = nullptr;
+    Info.align = 0;
+
+    Info.vol = false;
+    Info.readMem = false;
+    Info.writeMem = true;
+    return true;
+  }
   default:
     return false;
   }
 }
 
 bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II,
                                             SmallVectorImpl<Value*> &Ops,
                                             Type *&AccessTy) const {
   switch (II->getIntrinsicID()) {
   case Intrinsic::amdgcn_atomic_inc:

   case ISD::FP_ROUND:
     return lowerFP_ROUND(Op, DAG);
 
   case ISD::TRAP:
   case ISD::DEBUGTRAP:
     return lowerTRAP(Op, DAG);
   }
   return SDValue();
 }
 
+static SDValue ChangeResultType(SDValue Op, EVT EquivResultT, SelectionDAG &DAG) {
+  // Change from v4f16/v2f16 to EquivResultT.
+  SDVTList VTList = DAG.getVTList(EquivResultT, MVT::Other);
+  SDLoc DL(Op);
+  MemSDNode *M = cast<MemSDNode>(Op);
+  unsigned IID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+  if (IID == Intrinsic::amdgcn_tbuffer_load) {
+    SDValue Ops[] = {
+        Op.getOperand(0),  // Chain
+        Op.getOperand(2),  // rsrc
+        Op.getOperand(3),  // vindex
+        Op.getOperand(4),  // voffset
+        Op.getOperand(5),  // soffset
+        Op.getOperand(6),  // offset
+        Op.getOperand(7),  // dfmt
+        Op.getOperand(8),  // nfmt
+        Op.getOperand(9),  // glc
+        Op.getOperand(10)  // slc
+      };
+      return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16, DL,
+                                     VTList, Ops, M->getMemoryVT(),
+                                     M->getMemOperand());
+    } else if (IID == Intrinsic::amdgcn_buffer_load_format) {
+      SDValue Ops[] = {
+        Op.getOperand(0), // Chain
+        Op.getOperand(2), // rsrc
+        Op.getOperand(3), // vindex
+        Op.getOperand(4), // offset
+        Op.getOperand(5), // glc
+        Op.getOperand(6)  // slc
+      };
+      return DAG.getMemIntrinsicNode(AMDGPUISD::BUFFER_LOAD_FORMAT_D16,
+                                     DL, VTList, Ops, M->getMemoryVT(),
+                                     M->getMemOperand());
+   }
+   return SDValue();
+}
+
 void SITargetLowering::ReplaceNodeResults(SDNode *N,
                                           SmallVectorImpl<SDValue> &Results,
                                           SelectionDAG &DAG) const {
   switch (N->getOpcode()) {
   case ISD::INSERT_VECTOR_ELT: {
     if (SDValue Res = lowerINSERT_VECTOR_ELT(SDValue(N, 0), DAG))
       Results.push_back(Res);
     return;
   }
   case ISD::EXTRACT_VECTOR_ELT: {

       SDValue Src0 = N->getOperand(1);
       SDValue Src1 = N->getOperand(2);
       SDLoc SL(N);
       SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, SL, MVT::i32,
                                 Src0, Src1);
       Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Cvt));
       return;
     }
     break;
   }
+  case ISD::INTRINSIC_W_CHAIN: {
+    SDLoc SL(N);
+    SDValue Op = SDValue(N, 0);
+    EVT ResultT = Op.getValueType();
+    // TODO: handle v3f16.
+    if (ResultT != MVT::v2f16 && ResultT != MVT::v4f16)
+      return;
+
+    bool HasPacked = Subtarget->hasPackedD16VMem();
+    EVT ToVT = HasPacked ? getEquivalentMemType(*DAG.getContext(), ResultT)
+                         : getExtVT(ResultT); // v2f16/v4f16 to v2f32/v4f32.
+    if (SDValue Res = ChangeResultType(Op, ToVT, DAG)) {
+      if (!HasPacked) { // From v2f32/v4f32 back to v2f16/v4f16.
+        SDValue RFlag = DAG.getTargetConstant(0, SL, MVT::i32);
+        Results.push_back(DAG.getNode(ISD::FP_ROUND, SL, ResultT, Res, RFlag));
+       } else // Cast back to the original packed type.
+         Results.push_back(DAG.getNode(ISD::BITCAST, SL, ResultT, Res));
+      Results.push_back(Res.getOperand(0)); // Chain
+    }
+    break;
+  }
   case ISD::SELECT: {
     SDLoc SL(N);
     EVT VT = N->getValueType(0);
     EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
     SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1));
     SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2));
 
     EVT SelectVT = NewVT;
     if (NewVT.bitsLT(MVT::i32)) {
       LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS);

     return SDValue(DAG.getMachineNode(AMDGPU::WWM, DL, Src.getValueType(), Src),
                    0);
   }
   default:
     return Op;
   }
 }
 
 SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
                                                  SelectionDAG &DAG) const {
-  unsigned IntrID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
   SDLoc DL(Op);
-  MachineFunction &MF = DAG.getMachineFunction();
-
+  unsigned IntrID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
   switch (IntrID) {
   case Intrinsic::amdgcn_atomic_inc:
   case Intrinsic::amdgcn_atomic_dec: {
     MemSDNode *M = cast<MemSDNode>(Op);
     unsigned Opc = (IntrID == Intrinsic::amdgcn_atomic_inc) ?
       AMDGPUISD::ATOMIC_INC : AMDGPUISD::ATOMIC_DEC;
     SDValue Ops[] = {
       M->getOperand(0), // Chain
       M->getOperand(2), // Ptr
       M->getOperand(3)  // Value
     };
 
     return DAG.getMemIntrinsicNode(Opc, SDLoc(Op), M->getVTList(), Ops,
                                    M->getMemoryVT(), M->getMemOperand());
   }
   case Intrinsic::amdgcn_buffer_load:
   case Intrinsic::amdgcn_buffer_load_format: {
+    MemSDNode *M = cast<MemSDNode>(Op);
     SDValue Ops[] = {
       Op.getOperand(0), // Chain
       Op.getOperand(2), // rsrc
       Op.getOperand(3), // vindex
       Op.getOperand(4), // offset
       Op.getOperand(5), // glc
       Op.getOperand(6)  // slc
     };
-    SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
-
     unsigned Opc = (IntrID == Intrinsic::amdgcn_buffer_load) ?
         AMDGPUISD::BUFFER_LOAD : AMDGPUISD::BUFFER_LOAD_FORMAT;
-    EVT VT = Op.getValueType();
-    EVT IntVT = VT.changeTypeToInteger();
 
-    MachineMemOperand *MMO = MF.getMachineMemOperand(
-      MachinePointerInfo(MFI->getBufferPSV()),
-      MachineMemOperand::MOLoad,
-      VT.getStoreSize(), VT.getStoreSize());
-
-    return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT, MMO);
+    return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
+                                   M->getMemoryVT(), M->getMemOperand());
   }
   case Intrinsic::amdgcn_tbuffer_load: {
+    MemSDNode *M = cast<MemSDNode>(Op);
     SDValue Ops[] = {
       Op.getOperand(0),  // Chain
       Op.getOperand(2),  // rsrc
       Op.getOperand(3),  // vindex
       Op.getOperand(4),  // voffset
       Op.getOperand(5),  // soffset
       Op.getOperand(6),  // offset
       Op.getOperand(7),  // dfmt
       Op.getOperand(8),  // nfmt
       Op.getOperand(9),  // glc
-      Op.getOperand(10)   // slc
+      Op.getOperand(10)  // slc
     };
 
-    EVT VT = Op.getOperand(2).getValueType();
-
-    MachineMemOperand *MMO = MF.getMachineMemOperand(
-      MachinePointerInfo(),
-      MachineMemOperand::MOLoad,
-      VT.getStoreSize(), VT.getStoreSize());
     return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
-                                   Op->getVTList(), Ops, VT, MMO);
+                                   Op->getVTList(), Ops, M->getMemoryVT(),
+                                   M->getMemOperand());
   }
   // Basic sample.
   case Intrinsic::amdgcn_image_sample:
   case Intrinsic::amdgcn_image_sample_cl:
   case Intrinsic::amdgcn_image_sample_d:
   case Intrinsic::amdgcn_image_sample_d_cl:
   case Intrinsic::amdgcn_image_sample_l:
   case Intrinsic::amdgcn_image_sample_b:
   case Intrinsic::amdgcn_image_sample_b_cl:
   case Intrinsic::amdgcn_image_sample_lz:

 
     EVT VT = Op.getOperand(3).getValueType();
     MachineMemOperand *MMO = MF.getMachineMemOperand(
       MachinePointerInfo(),
       MachineMemOperand::MOStore,
       VT.getStoreSize(), 4);
     return DAG.getMemIntrinsicNode(Opcode, DL,
                                    Op->getVTList(), Ops, VT, MMO);
   }
 
+  case Intrinsic::amdgcn_buffer_store_format: {
+    SDValue VData = Op.getOperand(2);
+    EVT MemVT = VData.getValueType();
+    unsigned Opc = AMDGPUISD::BUFFER_STORE_FORMAT;
+    if (isHalfVT(MemVT)) {
+      Opc = AMDGPUISD::BUFFER_STORE_FORMAT_D16;
+      // TODO: Handle v3f16.
+      if (MemVT == MVT::v2f16 || MemVT== MVT::v4f16) {
+        if (Subtarget->hasPackedD16VMem()) {
+          if (!isTypeLegal(MemVT)) {
+            // If Target supports packed vmem, we just need to workaround
+            // the illegal type by casting to an equivalent one.
+            EVT EquivMemVT = getEquivalentMemType(*DAG.getContext(), MemVT);
+            VData = DAG.getNode(ISD::BITCAST, DL, EquivMemVT, VData);
+          }
+        } else {// We need to unpack the packed data to store.
+          EVT ExtendedT = getExtVT(MemVT);
+          VData = DAG.getNode(ISD::FP_EXTEND, DL, ExtendedT, VData);
+        }
+      }
+    }
+    SDValue Ops[] = {
+      Chain, // Chain
+      VData, // vdata
+      Op.getOperand(3), // rsrc
+      Op.getOperand(4), // vindex
+      Op.getOperand(5), // offset
+      Op.getOperand(6),  // glc
+      Op.getOperand(7)
+    };
+    MemSDNode *M = cast<MemSDNode>(Op);
+    return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
+                                   M->getMemoryVT(), M->getMemOperand());
+  }
   case Intrinsic::amdgcn_tbuffer_store: {
+    SDValue VData = Op.getOperand(2);
+    EVT MemVT = VData.getValueType();
+    unsigned Opc = AMDGPUISD::TBUFFER_STORE_FORMAT;
+    if (isHalfVT(MemVT)) {
+      Opc = AMDGPUISD::TBUFFER_STORE_FORMAT_D16;
+      // TODO: Handle v3f16.
+      if (MemVT == MVT::v2f16 || MemVT== MVT::v4f16) {
+        if (Subtarget->hasPackedD16VMem()) {
+          if (!isTypeLegal(MemVT)) {
+            // If Target supports packed vmem, we just need to workaround
+            // the illegal type by casting to an equivalent one.
+            EVT EquivMemVT = getEquivalentMemType(*DAG.getContext(), MemVT);
+            VData = DAG.getNode(ISD::BITCAST, DL, EquivMemVT, VData);
+          }
+        } else {// We need to unpack the packed data to store.
+          EVT ExtendedT = getExtVT(MemVT);
+          VData = DAG.getNode(ISD::FP_EXTEND, DL, ExtendedT, VData);
+        }
+      }
+    }
     SDValue Ops[] = {
       Chain,
-      Op.getOperand(2),  // vdata
+      VData,  // vdata
       Op.getOperand(3),  // rsrc
       Op.getOperand(4),  // vindex
       Op.getOperand(5),  // voffset
       Op.getOperand(6),  // soffset
       Op.getOperand(7),  // offset
       Op.getOperand(8),  // dfmt
       Op.getOperand(9),  // nfmt
       Op.getOperand(10), // glc
       Op.getOperand(11)  // slc
     };
-    EVT VT = Op.getOperand(3).getValueType();
-    MachineMemOperand *MMO = MF.getMachineMemOperand(
-      MachinePointerInfo(),
-      MachineMemOperand::MOStore,
-      VT.getStoreSize(), 4);
-    return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
-                                   Op->getVTList(), Ops, VT, MMO);
+    MemSDNode *M = cast<MemSDNode>(Op);
+    return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, 
+                                   M->getMemoryVT(), M->getMemOperand());
   }
-
   default:
     return Op;
   }
 }
 
 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
   SDLoc DL(Op);
   LoadSDNode *Load = cast<LoadSDNode>(Op);
   ISD::LoadExtType ExtType = Load->getExtensionType();
   EVT MemVT = Load->getMemoryVT();

lib/Target/AMDGPU/SIInstrInfo.td

 >;
 
 def SIatomic_inc : SDNode<"AMDGPUISD::ATOMIC_INC", SDTAtomic2,
   [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
 >;
 
 def SIatomic_dec : SDNode<"AMDGPUISD::ATOMIC_DEC", SDTAtomic2,
   [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
 >;
 
-def SItbuffer_load : SDNode<"AMDGPUISD::TBUFFER_LOAD_FORMAT",
-  SDTypeProfile<1, 9,
+
+def SDTbuffer_load : SDTypeProfile<1, 9,
     [                     // vdata
      SDTCisVT<1, v4i32>,  // rsrc
      SDTCisVT<2, i32>,    // vindex(VGPR)
      SDTCisVT<3, i32>,    // voffset(VGPR)
      SDTCisVT<4, i32>,    // soffset(SGPR)
      SDTCisVT<5, i32>,    // offset(imm)
      SDTCisVT<6, i32>,    // dfmt(imm)
      SDTCisVT<7, i32>,    // nfmt(imm)
      SDTCisVT<8, i32>,    // glc(imm)
      SDTCisVT<9, i32>     // slc(imm)
-    ]>,
-  [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
->;
+    ]>;
+
+def SItbuffer_load :   SDNode<"AMDGPUISD::TBUFFER_LOAD_FORMAT", SDTbuffer_load,
+                              [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]>;
+def SItbuffer_load_d16 : SDNode<"AMDGPUISD::TBUFFER_LOAD_FORMAT_D16",
+                                SDTbuffer_load,
+                                [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]>;
+
 
 def SDTtbuffer_store : SDTypeProfile<0, 10,
     [                     // vdata
      SDTCisVT<1, v4i32>,  // rsrc
      SDTCisVT<2, i32>,    // vindex(VGPR)
      SDTCisVT<3, i32>,    // voffset(VGPR)
      SDTCisVT<4, i32>,    // soffset(SGPR)
      SDTCisVT<5, i32>,    // offset(imm)
      SDTCisVT<6, i32>,    // dfmt(imm)
      SDTCisVT<7, i32>,    // nfmt(imm)
      SDTCisVT<8, i32>,    // glc(imm)
      SDTCisVT<9, i32>     // slc(imm)
     ]>;
 
 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT", SDTtbuffer_store,
                              [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
 def SItbuffer_store_x3 : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT_X3",
                                 SDTtbuffer_store,
                                 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
+def SItbuffer_store_d16 : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT_D16",
+                                SDTtbuffer_store,
+                                [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
 
 def SDTBufferLoad : SDTypeProfile<1, 5,
     [                    // vdata
      SDTCisVT<1, v4i32>, // rsrc
      SDTCisVT<2, i32>,   // vindex
      SDTCisVT<3, i32>,   // offset
      SDTCisVT<4, i1>,    // glc
      SDTCisVT<5, i1>]>;  // slc
 
 def SIbuffer_load : SDNode <"AMDGPUISD::BUFFER_LOAD", SDTBufferLoad,
                             [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
 def SIbuffer_load_format : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT", SDTBufferLoad,
                             [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
+def SIbuffer_load_format_d16 : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT_D16",
+                            SDTBufferLoad,
+                            [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
+
+def SDTBufferStore : SDTypeProfile<0, 6,
+    [                    // vdata
+     SDTCisVT<1, v4i32>, // rsrc
+     SDTCisVT<2, i32>,   // vindex
+     SDTCisVT<3, i32>,   // offset
+     SDTCisVT<4, i1>,    // glc
+     SDTCisVT<5, i1>]>;  // slc
+def SIbuffer_store_format : SDNode <"AMDGPUISD::BUFFER_STORE_FORMAT",
+                            SDTBufferStore,
+                            [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
+def SIbuffer_store_format_d16 : SDNode <"AMDGPUISD::BUFFER_STORE_FORMAT_D16",
+                            SDTBufferStore,
+                            [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
 
 class SDSample<string opcode> : SDNode <opcode,
   SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v8i32>,
                        SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
 >;
 
 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.d16.ll

+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=UNPACKED %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefix=PACKED %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx901 -verify-machineinstrs | FileCheck -check-prefix=PACKED %s
+
+;UNPACKED-LABEL: {{^}}buffer_load_format_d16_x:
+;UNPACKED: buffer_load_format_d16_x v0, off, s[0:3], 0
+;UNPACKED: s_waitcnt
+
+;PACKED-LABEL: {{^}}buffer_load_format_d16_x:
+;PACKED: buffer_load_format_d16_x v0, off, s[0:3], 0
+;PACKED: s_waitcnt
+define amdgpu_ps half @buffer_load_format_d16_x(<4 x i32> inreg %rsrc) {
+main_body:
+  %data = call half @llvm.amdgcn.buffer.load.format.f16(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
+  ret half %data
+}
+
+;UNPACKED-LABEL: {{^}}buffer_load_format_d16_xy:
+;UNPACKED: buffer_load_format_d16_xy v[0:1], off, s[0:3], 0
+;UNPACKED: s_waitcnt
+
+;PACKED-LABEL: {{^}}buffer_load_format_d16_xy:
+;PACKED: buffer_load_format_d16_xy v0, off, s[0:3], 0
+;PACKED: s_waitcnt
+define amdgpu_ps <2 x half> @buffer_load_format_d16_xy(<4 x i32> inreg %rsrc) {
+main_body:
+  %data = call <2 x half> @llvm.amdgcn.buffer.load.format.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
+  ret < 2 x half> %data
+}
+
+;UNPACKED-LABEL: {{^}}buffer_load_format_d16_xyzw:
+;UNPACKED: buffer_load_format_d16_xyzw v[0:3], off, s[0:3], 0
+;UNPACKED: s_waitcnt
+
+;PACKED-LABEL: {{^}}buffer_load_format_d16_xyzw:
+;PACKED: buffer_load_format_d16_xyzw v[0:1], off, s[0:3], 0
+;PACKED: s_waitcnt
+define amdgpu_ps <4 x half> @buffer_load_format_d16_xyzw(<4 x i32> inreg %rsrc) {
+main_body:
+  %data = call <4 x half> @llvm.amdgcn.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0)
+  ret <4 x half> %data
+}
+
+declare half @llvm.amdgcn.buffer.load.format.f16(<4 x i32>, i32, i32, i1, i1)
+declare <2 x half> @llvm.amdgcn.buffer.load.format.v2f16(<4 x i32>, i32, i32, i1, i1)
+declare <4 x half> @llvm.amdgcn.buffer.load.format.v4f16(<4 x i32>, i32, i32, i1, i1)

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.d16.ll

+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=UNPACKED %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefix=PACKED %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx901 -verify-machineinstrs | FileCheck -check-prefix=PACKED %s
+
+;UNPACKED-LABEL: {{^}}buffer_store_format_d16_x:
+;UNPACKED: buffer_store_format_d16_x v0, v1, s[4:7], 0 idxen
+;UNPACKED: s_endpgm
+
+;PACKED-LABEL: {{^}}buffer_store_format_d16_x:
+;PACKED: buffer_store_format_d16_x v0, v1, s[4:7], 0 idxen
+;PACKED: s_endpgm
+define amdgpu_kernel void @buffer_store_format_d16_x(<4 x i32> inreg %rsrc, half %data, i32 %index) {
+main_body:
+  call void @llvm.amdgcn.buffer.store.format.f16(half %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0)
+  ret void
+}
+
+;UNPACKED-LABEL: {{^}}buffer_store_format_d16_xy:
+;UNPACKED: buffer_store_format_d16_xy v[0:1], v2, s[4:7], 0 idxen
+;UNPACKED: s_endpgm
+
+;PACKED-LABEL: {{^}}buffer_store_format_d16_xy:
+;PACKED: buffer_store_format_d16_xy v0, v1, s[4:7], 0 idxen
+;PACKED: s_endpgm
+define amdgpu_kernel void @buffer_store_format_d16_xy(<4 x i32> inreg %rsrc, <2 x half> %data, i32 %index) {
+main_body:
+  call void @llvm.amdgcn.buffer.store.format.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0)
+  ret void
+}
+
+;UNPACKED-LABEL: {{^}}buffer_store_format_d16_xyzw:
+;UNPACKED: buffer_store_format_d16_xyzw v[0:3], v4, s[4:7], 0 idxen
+;UNPACKED: s_endpgm
+
+;PACKED-LABEL: {{^}}buffer_store_format_d16_xyzw:
+;PACKED: buffer_store_format_d16_xyzw v[0:1], v2, s[4:7], 0 idxen
+;PACKED: s_endpgm
+define amdgpu_kernel void @buffer_store_format_d16_xyzw(<4 x i32> inreg %rsrc, <4 x half> %data, i32 %index) {
+main_body:
+  call void @llvm.amdgcn.buffer.store.format.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0)
+  ret void
+}
+
+declare void @llvm.amdgcn.buffer.store.format.f16(half, <4 x i32>, i32, i32, i1, i1)
+declare void @llvm.amdgcn.buffer.store.format.v2f16(<2 x half>, <4 x i32>, i32, i32, i1, i1)
+declare void @llvm.amdgcn.buffer.store.format.v4f16(<4 x half>, <4 x i32>, i32, i32, i1, i1)

test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.d16.ll

+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=UNPACKED %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefix=PACKED %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx901 -verify-machineinstrs | FileCheck -check-prefix=PACKED %s
+
+
+;UNPACKED-LABEL: {{^}}tbuffer_load_d16_x:
+;UNPACKED: tbuffer_load_format_d16_x v0, off, s[0:3],  dfmt:6,  nfmt:1, 0
+;UNPACKED: s_waitcnt
+
+;PACKED-LABEL: {{^}}tbuffer_load_d16_x:
+;PACKED: tbuffer_load_format_d16_x v0, off, s[0:3],  dfmt:6,  nfmt:1, 0
+;PACKED: s_waitcnt
+define amdgpu_ps half @tbuffer_load_d16_x(<4 x i32> inreg %rsrc) {
+main_body:
+  %data = call half @llvm.amdgcn.tbuffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0, i32 6, i32 1, i1 0, i1 0)
+  ret half %data
+}
+
+;UNPACKED-LABEL: {{^}}tbuffer_load_d16_xy:
+;UNPACKED: tbuffer_load_format_d16_xy v[0:1], off, s[0:3],  dfmt:6,  nfmt:1, 0
+;UNPACKED: s_waitcnt
+
+;PACKED-LABEL: {{^}}tbuffer_load_d16_xy:
+;PACKED: tbuffer_load_format_d16_xy v0, off, s[0:3],  dfmt:6,  nfmt:1, 0
+;PACKED: s_waitcnt
+define amdgpu_ps <2 x half> @tbuffer_load_d16_xy(<4 x i32> inreg %rsrc) {
+main_body:
+  %data = call <2 x half> @llvm.amdgcn.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0, i32 6, i32 1, i1 0, i1 0)
+  ret < 2 x half> %data
+}
+
+;UNPACKED-LABEL: {{^}}tbuffer_load_d16_xyzw:
+;UNPACKED: tbuffer_load_format_d16_xyzw v[0:3], off, s[0:3],  dfmt:6,  nfmt:1, 0
+;UNPACKED: s_waitcnt
+
+;PACKED-LABEL: {{^}}tbuffer_load_d16_xyzw:
+;PACKED: tbuffer_load_format_d16_xyzw v[0:1], off, s[0:3],  dfmt:6,  nfmt:1, 0
+;PACKED: s_waitcnt
+define amdgpu_ps <4 x half> @tbuffer_load_d16_xyzw(<4 x i32> inreg %rsrc) {
+main_body:
+  %data = call <4 x half> @llvm.amdgcn.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0, i32 6, i32 1, i1 0, i1 0)
+  ret <4 x half> %data
+}
+
+declare half @llvm.amdgcn.tbuffer.load.f16(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
+declare <2 x half> @llvm.amdgcn.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
+declare <4 x half> @llvm.amdgcn.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)

test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.d16.ll

+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=UNPACKED %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefix=PACKED %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx901 -verify-machineinstrs | FileCheck -check-prefix=PACKED %s
+
+
+;UNPACKED-LABEL: {{^}}tbuffer_store_d16_x:
+;UNPACKED: tbuffer_store_format_d16_x  v0, v1, s[4:7],  dfmt:1,  nfmt:2, 0 idxen
+;UNPACKED: s_endpgm
+
+;PACKED-LABEL: {{^}}tbuffer_store_d16_x:
+;PACKED: tbuffer_store_format_d16_x  v0, v1, s[4:7],  dfmt:1,  nfmt:2, 0 idxen
+;PACKED: s_endpgm
+define amdgpu_kernel void @tbuffer_store_d16_x(<4 x i32> inreg %rsrc, half %data, i32 %vindex) {
+main_body:
+  call void @llvm.amdgcn.tbuffer.store.f16(half %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0, i32 1, i32 2, i1 0, i1 0)
+  ret void
+}
+
+
+;UNPACKED-LABEL: {{^}}tbuffer_store_d16_xy:
+;UNPACKED: tbuffer_store_format_d16_xy  v[0:1], v2, s[4:7],  dfmt:1,  nfmt:2, 0 idxen
+;UNPACKED: s_endpgm
+
+;PACKED-LABEL: {{^}}tbuffer_store_d16_xy:
+;PACKED: tbuffer_store_format_d16_xy  v0, v1, s[4:7],  dfmt:1,  nfmt:2, 0 idxen
+;PACKED: s_endpgm
+define amdgpu_kernel void @tbuffer_store_d16_xy(<4 x i32> inreg %rsrc, <2 x half> %data, i32 %vindex) {
+main_body:
+  call void @llvm.amdgcn.tbuffer.store.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0, i32 1, i32 2, i1 0, i1 0)
+  ret void
+}
+
+
+;UNPACKED-LABEL: {{^}}tbuffer_store_d16_xyzw:
+;UNPACKED: tbuffer_store_format_d16_xyzw  v[0:3], v4, s[4:7],  dfmt:1,  nfmt:2, 0 idxen
+;UNPACKED: s_endpgm
+
+;PACKED-LABEL: {{^}}tbuffer_store_d16_xyzw:
+;PACKED: tbuffer_store_format_d16_xyzw  v[0:1], v2, s[4:7],  dfmt:1,  nfmt:2, 0 idxen
+;PACKED: s_endpgm
+define amdgpu_kernel void @tbuffer_store_d16_xyzw(<4 x i32> inreg %rsrc, <4 x half> %data, i32 %vindex) {
+main_body:
+  call void @llvm.amdgcn.tbuffer.store.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0, i32 1, i32 2, i1 0, i1 0)
+  ret void
+}
+
+declare void @llvm.amdgcn.tbuffer.store.f16(half, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
+declare void @llvm.amdgcn.tbuffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
+declare void @llvm.amdgcn.tbuffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)